1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/export.h>
7 #include <linux/module.h>
8 #include <linux/regmap.h>
9 #include <linux/platform_device.h>
10 #include <linux/clk-provider.h>
11 #include <linux/interconnect-clk.h>
12 #include <linux/reset-controller.h>
13 #include <linux/of.h>
14 
15 #include "common.h"
16 #include "clk-rcg.h"
17 #include "clk-regmap.h"
18 #include "reset.h"
19 #include "gdsc.h"
20 
21 struct qcom_cc {
22 	struct qcom_reset_controller reset;
23 	struct clk_regmap **rclks;
24 	size_t num_rclks;
25 	struct dev_pm_domain_list *pd_list;
26 };
27 
28 const
qcom_find_freq(const struct freq_tbl * f,unsigned long rate)29 struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
30 {
31 	if (!f)
32 		return NULL;
33 
34 	if (!f->freq)
35 		return f;
36 
37 	for (; f->freq; f++)
38 		if (rate <= f->freq)
39 			return f;
40 
41 	/* Default to our fastest rate */
42 	return f - 1;
43 }
44 EXPORT_SYMBOL_GPL(qcom_find_freq);
45 
qcom_find_freq_multi(const struct freq_multi_tbl * f,unsigned long rate)46 const struct freq_multi_tbl *qcom_find_freq_multi(const struct freq_multi_tbl *f,
47 						  unsigned long rate)
48 {
49 	if (!f)
50 		return NULL;
51 
52 	if (!f->freq)
53 		return f;
54 
55 	for (; f->freq; f++)
56 		if (rate <= f->freq)
57 			return f;
58 
59 	/* Default to our fastest rate */
60 	return f - 1;
61 }
62 EXPORT_SYMBOL_GPL(qcom_find_freq_multi);
63 
qcom_find_freq_floor(const struct freq_tbl * f,unsigned long rate)64 const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
65 					    unsigned long rate)
66 {
67 	const struct freq_tbl *best = NULL;
68 
69 	for ( ; f->freq; f++) {
70 		if (rate >= f->freq)
71 			best = f;
72 		else
73 			break;
74 	}
75 
76 	return best;
77 }
78 EXPORT_SYMBOL_GPL(qcom_find_freq_floor);
79 
qcom_find_src_index(struct clk_hw * hw,const struct parent_map * map,u8 src)80 int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src)
81 {
82 	int i, num_parents = clk_hw_get_num_parents(hw);
83 
84 	for (i = 0; i < num_parents; i++)
85 		if (src == map[i].src)
86 			return i;
87 
88 	return -ENOENT;
89 }
90 EXPORT_SYMBOL_GPL(qcom_find_src_index);
91 
qcom_find_cfg_index(struct clk_hw * hw,const struct parent_map * map,u8 cfg)92 int qcom_find_cfg_index(struct clk_hw *hw, const struct parent_map *map, u8 cfg)
93 {
94 	int i, num_parents = clk_hw_get_num_parents(hw);
95 
96 	for (i = 0; i < num_parents; i++)
97 		if (cfg == map[i].cfg)
98 			return i;
99 
100 	return -ENOENT;
101 }
102 EXPORT_SYMBOL_GPL(qcom_find_cfg_index);
103 
104 struct regmap *
qcom_cc_map(struct platform_device * pdev,const struct qcom_cc_desc * desc)105 qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
106 {
107 	void __iomem *base;
108 	struct device *dev = &pdev->dev;
109 
110 	base = devm_platform_ioremap_resource(pdev, 0);
111 	if (IS_ERR(base))
112 		return ERR_CAST(base);
113 
114 	return devm_regmap_init_mmio(dev, base, desc->config);
115 }
116 EXPORT_SYMBOL_GPL(qcom_cc_map);
117 
118 void
qcom_pll_set_fsm_mode(struct regmap * map,u32 reg,u8 bias_count,u8 lock_count)119 qcom_pll_set_fsm_mode(struct regmap *map, u32 reg, u8 bias_count, u8 lock_count)
120 {
121 	u32 val;
122 	u32 mask;
123 
124 	/* De-assert reset to FSM */
125 	regmap_update_bits(map, reg, PLL_VOTE_FSM_RESET, 0);
126 
127 	/* Program bias count and lock count */
128 	val = bias_count << PLL_BIAS_COUNT_SHIFT |
129 		lock_count << PLL_LOCK_COUNT_SHIFT;
130 	mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
131 	mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
132 	regmap_update_bits(map, reg, mask, val);
133 
134 	/* Enable PLL FSM voting */
135 	regmap_update_bits(map, reg, PLL_VOTE_FSM_ENA, PLL_VOTE_FSM_ENA);
136 }
137 EXPORT_SYMBOL_GPL(qcom_pll_set_fsm_mode);
138 
qcom_cc_gdsc_unregister(void * data)139 static void qcom_cc_gdsc_unregister(void *data)
140 {
141 	gdsc_unregister(data);
142 }
143 
144 /*
145  * Backwards compatibility with old DTs. Register a pass-through factor 1/1
146  * clock to translate 'path' clk into 'name' clk and register the 'path'
147  * clk as a fixed rate clock if it isn't present.
148  */
_qcom_cc_register_board_clk(struct device * dev,const char * path,const char * name,unsigned long rate,bool add_factor)149 static int _qcom_cc_register_board_clk(struct device *dev, const char *path,
150 				       const char *name, unsigned long rate,
151 				       bool add_factor)
152 {
153 	struct device_node *node = NULL;
154 	struct device_node *clocks_node;
155 	struct clk_fixed_factor *factor;
156 	struct clk_fixed_rate *fixed;
157 	struct clk_init_data init_data = { };
158 	int ret;
159 
160 	clocks_node = of_find_node_by_path("/clocks");
161 	if (clocks_node) {
162 		node = of_get_child_by_name(clocks_node, path);
163 		of_node_put(clocks_node);
164 	}
165 
166 	if (!node) {
167 		fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
168 		if (!fixed)
169 			return -EINVAL;
170 
171 		fixed->fixed_rate = rate;
172 		fixed->hw.init = &init_data;
173 
174 		init_data.name = path;
175 		init_data.ops = &clk_fixed_rate_ops;
176 
177 		ret = devm_clk_hw_register(dev, &fixed->hw);
178 		if (ret)
179 			return ret;
180 	}
181 	of_node_put(node);
182 
183 	if (add_factor) {
184 		factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL);
185 		if (!factor)
186 			return -EINVAL;
187 
188 		factor->mult = factor->div = 1;
189 		factor->hw.init = &init_data;
190 
191 		init_data.name = name;
192 		init_data.parent_names = &path;
193 		init_data.num_parents = 1;
194 		init_data.flags = 0;
195 		init_data.ops = &clk_fixed_factor_ops;
196 
197 		ret = devm_clk_hw_register(dev, &factor->hw);
198 		if (ret)
199 			return ret;
200 	}
201 
202 	return 0;
203 }
204 
qcom_cc_register_board_clk(struct device * dev,const char * path,const char * name,unsigned long rate)205 int qcom_cc_register_board_clk(struct device *dev, const char *path,
206 			       const char *name, unsigned long rate)
207 {
208 	bool add_factor = true;
209 
210 	/*
211 	 * TODO: The RPM clock driver currently does not support the xo clock.
212 	 * When xo is added to the RPM clock driver, we should change this
213 	 * function to skip registration of xo factor clocks.
214 	 */
215 
216 	return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor);
217 }
218 EXPORT_SYMBOL_GPL(qcom_cc_register_board_clk);
219 
qcom_cc_register_sleep_clk(struct device * dev)220 int qcom_cc_register_sleep_clk(struct device *dev)
221 {
222 	return _qcom_cc_register_board_clk(dev, "sleep_clk", "sleep_clk_src",
223 					   32768, true);
224 }
225 EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);
226 
227 /* Drop 'protected-clocks' from the list of clocks to register */
qcom_cc_drop_protected(struct device * dev,struct qcom_cc * cc)228 static void qcom_cc_drop_protected(struct device *dev, struct qcom_cc *cc)
229 {
230 	struct device_node *np = dev->of_node;
231 	u32 i;
232 
233 	of_property_for_each_u32(np, "protected-clocks", i) {
234 		if (i >= cc->num_rclks)
235 			continue;
236 
237 		cc->rclks[i] = NULL;
238 	}
239 }
240 
qcom_cc_clk_hw_get(struct of_phandle_args * clkspec,void * data)241 static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec,
242 					 void *data)
243 {
244 	struct qcom_cc *cc = data;
245 	unsigned int idx = clkspec->args[0];
246 
247 	if (idx >= cc->num_rclks) {
248 		pr_err("%s: invalid index %u\n", __func__, idx);
249 		return ERR_PTR(-EINVAL);
250 	}
251 
252 	return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL;
253 }
254 
qcom_cc_icc_register(struct device * dev,const struct qcom_cc_desc * desc)255 static int qcom_cc_icc_register(struct device *dev,
256 				const struct qcom_cc_desc *desc)
257 {
258 	struct icc_clk_data *icd;
259 	struct clk_hw *hws;
260 	int i;
261 
262 	if (!IS_ENABLED(CONFIG_INTERCONNECT_CLK))
263 		return 0;
264 
265 	if (!desc->icc_hws)
266 		return 0;
267 
268 	icd = devm_kcalloc(dev, desc->num_icc_hws, sizeof(*icd), GFP_KERNEL);
269 	if (!icd)
270 		return -ENOMEM;
271 
272 	for (i = 0; i < desc->num_icc_hws; i++) {
273 		icd[i].master_id = desc->icc_hws[i].master_id;
274 		icd[i].slave_id = desc->icc_hws[i].slave_id;
275 		hws = &desc->clks[desc->icc_hws[i].clk_id]->hw;
276 		icd[i].clk = devm_clk_hw_get_clk(dev, hws, "icc");
277 		if (!icd[i].clk)
278 			return dev_err_probe(dev, -ENOENT,
279 					     "(%d) clock entry is null\n", i);
280 		icd[i].name = clk_hw_get_name(hws);
281 	}
282 
283 	return devm_icc_clk_register(dev, desc->icc_first_node_id,
284 						     desc->num_icc_hws, icd);
285 }
286 
qcom_cc_really_probe(struct device * dev,const struct qcom_cc_desc * desc,struct regmap * regmap)287 int qcom_cc_really_probe(struct device *dev,
288 			 const struct qcom_cc_desc *desc, struct regmap *regmap)
289 {
290 	int i, ret;
291 	struct qcom_reset_controller *reset;
292 	struct qcom_cc *cc;
293 	struct gdsc_desc *scd;
294 	size_t num_clks = desc->num_clks;
295 	struct clk_regmap **rclks = desc->clks;
296 	size_t num_clk_hws = desc->num_clk_hws;
297 	struct clk_hw **clk_hws = desc->clk_hws;
298 
299 	cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
300 	if (!cc)
301 		return -ENOMEM;
302 
303 	ret = devm_pm_domain_attach_list(dev, NULL, &cc->pd_list);
304 	if (ret < 0 && ret != -EEXIST)
305 		return ret;
306 
307 	reset = &cc->reset;
308 	reset->rcdev.of_node = dev->of_node;
309 	reset->rcdev.ops = &qcom_reset_ops;
310 	reset->rcdev.owner = dev->driver->owner;
311 	reset->rcdev.nr_resets = desc->num_resets;
312 	reset->regmap = regmap;
313 	reset->reset_map = desc->resets;
314 
315 	ret = devm_reset_controller_register(dev, &reset->rcdev);
316 	if (ret)
317 		return ret;
318 
319 	if (desc->gdscs && desc->num_gdscs) {
320 		scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL);
321 		if (!scd)
322 			return -ENOMEM;
323 		scd->dev = dev;
324 		scd->scs = desc->gdscs;
325 		scd->num = desc->num_gdscs;
326 		scd->pd_list = cc->pd_list;
327 		ret = gdsc_register(scd, &reset->rcdev, regmap);
328 		if (ret)
329 			return ret;
330 		ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister,
331 					       scd);
332 		if (ret)
333 			return ret;
334 	}
335 
336 	cc->rclks = rclks;
337 	cc->num_rclks = num_clks;
338 
339 	qcom_cc_drop_protected(dev, cc);
340 
341 	for (i = 0; i < num_clk_hws; i++) {
342 		ret = devm_clk_hw_register(dev, clk_hws[i]);
343 		if (ret)
344 			return ret;
345 	}
346 
347 	for (i = 0; i < num_clks; i++) {
348 		if (!rclks[i])
349 			continue;
350 
351 		ret = devm_clk_register_regmap(dev, rclks[i]);
352 		if (ret)
353 			return ret;
354 	}
355 
356 	ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc);
357 	if (ret)
358 		return ret;
359 
360 	return qcom_cc_icc_register(dev, desc);
361 }
362 EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
363 
qcom_cc_probe(struct platform_device * pdev,const struct qcom_cc_desc * desc)364 int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
365 {
366 	struct regmap *regmap;
367 
368 	regmap = qcom_cc_map(pdev, desc);
369 	if (IS_ERR(regmap))
370 		return PTR_ERR(regmap);
371 
372 	return qcom_cc_really_probe(&pdev->dev, desc, regmap);
373 }
374 EXPORT_SYMBOL_GPL(qcom_cc_probe);
375 
qcom_cc_probe_by_index(struct platform_device * pdev,int index,const struct qcom_cc_desc * desc)376 int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
377 			   const struct qcom_cc_desc *desc)
378 {
379 	struct regmap *regmap;
380 	void __iomem *base;
381 
382 	base = devm_platform_ioremap_resource(pdev, index);
383 	if (IS_ERR(base))
384 		return -ENOMEM;
385 
386 	regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config);
387 	if (IS_ERR(regmap))
388 		return PTR_ERR(regmap);
389 
390 	return qcom_cc_really_probe(&pdev->dev, desc, regmap);
391 }
392 EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index);
393 
394 MODULE_LICENSE("GPL v2");
395 MODULE_DESCRIPTION("QTI Common Clock module");
396