1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 #include "psp_v14_0.h" 42 #include "psp_v15_0.h" 43 #include "psp_v15_0_8.h" 44 45 #include "amdgpu_ras.h" 46 #include "amdgpu_securedisplay.h" 47 #include "amdgpu_atomfirmware.h" 48 49 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*16) 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 static int psp_ring_init(struct psp_context *psp, 56 enum psp_ring_type ring_type) 57 { 58 int ret = 0; 59 struct psp_ring *ring; 60 struct amdgpu_device *adev = psp->adev; 61 62 ring = &psp->km_ring; 63 64 ring->ring_type = ring_type; 65 66 /* allocate 4k Page of Local Frame Buffer memory for ring */ 67 ring->ring_size = 0x1000; 68 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 69 AMDGPU_GEM_DOMAIN_VRAM | 70 AMDGPU_GEM_DOMAIN_GTT, 71 &adev->firmware.rbuf, 72 &ring->ring_mem_mc_addr, 73 (void **)&ring->ring_mem); 74 if (ret) { 75 ring->ring_size = 0; 76 return ret; 77 } 78 79 return 0; 80 } 81 82 /* 83 * Due to DF Cstate management centralized to PMFW, the firmware 84 * loading sequence will be updated as below: 85 * - Load KDB 86 * - Load SYS_DRV 87 * - Load tOS 88 * - Load PMFW 89 * - Setup TMR 90 * - Load other non-psp fw 91 * - Load ASD 92 * - Load XGMI/RAS/HDCP/DTM TA if any 93 * 94 * This new sequence is required for 95 * - Arcturus and onwards 96 */ 97 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 98 { 99 struct amdgpu_device *adev = psp->adev; 100 101 if (amdgpu_sriov_vf(adev)) { 102 psp->pmfw_centralized_cstate_management = false; 103 return; 104 } 105 106 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 107 case IP_VERSION(11, 0, 0): 108 case IP_VERSION(11, 0, 4): 109 case IP_VERSION(11, 0, 5): 110 case IP_VERSION(11, 0, 7): 111 case IP_VERSION(11, 0, 9): 112 case IP_VERSION(11, 0, 11): 113 case IP_VERSION(11, 0, 12): 114 case IP_VERSION(11, 0, 13): 115 case IP_VERSION(13, 0, 0): 116 case IP_VERSION(13, 0, 2): 117 case IP_VERSION(13, 0, 7): 118 psp->pmfw_centralized_cstate_management = true; 119 break; 120 default: 121 psp->pmfw_centralized_cstate_management = false; 122 break; 123 } 124 } 125 126 static int psp_init_sriov_microcode(struct psp_context *psp) 127 { 128 struct amdgpu_device *adev = psp->adev; 129 char ucode_prefix[30]; 130 int ret = 0; 131 132 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 133 134 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 135 case IP_VERSION(9, 0, 0): 136 case IP_VERSION(11, 0, 7): 137 case IP_VERSION(11, 0, 9): 138 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 139 ret = psp_init_cap_microcode(psp, ucode_prefix); 140 break; 141 case IP_VERSION(13, 0, 2): 142 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 143 ret = psp_init_cap_microcode(psp, ucode_prefix); 144 ret &= psp_init_ta_microcode(psp, ucode_prefix); 145 break; 146 case IP_VERSION(13, 0, 0): 147 adev->virt.autoload_ucode_id = 0; 148 break; 149 case IP_VERSION(13, 0, 6): 150 case IP_VERSION(13, 0, 14): 151 case IP_VERSION(13, 0, 15): 152 ret = psp_init_cap_microcode(psp, ucode_prefix); 153 ret &= psp_init_ta_microcode(psp, ucode_prefix); 154 break; 155 case IP_VERSION(13, 0, 10): 156 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 157 ret = psp_init_cap_microcode(psp, ucode_prefix); 158 break; 159 case IP_VERSION(13, 0, 12): 160 ret = psp_init_ta_microcode(psp, ucode_prefix); 161 break; 162 default: 163 return -EINVAL; 164 } 165 return ret; 166 } 167 168 static int psp_early_init(struct amdgpu_ip_block *ip_block) 169 { 170 struct amdgpu_device *adev = ip_block->adev; 171 struct psp_context *psp = &adev->psp; 172 173 psp->autoload_supported = true; 174 psp->boot_time_tmr = true; 175 176 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 177 case IP_VERSION(9, 0, 0): 178 psp_v3_1_set_psp_funcs(psp); 179 psp->autoload_supported = false; 180 psp->boot_time_tmr = false; 181 break; 182 case IP_VERSION(10, 0, 0): 183 case IP_VERSION(10, 0, 1): 184 psp_v10_0_set_psp_funcs(psp); 185 psp->autoload_supported = false; 186 psp->boot_time_tmr = false; 187 break; 188 case IP_VERSION(11, 0, 2): 189 case IP_VERSION(11, 0, 4): 190 psp_v11_0_set_psp_funcs(psp); 191 psp->autoload_supported = false; 192 psp->boot_time_tmr = false; 193 break; 194 case IP_VERSION(11, 0, 0): 195 case IP_VERSION(11, 0, 7): 196 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev); 197 fallthrough; 198 case IP_VERSION(11, 0, 5): 199 case IP_VERSION(11, 0, 9): 200 case IP_VERSION(11, 0, 11): 201 case IP_VERSION(11, 5, 0): 202 case IP_VERSION(11, 5, 2): 203 case IP_VERSION(11, 0, 12): 204 case IP_VERSION(11, 0, 13): 205 psp_v11_0_set_psp_funcs(psp); 206 psp->boot_time_tmr = false; 207 break; 208 case IP_VERSION(11, 0, 3): 209 case IP_VERSION(12, 0, 1): 210 psp_v12_0_set_psp_funcs(psp); 211 psp->autoload_supported = false; 212 psp->boot_time_tmr = false; 213 break; 214 case IP_VERSION(13, 0, 2): 215 psp->boot_time_tmr = false; 216 fallthrough; 217 case IP_VERSION(13, 0, 6): 218 case IP_VERSION(13, 0, 14): 219 psp_v13_0_set_psp_funcs(psp); 220 psp->autoload_supported = false; 221 break; 222 case IP_VERSION(13, 0, 12): 223 case IP_VERSION(13, 0, 15): 224 psp_v13_0_set_psp_funcs(psp); 225 psp->autoload_supported = false; 226 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 227 break; 228 case IP_VERSION(13, 0, 1): 229 case IP_VERSION(13, 0, 3): 230 case IP_VERSION(13, 0, 5): 231 case IP_VERSION(13, 0, 8): 232 case IP_VERSION(13, 0, 11): 233 case IP_VERSION(14, 0, 0): 234 case IP_VERSION(14, 0, 1): 235 case IP_VERSION(14, 0, 4): 236 psp_v13_0_set_psp_funcs(psp); 237 psp->boot_time_tmr = false; 238 break; 239 case IP_VERSION(11, 0, 8): 240 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 241 psp_v11_0_8_set_psp_funcs(psp); 242 } 243 psp->autoload_supported = false; 244 psp->boot_time_tmr = false; 245 break; 246 case IP_VERSION(13, 0, 0): 247 case IP_VERSION(13, 0, 7): 248 case IP_VERSION(13, 0, 10): 249 psp_v13_0_set_psp_funcs(psp); 250 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 251 psp->boot_time_tmr = false; 252 break; 253 case IP_VERSION(13, 0, 4): 254 psp_v13_0_4_set_psp_funcs(psp); 255 psp->boot_time_tmr = false; 256 break; 257 case IP_VERSION(14, 0, 2): 258 case IP_VERSION(14, 0, 3): 259 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 260 psp_v14_0_set_psp_funcs(psp); 261 break; 262 case IP_VERSION(14, 0, 5): 263 psp_v14_0_set_psp_funcs(psp); 264 psp->boot_time_tmr = false; 265 break; 266 case IP_VERSION(15, 0, 0): 267 psp_v15_0_0_set_psp_funcs(psp); 268 psp->boot_time_tmr = false; 269 break; 270 case IP_VERSION(15, 0, 8): 271 psp_v15_0_8_set_psp_funcs(psp); 272 break; 273 default: 274 return -EINVAL; 275 } 276 277 psp->adev = adev; 278 279 adev->psp_timeout = 20000; 280 281 psp_check_pmfw_centralized_cstate_management(psp); 282 283 if (amdgpu_sriov_vf(adev)) 284 return psp_init_sriov_microcode(psp); 285 else 286 return psp_init_microcode(psp); 287 } 288 289 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 290 { 291 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 292 &mem_ctx->shared_buf); 293 mem_ctx->shared_bo = NULL; 294 } 295 296 static void psp_free_shared_bufs(struct psp_context *psp) 297 { 298 void *tmr_buf; 299 void **pptr; 300 301 /* free TMR memory buffer */ 302 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 303 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 304 psp->tmr_bo = NULL; 305 306 /* free xgmi shared memory */ 307 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 308 309 /* free ras shared memory */ 310 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 311 312 /* free hdcp shared memory */ 313 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 314 315 /* free dtm shared memory */ 316 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 317 318 /* free rap shared memory */ 319 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 320 321 /* free securedisplay shared memory */ 322 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 323 324 325 } 326 327 static void psp_memory_training_fini(struct psp_context *psp) 328 { 329 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 330 331 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 332 kfree(ctx->sys_cache); 333 ctx->sys_cache = NULL; 334 } 335 336 static int psp_memory_training_init(struct psp_context *psp) 337 { 338 int ret; 339 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 340 341 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 342 dev_dbg(psp->adev->dev, "memory training is not supported!\n"); 343 return 0; 344 } 345 346 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 347 if (ctx->sys_cache == NULL) { 348 dev_err(psp->adev->dev, "alloc mem_train_ctx.sys_cache failed!\n"); 349 ret = -ENOMEM; 350 goto Err_out; 351 } 352 353 dev_dbg(psp->adev->dev, 354 "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 355 ctx->train_data_size, 356 ctx->p2c_train_data_offset, 357 ctx->c2p_train_data_offset); 358 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 359 return 0; 360 361 Err_out: 362 psp_memory_training_fini(psp); 363 return ret; 364 } 365 366 /* 367 * Helper funciton to query psp runtime database entry 368 * 369 * @adev: amdgpu_device pointer 370 * @entry_type: the type of psp runtime database entry 371 * @db_entry: runtime database entry pointer 372 * 373 * Return false if runtime database doesn't exit or entry is invalid 374 * or true if the specific database entry is found, and copy to @db_entry 375 */ 376 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 377 enum psp_runtime_entry_type entry_type, 378 void *db_entry) 379 { 380 uint64_t db_header_pos, db_dir_pos; 381 struct psp_runtime_data_header db_header = {0}; 382 struct psp_runtime_data_directory db_dir = {0}; 383 bool ret = false; 384 int i; 385 386 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 387 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 388 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || 389 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) 390 return false; 391 392 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 393 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 394 395 /* read runtime db header from vram */ 396 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 397 sizeof(struct psp_runtime_data_header), false); 398 399 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 400 /* runtime db doesn't exist, exit */ 401 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 402 return false; 403 } 404 405 /* read runtime database entry from vram */ 406 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 407 sizeof(struct psp_runtime_data_directory), false); 408 409 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 410 /* invalid db entry count, exit */ 411 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 412 return false; 413 } 414 415 /* look up for requested entry type */ 416 for (i = 0; i < db_dir.entry_count && !ret; i++) { 417 if (db_dir.entry_list[i].entry_type == entry_type) { 418 switch (entry_type) { 419 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 420 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 421 /* invalid db entry size */ 422 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 423 return false; 424 } 425 /* read runtime database entry */ 426 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 427 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 428 ret = true; 429 break; 430 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 431 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 432 /* invalid db entry size */ 433 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 434 return false; 435 } 436 /* read runtime database entry */ 437 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 438 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 439 ret = true; 440 break; 441 default: 442 ret = false; 443 break; 444 } 445 } 446 } 447 448 return ret; 449 } 450 451 static int psp_sw_init(struct amdgpu_ip_block *ip_block) 452 { 453 struct amdgpu_device *adev = ip_block->adev; 454 struct psp_context *psp = &adev->psp; 455 int ret; 456 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 457 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 458 struct psp_runtime_scpm_entry scpm_entry; 459 460 psp->cmd = kzalloc_obj(struct psp_gfx_cmd_resp); 461 if (!psp->cmd) { 462 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n"); 463 return -ENOMEM; 464 } 465 466 adev->psp.xgmi_context.supports_extended_data = 467 !adev->gmc.xgmi.connected_to_cpu && 468 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2); 469 470 memset(&scpm_entry, 0, sizeof(scpm_entry)); 471 if ((psp_get_runtime_db_entry(adev, 472 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 473 &scpm_entry)) && 474 (scpm_entry.scpm_status != SCPM_DISABLE)) { 475 adev->scpm_enabled = true; 476 adev->scpm_status = scpm_entry.scpm_status; 477 } else { 478 adev->scpm_enabled = false; 479 adev->scpm_status = SCPM_DISABLE; 480 } 481 482 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 483 484 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 485 if (psp_get_runtime_db_entry(adev, 486 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 487 &boot_cfg_entry)) { 488 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 489 if ((psp->boot_cfg_bitmask) & 490 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 491 /* If psp runtime database exists, then 492 * only enable two stage memory training 493 * when TWO_STAGE_DRAM_TRAINING bit is set 494 * in runtime database 495 */ 496 mem_training_ctx->enable_mem_training = true; 497 } 498 499 } else { 500 /* If psp runtime database doesn't exist or is 501 * invalid, force enable two stage memory training 502 */ 503 mem_training_ctx->enable_mem_training = true; 504 } 505 506 if (mem_training_ctx->enable_mem_training) { 507 ret = psp_memory_training_init(psp); 508 if (ret) { 509 dev_err(adev->dev, "Failed to initialize memory training!\n"); 510 return ret; 511 } 512 513 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 514 if (ret) { 515 dev_err(adev->dev, "Failed to process memory training!\n"); 516 return ret; 517 } 518 } 519 520 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 521 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ? 522 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 523 &psp->fw_pri_bo, 524 &psp->fw_pri_mc_addr, 525 &psp->fw_pri_buf); 526 if (ret) 527 return ret; 528 529 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 530 AMDGPU_GEM_DOMAIN_VRAM | 531 AMDGPU_GEM_DOMAIN_GTT, 532 &psp->fence_buf_bo, 533 &psp->fence_buf_mc_addr, 534 &psp->fence_buf); 535 if (ret) 536 goto failed1; 537 538 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 539 AMDGPU_GEM_DOMAIN_VRAM | 540 AMDGPU_GEM_DOMAIN_GTT, 541 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 542 (void **)&psp->cmd_buf_mem); 543 if (ret) 544 goto failed2; 545 546 return 0; 547 548 failed2: 549 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 550 &psp->fence_buf_mc_addr, &psp->fence_buf); 551 failed1: 552 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 553 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 554 return ret; 555 } 556 557 static int psp_sw_fini(struct amdgpu_ip_block *ip_block) 558 { 559 struct amdgpu_device *adev = ip_block->adev; 560 struct psp_context *psp = &adev->psp; 561 562 psp_memory_training_fini(psp); 563 564 amdgpu_ucode_release(&psp->sos_fw); 565 amdgpu_ucode_release(&psp->asd_fw); 566 amdgpu_ucode_release(&psp->ta_fw); 567 amdgpu_ucode_release(&psp->cap_fw); 568 amdgpu_ucode_release(&psp->toc_fw); 569 570 kfree(psp->cmd); 571 psp->cmd = NULL; 572 573 psp_free_shared_bufs(psp); 574 575 if (psp->km_ring.ring_mem) 576 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 577 &psp->km_ring.ring_mem_mc_addr, 578 (void **)&psp->km_ring.ring_mem); 579 580 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 581 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 582 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 583 &psp->fence_buf_mc_addr, &psp->fence_buf); 584 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 585 (void **)&psp->cmd_buf_mem); 586 587 return 0; 588 } 589 590 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t reg_val, 591 uint32_t mask, uint32_t flags) 592 { 593 bool check_changed = flags & PSP_WAITREG_CHANGED; 594 bool verbose = !(flags & PSP_WAITREG_NOVERBOSE); 595 uint32_t val; 596 int i; 597 struct amdgpu_device *adev = psp->adev; 598 599 if (psp->adev->no_hw_access) 600 return 0; 601 602 for (i = 0; i < adev->usec_timeout; i++) { 603 val = RREG32(reg_index); 604 if (check_changed) { 605 if (val != reg_val) 606 return 0; 607 } else { 608 if ((val & mask) == reg_val) 609 return 0; 610 } 611 udelay(1); 612 } 613 614 if (verbose) 615 dev_err(adev->dev, 616 "psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x", 617 reg_index, mask, val, reg_val); 618 619 return -ETIME; 620 } 621 622 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 623 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout) 624 { 625 uint32_t val; 626 int i; 627 struct amdgpu_device *adev = psp->adev; 628 629 if (psp->adev->no_hw_access) 630 return 0; 631 632 for (i = 0; i < msec_timeout; i++) { 633 val = RREG32(reg_index); 634 if ((val & mask) == reg_val) 635 return 0; 636 msleep(1); 637 } 638 639 return -ETIME; 640 } 641 642 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 643 { 644 switch (cmd_id) { 645 case GFX_CMD_ID_LOAD_TA: 646 return "LOAD_TA"; 647 case GFX_CMD_ID_UNLOAD_TA: 648 return "UNLOAD_TA"; 649 case GFX_CMD_ID_INVOKE_CMD: 650 return "INVOKE_CMD"; 651 case GFX_CMD_ID_LOAD_ASD: 652 return "LOAD_ASD"; 653 case GFX_CMD_ID_SETUP_TMR: 654 return "SETUP_TMR"; 655 case GFX_CMD_ID_LOAD_IP_FW: 656 return "LOAD_IP_FW"; 657 case GFX_CMD_ID_DESTROY_TMR: 658 return "DESTROY_TMR"; 659 case GFX_CMD_ID_SAVE_RESTORE: 660 return "SAVE_RESTORE_IP_FW"; 661 case GFX_CMD_ID_SETUP_VMR: 662 return "SETUP_VMR"; 663 case GFX_CMD_ID_DESTROY_VMR: 664 return "DESTROY_VMR"; 665 case GFX_CMD_ID_PROG_REG: 666 return "PROG_REG"; 667 case GFX_CMD_ID_GET_FW_ATTESTATION: 668 return "GET_FW_ATTESTATION"; 669 case GFX_CMD_ID_LOAD_TOC: 670 return "ID_LOAD_TOC"; 671 case GFX_CMD_ID_AUTOLOAD_RLC: 672 return "AUTOLOAD_RLC"; 673 case GFX_CMD_ID_BOOT_CFG: 674 return "BOOT_CFG"; 675 case GFX_CMD_ID_CONFIG_SQ_PERFMON: 676 return "CONFIG_SQ_PERFMON"; 677 case GFX_CMD_ID_FB_FW_RESERV_ADDR: 678 return "FB_FW_RESERV_ADDR"; 679 case GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR: 680 return "FB_FW_RESERV_EXT_ADDR"; 681 case GFX_CMD_ID_SRIOV_SPATIAL_PART: 682 return "SPATIAL_PARTITION"; 683 case GFX_CMD_ID_FB_NPS_MODE: 684 return "NPS_MODE_CHANGE"; 685 default: 686 return "UNKNOWN CMD"; 687 } 688 } 689 690 static bool psp_err_warn(struct psp_context *psp) 691 { 692 struct psp_gfx_cmd_resp *cmd = psp->cmd_buf_mem; 693 694 /* This response indicates reg list is already loaded */ 695 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 696 cmd->cmd_id == GFX_CMD_ID_LOAD_IP_FW && 697 cmd->cmd.cmd_load_ip_fw.fw_type == GFX_FW_TYPE_REG_LIST && 698 cmd->resp.status == TEE_ERROR_CANCEL) 699 return false; 700 701 return true; 702 } 703 704 static int 705 psp_cmd_submit_buf(struct psp_context *psp, 706 struct amdgpu_firmware_info *ucode, 707 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 708 { 709 int ret; 710 int index; 711 int timeout = psp->adev->psp_timeout; 712 bool ras_intr = false; 713 bool skip_unsupport = false; 714 715 if (psp->adev->no_hw_access) 716 return 0; 717 718 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 719 720 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 721 722 index = atomic_inc_return(&psp->fence_value); 723 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 724 if (ret) { 725 atomic_dec(&psp->fence_value); 726 goto exit; 727 } 728 729 amdgpu_device_invalidate_hdp(psp->adev, NULL); 730 while (*((unsigned int *)psp->fence_buf) != index) { 731 if (--timeout == 0) 732 break; 733 /* 734 * Shouldn't wait for timeout when err_event_athub occurs, 735 * because gpu reset thread triggered and lock resource should 736 * be released for psp resume sequence. 737 */ 738 ras_intr = amdgpu_ras_intr_triggered(); 739 if (ras_intr) 740 break; 741 usleep_range(60, 100); 742 amdgpu_device_invalidate_hdp(psp->adev, NULL); 743 } 744 745 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 746 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 747 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 748 749 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 750 751 /* In some cases, psp response status is not 0 even there is no 752 * problem while the command is submitted. Some version of PSP FW 753 * doesn't write 0 to that field. 754 * So here we would like to only print a warning instead of an error 755 * during psp initialization to avoid breaking hw_init and it doesn't 756 * return -EINVAL. 757 */ 758 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 759 if (ucode) 760 dev_warn(psp->adev->dev, 761 "failed to load ucode %s(0x%X) ", 762 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 763 if (psp_err_warn(psp)) 764 dev_warn( 765 psp->adev->dev, 766 "psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 767 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), 768 psp->cmd_buf_mem->cmd_id, 769 psp->cmd_buf_mem->resp.status); 770 /* If any firmware (including CAP) load fails under SRIOV, it should 771 * return failure to stop the VF from initializing. 772 * Also return failure in case of timeout 773 */ 774 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 775 ret = -EINVAL; 776 goto exit; 777 } 778 } 779 780 if (ucode) { 781 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 782 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 783 } 784 785 exit: 786 return ret; 787 } 788 789 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 790 { 791 struct psp_gfx_cmd_resp *cmd = psp->cmd; 792 793 mutex_lock(&psp->mutex); 794 795 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 796 797 return cmd; 798 } 799 800 static void release_psp_cmd_buf(struct psp_context *psp) 801 { 802 mutex_unlock(&psp->mutex); 803 } 804 805 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 806 struct psp_gfx_cmd_resp *cmd, 807 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 808 { 809 struct amdgpu_device *adev = psp->adev; 810 uint32_t size = 0; 811 uint64_t tmr_pa = 0; 812 813 if (tmr_bo) { 814 size = amdgpu_bo_size(tmr_bo); 815 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 816 } 817 818 if (amdgpu_sriov_vf(psp->adev)) 819 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 820 else 821 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 822 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 823 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 824 cmd->cmd.cmd_setup_tmr.buf_size = size; 825 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 826 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 827 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 828 } 829 830 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 831 uint64_t pri_buf_mc, uint32_t size) 832 { 833 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 834 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 835 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 836 cmd->cmd.cmd_load_toc.toc_size = size; 837 } 838 839 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 840 static int psp_load_toc(struct psp_context *psp, 841 uint32_t *tmr_size) 842 { 843 int ret; 844 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 845 846 /* Copy toc to psp firmware private buffer */ 847 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 848 849 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 850 851 ret = psp_cmd_submit_buf(psp, NULL, cmd, 852 psp->fence_buf_mc_addr); 853 if (!ret) 854 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 855 856 release_psp_cmd_buf(psp); 857 858 return ret; 859 } 860 861 /* Set up Trusted Memory Region */ 862 static int psp_tmr_init(struct psp_context *psp) 863 { 864 int ret = 0; 865 int tmr_size; 866 void *tmr_buf; 867 void **pptr; 868 869 /* 870 * According to HW engineer, they prefer the TMR address be "naturally 871 * aligned" , e.g. the start address be an integer divide of TMR size. 872 * 873 * Note: this memory need be reserved till the driver 874 * uninitializes. 875 */ 876 tmr_size = PSP_TMR_SIZE(psp->adev); 877 878 /* For ASICs support RLC autoload, psp will parse the toc 879 * and calculate the total size of TMR needed 880 */ 881 if (!amdgpu_sriov_vf(psp->adev) && 882 psp->toc.start_addr && 883 psp->toc.size_bytes && 884 psp->fw_pri_buf) { 885 ret = psp_load_toc(psp, &tmr_size); 886 if (ret) { 887 dev_err(psp->adev->dev, "Failed to load toc\n"); 888 return ret; 889 } 890 } 891 892 if (!psp->tmr_bo && !psp->boot_time_tmr) { 893 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 894 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 895 PSP_TMR_ALIGNMENT, 896 AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM, 897 &psp->tmr_bo, &psp->tmr_mc_addr, 898 pptr); 899 } 900 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && psp->tmr_bo) 901 psp->tmr_mc_addr = amdgpu_bo_fb_aper_addr(psp->tmr_bo); 902 903 return ret; 904 } 905 906 static bool psp_skip_tmr(struct psp_context *psp) 907 { 908 u32 ip_version = amdgpu_ip_version(psp->adev, MP0_HWIP, 0); 909 910 if (amdgpu_sriov_vf(psp->adev)) 911 return (ip_version >= IP_VERSION(11, 0, 7)) ? true : false; 912 else 913 return (!psp->boot_time_tmr || !psp->autoload_supported) ? false : true; 914 } 915 916 static int psp_tmr_load(struct psp_context *psp) 917 { 918 int ret; 919 struct psp_gfx_cmd_resp *cmd; 920 921 if (psp_skip_tmr(psp)) 922 return 0; 923 924 cmd = acquire_psp_cmd_buf(psp); 925 926 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 927 if (psp->tmr_bo) 928 dev_info(psp->adev->dev, "reserve 0x%lx from 0x%llx for PSP TMR\n", 929 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 930 931 ret = psp_cmd_submit_buf(psp, NULL, cmd, 932 psp->fence_buf_mc_addr); 933 934 release_psp_cmd_buf(psp); 935 936 return ret; 937 } 938 939 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 940 struct psp_gfx_cmd_resp *cmd) 941 { 942 if (amdgpu_sriov_vf(psp->adev)) 943 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 944 else 945 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 946 } 947 948 static int psp_tmr_unload(struct psp_context *psp) 949 { 950 int ret; 951 struct psp_gfx_cmd_resp *cmd; 952 953 if (psp_skip_tmr(psp)) 954 return 0; 955 956 cmd = acquire_psp_cmd_buf(psp); 957 958 psp_prep_tmr_unload_cmd_buf(psp, cmd); 959 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 960 961 ret = psp_cmd_submit_buf(psp, NULL, cmd, 962 psp->fence_buf_mc_addr); 963 964 release_psp_cmd_buf(psp); 965 966 return ret; 967 } 968 969 static int psp_tmr_terminate(struct psp_context *psp) 970 { 971 return psp_tmr_unload(psp); 972 } 973 974 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 975 uint64_t *output_ptr) 976 { 977 int ret; 978 struct psp_gfx_cmd_resp *cmd; 979 980 if (!output_ptr) 981 return -EINVAL; 982 983 if (amdgpu_sriov_vf(psp->adev)) 984 return 0; 985 986 cmd = acquire_psp_cmd_buf(psp); 987 988 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 989 990 ret = psp_cmd_submit_buf(psp, NULL, cmd, 991 psp->fence_buf_mc_addr); 992 993 if (!ret) { 994 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 995 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 996 } 997 998 release_psp_cmd_buf(psp); 999 1000 return ret; 1001 } 1002 1003 static int psp_get_fw_reservation_info(struct psp_context *psp, 1004 uint32_t cmd_id, 1005 uint64_t *addr, 1006 uint32_t *size) 1007 { 1008 int ret; 1009 uint32_t status; 1010 struct psp_gfx_cmd_resp *cmd; 1011 1012 cmd = acquire_psp_cmd_buf(psp); 1013 1014 cmd->cmd_id = cmd_id; 1015 1016 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1017 psp->fence_buf_mc_addr); 1018 if (ret) { 1019 release_psp_cmd_buf(psp); 1020 return ret; 1021 } 1022 1023 status = cmd->resp.status; 1024 if (status == PSP_ERR_UNKNOWN_COMMAND) { 1025 release_psp_cmd_buf(psp); 1026 *addr = 0; 1027 *size = 0; 1028 return 0; 1029 } 1030 1031 *addr = (uint64_t)cmd->resp.uresp.fw_reserve_info.reserve_base_address_hi << 32 | 1032 cmd->resp.uresp.fw_reserve_info.reserve_base_address_lo; 1033 *size = cmd->resp.uresp.fw_reserve_info.reserve_size; 1034 1035 release_psp_cmd_buf(psp); 1036 1037 return 0; 1038 } 1039 1040 int psp_update_fw_reservation(struct psp_context *psp) 1041 { 1042 int ret; 1043 uint64_t reserv_addr, reserv_addr_ext; 1044 uint32_t reserv_size, reserv_size_ext, mp0_ip_ver; 1045 struct amdgpu_device *adev = psp->adev; 1046 1047 mp0_ip_ver = amdgpu_ip_version(adev, MP0_HWIP, 0); 1048 1049 if (amdgpu_sriov_vf(psp->adev)) 1050 return 0; 1051 1052 switch (mp0_ip_ver) { 1053 case IP_VERSION(14, 0, 2): 1054 if (adev->psp.sos.fw_version < 0x3b0e0d) 1055 return 0; 1056 break; 1057 1058 case IP_VERSION(14, 0, 3): 1059 if (adev->psp.sos.fw_version < 0x3a0e14) 1060 return 0; 1061 break; 1062 1063 default: 1064 return 0; 1065 } 1066 1067 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_ADDR, &reserv_addr, &reserv_size); 1068 if (ret) 1069 return ret; 1070 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR, &reserv_addr_ext, &reserv_size_ext); 1071 if (ret) 1072 return ret; 1073 1074 if (reserv_addr != adev->gmc.real_vram_size - reserv_size) { 1075 dev_warn(adev->dev, "reserve fw region is not valid!\n"); 1076 return 0; 1077 } 1078 1079 amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, NULL, NULL); 1080 1081 reserv_size = roundup(reserv_size, SZ_1M); 1082 1083 ret = amdgpu_bo_create_kernel_at(adev, reserv_addr, reserv_size, &adev->mman.fw_reserved_memory, NULL); 1084 if (ret) { 1085 dev_err(adev->dev, "reserve fw region failed(%d)!\n", ret); 1086 amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, NULL, NULL); 1087 return ret; 1088 } 1089 1090 reserv_size_ext = roundup(reserv_size_ext, SZ_1M); 1091 1092 ret = amdgpu_bo_create_kernel_at(adev, reserv_addr_ext, reserv_size_ext, 1093 &adev->mman.fw_reserved_memory_extend, NULL); 1094 if (ret) { 1095 dev_err(adev->dev, "reserve extend fw region failed(%d)!\n", ret); 1096 amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory_extend, NULL, NULL); 1097 return ret; 1098 } 1099 1100 return 0; 1101 } 1102 1103 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 1104 { 1105 struct psp_context *psp = &adev->psp; 1106 struct psp_gfx_cmd_resp *cmd; 1107 int ret; 1108 1109 if (amdgpu_sriov_vf(adev)) 1110 return 0; 1111 1112 cmd = acquire_psp_cmd_buf(psp); 1113 1114 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1115 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 1116 1117 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1118 if (!ret) { 1119 *boot_cfg = 1120 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 1121 } 1122 1123 release_psp_cmd_buf(psp); 1124 1125 return ret; 1126 } 1127 1128 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 1129 { 1130 int ret; 1131 struct psp_context *psp = &adev->psp; 1132 struct psp_gfx_cmd_resp *cmd; 1133 1134 if (amdgpu_sriov_vf(adev)) 1135 return 0; 1136 1137 cmd = acquire_psp_cmd_buf(psp); 1138 1139 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1140 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 1141 cmd->cmd.boot_cfg.boot_config = boot_cfg; 1142 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 1143 1144 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1145 1146 release_psp_cmd_buf(psp); 1147 1148 return ret; 1149 } 1150 1151 static int psp_rl_load(struct amdgpu_device *adev) 1152 { 1153 int ret; 1154 struct psp_context *psp = &adev->psp; 1155 struct psp_gfx_cmd_resp *cmd; 1156 1157 if (!is_psp_fw_valid(psp->rl)) 1158 return 0; 1159 1160 cmd = acquire_psp_cmd_buf(psp); 1161 1162 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1163 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 1164 1165 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1166 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 1167 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 1168 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 1169 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 1170 1171 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1172 1173 release_psp_cmd_buf(psp); 1174 1175 return ret; 1176 } 1177 1178 int psp_memory_partition(struct psp_context *psp, int mode) 1179 { 1180 struct psp_gfx_cmd_resp *cmd; 1181 int ret; 1182 1183 if (amdgpu_sriov_vf(psp->adev)) 1184 return 0; 1185 1186 cmd = acquire_psp_cmd_buf(psp); 1187 1188 cmd->cmd_id = GFX_CMD_ID_FB_NPS_MODE; 1189 cmd->cmd.cmd_memory_part.mode = mode; 1190 1191 dev_info(psp->adev->dev, 1192 "Requesting %d memory partition change through PSP", mode); 1193 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1194 if (ret) 1195 dev_err(psp->adev->dev, 1196 "PSP request failed to change to NPS%d mode\n", mode); 1197 1198 release_psp_cmd_buf(psp); 1199 1200 return ret; 1201 } 1202 1203 int psp_spatial_partition(struct psp_context *psp, int mode) 1204 { 1205 struct psp_gfx_cmd_resp *cmd; 1206 int ret; 1207 1208 if (amdgpu_sriov_vf(psp->adev)) 1209 return 0; 1210 1211 cmd = acquire_psp_cmd_buf(psp); 1212 1213 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART; 1214 cmd->cmd.cmd_spatial_part.mode = mode; 1215 1216 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode); 1217 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1218 1219 release_psp_cmd_buf(psp); 1220 1221 return ret; 1222 } 1223 1224 static int psp_asd_initialize(struct psp_context *psp) 1225 { 1226 int ret; 1227 1228 /* If PSP version doesn't match ASD version, asd loading will be failed. 1229 * add workaround to bypass it for sriov now. 1230 * TODO: add version check to make it common 1231 */ 1232 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 1233 return 0; 1234 1235 /* bypass asd if display hardware is not available */ 1236 if (!amdgpu_device_has_display_hardware(psp->adev) && 1237 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= IP_VERSION(13, 0, 10)) 1238 return 0; 1239 1240 psp->asd_context.mem_context.shared_mc_addr = 0; 1241 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 1242 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 1243 1244 ret = psp_ta_load(psp, &psp->asd_context); 1245 if (!ret) 1246 psp->asd_context.initialized = true; 1247 1248 return ret; 1249 } 1250 1251 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1252 uint32_t session_id) 1253 { 1254 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1255 cmd->cmd.cmd_unload_ta.session_id = session_id; 1256 } 1257 1258 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1259 { 1260 int ret; 1261 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1262 1263 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1264 1265 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1266 1267 context->resp_status = cmd->resp.status; 1268 1269 release_psp_cmd_buf(psp); 1270 1271 return ret; 1272 } 1273 1274 static int psp_asd_terminate(struct psp_context *psp) 1275 { 1276 int ret; 1277 1278 if (amdgpu_sriov_vf(psp->adev)) 1279 return 0; 1280 1281 if (!psp->asd_context.initialized) 1282 return 0; 1283 1284 ret = psp_ta_unload(psp, &psp->asd_context); 1285 if (!ret) 1286 psp->asd_context.initialized = false; 1287 1288 return ret; 1289 } 1290 1291 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1292 uint32_t id, uint32_t value) 1293 { 1294 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1295 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1296 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1297 } 1298 1299 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1300 uint32_t value) 1301 { 1302 struct psp_gfx_cmd_resp *cmd; 1303 int ret = 0; 1304 1305 if (reg >= PSP_REG_LAST) 1306 return -EINVAL; 1307 1308 cmd = acquire_psp_cmd_buf(psp); 1309 1310 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1311 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1312 if (ret) 1313 dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg); 1314 1315 release_psp_cmd_buf(psp); 1316 1317 return ret; 1318 } 1319 1320 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1321 uint64_t ta_bin_mc, 1322 struct ta_context *context) 1323 { 1324 cmd->cmd_id = context->ta_load_type; 1325 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1326 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1327 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1328 1329 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1330 lower_32_bits(context->mem_context.shared_mc_addr); 1331 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1332 upper_32_bits(context->mem_context.shared_mc_addr); 1333 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1334 } 1335 1336 int psp_ta_init_shared_buf(struct psp_context *psp, 1337 struct ta_mem_context *mem_ctx) 1338 { 1339 /* 1340 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1341 * physical) for ta to host memory 1342 */ 1343 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1344 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1345 AMDGPU_GEM_DOMAIN_GTT, 1346 &mem_ctx->shared_bo, 1347 &mem_ctx->shared_mc_addr, 1348 &mem_ctx->shared_buf); 1349 } 1350 1351 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1352 uint32_t ta_cmd_id, 1353 uint32_t session_id) 1354 { 1355 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1356 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1357 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1358 } 1359 1360 int psp_ta_invoke(struct psp_context *psp, 1361 uint32_t ta_cmd_id, 1362 struct ta_context *context) 1363 { 1364 int ret; 1365 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1366 1367 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1368 1369 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1370 psp->fence_buf_mc_addr); 1371 1372 context->resp_status = cmd->resp.status; 1373 1374 release_psp_cmd_buf(psp); 1375 1376 return ret; 1377 } 1378 1379 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1380 { 1381 int ret; 1382 struct psp_gfx_cmd_resp *cmd; 1383 1384 cmd = acquire_psp_cmd_buf(psp); 1385 1386 psp_copy_fw(psp, context->bin_desc.start_addr, 1387 context->bin_desc.size_bytes); 1388 1389 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && 1390 context->mem_context.shared_bo) 1391 context->mem_context.shared_mc_addr = 1392 amdgpu_bo_fb_aper_addr(context->mem_context.shared_bo); 1393 1394 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1395 1396 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1397 psp->fence_buf_mc_addr); 1398 1399 context->resp_status = cmd->resp.status; 1400 1401 if (!ret) 1402 context->session_id = cmd->resp.session_id; 1403 1404 release_psp_cmd_buf(psp); 1405 1406 return ret; 1407 } 1408 1409 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1410 { 1411 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1412 } 1413 1414 int psp_xgmi_terminate(struct psp_context *psp) 1415 { 1416 int ret; 1417 struct amdgpu_device *adev = psp->adev; 1418 1419 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1420 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 1421 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 1422 adev->gmc.xgmi.connected_to_cpu)) 1423 return 0; 1424 1425 if (!psp->xgmi_context.context.initialized) 1426 return 0; 1427 1428 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1429 1430 psp->xgmi_context.context.initialized = false; 1431 1432 return ret; 1433 } 1434 1435 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1436 { 1437 struct ta_xgmi_shared_memory *xgmi_cmd; 1438 int ret; 1439 1440 if (!psp->ta_fw || 1441 !psp->xgmi_context.context.bin_desc.size_bytes || 1442 !psp->xgmi_context.context.bin_desc.start_addr) 1443 return -ENOENT; 1444 1445 if (!load_ta) 1446 goto invoke; 1447 1448 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1449 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1450 1451 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1452 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1453 if (ret) 1454 return ret; 1455 } 1456 1457 /* Load XGMI TA */ 1458 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1459 if (!ret) 1460 psp->xgmi_context.context.initialized = true; 1461 else 1462 return ret; 1463 1464 invoke: 1465 /* Initialize XGMI session */ 1466 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1467 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1468 xgmi_cmd->flag_extend_link_record = set_extended_data; 1469 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1470 1471 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1472 /* note down the capbility flag for XGMI TA */ 1473 psp->xgmi_context.xgmi_ta_caps = xgmi_cmd->caps_flag; 1474 1475 return ret; 1476 } 1477 1478 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1479 { 1480 struct ta_xgmi_shared_memory *xgmi_cmd; 1481 int ret; 1482 1483 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1484 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1485 1486 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1487 1488 /* Invoke xgmi ta to get hive id */ 1489 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1490 if (ret) 1491 return ret; 1492 1493 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1494 1495 return 0; 1496 } 1497 1498 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1499 { 1500 struct ta_xgmi_shared_memory *xgmi_cmd; 1501 int ret; 1502 1503 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1504 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1505 1506 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1507 1508 /* Invoke xgmi ta to get the node id */ 1509 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1510 if (ret) 1511 return ret; 1512 1513 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1514 1515 return 0; 1516 } 1517 1518 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1519 { 1520 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1521 IP_VERSION(13, 0, 2) && 1522 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 1523 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= 1524 IP_VERSION(13, 0, 6); 1525 } 1526 1527 /* 1528 * Chips that support extended topology information require the driver to 1529 * reflect topology information in the opposite direction. This is 1530 * because the TA has already exceeded its link record limit and if the 1531 * TA holds bi-directional information, the driver would have to do 1532 * multiple fetches instead of just two. 1533 */ 1534 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1535 struct psp_xgmi_node_info node_info) 1536 { 1537 struct amdgpu_device *mirror_adev; 1538 struct amdgpu_hive_info *hive; 1539 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1540 uint64_t dst_node_id = node_info.node_id; 1541 uint8_t dst_num_hops = node_info.num_hops; 1542 uint8_t dst_is_sharing_enabled = node_info.is_sharing_enabled; 1543 uint8_t dst_num_links = node_info.num_links; 1544 1545 hive = amdgpu_get_xgmi_hive(psp->adev); 1546 if (WARN_ON(!hive)) 1547 return; 1548 1549 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1550 struct psp_xgmi_topology_info *mirror_top_info; 1551 int j; 1552 1553 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1554 continue; 1555 1556 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1557 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1558 if (mirror_top_info->nodes[j].node_id != src_node_id) 1559 continue; 1560 1561 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1562 mirror_top_info->nodes[j].is_sharing_enabled = dst_is_sharing_enabled; 1563 /* prevent 0 num_links value re-reflection since reflection 1564 * criteria is based on num_hops (direct or indirect). 1565 */ 1566 if (dst_num_links) { 1567 mirror_top_info->nodes[j].num_links = dst_num_links; 1568 /* swap src and dst due to frame of reference */ 1569 for (int k = 0; k < dst_num_links; k++) { 1570 mirror_top_info->nodes[j].port_num[k].src_xgmi_port_num = 1571 node_info.port_num[k].dst_xgmi_port_num; 1572 mirror_top_info->nodes[j].port_num[k].dst_xgmi_port_num = 1573 node_info.port_num[k].src_xgmi_port_num; 1574 } 1575 } 1576 1577 break; 1578 } 1579 1580 break; 1581 } 1582 1583 amdgpu_put_xgmi_hive(hive); 1584 } 1585 1586 int psp_xgmi_get_topology_info(struct psp_context *psp, 1587 int number_devices, 1588 struct psp_xgmi_topology_info *topology, 1589 bool get_extended_data) 1590 { 1591 struct ta_xgmi_shared_memory *xgmi_cmd; 1592 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1593 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1594 int i; 1595 int ret; 1596 1597 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1598 return -EINVAL; 1599 1600 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1601 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1602 xgmi_cmd->flag_extend_link_record = get_extended_data; 1603 1604 /* Fill in the shared memory with topology information as input */ 1605 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1606 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_TOPOLOGY_INFO; 1607 topology_info_input->num_nodes = number_devices; 1608 1609 for (i = 0; i < topology_info_input->num_nodes; i++) { 1610 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1611 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1612 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1613 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1614 } 1615 1616 /* Invoke xgmi ta to get the topology information */ 1617 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_TOPOLOGY_INFO); 1618 if (ret) 1619 return ret; 1620 1621 /* Read the output topology information from the shared memory */ 1622 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1623 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1624 for (i = 0; i < topology->num_nodes; i++) { 1625 /* extended data will either be 0 or equal to non-extended data */ 1626 if (topology_info_output->nodes[i].num_hops) 1627 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1628 1629 /* non-extended data gets everything here so no need to update */ 1630 if (!get_extended_data) { 1631 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1632 topology->nodes[i].is_sharing_enabled = 1633 topology_info_output->nodes[i].is_sharing_enabled; 1634 topology->nodes[i].sdma_engine = 1635 topology_info_output->nodes[i].sdma_engine; 1636 } 1637 1638 } 1639 1640 /* Invoke xgmi ta again to get the link information */ 1641 if (psp_xgmi_peer_link_info_supported(psp)) { 1642 struct ta_xgmi_cmd_get_peer_link_info *link_info_output; 1643 struct ta_xgmi_cmd_get_extend_peer_link_info *link_extend_info_output; 1644 bool requires_reflection = 1645 (psp->xgmi_context.supports_extended_data && 1646 get_extended_data) || 1647 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1648 IP_VERSION(13, 0, 6) || 1649 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1650 IP_VERSION(13, 0, 14) || 1651 amdgpu_sriov_vf(psp->adev); 1652 bool ta_port_num_support = psp->xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG || 1653 amdgpu_sriov_xgmi_ta_ext_peer_link_en(psp->adev); 1654 1655 /* popluate the shared output buffer rather than the cmd input buffer 1656 * with node_ids as the input for GET_PEER_LINKS command execution. 1657 * This is required for GET_PEER_LINKS per xgmi ta implementation. 1658 * The same requirement for GET_EXTEND_PEER_LINKS command. 1659 */ 1660 if (ta_port_num_support) { 1661 link_extend_info_output = &xgmi_cmd->xgmi_out_message.get_extend_link_info; 1662 1663 for (i = 0; i < topology->num_nodes; i++) 1664 link_extend_info_output->nodes[i].node_id = topology->nodes[i].node_id; 1665 1666 link_extend_info_output->num_nodes = topology->num_nodes; 1667 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS; 1668 } else { 1669 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1670 1671 for (i = 0; i < topology->num_nodes; i++) 1672 link_info_output->nodes[i].node_id = topology->nodes[i].node_id; 1673 1674 link_info_output->num_nodes = topology->num_nodes; 1675 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1676 } 1677 1678 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1679 if (ret) 1680 return ret; 1681 1682 for (i = 0; i < topology->num_nodes; i++) { 1683 uint8_t node_num_links = ta_port_num_support ? 1684 link_extend_info_output->nodes[i].num_links : link_info_output->nodes[i].num_links; 1685 /* accumulate num_links on extended data */ 1686 if (get_extended_data) { 1687 topology->nodes[i].num_links = topology->nodes[i].num_links + node_num_links; 1688 } else { 1689 topology->nodes[i].num_links = (requires_reflection && topology->nodes[i].num_links) ? 1690 topology->nodes[i].num_links : node_num_links; 1691 } 1692 /* popluate the connected port num info if supported and available */ 1693 if (ta_port_num_support && topology->nodes[i].num_links) { 1694 memcpy(topology->nodes[i].port_num, link_extend_info_output->nodes[i].port_num, 1695 sizeof(struct xgmi_connected_port_num) * TA_XGMI__MAX_PORT_NUM); 1696 } 1697 1698 /* reflect the topology information for bi-directionality */ 1699 if (requires_reflection && topology->nodes[i].num_hops) 1700 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1701 } 1702 } 1703 1704 return 0; 1705 } 1706 1707 int psp_xgmi_set_topology_info(struct psp_context *psp, 1708 int number_devices, 1709 struct psp_xgmi_topology_info *topology) 1710 { 1711 struct ta_xgmi_shared_memory *xgmi_cmd; 1712 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1713 int i; 1714 1715 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1716 return -EINVAL; 1717 1718 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1719 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1720 1721 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1722 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1723 topology_info_input->num_nodes = number_devices; 1724 1725 for (i = 0; i < topology_info_input->num_nodes; i++) { 1726 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1727 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1728 topology_info_input->nodes[i].is_sharing_enabled = 1; 1729 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1730 } 1731 1732 /* Invoke xgmi ta to set topology information */ 1733 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1734 } 1735 1736 // ras begin 1737 static void psp_ras_ta_check_status(struct psp_context *psp) 1738 { 1739 struct ta_ras_shared_memory *ras_cmd = 1740 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1741 1742 switch (ras_cmd->ras_status) { 1743 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1744 dev_warn(psp->adev->dev, 1745 "RAS WARNING: cmd failed due to unsupported ip\n"); 1746 break; 1747 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1748 dev_warn(psp->adev->dev, 1749 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1750 break; 1751 case TA_RAS_STATUS__SUCCESS: 1752 break; 1753 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1754 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1755 dev_warn(psp->adev->dev, 1756 "RAS WARNING: Inject error to critical region is not allowed\n"); 1757 break; 1758 default: 1759 dev_warn(psp->adev->dev, 1760 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1761 break; 1762 } 1763 } 1764 1765 static int psp_ras_send_cmd(struct psp_context *psp, 1766 enum ras_command cmd_id, void *in, void *out) 1767 { 1768 struct ta_ras_shared_memory *ras_cmd; 1769 uint32_t cmd = cmd_id; 1770 int ret = 0; 1771 1772 if (!in) 1773 return -EINVAL; 1774 1775 mutex_lock(&psp->ras_context.mutex); 1776 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1777 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1778 1779 switch (cmd) { 1780 case TA_RAS_COMMAND__ENABLE_FEATURES: 1781 case TA_RAS_COMMAND__DISABLE_FEATURES: 1782 memcpy(&ras_cmd->ras_in_message, 1783 in, sizeof(ras_cmd->ras_in_message)); 1784 break; 1785 case TA_RAS_COMMAND__TRIGGER_ERROR: 1786 memcpy(&ras_cmd->ras_in_message.trigger_error, 1787 in, sizeof(ras_cmd->ras_in_message.trigger_error)); 1788 break; 1789 case TA_RAS_COMMAND__QUERY_ADDRESS: 1790 memcpy(&ras_cmd->ras_in_message.address, 1791 in, sizeof(ras_cmd->ras_in_message.address)); 1792 break; 1793 default: 1794 dev_err(psp->adev->dev, "Invalid ras cmd id: %u\n", cmd); 1795 ret = -EINVAL; 1796 goto err_out; 1797 } 1798 1799 ras_cmd->cmd_id = cmd; 1800 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1801 1802 switch (cmd) { 1803 case TA_RAS_COMMAND__TRIGGER_ERROR: 1804 if (!ret && out) 1805 memcpy(out, &ras_cmd->ras_status, sizeof(ras_cmd->ras_status)); 1806 break; 1807 case TA_RAS_COMMAND__QUERY_ADDRESS: 1808 if (ret || ras_cmd->ras_status || psp->cmd_buf_mem->resp.status) 1809 ret = -EINVAL; 1810 else if (out) 1811 memcpy(out, 1812 &ras_cmd->ras_out_message.address, 1813 sizeof(ras_cmd->ras_out_message.address)); 1814 break; 1815 default: 1816 break; 1817 } 1818 1819 err_out: 1820 mutex_unlock(&psp->ras_context.mutex); 1821 1822 return ret; 1823 } 1824 1825 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1826 { 1827 struct ta_ras_shared_memory *ras_cmd; 1828 int ret; 1829 1830 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1831 1832 /* 1833 * TODO: bypass the loading in sriov for now 1834 */ 1835 if (amdgpu_sriov_vf(psp->adev)) 1836 return 0; 1837 1838 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1839 1840 if (amdgpu_ras_intr_triggered()) 1841 return ret; 1842 1843 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 1844 dev_warn(psp->adev->dev, "RAS: Unsupported Interface\n"); 1845 return -EINVAL; 1846 } 1847 1848 if (!ret) { 1849 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1850 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1851 1852 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1853 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1854 dev_warn(psp->adev->dev, 1855 "RAS internal register access blocked\n"); 1856 1857 psp_ras_ta_check_status(psp); 1858 } 1859 1860 return ret; 1861 } 1862 1863 int psp_ras_enable_features(struct psp_context *psp, 1864 union ta_ras_cmd_input *info, bool enable) 1865 { 1866 enum ras_command cmd_id; 1867 int ret; 1868 1869 if (!psp->ras_context.context.initialized || !info) 1870 return -EINVAL; 1871 1872 cmd_id = enable ? 1873 TA_RAS_COMMAND__ENABLE_FEATURES : TA_RAS_COMMAND__DISABLE_FEATURES; 1874 ret = psp_ras_send_cmd(psp, cmd_id, info, NULL); 1875 if (ret) 1876 return -EINVAL; 1877 1878 return 0; 1879 } 1880 1881 int psp_ras_terminate(struct psp_context *psp) 1882 { 1883 int ret; 1884 1885 /* 1886 * TODO: bypass the terminate in sriov for now 1887 */ 1888 if (amdgpu_sriov_vf(psp->adev)) 1889 return 0; 1890 1891 if (!psp->ras_context.context.initialized) 1892 return 0; 1893 1894 ret = psp_ta_unload(psp, &psp->ras_context.context); 1895 1896 psp->ras_context.context.initialized = false; 1897 1898 mutex_destroy(&psp->ras_context.mutex); 1899 1900 return ret; 1901 } 1902 1903 int psp_ras_initialize(struct psp_context *psp) 1904 { 1905 int ret; 1906 uint32_t boot_cfg = 0xFF; 1907 struct amdgpu_device *adev = psp->adev; 1908 struct ta_ras_shared_memory *ras_cmd; 1909 1910 /* 1911 * TODO: bypass the initialize in sriov for now 1912 */ 1913 if (amdgpu_sriov_vf(adev)) 1914 return 0; 1915 1916 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1917 !adev->psp.ras_context.context.bin_desc.start_addr) { 1918 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1919 return 0; 1920 } 1921 1922 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1923 /* query GECC enablement status from boot config 1924 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1925 */ 1926 ret = psp_boot_config_get(adev, &boot_cfg); 1927 if (ret) 1928 dev_warn(adev->dev, "PSP get boot config failed\n"); 1929 1930 if (boot_cfg == 1 && !adev->ras_default_ecc_enabled && 1931 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 1932 dev_warn(adev->dev, "GECC is currently enabled, which may affect performance\n"); 1933 dev_warn(adev->dev, 1934 "To disable GECC, please reboot the system and load the amdgpu driver with the parameter amdgpu_ras_enable=0\n"); 1935 } else { 1936 if ((adev->ras_default_ecc_enabled || amdgpu_ras_enable == 1) && 1937 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 1938 if (boot_cfg == 1) { 1939 dev_info(adev->dev, "GECC is enabled\n"); 1940 } else { 1941 /* enable GECC in next boot cycle if it is disabled 1942 * in boot config, or force enable GECC if failed to 1943 * get boot configuration 1944 */ 1945 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1946 if (ret) 1947 dev_warn(adev->dev, "PSP set boot config failed\n"); 1948 else 1949 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1950 } 1951 } else { 1952 if (!boot_cfg) { 1953 if (!adev->ras_default_ecc_enabled && 1954 amdgpu_ras_enable != 1 && 1955 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 1956 dev_warn(adev->dev, "GECC is disabled, set amdgpu_ras_enable=1 to enable GECC in next boot cycle if needed\n"); 1957 else 1958 dev_info(adev->dev, "GECC is disabled\n"); 1959 } else { 1960 /* disable GECC in next boot cycle if ras is 1961 * disabled by module parameter amdgpu_ras_enable 1962 * and/or amdgpu_ras_mask, or boot_config_get call 1963 * is failed 1964 */ 1965 ret = psp_boot_config_set(adev, 0); 1966 if (ret) 1967 dev_warn(adev->dev, "PSP set boot config failed\n"); 1968 else 1969 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1970 } 1971 } 1972 } 1973 } 1974 1975 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1976 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1977 1978 if (!psp->ras_context.context.mem_context.shared_buf) { 1979 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1980 if (ret) 1981 return ret; 1982 } 1983 1984 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1985 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1986 1987 if (amdgpu_ras_is_poison_mode_supported(adev)) 1988 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1989 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1990 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1991 ras_cmd->ras_in_message.init_flags.xcc_mask = 1992 adev->gfx.xcc_mask; 1993 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 1994 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 1995 ras_cmd->ras_in_message.init_flags.nps_mode = 1996 adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 1997 ras_cmd->ras_in_message.init_flags.active_umc_mask = adev->umc.active_mask; 1998 ras_cmd->ras_in_message.init_flags.vram_type = (uint8_t)adev->gmc.vram_type; 1999 2000 ret = psp_ta_load(psp, &psp->ras_context.context); 2001 2002 if (!ret && !ras_cmd->ras_status) { 2003 psp->ras_context.context.initialized = true; 2004 mutex_init(&psp->ras_context.mutex); 2005 } else { 2006 if (ras_cmd->ras_status) 2007 dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 2008 2009 /* fail to load RAS TA */ 2010 psp->ras_context.context.initialized = false; 2011 } 2012 2013 return ret; 2014 } 2015 2016 int psp_ras_trigger_error(struct psp_context *psp, 2017 struct ta_ras_trigger_error_input *info, uint32_t instance_mask) 2018 { 2019 struct amdgpu_device *adev = psp->adev; 2020 int ret; 2021 uint32_t dev_mask; 2022 uint32_t ras_status = 0; 2023 2024 if (!psp->ras_context.context.initialized || !info) 2025 return -EINVAL; 2026 2027 switch (info->block_id) { 2028 case TA_RAS_BLOCK__GFX: 2029 dev_mask = GET_MASK(GC, instance_mask); 2030 break; 2031 case TA_RAS_BLOCK__SDMA: 2032 dev_mask = GET_MASK(SDMA0, instance_mask); 2033 break; 2034 case TA_RAS_BLOCK__VCN: 2035 case TA_RAS_BLOCK__JPEG: 2036 dev_mask = GET_MASK(VCN, instance_mask); 2037 break; 2038 default: 2039 dev_mask = instance_mask; 2040 break; 2041 } 2042 2043 /* reuse sub_block_index for backward compatibility */ 2044 dev_mask <<= AMDGPU_RAS_INST_SHIFT; 2045 dev_mask &= AMDGPU_RAS_INST_MASK; 2046 info->sub_block_index |= dev_mask; 2047 2048 ret = psp_ras_send_cmd(psp, 2049 TA_RAS_COMMAND__TRIGGER_ERROR, info, &ras_status); 2050 if (ret) 2051 return -EINVAL; 2052 2053 /* If err_event_athub occurs error inject was successful, however 2054 * return status from TA is no long reliable 2055 */ 2056 if (amdgpu_ras_intr_triggered()) 2057 return 0; 2058 2059 if (ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 2060 return -EACCES; 2061 else if (ras_status) 2062 return -EINVAL; 2063 2064 return 0; 2065 } 2066 2067 int psp_ras_query_address(struct psp_context *psp, 2068 struct ta_ras_query_address_input *addr_in, 2069 struct ta_ras_query_address_output *addr_out) 2070 { 2071 int ret; 2072 2073 if (!psp->ras_context.context.initialized || 2074 !addr_in || !addr_out) 2075 return -EINVAL; 2076 2077 ret = psp_ras_send_cmd(psp, 2078 TA_RAS_COMMAND__QUERY_ADDRESS, addr_in, addr_out); 2079 2080 return ret; 2081 } 2082 // ras end 2083 2084 // HDCP start 2085 static int psp_hdcp_initialize(struct psp_context *psp) 2086 { 2087 int ret; 2088 2089 /* 2090 * TODO: bypass the initialize in sriov for now 2091 */ 2092 if (amdgpu_sriov_vf(psp->adev)) 2093 return 0; 2094 2095 /* bypass hdcp initialization if dmu is harvested */ 2096 if (!amdgpu_device_has_display_hardware(psp->adev)) 2097 return 0; 2098 2099 if (!psp->hdcp_context.context.bin_desc.size_bytes || 2100 !psp->hdcp_context.context.bin_desc.start_addr) { 2101 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 2102 return 0; 2103 } 2104 2105 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 2106 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2107 2108 if (!psp->hdcp_context.context.mem_context.shared_buf) { 2109 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 2110 if (ret) 2111 return ret; 2112 } 2113 2114 ret = psp_ta_load(psp, &psp->hdcp_context.context); 2115 if (!ret) { 2116 psp->hdcp_context.context.initialized = true; 2117 mutex_init(&psp->hdcp_context.mutex); 2118 } 2119 2120 return ret; 2121 } 2122 2123 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2124 { 2125 /* 2126 * TODO: bypass the loading in sriov for now 2127 */ 2128 if (amdgpu_sriov_vf(psp->adev)) 2129 return 0; 2130 2131 if (!psp->hdcp_context.context.initialized) 2132 return 0; 2133 2134 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 2135 } 2136 2137 static int psp_hdcp_terminate(struct psp_context *psp) 2138 { 2139 int ret; 2140 2141 /* 2142 * TODO: bypass the terminate in sriov for now 2143 */ 2144 if (amdgpu_sriov_vf(psp->adev)) 2145 return 0; 2146 2147 if (!psp->hdcp_context.context.initialized) 2148 return 0; 2149 2150 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 2151 2152 psp->hdcp_context.context.initialized = false; 2153 2154 return ret; 2155 } 2156 // HDCP end 2157 2158 // DTM start 2159 static int psp_dtm_initialize(struct psp_context *psp) 2160 { 2161 int ret; 2162 2163 /* 2164 * TODO: bypass the initialize in sriov for now 2165 */ 2166 if (amdgpu_sriov_vf(psp->adev)) 2167 return 0; 2168 2169 /* bypass dtm initialization if dmu is harvested */ 2170 if (!amdgpu_device_has_display_hardware(psp->adev)) 2171 return 0; 2172 2173 if (!psp->dtm_context.context.bin_desc.size_bytes || 2174 !psp->dtm_context.context.bin_desc.start_addr) { 2175 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 2176 return 0; 2177 } 2178 2179 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 2180 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2181 2182 if (!psp->dtm_context.context.mem_context.shared_buf) { 2183 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 2184 if (ret) 2185 return ret; 2186 } 2187 2188 ret = psp_ta_load(psp, &psp->dtm_context.context); 2189 if (!ret) { 2190 psp->dtm_context.context.initialized = true; 2191 mutex_init(&psp->dtm_context.mutex); 2192 } 2193 2194 return ret; 2195 } 2196 2197 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2198 { 2199 /* 2200 * TODO: bypass the loading in sriov for now 2201 */ 2202 if (amdgpu_sriov_vf(psp->adev)) 2203 return 0; 2204 2205 if (!psp->dtm_context.context.initialized) 2206 return 0; 2207 2208 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 2209 } 2210 2211 static int psp_dtm_terminate(struct psp_context *psp) 2212 { 2213 int ret; 2214 2215 /* 2216 * TODO: bypass the terminate in sriov for now 2217 */ 2218 if (amdgpu_sriov_vf(psp->adev)) 2219 return 0; 2220 2221 if (!psp->dtm_context.context.initialized) 2222 return 0; 2223 2224 ret = psp_ta_unload(psp, &psp->dtm_context.context); 2225 2226 psp->dtm_context.context.initialized = false; 2227 2228 return ret; 2229 } 2230 // DTM end 2231 2232 // RAP start 2233 static int psp_rap_initialize(struct psp_context *psp) 2234 { 2235 int ret; 2236 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 2237 2238 /* 2239 * TODO: bypass the initialize in sriov for now 2240 */ 2241 if (amdgpu_sriov_vf(psp->adev)) 2242 return 0; 2243 2244 if (!psp->rap_context.context.bin_desc.size_bytes || 2245 !psp->rap_context.context.bin_desc.start_addr) { 2246 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 2247 return 0; 2248 } 2249 2250 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 2251 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2252 2253 if (!psp->rap_context.context.mem_context.shared_buf) { 2254 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 2255 if (ret) 2256 return ret; 2257 } 2258 2259 ret = psp_ta_load(psp, &psp->rap_context.context); 2260 if (!ret) { 2261 psp->rap_context.context.initialized = true; 2262 mutex_init(&psp->rap_context.mutex); 2263 } else 2264 return ret; 2265 2266 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 2267 if (ret || status != TA_RAP_STATUS__SUCCESS) { 2268 psp_rap_terminate(psp); 2269 /* free rap shared memory */ 2270 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 2271 2272 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 2273 ret, status); 2274 2275 return ret; 2276 } 2277 2278 return 0; 2279 } 2280 2281 static int psp_rap_terminate(struct psp_context *psp) 2282 { 2283 int ret; 2284 2285 if (!psp->rap_context.context.initialized) 2286 return 0; 2287 2288 ret = psp_ta_unload(psp, &psp->rap_context.context); 2289 2290 psp->rap_context.context.initialized = false; 2291 2292 return ret; 2293 } 2294 2295 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 2296 { 2297 struct ta_rap_shared_memory *rap_cmd; 2298 int ret = 0; 2299 2300 if (!psp->rap_context.context.initialized) 2301 return 0; 2302 2303 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 2304 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 2305 return -EINVAL; 2306 2307 mutex_lock(&psp->rap_context.mutex); 2308 2309 rap_cmd = (struct ta_rap_shared_memory *) 2310 psp->rap_context.context.mem_context.shared_buf; 2311 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 2312 2313 rap_cmd->cmd_id = ta_cmd_id; 2314 rap_cmd->validation_method_id = METHOD_A; 2315 2316 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 2317 if (ret) 2318 goto out_unlock; 2319 2320 if (status) 2321 *status = rap_cmd->rap_status; 2322 2323 out_unlock: 2324 mutex_unlock(&psp->rap_context.mutex); 2325 2326 return ret; 2327 } 2328 // RAP end 2329 2330 /* securedisplay start */ 2331 static int psp_securedisplay_initialize(struct psp_context *psp) 2332 { 2333 int ret; 2334 struct ta_securedisplay_cmd *securedisplay_cmd; 2335 2336 /* 2337 * TODO: bypass the initialize in sriov for now 2338 */ 2339 if (amdgpu_sriov_vf(psp->adev)) 2340 return 0; 2341 2342 /* bypass securedisplay initialization if dmu is harvested */ 2343 if (!amdgpu_device_has_display_hardware(psp->adev)) 2344 return 0; 2345 2346 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 2347 !psp->securedisplay_context.context.bin_desc.start_addr) { 2348 dev_info(psp->adev->dev, 2349 "SECUREDISPLAY: optional securedisplay ta ucode is not available\n"); 2350 return 0; 2351 } 2352 2353 psp->securedisplay_context.context.mem_context.shared_mem_size = 2354 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 2355 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2356 2357 if (!psp->securedisplay_context.context.initialized) { 2358 ret = psp_ta_init_shared_buf(psp, 2359 &psp->securedisplay_context.context.mem_context); 2360 if (ret) 2361 return ret; 2362 } 2363 2364 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 2365 if (!ret && !psp->securedisplay_context.context.resp_status) { 2366 psp->securedisplay_context.context.initialized = true; 2367 mutex_init(&psp->securedisplay_context.mutex); 2368 } else { 2369 /* don't try again */ 2370 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2371 return ret; 2372 } 2373 2374 mutex_lock(&psp->securedisplay_context.mutex); 2375 2376 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2377 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2378 2379 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2380 2381 mutex_unlock(&psp->securedisplay_context.mutex); 2382 2383 if (ret) { 2384 psp_securedisplay_terminate(psp); 2385 /* free securedisplay shared memory */ 2386 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2387 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2388 return -EINVAL; 2389 } 2390 2391 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2392 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2393 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2394 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2395 /* don't try again */ 2396 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2397 } 2398 2399 return 0; 2400 } 2401 2402 static int psp_securedisplay_terminate(struct psp_context *psp) 2403 { 2404 int ret; 2405 2406 /* 2407 * TODO:bypass the terminate in sriov for now 2408 */ 2409 if (amdgpu_sriov_vf(psp->adev)) 2410 return 0; 2411 2412 if (!psp->securedisplay_context.context.initialized) 2413 return 0; 2414 2415 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 2416 2417 psp->securedisplay_context.context.initialized = false; 2418 2419 return ret; 2420 } 2421 2422 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2423 { 2424 int ret; 2425 2426 if (!psp->securedisplay_context.context.initialized) 2427 return -EINVAL; 2428 2429 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2430 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC && 2431 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC_V2) 2432 return -EINVAL; 2433 2434 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2435 2436 return ret; 2437 } 2438 /* SECUREDISPLAY end */ 2439 2440 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev) 2441 { 2442 struct psp_context *psp = &adev->psp; 2443 int ret = 0; 2444 2445 if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL) 2446 ret = psp->funcs->wait_for_bootloader(psp); 2447 2448 return ret; 2449 } 2450 2451 bool amdgpu_psp_get_ras_capability(struct psp_context *psp) 2452 { 2453 if (psp->funcs && 2454 psp->funcs->get_ras_capability) { 2455 return psp->funcs->get_ras_capability(psp); 2456 } else { 2457 return false; 2458 } 2459 } 2460 2461 bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev) 2462 { 2463 struct psp_context *psp = &adev->psp; 2464 2465 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) 2466 return false; 2467 2468 if (psp->funcs && psp->funcs->is_reload_needed) 2469 return psp->funcs->is_reload_needed(psp); 2470 2471 return false; 2472 } 2473 2474 static void psp_update_gpu_addresses(struct amdgpu_device *adev) 2475 { 2476 struct psp_context *psp = &adev->psp; 2477 2478 if (psp->cmd_buf_bo && psp->cmd_buf_mem) { 2479 psp->fw_pri_mc_addr = amdgpu_bo_fb_aper_addr(psp->fw_pri_bo); 2480 psp->fence_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->fence_buf_bo); 2481 psp->cmd_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->cmd_buf_bo); 2482 } 2483 if (adev->firmware.rbuf && psp->km_ring.ring_mem) 2484 psp->km_ring.ring_mem_mc_addr = amdgpu_bo_fb_aper_addr(adev->firmware.rbuf); 2485 } 2486 2487 static int psp_hw_start(struct psp_context *psp) 2488 { 2489 struct amdgpu_device *adev = psp->adev; 2490 int ret; 2491 2492 if (amdgpu_virt_xgmi_migrate_enabled(adev)) 2493 psp_update_gpu_addresses(adev); 2494 2495 if (!amdgpu_sriov_vf(adev)) { 2496 if ((is_psp_fw_valid(psp->kdb)) && 2497 (psp->funcs->bootloader_load_kdb != NULL)) { 2498 ret = psp_bootloader_load_kdb(psp); 2499 if (ret) { 2500 dev_err(adev->dev, "PSP load kdb failed!\n"); 2501 return ret; 2502 } 2503 } 2504 2505 if ((is_psp_fw_valid(psp->spl)) && 2506 (psp->funcs->bootloader_load_spl != NULL)) { 2507 ret = psp_bootloader_load_spl(psp); 2508 if (ret) { 2509 dev_err(adev->dev, "PSP load spl failed!\n"); 2510 return ret; 2511 } 2512 } 2513 2514 if ((is_psp_fw_valid(psp->sys)) && 2515 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2516 ret = psp_bootloader_load_sysdrv(psp); 2517 if (ret) { 2518 dev_err(adev->dev, "PSP load sys drv failed!\n"); 2519 return ret; 2520 } 2521 } 2522 2523 if ((is_psp_fw_valid(psp->soc_drv)) && 2524 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2525 ret = psp_bootloader_load_soc_drv(psp); 2526 if (ret) { 2527 dev_err(adev->dev, "PSP load soc drv failed!\n"); 2528 return ret; 2529 } 2530 } 2531 2532 if ((is_psp_fw_valid(psp->intf_drv)) && 2533 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2534 ret = psp_bootloader_load_intf_drv(psp); 2535 if (ret) { 2536 dev_err(adev->dev, "PSP load intf drv failed!\n"); 2537 return ret; 2538 } 2539 } 2540 2541 if ((is_psp_fw_valid(psp->dbg_drv)) && 2542 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2543 ret = psp_bootloader_load_dbg_drv(psp); 2544 if (ret) { 2545 dev_err(adev->dev, "PSP load dbg drv failed!\n"); 2546 return ret; 2547 } 2548 } 2549 2550 if ((is_psp_fw_valid(psp->ras_drv)) && 2551 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2552 ret = psp_bootloader_load_ras_drv(psp); 2553 if (ret) { 2554 dev_err(adev->dev, "PSP load ras_drv failed!\n"); 2555 return ret; 2556 } 2557 } 2558 2559 if ((is_psp_fw_valid(psp->ipkeymgr_drv)) && 2560 (psp->funcs->bootloader_load_ipkeymgr_drv != NULL)) { 2561 ret = psp_bootloader_load_ipkeymgr_drv(psp); 2562 if (ret) { 2563 dev_err(adev->dev, "PSP load ipkeymgr_drv failed!\n"); 2564 return ret; 2565 } 2566 } 2567 2568 if ((is_psp_fw_valid(psp->spdm_drv)) && 2569 (psp->funcs->bootloader_load_spdm_drv != NULL)) { 2570 ret = psp_bootloader_load_spdm_drv(psp); 2571 if (ret) { 2572 dev_err(adev->dev, "PSP load spdm_drv failed!\n"); 2573 return ret; 2574 } 2575 } 2576 2577 if ((is_psp_fw_valid(psp->sos)) && 2578 (psp->funcs->bootloader_load_sos != NULL)) { 2579 ret = psp_bootloader_load_sos(psp); 2580 if (ret) { 2581 dev_err(adev->dev, "PSP load sos failed!\n"); 2582 return ret; 2583 } 2584 } 2585 } 2586 2587 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2588 if (ret) { 2589 dev_err(adev->dev, "PSP create ring failed!\n"); 2590 return ret; 2591 } 2592 2593 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2594 ret = psp_update_fw_reservation(psp); 2595 if (ret) { 2596 dev_err(adev->dev, "update fw reservation failed!\n"); 2597 return ret; 2598 } 2599 } 2600 2601 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2602 goto skip_pin_bo; 2603 2604 if (!psp->boot_time_tmr || psp->autoload_supported) { 2605 ret = psp_tmr_init(psp); 2606 if (ret) { 2607 dev_err(adev->dev, "PSP tmr init failed!\n"); 2608 return ret; 2609 } 2610 } 2611 2612 skip_pin_bo: 2613 /* 2614 * For ASICs with DF Cstate management centralized 2615 * to PMFW, TMR setup should be performed after PMFW 2616 * loaded and before other non-psp firmware loaded. 2617 */ 2618 if (psp->pmfw_centralized_cstate_management) { 2619 ret = psp_load_smu_fw(psp); 2620 if (ret) 2621 return ret; 2622 } 2623 2624 ret = psp_tmr_load(psp); 2625 if (ret) { 2626 dev_err(adev->dev, "PSP load tmr failed!\n"); 2627 return ret; 2628 } 2629 2630 return 0; 2631 } 2632 2633 int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2634 enum psp_gfx_fw_type *type) 2635 { 2636 switch (ucode->ucode_id) { 2637 case AMDGPU_UCODE_ID_CAP: 2638 *type = GFX_FW_TYPE_CAP; 2639 break; 2640 case AMDGPU_UCODE_ID_SDMA0: 2641 *type = GFX_FW_TYPE_SDMA0; 2642 break; 2643 case AMDGPU_UCODE_ID_SDMA1: 2644 *type = GFX_FW_TYPE_SDMA1; 2645 break; 2646 case AMDGPU_UCODE_ID_SDMA2: 2647 *type = GFX_FW_TYPE_SDMA2; 2648 break; 2649 case AMDGPU_UCODE_ID_SDMA3: 2650 *type = GFX_FW_TYPE_SDMA3; 2651 break; 2652 case AMDGPU_UCODE_ID_SDMA4: 2653 *type = GFX_FW_TYPE_SDMA4; 2654 break; 2655 case AMDGPU_UCODE_ID_SDMA5: 2656 *type = GFX_FW_TYPE_SDMA5; 2657 break; 2658 case AMDGPU_UCODE_ID_SDMA6: 2659 *type = GFX_FW_TYPE_SDMA6; 2660 break; 2661 case AMDGPU_UCODE_ID_SDMA7: 2662 *type = GFX_FW_TYPE_SDMA7; 2663 break; 2664 case AMDGPU_UCODE_ID_CP_MES: 2665 *type = GFX_FW_TYPE_CP_MES; 2666 break; 2667 case AMDGPU_UCODE_ID_CP_MES_DATA: 2668 *type = GFX_FW_TYPE_MES_STACK; 2669 break; 2670 case AMDGPU_UCODE_ID_CP_MES1: 2671 *type = GFX_FW_TYPE_CP_MES_KIQ; 2672 break; 2673 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2674 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2675 break; 2676 case AMDGPU_UCODE_ID_CP_CE: 2677 *type = GFX_FW_TYPE_CP_CE; 2678 break; 2679 case AMDGPU_UCODE_ID_CP_PFP: 2680 *type = GFX_FW_TYPE_CP_PFP; 2681 break; 2682 case AMDGPU_UCODE_ID_CP_ME: 2683 *type = GFX_FW_TYPE_CP_ME; 2684 break; 2685 case AMDGPU_UCODE_ID_CP_MEC1: 2686 *type = GFX_FW_TYPE_CP_MEC; 2687 break; 2688 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2689 *type = GFX_FW_TYPE_CP_MEC_ME1; 2690 break; 2691 case AMDGPU_UCODE_ID_CP_MEC2: 2692 *type = GFX_FW_TYPE_CP_MEC; 2693 break; 2694 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2695 *type = GFX_FW_TYPE_CP_MEC_ME2; 2696 break; 2697 case AMDGPU_UCODE_ID_RLC_P: 2698 *type = GFX_FW_TYPE_RLC_P; 2699 break; 2700 case AMDGPU_UCODE_ID_RLC_V: 2701 *type = GFX_FW_TYPE_RLC_V; 2702 break; 2703 case AMDGPU_UCODE_ID_RLC_G: 2704 *type = GFX_FW_TYPE_RLC_G; 2705 break; 2706 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2707 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2708 break; 2709 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2710 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2711 break; 2712 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2713 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2714 break; 2715 case AMDGPU_UCODE_ID_RLC_IRAM: 2716 *type = GFX_FW_TYPE_RLC_IRAM; 2717 break; 2718 case AMDGPU_UCODE_ID_RLC_DRAM: 2719 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2720 break; 2721 case AMDGPU_UCODE_ID_RLC_IRAM_1: 2722 *type = GFX_FW_TYPE_RLX6_UCODE_CORE1; 2723 break; 2724 case AMDGPU_UCODE_ID_RLC_DRAM_1: 2725 *type = GFX_FW_TYPE_RLX6_DRAM_BOOT_CORE1; 2726 break; 2727 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2728 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2729 break; 2730 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2731 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2732 break; 2733 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2734 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2735 break; 2736 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2737 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2738 break; 2739 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2740 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2741 break; 2742 case AMDGPU_UCODE_ID_SMC: 2743 *type = GFX_FW_TYPE_SMU; 2744 break; 2745 case AMDGPU_UCODE_ID_PPTABLE: 2746 *type = GFX_FW_TYPE_PPTABLE; 2747 break; 2748 case AMDGPU_UCODE_ID_UVD: 2749 *type = GFX_FW_TYPE_UVD; 2750 break; 2751 case AMDGPU_UCODE_ID_UVD1: 2752 *type = GFX_FW_TYPE_UVD1; 2753 break; 2754 case AMDGPU_UCODE_ID_VCE: 2755 *type = GFX_FW_TYPE_VCE; 2756 break; 2757 case AMDGPU_UCODE_ID_VCN: 2758 *type = GFX_FW_TYPE_VCN; 2759 break; 2760 case AMDGPU_UCODE_ID_VCN1: 2761 *type = GFX_FW_TYPE_VCN1; 2762 break; 2763 case AMDGPU_UCODE_ID_DMCU_ERAM: 2764 *type = GFX_FW_TYPE_DMCU_ERAM; 2765 break; 2766 case AMDGPU_UCODE_ID_DMCU_INTV: 2767 *type = GFX_FW_TYPE_DMCU_ISR; 2768 break; 2769 case AMDGPU_UCODE_ID_VCN0_RAM: 2770 *type = GFX_FW_TYPE_VCN0_RAM; 2771 break; 2772 case AMDGPU_UCODE_ID_VCN1_RAM: 2773 *type = GFX_FW_TYPE_VCN1_RAM; 2774 break; 2775 case AMDGPU_UCODE_ID_DMCUB: 2776 *type = GFX_FW_TYPE_DMUB; 2777 break; 2778 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2779 case AMDGPU_UCODE_ID_SDMA_RS64: 2780 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2781 break; 2782 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2783 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2784 break; 2785 case AMDGPU_UCODE_ID_IMU_I: 2786 *type = GFX_FW_TYPE_IMU_I; 2787 break; 2788 case AMDGPU_UCODE_ID_IMU_D: 2789 *type = GFX_FW_TYPE_IMU_D; 2790 break; 2791 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2792 *type = GFX_FW_TYPE_RS64_PFP; 2793 break; 2794 case AMDGPU_UCODE_ID_CP_RS64_ME: 2795 *type = GFX_FW_TYPE_RS64_ME; 2796 break; 2797 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2798 *type = GFX_FW_TYPE_RS64_MEC; 2799 break; 2800 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2801 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2802 break; 2803 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2804 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2805 break; 2806 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2807 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2808 break; 2809 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2810 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2811 break; 2812 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2813 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2814 break; 2815 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2816 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2817 break; 2818 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2819 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2820 break; 2821 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2822 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2823 break; 2824 case AMDGPU_UCODE_ID_VPE_CTX: 2825 *type = GFX_FW_TYPE_VPEC_FW1; 2826 break; 2827 case AMDGPU_UCODE_ID_VPE_CTL: 2828 *type = GFX_FW_TYPE_VPEC_FW2; 2829 break; 2830 case AMDGPU_UCODE_ID_VPE: 2831 *type = GFX_FW_TYPE_VPE; 2832 break; 2833 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 2834 *type = GFX_FW_TYPE_UMSCH_UCODE; 2835 break; 2836 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 2837 *type = GFX_FW_TYPE_UMSCH_DATA; 2838 break; 2839 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 2840 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER; 2841 break; 2842 case AMDGPU_UCODE_ID_P2S_TABLE: 2843 *type = GFX_FW_TYPE_P2S_TABLE; 2844 break; 2845 case AMDGPU_UCODE_ID_JPEG_RAM: 2846 *type = GFX_FW_TYPE_JPEG_RAM; 2847 break; 2848 case AMDGPU_UCODE_ID_ISP: 2849 *type = GFX_FW_TYPE_ISP; 2850 break; 2851 case AMDGPU_UCODE_ID_MAXIMUM: 2852 default: 2853 return -EINVAL; 2854 } 2855 2856 return 0; 2857 } 2858 2859 static void psp_print_fw_hdr(struct psp_context *psp, 2860 struct amdgpu_firmware_info *ucode) 2861 { 2862 struct amdgpu_device *adev = psp->adev; 2863 struct common_firmware_header *hdr; 2864 2865 switch (ucode->ucode_id) { 2866 case AMDGPU_UCODE_ID_SDMA0: 2867 case AMDGPU_UCODE_ID_SDMA1: 2868 case AMDGPU_UCODE_ID_SDMA2: 2869 case AMDGPU_UCODE_ID_SDMA3: 2870 case AMDGPU_UCODE_ID_SDMA4: 2871 case AMDGPU_UCODE_ID_SDMA5: 2872 case AMDGPU_UCODE_ID_SDMA6: 2873 case AMDGPU_UCODE_ID_SDMA7: 2874 hdr = (struct common_firmware_header *) 2875 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2876 amdgpu_ucode_print_sdma_hdr(hdr); 2877 break; 2878 case AMDGPU_UCODE_ID_CP_CE: 2879 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2880 amdgpu_ucode_print_gfx_hdr(hdr); 2881 break; 2882 case AMDGPU_UCODE_ID_CP_PFP: 2883 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2884 amdgpu_ucode_print_gfx_hdr(hdr); 2885 break; 2886 case AMDGPU_UCODE_ID_CP_ME: 2887 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2888 amdgpu_ucode_print_gfx_hdr(hdr); 2889 break; 2890 case AMDGPU_UCODE_ID_CP_MEC1: 2891 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2892 amdgpu_ucode_print_gfx_hdr(hdr); 2893 break; 2894 case AMDGPU_UCODE_ID_RLC_G: 2895 case AMDGPU_UCODE_ID_RLC_DRAM_1: 2896 case AMDGPU_UCODE_ID_RLC_IRAM_1: 2897 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2898 amdgpu_ucode_print_rlc_hdr(hdr); 2899 break; 2900 case AMDGPU_UCODE_ID_SMC: 2901 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2902 amdgpu_ucode_print_smc_hdr(hdr); 2903 break; 2904 default: 2905 break; 2906 } 2907 } 2908 2909 static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp, 2910 struct amdgpu_firmware_info *ucode, 2911 struct psp_gfx_cmd_resp *cmd) 2912 { 2913 int ret; 2914 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2915 2916 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2917 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2918 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2919 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2920 2921 ret = psp_get_fw_type(psp, ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2922 if (ret) 2923 dev_err(psp->adev->dev, "Unknown firmware type %d\n", ucode->ucode_id); 2924 return ret; 2925 } 2926 2927 int psp_execute_ip_fw_load(struct psp_context *psp, 2928 struct amdgpu_firmware_info *ucode) 2929 { 2930 int ret = 0; 2931 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2932 2933 ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd); 2934 if (!ret) { 2935 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2936 psp->fence_buf_mc_addr); 2937 } 2938 2939 release_psp_cmd_buf(psp); 2940 2941 return ret; 2942 } 2943 2944 static int psp_load_p2s_table(struct psp_context *psp) 2945 { 2946 int ret; 2947 struct amdgpu_device *adev = psp->adev; 2948 struct amdgpu_firmware_info *ucode = 2949 &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE]; 2950 2951 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2952 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 2953 return 0; 2954 2955 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 2956 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 2957 uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D : 2958 0x0036003C; 2959 if (psp->sos.fw_version < supp_vers) 2960 return 0; 2961 } 2962 2963 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2964 return 0; 2965 2966 ret = psp_execute_ip_fw_load(psp, ucode); 2967 2968 return ret; 2969 } 2970 2971 static int psp_load_smu_fw(struct psp_context *psp) 2972 { 2973 int ret; 2974 struct amdgpu_device *adev = psp->adev; 2975 struct amdgpu_firmware_info *ucode = 2976 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2977 struct amdgpu_ras *ras = psp->ras_context.ras; 2978 2979 /* 2980 * Skip SMU FW reloading in case of using BACO for runpm only, 2981 * as SMU is always alive. 2982 */ 2983 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2984 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 2985 return 0; 2986 2987 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2988 return 0; 2989 2990 if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled && 2991 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 2992 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) { 2993 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2994 if (ret) 2995 dev_err(adev->dev, "Failed to set MP1 state prepare for reload\n"); 2996 } 2997 2998 ret = psp_execute_ip_fw_load(psp, ucode); 2999 3000 if (ret) 3001 dev_err(adev->dev, "PSP load smu failed!\n"); 3002 3003 return ret; 3004 } 3005 3006 static bool fw_load_skip_check(struct psp_context *psp, 3007 struct amdgpu_firmware_info *ucode) 3008 { 3009 if (!ucode->fw || !ucode->ucode_size) 3010 return true; 3011 3012 if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE) 3013 return true; 3014 3015 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3016 (psp_smu_reload_quirk(psp) || 3017 psp->autoload_supported || 3018 psp->pmfw_centralized_cstate_management)) 3019 return true; 3020 3021 if (amdgpu_sriov_vf(psp->adev) && 3022 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 3023 return true; 3024 3025 if (psp->autoload_supported && 3026 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 3027 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 3028 /* skip mec JT when autoload is enabled */ 3029 return true; 3030 3031 return false; 3032 } 3033 3034 int psp_load_fw_list(struct psp_context *psp, 3035 struct amdgpu_firmware_info **ucode_list, int ucode_count) 3036 { 3037 int ret = 0, i; 3038 struct amdgpu_firmware_info *ucode; 3039 3040 for (i = 0; i < ucode_count; ++i) { 3041 ucode = ucode_list[i]; 3042 psp_print_fw_hdr(psp, ucode); 3043 ret = psp_execute_ip_fw_load(psp, ucode); 3044 if (ret) 3045 return ret; 3046 } 3047 return ret; 3048 } 3049 3050 static int psp_load_non_psp_fw(struct psp_context *psp) 3051 { 3052 int i, ret; 3053 struct amdgpu_firmware_info *ucode; 3054 struct amdgpu_device *adev = psp->adev; 3055 3056 if (psp->autoload_supported && 3057 !psp->pmfw_centralized_cstate_management) { 3058 ret = psp_load_smu_fw(psp); 3059 if (ret) 3060 return ret; 3061 } 3062 3063 /* Load P2S table first if it's available */ 3064 psp_load_p2s_table(psp); 3065 3066 for (i = 0; i < adev->firmware.max_ucodes; i++) { 3067 ucode = &adev->firmware.ucode[i]; 3068 3069 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3070 !fw_load_skip_check(psp, ucode)) { 3071 ret = psp_load_smu_fw(psp); 3072 if (ret) 3073 return ret; 3074 continue; 3075 } 3076 3077 if (fw_load_skip_check(psp, ucode)) 3078 continue; 3079 3080 if (psp->autoload_supported && 3081 (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3082 IP_VERSION(11, 0, 7) || 3083 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3084 IP_VERSION(11, 0, 11) || 3085 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3086 IP_VERSION(11, 0, 12) || 3087 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3088 IP_VERSION(15, 0, 0) || 3089 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3090 IP_VERSION(15, 0, 8)) && 3091 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 3092 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 3093 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 3094 /* PSP only receive one SDMA fw for sienna_cichlid, 3095 * as all four sdma fw are same 3096 */ 3097 continue; 3098 3099 /* IMU ucode is part of IFWI and MP0 15.0.8 would load it */ 3100 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3101 IP_VERSION(15, 0, 8) && 3102 (ucode->ucode_id == AMDGPU_UCODE_ID_IMU_I || 3103 ucode->ucode_id == AMDGPU_UCODE_ID_IMU_D)) 3104 continue; 3105 3106 psp_print_fw_hdr(psp, ucode); 3107 3108 ret = psp_execute_ip_fw_load(psp, ucode); 3109 if (ret) 3110 return ret; 3111 3112 /* Start rlc autoload after psp received all the gfx firmware */ 3113 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 3114 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 3115 ret = psp_rlc_autoload_start(psp); 3116 if (ret) { 3117 dev_err(adev->dev, "Failed to start rlc autoload\n"); 3118 return ret; 3119 } 3120 } 3121 } 3122 3123 return 0; 3124 } 3125 3126 static int psp_load_fw(struct amdgpu_device *adev) 3127 { 3128 int ret; 3129 struct psp_context *psp = &adev->psp; 3130 3131 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 3132 /* should not destroy ring, only stop */ 3133 psp_ring_stop(psp, PSP_RING_TYPE__KM); 3134 } else { 3135 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 3136 3137 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 3138 if (ret) { 3139 dev_err(adev->dev, "PSP ring init failed!\n"); 3140 goto failed; 3141 } 3142 } 3143 3144 ret = psp_hw_start(psp); 3145 if (ret) 3146 goto failed; 3147 3148 ret = psp_load_non_psp_fw(psp); 3149 if (ret) 3150 goto failed1; 3151 3152 ret = psp_asd_initialize(psp); 3153 if (ret) { 3154 dev_err(adev->dev, "PSP load asd failed!\n"); 3155 goto failed1; 3156 } 3157 3158 ret = psp_rl_load(adev); 3159 if (ret) { 3160 dev_err(adev->dev, "PSP load RL failed!\n"); 3161 goto failed1; 3162 } 3163 3164 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 3165 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3166 ret = psp_xgmi_initialize(psp, false, true); 3167 /* Warning the XGMI seesion initialize failure 3168 * Instead of stop driver initialization 3169 */ 3170 if (ret) 3171 dev_err(psp->adev->dev, 3172 "XGMI: Failed to initialize XGMI session\n"); 3173 } 3174 } 3175 3176 if (psp->ta_fw) { 3177 ret = psp_ras_initialize(psp); 3178 if (ret) 3179 dev_err(psp->adev->dev, 3180 "RAS: Failed to initialize RAS\n"); 3181 3182 ret = psp_hdcp_initialize(psp); 3183 if (ret) 3184 dev_err(psp->adev->dev, 3185 "HDCP: Failed to initialize HDCP\n"); 3186 3187 ret = psp_dtm_initialize(psp); 3188 if (ret) 3189 dev_err(psp->adev->dev, 3190 "DTM: Failed to initialize DTM\n"); 3191 3192 ret = psp_rap_initialize(psp); 3193 if (ret) 3194 dev_err(psp->adev->dev, 3195 "RAP: Failed to initialize RAP\n"); 3196 3197 ret = psp_securedisplay_initialize(psp); 3198 if (ret) 3199 dev_err(psp->adev->dev, 3200 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3201 } 3202 3203 return 0; 3204 3205 failed1: 3206 psp_free_shared_bufs(psp); 3207 failed: 3208 /* 3209 * all cleanup jobs (xgmi terminate, ras terminate, 3210 * ring destroy, cmd/fence/fw buffers destory, 3211 * psp->cmd destory) are delayed to psp_hw_fini 3212 */ 3213 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3214 return ret; 3215 } 3216 3217 static int psp_hw_init(struct amdgpu_ip_block *ip_block) 3218 { 3219 int ret; 3220 struct amdgpu_device *adev = ip_block->adev; 3221 3222 mutex_lock(&adev->firmware.mutex); 3223 3224 ret = amdgpu_ucode_init_bo(adev); 3225 if (ret) 3226 goto failed; 3227 3228 ret = psp_load_fw(adev); 3229 if (ret) { 3230 dev_err(adev->dev, "PSP firmware loading failed\n"); 3231 goto failed; 3232 } 3233 3234 mutex_unlock(&adev->firmware.mutex); 3235 return 0; 3236 3237 failed: 3238 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 3239 mutex_unlock(&adev->firmware.mutex); 3240 return -EINVAL; 3241 } 3242 3243 static int psp_hw_fini(struct amdgpu_ip_block *ip_block) 3244 { 3245 struct amdgpu_device *adev = ip_block->adev; 3246 struct psp_context *psp = &adev->psp; 3247 3248 if (psp->ta_fw) { 3249 psp_ras_terminate(psp); 3250 psp_securedisplay_terminate(psp); 3251 psp_rap_terminate(psp); 3252 psp_dtm_terminate(psp); 3253 psp_hdcp_terminate(psp); 3254 3255 if (adev->gmc.xgmi.num_physical_nodes > 1) 3256 psp_xgmi_terminate(psp); 3257 } 3258 3259 psp_asd_terminate(psp); 3260 psp_tmr_terminate(psp); 3261 3262 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3263 3264 return 0; 3265 } 3266 3267 static int psp_suspend(struct amdgpu_ip_block *ip_block) 3268 { 3269 int ret = 0; 3270 struct amdgpu_device *adev = ip_block->adev; 3271 struct psp_context *psp = &adev->psp; 3272 3273 if (adev->gmc.xgmi.num_physical_nodes > 1 && 3274 psp->xgmi_context.context.initialized) { 3275 ret = psp_xgmi_terminate(psp); 3276 if (ret) { 3277 dev_err(adev->dev, "Failed to terminate xgmi ta\n"); 3278 goto out; 3279 } 3280 } 3281 3282 if (psp->ta_fw) { 3283 ret = psp_ras_terminate(psp); 3284 if (ret) { 3285 dev_err(adev->dev, "Failed to terminate ras ta\n"); 3286 goto out; 3287 } 3288 ret = psp_hdcp_terminate(psp); 3289 if (ret) { 3290 dev_err(adev->dev, "Failed to terminate hdcp ta\n"); 3291 goto out; 3292 } 3293 ret = psp_dtm_terminate(psp); 3294 if (ret) { 3295 dev_err(adev->dev, "Failed to terminate dtm ta\n"); 3296 goto out; 3297 } 3298 ret = psp_rap_terminate(psp); 3299 if (ret) { 3300 dev_err(adev->dev, "Failed to terminate rap ta\n"); 3301 goto out; 3302 } 3303 ret = psp_securedisplay_terminate(psp); 3304 if (ret) { 3305 dev_err(adev->dev, "Failed to terminate securedisplay ta\n"); 3306 goto out; 3307 } 3308 } 3309 3310 ret = psp_asd_terminate(psp); 3311 if (ret) { 3312 dev_err(adev->dev, "Failed to terminate asd\n"); 3313 goto out; 3314 } 3315 3316 ret = psp_tmr_terminate(psp); 3317 if (ret) { 3318 dev_err(adev->dev, "Failed to terminate tmr\n"); 3319 goto out; 3320 } 3321 3322 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 3323 if (ret) 3324 dev_err(adev->dev, "PSP ring stop failed\n"); 3325 3326 out: 3327 return ret; 3328 } 3329 3330 static int psp_resume(struct amdgpu_ip_block *ip_block) 3331 { 3332 int ret; 3333 struct amdgpu_device *adev = ip_block->adev; 3334 struct psp_context *psp = &adev->psp; 3335 3336 dev_info(adev->dev, "PSP is resuming...\n"); 3337 3338 if (psp->mem_train_ctx.enable_mem_training) { 3339 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 3340 if (ret) { 3341 dev_err(adev->dev, "Failed to process memory training!\n"); 3342 return ret; 3343 } 3344 } 3345 3346 mutex_lock(&adev->firmware.mutex); 3347 3348 ret = amdgpu_ucode_init_bo(adev); 3349 if (ret) 3350 goto failed; 3351 3352 ret = psp_hw_start(psp); 3353 if (ret) 3354 goto failed; 3355 3356 ret = psp_load_non_psp_fw(psp); 3357 if (ret) 3358 goto failed; 3359 3360 ret = psp_asd_initialize(psp); 3361 if (ret) { 3362 dev_err(adev->dev, "PSP load asd failed!\n"); 3363 goto failed; 3364 } 3365 3366 ret = psp_rl_load(adev); 3367 if (ret) { 3368 dev_err(adev->dev, "PSP load RL failed!\n"); 3369 goto failed; 3370 } 3371 3372 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3373 ret = psp_xgmi_initialize(psp, false, true); 3374 /* Warning the XGMI seesion initialize failure 3375 * Instead of stop driver initialization 3376 */ 3377 if (ret) 3378 dev_err(psp->adev->dev, 3379 "XGMI: Failed to initialize XGMI session\n"); 3380 } 3381 3382 if (psp->ta_fw) { 3383 ret = psp_ras_initialize(psp); 3384 if (ret) 3385 dev_err(psp->adev->dev, 3386 "RAS: Failed to initialize RAS\n"); 3387 3388 ret = psp_hdcp_initialize(psp); 3389 if (ret) 3390 dev_err(psp->adev->dev, 3391 "HDCP: Failed to initialize HDCP\n"); 3392 3393 ret = psp_dtm_initialize(psp); 3394 if (ret) 3395 dev_err(psp->adev->dev, 3396 "DTM: Failed to initialize DTM\n"); 3397 3398 ret = psp_rap_initialize(psp); 3399 if (ret) 3400 dev_err(psp->adev->dev, 3401 "RAP: Failed to initialize RAP\n"); 3402 3403 ret = psp_securedisplay_initialize(psp); 3404 if (ret) 3405 dev_err(psp->adev->dev, 3406 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3407 } 3408 3409 mutex_unlock(&adev->firmware.mutex); 3410 3411 return 0; 3412 3413 failed: 3414 dev_err(adev->dev, "PSP resume failed\n"); 3415 mutex_unlock(&adev->firmware.mutex); 3416 return ret; 3417 } 3418 3419 int psp_gpu_reset(struct amdgpu_device *adev) 3420 { 3421 int ret; 3422 3423 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 3424 return 0; 3425 3426 mutex_lock(&adev->psp.mutex); 3427 ret = psp_mode1_reset(&adev->psp); 3428 mutex_unlock(&adev->psp.mutex); 3429 3430 return ret; 3431 } 3432 3433 int psp_rlc_autoload_start(struct psp_context *psp) 3434 { 3435 int ret; 3436 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3437 3438 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 3439 3440 ret = psp_cmd_submit_buf(psp, NULL, cmd, 3441 psp->fence_buf_mc_addr); 3442 3443 release_psp_cmd_buf(psp); 3444 3445 return ret; 3446 } 3447 3448 int psp_ring_cmd_submit(struct psp_context *psp, 3449 uint64_t cmd_buf_mc_addr, 3450 uint64_t fence_mc_addr, 3451 int index) 3452 { 3453 unsigned int psp_write_ptr_reg = 0; 3454 struct psp_gfx_rb_frame *write_frame; 3455 struct psp_ring *ring = &psp->km_ring; 3456 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 3457 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 3458 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 3459 struct amdgpu_device *adev = psp->adev; 3460 uint32_t ring_size_dw = ring->ring_size / 4; 3461 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 3462 3463 /* KM (GPCOM) prepare write pointer */ 3464 psp_write_ptr_reg = psp_ring_get_wptr(psp); 3465 3466 /* Update KM RB frame pointer to new frame */ 3467 /* write_frame ptr increments by size of rb_frame in bytes */ 3468 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 3469 if ((psp_write_ptr_reg % ring_size_dw) == 0) 3470 write_frame = ring_buffer_start; 3471 else 3472 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 3473 /* Check invalid write_frame ptr address */ 3474 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 3475 dev_err(adev->dev, 3476 "ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 3477 ring_buffer_start, ring_buffer_end, write_frame); 3478 dev_err(adev->dev, 3479 "write_frame is pointing to address out of bounds\n"); 3480 return -EINVAL; 3481 } 3482 3483 /* Initialize KM RB frame */ 3484 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 3485 3486 /* Update KM RB frame */ 3487 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 3488 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 3489 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 3490 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 3491 write_frame->fence_value = index; 3492 amdgpu_device_flush_hdp(adev, NULL); 3493 3494 /* Update the write Pointer in DWORDs */ 3495 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 3496 psp_ring_set_wptr(psp, psp_write_ptr_reg); 3497 return 0; 3498 } 3499 3500 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 3501 { 3502 struct amdgpu_device *adev = psp->adev; 3503 const struct psp_firmware_header_v1_0 *asd_hdr; 3504 int err = 0; 3505 3506 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, AMDGPU_UCODE_REQUIRED, 3507 "amdgpu/%s_asd.bin", chip_name); 3508 if (err) 3509 goto out; 3510 3511 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 3512 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 3513 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 3514 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 3515 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 3516 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 3517 return 0; 3518 out: 3519 amdgpu_ucode_release(&adev->psp.asd_fw); 3520 return err; 3521 } 3522 3523 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 3524 { 3525 struct amdgpu_device *adev = psp->adev; 3526 const struct psp_firmware_header_v1_0 *toc_hdr; 3527 int err = 0; 3528 3529 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, 3530 "amdgpu/%s_toc.bin", chip_name); 3531 if (err) 3532 goto out; 3533 3534 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3535 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3536 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3537 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3538 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3539 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3540 return 0; 3541 out: 3542 amdgpu_ucode_release(&adev->psp.toc_fw); 3543 return err; 3544 } 3545 3546 static int parse_sos_bin_descriptor(struct psp_context *psp, 3547 const struct psp_fw_bin_desc *desc, 3548 const struct psp_firmware_header_v2_0 *sos_hdr) 3549 { 3550 uint8_t *ucode_start_addr = NULL; 3551 3552 if (!psp || !desc || !sos_hdr) 3553 return -EINVAL; 3554 3555 ucode_start_addr = (uint8_t *)sos_hdr + 3556 le32_to_cpu(desc->offset_bytes) + 3557 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3558 3559 switch (desc->fw_type) { 3560 case PSP_FW_TYPE_PSP_SOS: 3561 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3562 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3563 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3564 psp->sos.start_addr = ucode_start_addr; 3565 break; 3566 case PSP_FW_TYPE_PSP_SYS_DRV: 3567 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3568 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3569 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3570 psp->sys.start_addr = ucode_start_addr; 3571 break; 3572 case PSP_FW_TYPE_PSP_KDB: 3573 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3574 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3575 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3576 psp->kdb.start_addr = ucode_start_addr; 3577 break; 3578 case PSP_FW_TYPE_PSP_TOC: 3579 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3580 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3581 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3582 psp->toc.start_addr = ucode_start_addr; 3583 break; 3584 case PSP_FW_TYPE_PSP_SPL: 3585 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3586 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3587 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3588 psp->spl.start_addr = ucode_start_addr; 3589 break; 3590 case PSP_FW_TYPE_PSP_RL: 3591 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3592 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3593 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3594 psp->rl.start_addr = ucode_start_addr; 3595 break; 3596 case PSP_FW_TYPE_PSP_SOC_DRV: 3597 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3598 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3599 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3600 psp->soc_drv.start_addr = ucode_start_addr; 3601 break; 3602 case PSP_FW_TYPE_PSP_INTF_DRV: 3603 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3604 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3605 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3606 psp->intf_drv.start_addr = ucode_start_addr; 3607 break; 3608 case PSP_FW_TYPE_PSP_DBG_DRV: 3609 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3610 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3611 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3612 psp->dbg_drv.start_addr = ucode_start_addr; 3613 break; 3614 case PSP_FW_TYPE_PSP_RAS_DRV: 3615 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3616 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3617 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3618 psp->ras_drv.start_addr = ucode_start_addr; 3619 break; 3620 case PSP_FW_TYPE_PSP_IPKEYMGR_DRV: 3621 psp->ipkeymgr_drv.fw_version = le32_to_cpu(desc->fw_version); 3622 psp->ipkeymgr_drv.feature_version = le32_to_cpu(desc->fw_version); 3623 psp->ipkeymgr_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3624 psp->ipkeymgr_drv.start_addr = ucode_start_addr; 3625 break; 3626 case PSP_FW_TYPE_PSP_SPDM_DRV: 3627 psp->spdm_drv.fw_version = le32_to_cpu(desc->fw_version); 3628 psp->spdm_drv.feature_version = le32_to_cpu(desc->fw_version); 3629 psp->spdm_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3630 psp->spdm_drv.start_addr = ucode_start_addr; 3631 break; 3632 default: 3633 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3634 break; 3635 } 3636 3637 return 0; 3638 } 3639 3640 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3641 { 3642 const struct psp_firmware_header_v1_0 *sos_hdr; 3643 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3644 uint8_t *ucode_array_start_addr; 3645 3646 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3647 ucode_array_start_addr = (uint8_t *)sos_hdr + 3648 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3649 3650 if (adev->gmc.xgmi.connected_to_cpu || 3651 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) { 3652 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3653 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3654 3655 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3656 adev->psp.sys.start_addr = ucode_array_start_addr; 3657 3658 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3659 adev->psp.sos.start_addr = ucode_array_start_addr + 3660 le32_to_cpu(sos_hdr->sos.offset_bytes); 3661 } else { 3662 /* Load alternate PSP SOS FW */ 3663 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3664 3665 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3666 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3667 3668 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3669 adev->psp.sys.start_addr = ucode_array_start_addr + 3670 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3671 3672 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3673 adev->psp.sos.start_addr = ucode_array_start_addr + 3674 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3675 } 3676 3677 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3678 dev_warn(adev->dev, "PSP SOS FW not available"); 3679 return -EINVAL; 3680 } 3681 3682 return 0; 3683 } 3684 3685 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 3686 { 3687 struct amdgpu_device *adev = psp->adev; 3688 const struct psp_firmware_header_v1_0 *sos_hdr; 3689 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3690 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3691 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3692 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3693 const struct psp_firmware_header_v2_1 *sos_hdr_v2_1; 3694 int fw_index, fw_bin_count, start_index = 0; 3695 const struct psp_fw_bin_desc *fw_bin; 3696 uint8_t *ucode_array_start_addr; 3697 int err = 0; 3698 3699 if (amdgpu_is_kicker_fw(adev)) 3700 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 3701 "amdgpu/%s_sos_kicker.bin", chip_name); 3702 else 3703 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 3704 "amdgpu/%s_sos.bin", chip_name); 3705 if (err) 3706 goto out; 3707 3708 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3709 ucode_array_start_addr = (uint8_t *)sos_hdr + 3710 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3711 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3712 3713 switch (sos_hdr->header.header_version_major) { 3714 case 1: 3715 err = psp_init_sos_base_fw(adev); 3716 if (err) 3717 goto out; 3718 3719 if (sos_hdr->header.header_version_minor == 1) { 3720 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3721 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3722 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3723 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3724 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3725 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3726 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3727 } 3728 if (sos_hdr->header.header_version_minor == 2) { 3729 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3730 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3731 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3732 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3733 } 3734 if (sos_hdr->header.header_version_minor == 3) { 3735 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3736 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3737 adev->psp.toc.start_addr = ucode_array_start_addr + 3738 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3739 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3740 adev->psp.kdb.start_addr = ucode_array_start_addr + 3741 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3742 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3743 adev->psp.spl.start_addr = ucode_array_start_addr + 3744 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3745 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3746 adev->psp.rl.start_addr = ucode_array_start_addr + 3747 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3748 } 3749 break; 3750 case 2: 3751 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3752 3753 fw_bin_count = le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); 3754 3755 if (fw_bin_count >= UCODE_MAX_PSP_PACKAGING) { 3756 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3757 err = -EINVAL; 3758 goto out; 3759 } 3760 3761 if (sos_hdr_v2_0->header.header_version_minor == 1) { 3762 sos_hdr_v2_1 = (const struct psp_firmware_header_v2_1 *)adev->psp.sos_fw->data; 3763 3764 fw_bin = sos_hdr_v2_1->psp_fw_bin; 3765 3766 if (psp_is_aux_sos_load_required(psp)) 3767 start_index = le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 3768 else 3769 fw_bin_count -= le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 3770 3771 } else { 3772 fw_bin = sos_hdr_v2_0->psp_fw_bin; 3773 } 3774 3775 for (fw_index = start_index; fw_index < fw_bin_count; fw_index++) { 3776 err = parse_sos_bin_descriptor(psp, fw_bin + fw_index, 3777 sos_hdr_v2_0); 3778 if (err) 3779 goto out; 3780 } 3781 break; 3782 default: 3783 dev_err(adev->dev, 3784 "unsupported psp sos firmware\n"); 3785 err = -EINVAL; 3786 goto out; 3787 } 3788 3789 return 0; 3790 out: 3791 amdgpu_ucode_release(&adev->psp.sos_fw); 3792 3793 return err; 3794 } 3795 3796 static bool is_ta_fw_applicable(struct psp_context *psp, 3797 const struct psp_fw_bin_desc *desc) 3798 { 3799 struct amdgpu_device *adev = psp->adev; 3800 uint32_t fw_version; 3801 3802 switch (desc->fw_type) { 3803 case TA_FW_TYPE_PSP_XGMI: 3804 case TA_FW_TYPE_PSP_XGMI_AUX: 3805 /* for now, AUX TA only exists on 13.0.6 ta bin, 3806 * from v20.00.0x.14 3807 */ 3808 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3809 IP_VERSION(13, 0, 6)) { 3810 fw_version = le32_to_cpu(desc->fw_version); 3811 3812 if (adev->flags & AMD_IS_APU && 3813 (fw_version & 0xff) >= 0x14) 3814 return desc->fw_type == TA_FW_TYPE_PSP_XGMI_AUX; 3815 else 3816 return desc->fw_type == TA_FW_TYPE_PSP_XGMI; 3817 } 3818 break; 3819 default: 3820 break; 3821 } 3822 3823 return true; 3824 } 3825 3826 static int parse_ta_bin_descriptor(struct psp_context *psp, 3827 const struct psp_fw_bin_desc *desc, 3828 const struct ta_firmware_header_v2_0 *ta_hdr) 3829 { 3830 uint8_t *ucode_start_addr = NULL; 3831 3832 if (!psp || !desc || !ta_hdr) 3833 return -EINVAL; 3834 3835 if (!is_ta_fw_applicable(psp, desc)) 3836 return 0; 3837 3838 ucode_start_addr = (uint8_t *)ta_hdr + 3839 le32_to_cpu(desc->offset_bytes) + 3840 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3841 3842 switch (desc->fw_type) { 3843 case TA_FW_TYPE_PSP_ASD: 3844 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3845 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3846 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3847 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3848 break; 3849 case TA_FW_TYPE_PSP_XGMI: 3850 case TA_FW_TYPE_PSP_XGMI_AUX: 3851 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3852 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3853 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3854 break; 3855 case TA_FW_TYPE_PSP_RAS: 3856 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3857 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3858 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3859 break; 3860 case TA_FW_TYPE_PSP_HDCP: 3861 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3862 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3863 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3864 break; 3865 case TA_FW_TYPE_PSP_DTM: 3866 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3867 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3868 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3869 break; 3870 case TA_FW_TYPE_PSP_RAP: 3871 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3872 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3873 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3874 break; 3875 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3876 psp->securedisplay_context.context.bin_desc.fw_version = 3877 le32_to_cpu(desc->fw_version); 3878 psp->securedisplay_context.context.bin_desc.size_bytes = 3879 le32_to_cpu(desc->size_bytes); 3880 psp->securedisplay_context.context.bin_desc.start_addr = 3881 ucode_start_addr; 3882 break; 3883 default: 3884 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3885 break; 3886 } 3887 3888 return 0; 3889 } 3890 3891 static int parse_ta_v1_microcode(struct psp_context *psp) 3892 { 3893 const struct ta_firmware_header_v1_0 *ta_hdr; 3894 struct amdgpu_device *adev = psp->adev; 3895 3896 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 3897 3898 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 3899 return -EINVAL; 3900 3901 adev->psp.xgmi_context.context.bin_desc.fw_version = 3902 le32_to_cpu(ta_hdr->xgmi.fw_version); 3903 adev->psp.xgmi_context.context.bin_desc.size_bytes = 3904 le32_to_cpu(ta_hdr->xgmi.size_bytes); 3905 adev->psp.xgmi_context.context.bin_desc.start_addr = 3906 (uint8_t *)ta_hdr + 3907 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3908 3909 adev->psp.ras_context.context.bin_desc.fw_version = 3910 le32_to_cpu(ta_hdr->ras.fw_version); 3911 adev->psp.ras_context.context.bin_desc.size_bytes = 3912 le32_to_cpu(ta_hdr->ras.size_bytes); 3913 adev->psp.ras_context.context.bin_desc.start_addr = 3914 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 3915 le32_to_cpu(ta_hdr->ras.offset_bytes); 3916 3917 adev->psp.hdcp_context.context.bin_desc.fw_version = 3918 le32_to_cpu(ta_hdr->hdcp.fw_version); 3919 adev->psp.hdcp_context.context.bin_desc.size_bytes = 3920 le32_to_cpu(ta_hdr->hdcp.size_bytes); 3921 adev->psp.hdcp_context.context.bin_desc.start_addr = 3922 (uint8_t *)ta_hdr + 3923 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3924 3925 adev->psp.dtm_context.context.bin_desc.fw_version = 3926 le32_to_cpu(ta_hdr->dtm.fw_version); 3927 adev->psp.dtm_context.context.bin_desc.size_bytes = 3928 le32_to_cpu(ta_hdr->dtm.size_bytes); 3929 adev->psp.dtm_context.context.bin_desc.start_addr = 3930 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3931 le32_to_cpu(ta_hdr->dtm.offset_bytes); 3932 3933 adev->psp.securedisplay_context.context.bin_desc.fw_version = 3934 le32_to_cpu(ta_hdr->securedisplay.fw_version); 3935 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 3936 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 3937 adev->psp.securedisplay_context.context.bin_desc.start_addr = 3938 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3939 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 3940 3941 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 3942 3943 return 0; 3944 } 3945 3946 static int parse_ta_v2_microcode(struct psp_context *psp) 3947 { 3948 const struct ta_firmware_header_v2_0 *ta_hdr; 3949 struct amdgpu_device *adev = psp->adev; 3950 int err = 0; 3951 int ta_index = 0; 3952 3953 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3954 3955 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 3956 return -EINVAL; 3957 3958 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3959 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3960 return -EINVAL; 3961 } 3962 3963 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3964 err = parse_ta_bin_descriptor(psp, 3965 &ta_hdr->ta_fw_bin[ta_index], 3966 ta_hdr); 3967 if (err) 3968 return err; 3969 } 3970 3971 return 0; 3972 } 3973 3974 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 3975 { 3976 const struct common_firmware_header *hdr; 3977 struct amdgpu_device *adev = psp->adev; 3978 int err; 3979 3980 if (amdgpu_is_kicker_fw(adev)) 3981 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 3982 "amdgpu/%s_ta_kicker.bin", chip_name); 3983 else 3984 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 3985 "amdgpu/%s_ta.bin", chip_name); 3986 if (err) 3987 return err; 3988 3989 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 3990 switch (le16_to_cpu(hdr->header_version_major)) { 3991 case 1: 3992 err = parse_ta_v1_microcode(psp); 3993 break; 3994 case 2: 3995 err = parse_ta_v2_microcode(psp); 3996 break; 3997 default: 3998 dev_err(adev->dev, "unsupported TA header version\n"); 3999 err = -EINVAL; 4000 } 4001 4002 if (err) 4003 amdgpu_ucode_release(&adev->psp.ta_fw); 4004 4005 return err; 4006 } 4007 4008 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 4009 { 4010 struct amdgpu_device *adev = psp->adev; 4011 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 4012 struct amdgpu_firmware_info *info = NULL; 4013 int err = 0; 4014 4015 if (!amdgpu_sriov_vf(adev)) { 4016 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 4017 return -EINVAL; 4018 } 4019 4020 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, AMDGPU_UCODE_OPTIONAL, 4021 "amdgpu/%s_cap.bin", chip_name); 4022 if (err) { 4023 if (err == -ENODEV) { 4024 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 4025 err = 0; 4026 } else { 4027 dev_err(adev->dev, "fail to initialize cap microcode\n"); 4028 } 4029 goto out; 4030 } 4031 4032 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 4033 info->ucode_id = AMDGPU_UCODE_ID_CAP; 4034 info->fw = adev->psp.cap_fw; 4035 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 4036 adev->psp.cap_fw->data; 4037 adev->firmware.fw_size += ALIGN( 4038 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 4039 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 4040 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 4041 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 4042 4043 return 0; 4044 4045 out: 4046 amdgpu_ucode_release(&adev->psp.cap_fw); 4047 return err; 4048 } 4049 4050 int psp_config_sq_perfmon(struct psp_context *psp, 4051 uint32_t xcp_id, bool core_override_enable, 4052 bool reg_override_enable, bool perfmon_override_enable) 4053 { 4054 int ret; 4055 4056 if (amdgpu_sriov_vf(psp->adev)) 4057 return 0; 4058 4059 if (xcp_id > MAX_XCP) { 4060 dev_err(psp->adev->dev, "invalid xcp_id %d\n", xcp_id); 4061 return -EINVAL; 4062 } 4063 4064 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) { 4065 dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n", 4066 amdgpu_ip_version(psp->adev, MP0_HWIP, 0)); 4067 return -EINVAL; 4068 } 4069 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 4070 4071 cmd->cmd_id = GFX_CMD_ID_CONFIG_SQ_PERFMON; 4072 cmd->cmd.config_sq_perfmon.gfx_xcp_mask = BIT_MASK(xcp_id); 4073 cmd->cmd.config_sq_perfmon.core_override = core_override_enable; 4074 cmd->cmd.config_sq_perfmon.reg_override = reg_override_enable; 4075 cmd->cmd.config_sq_perfmon.perfmon_override = perfmon_override_enable; 4076 4077 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 4078 if (ret) 4079 dev_warn(psp->adev->dev, "PSP failed to config sq: xcp%d core%d reg%d perfmon%d\n", 4080 xcp_id, core_override_enable, reg_override_enable, perfmon_override_enable); 4081 4082 release_psp_cmd_buf(psp); 4083 return ret; 4084 } 4085 4086 static int psp_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4087 enum amd_clockgating_state state) 4088 { 4089 return 0; 4090 } 4091 4092 static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block, 4093 enum amd_powergating_state state) 4094 { 4095 return 0; 4096 } 4097 4098 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 4099 struct device_attribute *attr, 4100 char *buf) 4101 { 4102 struct drm_device *ddev = dev_get_drvdata(dev); 4103 struct amdgpu_device *adev = drm_to_adev(ddev); 4104 struct amdgpu_ip_block *ip_block; 4105 uint32_t fw_ver; 4106 int ret; 4107 4108 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 4109 if (!ip_block || !ip_block->status.late_initialized) { 4110 dev_info(adev->dev, "PSP block is not ready yet\n."); 4111 return -EBUSY; 4112 } 4113 4114 mutex_lock(&adev->psp.mutex); 4115 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 4116 mutex_unlock(&adev->psp.mutex); 4117 4118 if (ret) { 4119 dev_err(adev->dev, "Failed to read USBC PD FW, err = %d\n", ret); 4120 return ret; 4121 } 4122 4123 return sysfs_emit(buf, "%x\n", fw_ver); 4124 } 4125 4126 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 4127 struct device_attribute *attr, 4128 const char *buf, 4129 size_t count) 4130 { 4131 struct drm_device *ddev = dev_get_drvdata(dev); 4132 struct amdgpu_device *adev = drm_to_adev(ddev); 4133 int ret, idx; 4134 const struct firmware *usbc_pd_fw; 4135 struct amdgpu_bo *fw_buf_bo = NULL; 4136 uint64_t fw_pri_mc_addr; 4137 void *fw_pri_cpu_addr; 4138 struct amdgpu_ip_block *ip_block; 4139 4140 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 4141 if (!ip_block || !ip_block->status.late_initialized) { 4142 dev_err(adev->dev, "PSP block is not ready yet."); 4143 return -EBUSY; 4144 } 4145 4146 if (!drm_dev_enter(ddev, &idx)) 4147 return -ENODEV; 4148 4149 ret = amdgpu_ucode_request(adev, &usbc_pd_fw, AMDGPU_UCODE_REQUIRED, 4150 "amdgpu/%s", buf); 4151 if (ret) 4152 goto fail; 4153 4154 /* LFB address which is aligned to 1MB boundary per PSP request */ 4155 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 4156 AMDGPU_GEM_DOMAIN_VRAM | 4157 AMDGPU_GEM_DOMAIN_GTT, 4158 &fw_buf_bo, &fw_pri_mc_addr, 4159 &fw_pri_cpu_addr); 4160 if (ret) 4161 goto rel_buf; 4162 4163 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 4164 4165 mutex_lock(&adev->psp.mutex); 4166 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 4167 mutex_unlock(&adev->psp.mutex); 4168 4169 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4170 4171 rel_buf: 4172 amdgpu_ucode_release(&usbc_pd_fw); 4173 fail: 4174 if (ret) { 4175 dev_err(adev->dev, "Failed to load USBC PD FW, err = %d", ret); 4176 count = ret; 4177 } 4178 4179 drm_dev_exit(idx); 4180 return count; 4181 } 4182 4183 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 4184 { 4185 int idx; 4186 4187 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 4188 return; 4189 4190 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 4191 memcpy(psp->fw_pri_buf, start_addr, bin_size); 4192 4193 drm_dev_exit(idx); 4194 } 4195 4196 /** 4197 * DOC: usbc_pd_fw 4198 * Reading from this file will retrieve the USB-C PD firmware version. Writing to 4199 * this file will trigger the update process. 4200 */ 4201 static DEVICE_ATTR(usbc_pd_fw, 0644, 4202 psp_usbc_pd_fw_sysfs_read, 4203 psp_usbc_pd_fw_sysfs_write); 4204 4205 int is_psp_fw_valid(struct psp_bin_desc bin) 4206 { 4207 return bin.size_bytes; 4208 } 4209 4210 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 4211 const struct bin_attribute *bin_attr, 4212 char *buffer, loff_t pos, size_t count) 4213 { 4214 struct device *dev = kobj_to_dev(kobj); 4215 struct drm_device *ddev = dev_get_drvdata(dev); 4216 struct amdgpu_device *adev = drm_to_adev(ddev); 4217 4218 adev->psp.vbflash_done = false; 4219 4220 /* Safeguard against memory drain */ 4221 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 4222 dev_err(adev->dev, "File size cannot exceed %u\n", AMD_VBIOS_FILE_MAX_SIZE_B); 4223 kvfree(adev->psp.vbflash_tmp_buf); 4224 adev->psp.vbflash_tmp_buf = NULL; 4225 adev->psp.vbflash_image_size = 0; 4226 return -ENOMEM; 4227 } 4228 4229 /* TODO Just allocate max for now and optimize to realloc later if needed */ 4230 if (!adev->psp.vbflash_tmp_buf) { 4231 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 4232 if (!adev->psp.vbflash_tmp_buf) 4233 return -ENOMEM; 4234 } 4235 4236 mutex_lock(&adev->psp.mutex); 4237 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 4238 adev->psp.vbflash_image_size += count; 4239 mutex_unlock(&adev->psp.mutex); 4240 4241 dev_dbg(adev->dev, "IFWI staged for update\n"); 4242 4243 return count; 4244 } 4245 4246 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 4247 const struct bin_attribute *bin_attr, char *buffer, 4248 loff_t pos, size_t count) 4249 { 4250 struct device *dev = kobj_to_dev(kobj); 4251 struct drm_device *ddev = dev_get_drvdata(dev); 4252 struct amdgpu_device *adev = drm_to_adev(ddev); 4253 struct amdgpu_bo *fw_buf_bo = NULL; 4254 uint64_t fw_pri_mc_addr; 4255 void *fw_pri_cpu_addr; 4256 int ret; 4257 4258 if (adev->psp.vbflash_image_size == 0) 4259 return -EINVAL; 4260 4261 dev_dbg(adev->dev, "PSP IFWI flash process initiated\n"); 4262 4263 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 4264 AMDGPU_GPU_PAGE_SIZE, 4265 AMDGPU_GEM_DOMAIN_VRAM, 4266 &fw_buf_bo, 4267 &fw_pri_mc_addr, 4268 &fw_pri_cpu_addr); 4269 if (ret) 4270 goto rel_buf; 4271 4272 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 4273 4274 mutex_lock(&adev->psp.mutex); 4275 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 4276 mutex_unlock(&adev->psp.mutex); 4277 4278 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4279 4280 rel_buf: 4281 kvfree(adev->psp.vbflash_tmp_buf); 4282 adev->psp.vbflash_tmp_buf = NULL; 4283 adev->psp.vbflash_image_size = 0; 4284 4285 if (ret) { 4286 dev_err(adev->dev, "Failed to load IFWI, err = %d\n", ret); 4287 return ret; 4288 } 4289 4290 dev_dbg(adev->dev, "PSP IFWI flash process done\n"); 4291 return 0; 4292 } 4293 4294 /** 4295 * DOC: psp_vbflash 4296 * Writing to this file will stage an IFWI for update. Reading from this file 4297 * will trigger the update process. 4298 */ 4299 static const struct bin_attribute psp_vbflash_bin_attr = { 4300 .attr = {.name = "psp_vbflash", .mode = 0660}, 4301 .size = 0, 4302 .write = amdgpu_psp_vbflash_write, 4303 .read = amdgpu_psp_vbflash_read, 4304 }; 4305 4306 /** 4307 * DOC: psp_vbflash_status 4308 * The status of the flash process. 4309 * 0: IFWI flash not complete. 4310 * 1: IFWI flash complete. 4311 */ 4312 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 4313 struct device_attribute *attr, 4314 char *buf) 4315 { 4316 struct drm_device *ddev = dev_get_drvdata(dev); 4317 struct amdgpu_device *adev = drm_to_adev(ddev); 4318 uint32_t vbflash_status; 4319 4320 vbflash_status = psp_vbflash_status(&adev->psp); 4321 if (!adev->psp.vbflash_done) 4322 vbflash_status = 0; 4323 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 4324 vbflash_status = 1; 4325 4326 return sysfs_emit(buf, "0x%x\n", vbflash_status); 4327 } 4328 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 4329 4330 static const struct bin_attribute *const bin_flash_attrs[] = { 4331 &psp_vbflash_bin_attr, 4332 NULL 4333 }; 4334 4335 static struct attribute *flash_attrs[] = { 4336 &dev_attr_psp_vbflash_status.attr, 4337 &dev_attr_usbc_pd_fw.attr, 4338 NULL 4339 }; 4340 4341 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 4342 { 4343 struct device *dev = kobj_to_dev(kobj); 4344 struct drm_device *ddev = dev_get_drvdata(dev); 4345 struct amdgpu_device *adev = drm_to_adev(ddev); 4346 4347 if (attr == &dev_attr_usbc_pd_fw.attr) 4348 return adev->psp.sup_pd_fw_up ? 0660 : 0; 4349 4350 return adev->psp.sup_ifwi_up ? 0440 : 0; 4351 } 4352 4353 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, 4354 const struct bin_attribute *attr, 4355 int idx) 4356 { 4357 struct device *dev = kobj_to_dev(kobj); 4358 struct drm_device *ddev = dev_get_drvdata(dev); 4359 struct amdgpu_device *adev = drm_to_adev(ddev); 4360 4361 return adev->psp.sup_ifwi_up ? 0660 : 0; 4362 } 4363 4364 const struct attribute_group amdgpu_flash_attr_group = { 4365 .attrs = flash_attrs, 4366 .bin_attrs = bin_flash_attrs, 4367 .is_bin_visible = amdgpu_bin_flash_attr_is_visible, 4368 .is_visible = amdgpu_flash_attr_is_visible, 4369 }; 4370 4371 #if defined(CONFIG_DEBUG_FS) 4372 static int psp_read_spirom_debugfs_open(struct inode *inode, struct file *filp) 4373 { 4374 struct amdgpu_device *adev = filp->f_inode->i_private; 4375 struct spirom_bo *bo_triplet; 4376 int ret; 4377 4378 /* serialize the open() file calling */ 4379 if (!mutex_trylock(&adev->psp.mutex)) 4380 return -EBUSY; 4381 4382 /* 4383 * make sure only one userpace process is alive for dumping so that 4384 * only one memory buffer of AMD_VBIOS_FILE_MAX_SIZE * 2 is consumed. 4385 * let's say the case where one process try opening the file while 4386 * another one has proceeded to read or release. In this way, eliminate 4387 * the use of mutex for read() or release() callback as well. 4388 */ 4389 if (adev->psp.spirom_dump_trip) { 4390 mutex_unlock(&adev->psp.mutex); 4391 return -EBUSY; 4392 } 4393 4394 bo_triplet = kzalloc_obj(struct spirom_bo); 4395 if (!bo_triplet) { 4396 mutex_unlock(&adev->psp.mutex); 4397 return -ENOMEM; 4398 } 4399 4400 ret = amdgpu_bo_create_kernel(adev, AMD_VBIOS_FILE_MAX_SIZE_B * 2, 4401 AMDGPU_GPU_PAGE_SIZE, 4402 AMDGPU_GEM_DOMAIN_GTT, 4403 &bo_triplet->bo, 4404 &bo_triplet->mc_addr, 4405 &bo_triplet->cpu_addr); 4406 if (ret) 4407 goto rel_trip; 4408 4409 ret = psp_dump_spirom(&adev->psp, bo_triplet->mc_addr); 4410 if (ret) 4411 goto rel_bo; 4412 4413 adev->psp.spirom_dump_trip = bo_triplet; 4414 mutex_unlock(&adev->psp.mutex); 4415 return 0; 4416 rel_bo: 4417 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 4418 &bo_triplet->cpu_addr); 4419 rel_trip: 4420 kfree(bo_triplet); 4421 mutex_unlock(&adev->psp.mutex); 4422 dev_err(adev->dev, "Trying IFWI dump fails, err = %d\n", ret); 4423 return ret; 4424 } 4425 4426 static ssize_t psp_read_spirom_debugfs_read(struct file *filp, char __user *buf, size_t size, 4427 loff_t *pos) 4428 { 4429 struct amdgpu_device *adev = filp->f_inode->i_private; 4430 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 4431 4432 if (!bo_triplet) 4433 return -EINVAL; 4434 4435 return simple_read_from_buffer(buf, 4436 size, 4437 pos, bo_triplet->cpu_addr, 4438 AMD_VBIOS_FILE_MAX_SIZE_B * 2); 4439 } 4440 4441 static int psp_read_spirom_debugfs_release(struct inode *inode, struct file *filp) 4442 { 4443 struct amdgpu_device *adev = filp->f_inode->i_private; 4444 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 4445 4446 if (bo_triplet) { 4447 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 4448 &bo_triplet->cpu_addr); 4449 kfree(bo_triplet); 4450 } 4451 4452 adev->psp.spirom_dump_trip = NULL; 4453 return 0; 4454 } 4455 4456 static const struct file_operations psp_dump_spirom_debugfs_ops = { 4457 .owner = THIS_MODULE, 4458 .open = psp_read_spirom_debugfs_open, 4459 .read = psp_read_spirom_debugfs_read, 4460 .release = psp_read_spirom_debugfs_release, 4461 .llseek = default_llseek, 4462 }; 4463 #endif 4464 4465 void amdgpu_psp_debugfs_init(struct amdgpu_device *adev) 4466 { 4467 #if defined(CONFIG_DEBUG_FS) 4468 struct drm_minor *minor = adev_to_drm(adev)->primary; 4469 4470 debugfs_create_file_size("psp_spirom_dump", 0444, minor->debugfs_root, 4471 adev, &psp_dump_spirom_debugfs_ops, AMD_VBIOS_FILE_MAX_SIZE_B * 2); 4472 #endif 4473 } 4474 4475 const struct amd_ip_funcs psp_ip_funcs = { 4476 .name = "psp", 4477 .early_init = psp_early_init, 4478 .sw_init = psp_sw_init, 4479 .sw_fini = psp_sw_fini, 4480 .hw_init = psp_hw_init, 4481 .hw_fini = psp_hw_fini, 4482 .suspend = psp_suspend, 4483 .resume = psp_resume, 4484 .set_clockgating_state = psp_set_clockgating_state, 4485 .set_powergating_state = psp_set_powergating_state, 4486 }; 4487 4488 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 4489 .type = AMD_IP_BLOCK_TYPE_PSP, 4490 .major = 3, 4491 .minor = 1, 4492 .rev = 0, 4493 .funcs = &psp_ip_funcs, 4494 }; 4495 4496 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 4497 .type = AMD_IP_BLOCK_TYPE_PSP, 4498 .major = 10, 4499 .minor = 0, 4500 .rev = 0, 4501 .funcs = &psp_ip_funcs, 4502 }; 4503 4504 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 4505 .type = AMD_IP_BLOCK_TYPE_PSP, 4506 .major = 11, 4507 .minor = 0, 4508 .rev = 0, 4509 .funcs = &psp_ip_funcs, 4510 }; 4511 4512 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 4513 .type = AMD_IP_BLOCK_TYPE_PSP, 4514 .major = 11, 4515 .minor = 0, 4516 .rev = 8, 4517 .funcs = &psp_ip_funcs, 4518 }; 4519 4520 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 4521 .type = AMD_IP_BLOCK_TYPE_PSP, 4522 .major = 12, 4523 .minor = 0, 4524 .rev = 0, 4525 .funcs = &psp_ip_funcs, 4526 }; 4527 4528 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 4529 .type = AMD_IP_BLOCK_TYPE_PSP, 4530 .major = 13, 4531 .minor = 0, 4532 .rev = 0, 4533 .funcs = &psp_ip_funcs, 4534 }; 4535 4536 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 4537 .type = AMD_IP_BLOCK_TYPE_PSP, 4538 .major = 13, 4539 .minor = 0, 4540 .rev = 4, 4541 .funcs = &psp_ip_funcs, 4542 }; 4543 4544 const struct amdgpu_ip_block_version psp_v14_0_ip_block = { 4545 .type = AMD_IP_BLOCK_TYPE_PSP, 4546 .major = 14, 4547 .minor = 0, 4548 .rev = 0, 4549 .funcs = &psp_ip_funcs, 4550 }; 4551 4552 const struct amdgpu_ip_block_version psp_v15_0_ip_block = { 4553 .type = AMD_IP_BLOCK_TYPE_PSP, 4554 .major = 15, 4555 .minor = 0, 4556 .rev = 0, 4557 .funcs = &psp_ip_funcs, 4558 }; 4559 4560 const struct amdgpu_ip_block_version psp_v15_0_8_ip_block = { 4561 .type = AMD_IP_BLOCK_TYPE_PSP, 4562 .major = 15, 4563 .minor = 0, 4564 .rev = 8, 4565 .funcs = &psp_ip_funcs, 4566 }; 4567