1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // es8326.c -- es8326 ALSA SoC audio driver
4 // Copyright Everest Semiconductor Co., Ltd
5 //
6 // Authors: David Yang <yangxiaohua@everest-semi.com>
7 //
8
9 #include <linux/clk.h>
10 #include <linux/i2c.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/module.h>
14 #include <sound/jack.h>
15 #include <sound/pcm_params.h>
16 #include <sound/soc.h>
17 #include <sound/soc-dapm.h>
18 #include <sound/tlv.h>
19 #include "es8326.h"
20
21 struct es8326_priv {
22 struct clk *mclk;
23 struct i2c_client *i2c;
24 struct regmap *regmap;
25 struct snd_soc_component *component;
26 struct delayed_work jack_detect_work;
27 struct delayed_work button_press_work;
28 struct snd_soc_jack *jack;
29 int irq;
30 /* The lock protects the situation that an irq is generated
31 * while enabling or disabling or during an irq.
32 */
33 struct mutex lock;
34 u8 mic1_src;
35 u8 mic2_src;
36 u8 jack_pol;
37 u8 interrupt_src;
38 u8 interrupt_clk;
39 bool jd_inverted;
40 unsigned int sysclk;
41
42 bool calibrated;
43 int version;
44 int hp;
45 int jack_remove_retry;
46 };
47
es8326_crosstalk1_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)48 static int es8326_crosstalk1_get(struct snd_kcontrol *kcontrol,
49 struct snd_ctl_elem_value *ucontrol)
50 {
51 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
52 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
53 unsigned int crosstalk_h, crosstalk_l;
54 unsigned int crosstalk;
55
56 regmap_read(es8326->regmap, ES8326_DAC_RAMPRATE, &crosstalk_h);
57 regmap_read(es8326->regmap, ES8326_DAC_CROSSTALK, &crosstalk_l);
58 crosstalk_h &= 0x20;
59 crosstalk_l &= 0xf0;
60 crosstalk = crosstalk_h >> 1 | crosstalk_l >> 4;
61 ucontrol->value.integer.value[0] = crosstalk;
62
63 return 0;
64 }
65
es8326_crosstalk1_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)66 static int es8326_crosstalk1_set(struct snd_kcontrol *kcontrol,
67 struct snd_ctl_elem_value *ucontrol)
68 {
69 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
70 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
71 unsigned int crosstalk_h, crosstalk_l;
72 unsigned int crosstalk;
73
74 crosstalk = ucontrol->value.integer.value[0];
75 regmap_read(es8326->regmap, ES8326_DAC_CROSSTALK, &crosstalk_l);
76 crosstalk_h = (crosstalk & 0x10) << 1;
77 crosstalk_l &= 0x0f;
78 crosstalk_l |= (crosstalk & 0x0f) << 4;
79 regmap_update_bits(es8326->regmap, ES8326_DAC_RAMPRATE,
80 0x20, crosstalk_h);
81 regmap_write(es8326->regmap, ES8326_DAC_CROSSTALK, crosstalk_l);
82
83 return 0;
84 }
85
es8326_crosstalk2_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)86 static int es8326_crosstalk2_get(struct snd_kcontrol *kcontrol,
87 struct snd_ctl_elem_value *ucontrol)
88 {
89 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
90 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
91 unsigned int crosstalk_h, crosstalk_l;
92 unsigned int crosstalk;
93
94 regmap_read(es8326->regmap, ES8326_DAC_RAMPRATE, &crosstalk_h);
95 regmap_read(es8326->regmap, ES8326_DAC_CROSSTALK, &crosstalk_l);
96 crosstalk_h &= 0x10;
97 crosstalk_l &= 0x0f;
98 crosstalk = crosstalk_h | crosstalk_l;
99 ucontrol->value.integer.value[0] = crosstalk;
100
101 return 0;
102 }
103
es8326_crosstalk2_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)104 static int es8326_crosstalk2_set(struct snd_kcontrol *kcontrol,
105 struct snd_ctl_elem_value *ucontrol)
106 {
107 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
108 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
109 unsigned int crosstalk_h, crosstalk_l;
110 unsigned int crosstalk;
111
112 crosstalk = ucontrol->value.integer.value[0];
113 regmap_read(es8326->regmap, ES8326_DAC_CROSSTALK, &crosstalk_l);
114 crosstalk_h = crosstalk & 0x10;
115 crosstalk_l &= 0xf0;
116 crosstalk_l |= crosstalk & 0x0f;
117 regmap_update_bits(es8326->regmap, ES8326_DAC_RAMPRATE,
118 0x10, crosstalk_h);
119 regmap_write(es8326->regmap, ES8326_DAC_CROSSTALK, crosstalk_l);
120
121 return 0;
122 }
123
124 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(dac_vol_tlv, -9550, 50, 0);
125 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_vol_tlv, -9550, 50, 0);
126 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_analog_pga_tlv, 0, 300, 0);
127 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_pga_tlv, 0, 600, 0);
128 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(softramp_rate, 0, 100, 0);
129 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(drc_target_tlv, -3200, 200, 0);
130 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(drc_recovery_tlv, -125, 250, 0);
131
132 static const char *const winsize[] = {
133 "0.25db/2 LRCK",
134 "0.25db/4 LRCK",
135 "0.25db/8 LRCK",
136 "0.25db/16 LRCK",
137 "0.25db/32 LRCK",
138 "0.25db/64 LRCK",
139 "0.25db/128 LRCK",
140 "0.25db/256 LRCK",
141 "0.25db/512 LRCK",
142 "0.25db/1024 LRCK",
143 "0.25db/2048 LRCK",
144 "0.25db/4096 LRCK",
145 "0.25db/8192 LRCK",
146 "0.25db/16384 LRCK",
147 "0.25db/32768 LRCK",
148 "0.25db/65536 LRCK",
149 };
150
151 static const char *const dacpol_txt[] = {
152 "Normal", "R Invert", "L Invert", "L + R Invert" };
153
154 static const struct soc_enum dacpol =
155 SOC_ENUM_SINGLE(ES8326_DAC_DSM, 4, 4, dacpol_txt);
156 static const struct soc_enum alc_winsize =
157 SOC_ENUM_SINGLE(ES8326_ADC_RAMPRATE, 4, 16, winsize);
158 static const struct soc_enum drc_winsize =
159 SOC_ENUM_SINGLE(ES8326_DRC_WINSIZE, 4, 16, winsize);
160
161 static const struct snd_kcontrol_new es8326_snd_controls[] = {
162 SOC_SINGLE_TLV("DAC Playback Volume", ES8326_DAC_VOL, 0, 0xbf, 0, dac_vol_tlv),
163 SOC_ENUM("Playback Polarity", dacpol),
164 SOC_SINGLE_TLV("DAC Ramp Rate", ES8326_DAC_RAMPRATE, 0, 0x0f, 0, softramp_rate),
165 SOC_SINGLE_TLV("DRC Recovery Level", ES8326_DRC_RECOVERY, 0, 4, 0, drc_recovery_tlv),
166 SOC_ENUM("DRC Winsize", drc_winsize),
167 SOC_SINGLE_TLV("DRC Target Level", ES8326_DRC_WINSIZE, 0, 0x0f, 0, drc_target_tlv),
168
169 SOC_DOUBLE_R_TLV("ADC Capture Volume", ES8326_ADC1_VOL, ES8326_ADC2_VOL, 0, 0xff, 0,
170 adc_vol_tlv),
171 SOC_DOUBLE_TLV("ADC PGA Volume", ES8326_ADC_SCALE, 4, 0, 5, 0, adc_pga_tlv),
172 SOC_SINGLE_TLV("ADC PGA Gain Volume", ES8326_PGAGAIN, 0, 10, 0, adc_analog_pga_tlv),
173 SOC_SINGLE_TLV("ADC Ramp Rate", ES8326_ADC_RAMPRATE, 0, 0x0f, 0, softramp_rate),
174 SOC_SINGLE("ALC Capture Switch", ES8326_ALC_RECOVERY, 3, 1, 0),
175 SOC_SINGLE_TLV("ALC Capture Recovery Level", ES8326_ALC_LEVEL,
176 0, 4, 0, drc_recovery_tlv),
177 SOC_ENUM("ALC Capture Winsize", alc_winsize),
178 SOC_SINGLE_TLV("ALC Capture Target Level", ES8326_ALC_LEVEL,
179 0, 0x0f, 0, drc_target_tlv),
180
181 SOC_SINGLE_EXT("CROSSTALK1", SND_SOC_NOPM, 0, 31, 0,
182 es8326_crosstalk1_get, es8326_crosstalk1_set),
183 SOC_SINGLE_EXT("CROSSTALK2", SND_SOC_NOPM, 0, 31, 0,
184 es8326_crosstalk2_get, es8326_crosstalk2_set),
185 };
186
187 static const struct snd_soc_dapm_widget es8326_dapm_widgets[] = {
188 SND_SOC_DAPM_INPUT("MIC1"),
189 SND_SOC_DAPM_INPUT("MIC2"),
190 SND_SOC_DAPM_INPUT("MIC3"),
191 SND_SOC_DAPM_INPUT("MIC4"),
192
193 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
194 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
195
196 /* Digital Interface */
197 SND_SOC_DAPM_AIF_OUT("I2S OUT", "I2S1 Capture", 0, SND_SOC_NOPM, 0, 0),
198 SND_SOC_DAPM_AIF_IN("I2S IN", "I2S1 Playback", 0, SND_SOC_NOPM, 0, 0),
199
200 /* Analog Power Supply*/
201 SND_SOC_DAPM_DAC("Right DAC", NULL, ES8326_ANA_PDN, 0, 1),
202 SND_SOC_DAPM_DAC("Left DAC", NULL, ES8326_ANA_PDN, 1, 1),
203 SND_SOC_DAPM_SUPPLY("MICBIAS1", ES8326_ANA_MICBIAS, 2, 0, NULL, 0),
204 SND_SOC_DAPM_SUPPLY("MICBIAS2", ES8326_ANA_MICBIAS, 3, 0, NULL, 0),
205
206 SND_SOC_DAPM_PGA("LHPMIX", ES8326_DAC2HPMIX, 7, 0, NULL, 0),
207 SND_SOC_DAPM_PGA("RHPMIX", ES8326_DAC2HPMIX, 3, 0, NULL, 0),
208
209 SND_SOC_DAPM_REG(snd_soc_dapm_supply, "HPOR Supply", ES8326_HP_CAL,
210 4, 7, 0, 0),
211 SND_SOC_DAPM_REG(snd_soc_dapm_supply, "HPOL Supply", ES8326_HP_CAL,
212 0, 7, 0, 0),
213
214 SND_SOC_DAPM_OUTPUT("HPOL"),
215 SND_SOC_DAPM_OUTPUT("HPOR"),
216 };
217
218 static const struct snd_soc_dapm_route es8326_dapm_routes[] = {
219 {"ADC L", NULL, "MIC1"},
220 {"ADC R", NULL, "MIC2"},
221 {"ADC L", NULL, "MIC3"},
222 {"ADC R", NULL, "MIC4"},
223
224 {"I2S OUT", NULL, "ADC L"},
225 {"I2S OUT", NULL, "ADC R"},
226
227 {"Right DAC", NULL, "I2S IN"},
228 {"Left DAC", NULL, "I2S IN"},
229
230 {"LHPMIX", NULL, "Left DAC"},
231 {"RHPMIX", NULL, "Right DAC"},
232
233 {"HPOR", NULL, "HPOR Supply"},
234 {"HPOL", NULL, "HPOL Supply"},
235
236 {"HPOL", NULL, "LHPMIX"},
237 {"HPOR", NULL, "RHPMIX"},
238 };
239
es8326_volatile_register(struct device * dev,unsigned int reg)240 static bool es8326_volatile_register(struct device *dev, unsigned int reg)
241 {
242 switch (reg) {
243 case ES8326_HPL_OFFSET_INI:
244 case ES8326_HPR_OFFSET_INI:
245 case ES8326_HPDET_STA:
246 case ES8326_CTIA_OMTP_STA:
247 case ES8326_CSM_MUTE_STA:
248 return true;
249 default:
250 return false;
251 }
252 }
253
254 static const struct regmap_config es8326_regmap_config = {
255 .reg_bits = 8,
256 .val_bits = 8,
257 .max_register = 0xff,
258 .volatile_reg = es8326_volatile_register,
259 .cache_type = REGCACHE_RBTREE,
260 };
261
262 struct _coeff_div {
263 u16 fs;
264 u32 rate;
265 u32 mclk;
266 u8 reg4;
267 u8 reg5;
268 u8 reg6;
269 u8 reg7;
270 u8 reg8;
271 u8 reg9;
272 u8 rega;
273 u8 regb;
274 };
275
276 /* codec hifi mclk clock divider coefficients */
277 /* {ratio, LRCK, MCLK, REG04, REG05, REG06, REG07, REG08, REG09, REG10, REG11} */
278 static const struct _coeff_div coeff_div_v0[] = {
279 {64, 8000, 512000, 0x60, 0x01, 0x0F, 0x75, 0x0A, 0x1B, 0x1F, 0x7F},
280 {64, 16000, 1024000, 0x20, 0x00, 0x33, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
281 {64, 44100, 2822400, 0xE0, 0x00, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
282 {64, 48000, 3072000, 0xE0, 0x00, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
283 {128, 8000, 1024000, 0x60, 0x00, 0x33, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
284 {128, 16000, 2048000, 0x20, 0x00, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
285 {128, 44100, 5644800, 0xE0, 0x01, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
286 {128, 48000, 6144000, 0xE0, 0x01, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
287
288 {192, 32000, 6144000, 0xE0, 0x02, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
289 {256, 8000, 2048000, 0x60, 0x00, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
290 {256, 16000, 4096000, 0x20, 0x01, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
291 {256, 44100, 11289600, 0xE0, 0x00, 0x30, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
292 {256, 48000, 12288000, 0xE0, 0x00, 0x30, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
293 {384, 32000, 12288000, 0xE0, 0x05, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
294 {400, 48000, 19200000, 0xE9, 0x04, 0x0F, 0x6d, 0x4A, 0x0A, 0x1F, 0x1F},
295
296 {500, 48000, 24000000, 0xF8, 0x04, 0x3F, 0x6D, 0x4A, 0x0A, 0x1F, 0x1F},
297 {512, 8000, 4096000, 0x60, 0x01, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
298 {512, 16000, 8192000, 0x20, 0x00, 0x30, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
299 {512, 44100, 22579200, 0xE0, 0x00, 0x00, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
300 {512, 48000, 24576000, 0xE0, 0x00, 0x00, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
301 {768, 32000, 24576000, 0xE0, 0x02, 0x30, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
302 {1024, 8000, 8192000, 0x60, 0x00, 0x30, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
303 {1024, 16000, 16384000, 0x20, 0x00, 0x00, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
304 };
305
306 static const struct _coeff_div coeff_div_v3[] = {
307 {32, 8000, 256000, 0x60, 0x00, 0x0F, 0x75, 0x8A, 0x1B, 0x1F, 0x7F},
308 {32, 16000, 512000, 0x20, 0x00, 0x0D, 0x75, 0x8A, 0x1B, 0x1F, 0x3F},
309 {32, 44100, 1411200, 0x00, 0x00, 0x13, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F},
310 {32, 48000, 1536000, 0x00, 0x00, 0x13, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F},
311 {36, 8000, 288000, 0x20, 0x00, 0x0D, 0x75, 0x8A, 0x1B, 0x23, 0x47},
312 {36, 16000, 576000, 0x20, 0x00, 0x0D, 0x75, 0x8A, 0x1B, 0x23, 0x47},
313 {48, 8000, 384000, 0x60, 0x02, 0x1F, 0x75, 0x8A, 0x1B, 0x1F, 0x7F},
314 {48, 16000, 768000, 0x20, 0x02, 0x0F, 0x75, 0x8A, 0x1B, 0x1F, 0x3F},
315 {48, 48000, 2304000, 0x00, 0x02, 0x0D, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F},
316
317 {64, 8000, 512000, 0x60, 0x00, 0x35, 0x75, 0x8A, 0x1B, 0x1F, 0x7F},
318 {64, 16000, 1024000, 0x20, 0x00, 0x05, 0x75, 0x8A, 0x1B, 0x1F, 0x3F},
319 {64, 44100, 2822400, 0xE0, 0x00, 0x31, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F},
320 {64, 48000, 3072000, 0xE0, 0x00, 0x31, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F},
321 {72, 8000, 576000, 0x20, 0x00, 0x13, 0x35, 0x8A, 0x1B, 0x23, 0x47},
322 {72, 16000, 1152000, 0x20, 0x00, 0x05, 0x75, 0x8A, 0x1B, 0x23, 0x47},
323 {96, 8000, 768000, 0x60, 0x02, 0x1D, 0x75, 0x8A, 0x1B, 0x1F, 0x7F},
324 {96, 16000, 1536000, 0x20, 0x02, 0x0D, 0x75, 0x8A, 0x1B, 0x1F, 0x3F},
325 {100, 48000, 4800000, 0x04, 0x04, 0x3F, 0x6D, 0xB8, 0x08, 0x4f, 0x1f},
326 {125, 48000, 6000000, 0x04, 0x04, 0x1F, 0x2D, 0x8A, 0x0A, 0x27, 0x27},
327
328 {128, 8000, 1024000, 0x60, 0x00, 0x05, 0x75, 0x8A, 0x1B, 0x1F, 0x7F},
329 {128, 16000, 2048000, 0x20, 0x00, 0x31, 0x35, 0x8A, 0x1B, 0x1F, 0x3F},
330 {128, 44100, 5644800, 0xE0, 0x00, 0x01, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F},
331 {128, 48000, 6144000, 0xE0, 0x00, 0x01, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F},
332 {144, 8000, 1152000, 0x20, 0x00, 0x03, 0x35, 0x8A, 0x1B, 0x23, 0x47},
333 {144, 16000, 2304000, 0x20, 0x00, 0x11, 0x35, 0x8A, 0x1B, 0x23, 0x47},
334 {192, 8000, 1536000, 0x60, 0x02, 0x0D, 0x75, 0x8A, 0x1B, 0x1F, 0x7F},
335 {192, 32000, 6144000, 0xE0, 0x02, 0x31, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F},
336 {192, 16000, 3072000, 0x20, 0x02, 0x05, 0x75, 0xCA, 0x1B, 0x1F, 0x3F},
337
338 {200, 48000, 9600000, 0x04, 0x04, 0x0F, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F},
339 {250, 48000, 12000000, 0x04, 0x04, 0x0F, 0x2D, 0xCA, 0x0A, 0x27, 0x27},
340 {256, 8000, 2048000, 0x60, 0x00, 0x31, 0x35, 0x8A, 0x1B, 0x1F, 0x7F},
341 {256, 16000, 4096000, 0x20, 0x00, 0x01, 0x35, 0x8A, 0x1B, 0x1F, 0x3F},
342 {256, 44100, 11289600, 0xE0, 0x00, 0x30, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F},
343 {256, 48000, 12288000, 0xE0, 0x00, 0x30, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F},
344 {288, 8000, 2304000, 0x20, 0x00, 0x01, 0x35, 0x8A, 0x1B, 0x23, 0x47},
345 {384, 8000, 3072000, 0x60, 0x02, 0x05, 0x75, 0x8A, 0x1B, 0x1F, 0x7F},
346 {384, 16000, 6144000, 0x20, 0x02, 0x03, 0x35, 0x8A, 0x1B, 0x1F, 0x3F},
347 {384, 32000, 12288000, 0xE0, 0x02, 0x01, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F},
348 {384, 48000, 18432000, 0x00, 0x02, 0x01, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F},
349
350 {400, 48000, 19200000, 0xE4, 0x04, 0x35, 0x6d, 0xCA, 0x0A, 0x1F, 0x1F},
351 {500, 48000, 24000000, 0xF8, 0x04, 0x3F, 0x6D, 0xCA, 0x0A, 0x1F, 0x1F},
352 {512, 8000, 4096000, 0x60, 0x00, 0x01, 0x35, 0x8A, 0x1B, 0x1F, 0x7F},
353 {512, 16000, 8192000, 0x20, 0x00, 0x30, 0x35, 0x8A, 0x1B, 0x1F, 0x3F},
354 {512, 44100, 22579200, 0xE0, 0x00, 0x00, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F},
355 {512, 48000, 24576000, 0xE0, 0x00, 0x00, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F},
356 {768, 8000, 6144000, 0x60, 0x02, 0x11, 0x35, 0x8A, 0x1B, 0x1F, 0x7F},
357 {768, 16000, 12288000, 0x20, 0x02, 0x01, 0x35, 0x8A, 0x1B, 0x1F, 0x3F},
358 {768, 32000, 24576000, 0xE0, 0x02, 0x30, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F},
359 {800, 48000, 38400000, 0x00, 0x18, 0x13, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F},
360
361 {1024, 8000, 8192000, 0x60, 0x00, 0x30, 0x35, 0x8A, 0x1B, 0x1F, 0x7F},
362 {1024, 16000, 16384000, 0x20, 0x00, 0x00, 0x35, 0x8A, 0x1B, 0x1F, 0x3F},
363 {1152, 16000, 18432000, 0x20, 0x08, 0x11, 0x35, 0x8A, 0x1B, 0x1F, 0x3F},
364 {1536, 8000, 12288000, 0x60, 0x02, 0x01, 0x35, 0x8A, 0x1B, 0x1F, 0x7F},
365 {1536, 16000, 24576000, 0x20, 0x02, 0x10, 0x35, 0x8A, 0x1B, 0x1F, 0x3F},
366 {1625, 8000, 13000000, 0x0C, 0x18, 0x1F, 0x2D, 0x8A, 0x0A, 0x27, 0x27},
367 {1625, 16000, 26000000, 0x0C, 0x18, 0x1F, 0x2D, 0x8A, 0x0A, 0x27, 0x27},
368 {2048, 8000, 16384000, 0x60, 0x00, 0x00, 0x35, 0x8A, 0x1B, 0x1F, 0x7F},
369 {2304, 8000, 18432000, 0x40, 0x02, 0x10, 0x35, 0x8A, 0x1B, 0x1F, 0x5F},
370 {3072, 8000, 24576000, 0x60, 0x02, 0x10, 0x35, 0x8A, 0x1B, 0x1F, 0x7F},
371 {3250, 8000, 26000000, 0x0C, 0x18, 0x0F, 0x2D, 0x8A, 0x0A, 0x27, 0x27},
372 };
373
get_coeff(int mclk,int rate,int array,const struct _coeff_div * coeff_div)374 static inline int get_coeff(int mclk, int rate, int array,
375 const struct _coeff_div *coeff_div)
376 {
377 int i;
378
379 for (i = 0; i < array; i++) {
380 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
381 return i;
382 }
383
384 return -EINVAL;
385 }
386
es8326_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)387 static int es8326_set_dai_sysclk(struct snd_soc_dai *codec_dai,
388 int clk_id, unsigned int freq, int dir)
389 {
390 struct snd_soc_component *codec = codec_dai->component;
391 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(codec);
392
393 es8326->sysclk = freq;
394
395 return 0;
396 }
397
es8326_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)398 static int es8326_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
399 {
400 struct snd_soc_component *component = codec_dai->component;
401 u8 iface = 0;
402
403 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
404 case SND_SOC_DAIFMT_CBC_CFP:
405 snd_soc_component_update_bits(component, ES8326_RESET,
406 ES8326_MASTER_MODE_EN, ES8326_MASTER_MODE_EN);
407 break;
408 case SND_SOC_DAIFMT_CBC_CFC:
409 break;
410 default:
411 return -EINVAL;
412 }
413
414 /* interface format */
415 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
416 case SND_SOC_DAIFMT_I2S:
417 break;
418 case SND_SOC_DAIFMT_RIGHT_J:
419 dev_err(component->dev, "Codec driver does not support right justified\n");
420 return -EINVAL;
421 case SND_SOC_DAIFMT_LEFT_J:
422 iface |= ES8326_DAIFMT_LEFT_J;
423 break;
424 case SND_SOC_DAIFMT_DSP_A:
425 iface |= ES8326_DAIFMT_DSP_A;
426 break;
427 case SND_SOC_DAIFMT_DSP_B:
428 iface |= ES8326_DAIFMT_DSP_B;
429 break;
430 default:
431 return -EINVAL;
432 }
433
434 snd_soc_component_update_bits(component, ES8326_FMT, ES8326_DAIFMT_MASK, iface);
435
436 return 0;
437 }
438
es8326_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)439 static int es8326_pcm_hw_params(struct snd_pcm_substream *substream,
440 struct snd_pcm_hw_params *params,
441 struct snd_soc_dai *dai)
442 {
443 struct snd_soc_component *component = dai->component;
444 const struct _coeff_div *coeff_div;
445 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
446 u8 srate = 0;
447 int coeff, array;
448
449 if (es8326->version == 0) {
450 coeff_div = coeff_div_v0;
451 array = ARRAY_SIZE(coeff_div_v0);
452 } else {
453 coeff_div = coeff_div_v3;
454 array = ARRAY_SIZE(coeff_div_v3);
455 }
456 coeff = get_coeff(es8326->sysclk, params_rate(params), array, coeff_div);
457 /* bit size */
458 switch (params_format(params)) {
459 case SNDRV_PCM_FORMAT_S16_LE:
460 srate |= ES8326_S16_LE;
461 break;
462 case SNDRV_PCM_FORMAT_S20_3LE:
463 srate |= ES8326_S20_3_LE;
464 break;
465 case SNDRV_PCM_FORMAT_S18_3LE:
466 srate |= ES8326_S18_LE;
467 break;
468 case SNDRV_PCM_FORMAT_S24_LE:
469 srate |= ES8326_S24_LE;
470 break;
471 case SNDRV_PCM_FORMAT_S32_LE:
472 srate |= ES8326_S32_LE;
473 break;
474 default:
475 return -EINVAL;
476 }
477
478 /* set iface & srate */
479 snd_soc_component_update_bits(component, ES8326_FMT, ES8326_DATA_LEN_MASK, srate);
480
481 if (coeff >= 0) {
482 regmap_write(es8326->regmap, ES8326_CLK_DIV1,
483 coeff_div[coeff].reg4);
484 regmap_write(es8326->regmap, ES8326_CLK_DIV2,
485 coeff_div[coeff].reg5);
486 regmap_write(es8326->regmap, ES8326_CLK_DLL,
487 coeff_div[coeff].reg6);
488 regmap_write(es8326->regmap, ES8326_CLK_MUX,
489 coeff_div[coeff].reg7);
490 regmap_write(es8326->regmap, ES8326_CLK_ADC_SEL,
491 coeff_div[coeff].reg8);
492 regmap_write(es8326->regmap, ES8326_CLK_DAC_SEL,
493 coeff_div[coeff].reg9);
494 regmap_write(es8326->regmap, ES8326_CLK_ADC_OSR,
495 coeff_div[coeff].rega);
496 regmap_write(es8326->regmap, ES8326_CLK_DAC_OSR,
497 coeff_div[coeff].regb);
498 } else {
499 dev_warn(component->dev, "Clock coefficients do not match");
500 }
501
502 return 0;
503 }
504
es8326_mute(struct snd_soc_dai * dai,int mute,int direction)505 static int es8326_mute(struct snd_soc_dai *dai, int mute, int direction)
506 {
507 struct snd_soc_component *component = dai->component;
508 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
509 unsigned int offset_l, offset_r;
510
511 if (mute) {
512 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
513 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF);
514 regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE,
515 ES8326_MUTE_MASK, ES8326_MUTE);
516 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF,
517 0x30, 0x00);
518 } else {
519 regmap_update_bits(es8326->regmap, ES8326_ADC_MUTE,
520 0x0F, 0x0F);
521 }
522 } else {
523 if (!es8326->calibrated) {
524 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_FORCE_CAL);
525 msleep(30);
526 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF);
527 regmap_read(es8326->regmap, ES8326_HPL_OFFSET_INI, &offset_l);
528 regmap_read(es8326->regmap, ES8326_HPR_OFFSET_INI, &offset_r);
529 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, 0x8c);
530 regmap_write(es8326->regmap, ES8326_HPL_OFFSET_INI, offset_l);
531 regmap_write(es8326->regmap, ES8326_HPR_OFFSET_INI, offset_r);
532 es8326->calibrated = true;
533 }
534 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
535 regmap_update_bits(es8326->regmap, ES8326_DAC_DSM, 0x01, 0x01);
536 usleep_range(1000, 5000);
537 regmap_update_bits(es8326->regmap, ES8326_DAC_DSM, 0x01, 0x00);
538 usleep_range(1000, 5000);
539 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 0x30, 0x20);
540 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 0x30, 0x30);
541 regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xa1);
542 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_ON);
543 regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE,
544 ES8326_MUTE_MASK, ~(ES8326_MUTE));
545 } else {
546 msleep(300);
547 regmap_update_bits(es8326->regmap, ES8326_ADC_MUTE,
548 0x0F, 0x00);
549 }
550 }
551 return 0;
552 }
553
es8326_set_bias_level(struct snd_soc_component * codec,enum snd_soc_bias_level level)554 static int es8326_set_bias_level(struct snd_soc_component *codec,
555 enum snd_soc_bias_level level)
556 {
557 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(codec);
558 int ret;
559
560 switch (level) {
561 case SND_SOC_BIAS_ON:
562 ret = clk_prepare_enable(es8326->mclk);
563 if (ret)
564 return ret;
565
566 regmap_update_bits(es8326->regmap, ES8326_RESET, 0x02, 0x02);
567 usleep_range(5000, 10000);
568 regmap_write(es8326->regmap, ES8326_INTOUT_IO, es8326->interrupt_clk);
569 regmap_write(es8326->regmap, ES8326_SDINOUT1_IO,
570 (ES8326_IO_DMIC_CLK << ES8326_SDINOUT1_SHIFT));
571 regmap_write(es8326->regmap, ES8326_PGA_PDN, 0x40);
572 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x00);
573 regmap_update_bits(es8326->regmap, ES8326_CLK_CTL, 0x20, 0x20);
574 regmap_update_bits(es8326->regmap, ES8326_RESET, 0x02, 0x00);
575 break;
576 case SND_SOC_BIAS_PREPARE:
577 break;
578 case SND_SOC_BIAS_STANDBY:
579 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x3b);
580 regmap_update_bits(es8326->regmap, ES8326_CLK_CTL, 0x20, 0x00);
581 regmap_write(es8326->regmap, ES8326_SDINOUT1_IO, ES8326_IO_INPUT);
582 break;
583 case SND_SOC_BIAS_OFF:
584 clk_disable_unprepare(es8326->mclk);
585 break;
586 }
587
588 return 0;
589 }
590
591 #define es8326_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
592 SNDRV_PCM_FMTBIT_S24_LE)
593
594 static const struct snd_soc_dai_ops es8326_ops = {
595 .hw_params = es8326_pcm_hw_params,
596 .set_fmt = es8326_set_dai_fmt,
597 .set_sysclk = es8326_set_dai_sysclk,
598 .mute_stream = es8326_mute,
599 .no_capture_mute = 0,
600 };
601
602 static struct snd_soc_dai_driver es8326_dai = {
603 .name = "ES8326 HiFi",
604 .playback = {
605 .stream_name = "Playback",
606 .channels_min = 1,
607 .channels_max = 2,
608 .rates = SNDRV_PCM_RATE_8000_48000,
609 .formats = es8326_FORMATS,
610 },
611 .capture = {
612 .stream_name = "Capture",
613 .channels_min = 1,
614 .channels_max = 2,
615 .rates = SNDRV_PCM_RATE_8000_48000,
616 .formats = es8326_FORMATS,
617 },
618 .ops = &es8326_ops,
619 .symmetric_rate = 1,
620 };
621
es8326_enable_micbias(struct snd_soc_component * component)622 static void es8326_enable_micbias(struct snd_soc_component *component)
623 {
624 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
625
626 snd_soc_dapm_mutex_lock(dapm);
627 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS1");
628 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS2");
629 snd_soc_dapm_sync_unlocked(dapm);
630 snd_soc_dapm_mutex_unlock(dapm);
631 }
632
es8326_disable_micbias(struct snd_soc_component * component)633 static void es8326_disable_micbias(struct snd_soc_component *component)
634 {
635 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
636
637 snd_soc_dapm_mutex_lock(dapm);
638 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS1");
639 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS2");
640 snd_soc_dapm_sync_unlocked(dapm);
641 snd_soc_dapm_mutex_unlock(dapm);
642 }
643
644 /*
645 * For button detection, set the following in soundcard
646 * snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
647 * snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOLUMEUP);
648 * snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEDOWN);
649 */
es8326_jack_button_handler(struct work_struct * work)650 static void es8326_jack_button_handler(struct work_struct *work)
651 {
652 struct es8326_priv *es8326 =
653 container_of(work, struct es8326_priv, button_press_work.work);
654 struct snd_soc_component *comp = es8326->component;
655 unsigned int iface;
656 static int button_to_report, press_count;
657 static int prev_button, cur_button;
658
659 if (!(es8326->jack->status & SND_JACK_HEADSET)) /* Jack unplugged */
660 return;
661
662 mutex_lock(&es8326->lock);
663 iface = snd_soc_component_read(comp, ES8326_HPDET_STA);
664 switch (iface) {
665 case 0x93:
666 /* pause button detected */
667 cur_button = SND_JACK_BTN_0;
668 break;
669 case 0x6f:
670 case 0x4b:
671 /* button volume up */
672 cur_button = SND_JACK_BTN_1;
673 break;
674 case 0x27:
675 /* button volume down */
676 cur_button = SND_JACK_BTN_2;
677 break;
678 case 0x1e:
679 case 0xe2:
680 /* button released or not pressed */
681 cur_button = 0;
682 break;
683 default:
684 break;
685 }
686
687 if ((prev_button == cur_button) && (cur_button != 0)) {
688 press_count++;
689 if (press_count > 3) {
690 /* report a press every 120ms */
691 snd_soc_jack_report(es8326->jack, cur_button,
692 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2);
693 press_count = 0;
694 }
695 button_to_report = cur_button;
696 queue_delayed_work(system_wq, &es8326->button_press_work,
697 msecs_to_jiffies(35));
698 } else if (prev_button != cur_button) {
699 /* mismatch, detect again */
700 prev_button = cur_button;
701 queue_delayed_work(system_wq, &es8326->button_press_work,
702 msecs_to_jiffies(35));
703 } else {
704 /* released or no pressed */
705 if (button_to_report != 0) {
706 snd_soc_jack_report(es8326->jack, button_to_report,
707 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2);
708 snd_soc_jack_report(es8326->jack, 0,
709 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2);
710 button_to_report = 0;
711 }
712 }
713 mutex_unlock(&es8326->lock);
714 }
715
es8326_jack_detect_handler(struct work_struct * work)716 static void es8326_jack_detect_handler(struct work_struct *work)
717 {
718 struct es8326_priv *es8326 =
719 container_of(work, struct es8326_priv, jack_detect_work.work);
720 struct snd_soc_component *comp = es8326->component;
721 unsigned int iface;
722
723 mutex_lock(&es8326->lock);
724 iface = snd_soc_component_read(comp, ES8326_HPDET_STA);
725 dev_dbg(comp->dev, "gpio flag %#04x", iface);
726
727 if ((es8326->jack_remove_retry == 1) && (es8326->version != ES8326_VERSION_B)) {
728 if (iface & ES8326_HPINSERT_FLAG)
729 es8326->jack_remove_retry = 2;
730 else
731 es8326->jack_remove_retry = 0;
732
733 dev_dbg(comp->dev, "remove event check, set HPJACK_POL normal, cnt = %d\n",
734 es8326->jack_remove_retry);
735 /*
736 * Inverted HPJACK_POL bit to trigger one IRQ to double check HP Removal event
737 */
738 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE,
739 ES8326_HP_DET_JACK_POL, (es8326->jd_inverted ?
740 ~es8326->jack_pol : es8326->jack_pol));
741 goto exit;
742 }
743
744 if ((iface & ES8326_HPINSERT_FLAG) == 0) {
745 /* Jack unplugged or spurious IRQ */
746 dev_dbg(comp->dev, "No headset detected\n");
747 es8326_disable_micbias(es8326->component);
748 if (es8326->jack->status & SND_JACK_HEADPHONE) {
749 dev_dbg(comp->dev, "Report hp remove event\n");
750 snd_soc_jack_report(es8326->jack, 0, SND_JACK_HEADSET);
751 /* mute adc when mic path switch */
752 regmap_write(es8326->regmap, ES8326_ADC_SCALE, 0x33);
753 regmap_write(es8326->regmap, ES8326_ADC1_SRC, 0x44);
754 regmap_write(es8326->regmap, ES8326_ADC2_SRC, 0x66);
755 es8326->hp = 0;
756 }
757 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x01);
758 regmap_write(es8326->regmap, ES8326_SYS_BIAS, 0x0a);
759 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 0x0f, 0x03);
760 /*
761 * Inverted HPJACK_POL bit to trigger one IRQ to double check HP Removal event
762 */
763 if ((es8326->jack_remove_retry == 0) && (es8326->version != ES8326_VERSION_B)) {
764 es8326->jack_remove_retry = 1;
765 dev_dbg(comp->dev, "remove event check, invert HPJACK_POL, cnt = %d\n",
766 es8326->jack_remove_retry);
767 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE,
768 ES8326_HP_DET_JACK_POL, (es8326->jd_inverted ?
769 es8326->jack_pol : ~es8326->jack_pol));
770
771 } else {
772 es8326->jack_remove_retry = 0;
773 }
774 } else if ((iface & ES8326_HPINSERT_FLAG) == ES8326_HPINSERT_FLAG) {
775 es8326->jack_remove_retry = 0;
776 if (es8326->hp == 0) {
777 dev_dbg(comp->dev, "First insert, start OMTP/CTIA type check\n");
778 /*
779 * set auto-check mode, then restart jack_detect_work after 400ms.
780 * Don't report jack status.
781 */
782 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x01);
783 es8326_enable_micbias(es8326->component);
784 usleep_range(50000, 70000);
785 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x00);
786 regmap_write(es8326->regmap, ES8326_SYS_BIAS, 0x1f);
787 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 0x0f, 0x08);
788 queue_delayed_work(system_wq, &es8326->jack_detect_work,
789 msecs_to_jiffies(400));
790 es8326->hp = 1;
791 goto exit;
792 }
793 if (es8326->jack->status & SND_JACK_HEADSET) {
794 /* detect button */
795 dev_dbg(comp->dev, "button pressed\n");
796 queue_delayed_work(system_wq, &es8326->button_press_work, 10);
797 goto exit;
798 }
799 if ((iface & ES8326_HPBUTTON_FLAG) == 0x01) {
800 dev_dbg(comp->dev, "Headphone detected\n");
801 snd_soc_jack_report(es8326->jack,
802 SND_JACK_HEADPHONE, SND_JACK_HEADSET);
803 } else {
804 dev_dbg(comp->dev, "Headset detected\n");
805 snd_soc_jack_report(es8326->jack,
806 SND_JACK_HEADSET, SND_JACK_HEADSET);
807
808 regmap_write(es8326->regmap, ES8326_ADC_SCALE, 0x33);
809 regmap_update_bits(es8326->regmap, ES8326_PGA_PDN,
810 0x08, 0x08);
811 regmap_update_bits(es8326->regmap, ES8326_PGAGAIN,
812 0x80, 0x80);
813 regmap_write(es8326->regmap, ES8326_ADC1_SRC, 0x00);
814 regmap_write(es8326->regmap, ES8326_ADC2_SRC, 0x00);
815 regmap_update_bits(es8326->regmap, ES8326_PGA_PDN,
816 0x08, 0x00);
817 usleep_range(10000, 15000);
818 }
819 }
820 exit:
821 mutex_unlock(&es8326->lock);
822 }
823
es8326_irq(int irq,void * dev_id)824 static irqreturn_t es8326_irq(int irq, void *dev_id)
825 {
826 struct es8326_priv *es8326 = dev_id;
827
828 if (!es8326->jack)
829 goto out;
830
831 if (es8326->jack->status & SND_JACK_HEADSET)
832 queue_delayed_work(system_wq, &es8326->jack_detect_work,
833 msecs_to_jiffies(10));
834 else
835 queue_delayed_work(system_wq, &es8326->jack_detect_work,
836 msecs_to_jiffies(300));
837
838 out:
839 return IRQ_HANDLED;
840 }
841
es8326_calibrate(struct snd_soc_component * component)842 static int es8326_calibrate(struct snd_soc_component *component)
843 {
844 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
845 unsigned int reg;
846 unsigned int offset_l, offset_r;
847
848 regmap_read(es8326->regmap, ES8326_CHIP_VERSION, ®);
849 es8326->version = reg;
850
851 if ((es8326->version == ES8326_VERSION_B) && (es8326->calibrated == false)) {
852 dev_dbg(component->dev, "ES8326_VERSION_B, calibrating\n");
853 regmap_write(es8326->regmap, ES8326_CLK_INV, 0xc0);
854 regmap_write(es8326->regmap, ES8326_CLK_DIV1, 0x03);
855 regmap_write(es8326->regmap, ES8326_CLK_DLL, 0x30);
856 regmap_write(es8326->regmap, ES8326_CLK_MUX, 0xed);
857 regmap_write(es8326->regmap, ES8326_CLK_DAC_SEL, 0x08);
858 regmap_write(es8326->regmap, ES8326_CLK_TRI, 0xc1);
859 regmap_write(es8326->regmap, ES8326_DAC_MUTE, 0x03);
860 regmap_write(es8326->regmap, ES8326_ANA_VSEL, 0x7f);
861 regmap_write(es8326->regmap, ES8326_VMIDLOW, 0x23);
862 regmap_write(es8326->regmap, ES8326_DAC2HPMIX, 0x88);
863 usleep_range(15000, 20000);
864 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, 0x8c);
865 usleep_range(15000, 20000);
866 regmap_write(es8326->regmap, ES8326_RESET, 0xc0);
867 usleep_range(15000, 20000);
868
869 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, ES8326_HP_OFF);
870 regmap_read(es8326->regmap, ES8326_CSM_MUTE_STA, ®);
871 if ((reg & 0xf0) != 0x40)
872 msleep(50);
873
874 regmap_write(es8326->regmap, ES8326_HP_CAL, 0xd4);
875 msleep(200);
876 regmap_write(es8326->regmap, ES8326_HP_CAL, 0x4d);
877 msleep(200);
878 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF);
879 regmap_read(es8326->regmap, ES8326_HPL_OFFSET_INI, &offset_l);
880 regmap_read(es8326->regmap, ES8326_HPR_OFFSET_INI, &offset_r);
881 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, 0x8c);
882 regmap_write(es8326->regmap, ES8326_HPL_OFFSET_INI, offset_l);
883 regmap_write(es8326->regmap, ES8326_HPR_OFFSET_INI, offset_r);
884 regmap_write(es8326->regmap, ES8326_CLK_INV, 0x00);
885
886 es8326->calibrated = true;
887 }
888
889 return 0;
890 }
891
es8326_resume(struct snd_soc_component * component)892 static int es8326_resume(struct snd_soc_component *component)
893 {
894 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
895
896 regcache_cache_only(es8326->regmap, false);
897 regcache_sync(es8326->regmap);
898
899 /* reset internal clock state */
900 regmap_write(es8326->regmap, ES8326_RESET, 0x1f);
901 regmap_write(es8326->regmap, ES8326_VMIDSEL, 0x0E);
902 regmap_write(es8326->regmap, ES8326_ANA_LP, 0xf0);
903 usleep_range(10000, 15000);
904 regmap_write(es8326->regmap, ES8326_HPJACK_TIMER, 0xe9);
905 regmap_write(es8326->regmap, ES8326_ANA_MICBIAS, 0xcb);
906 /* set headphone default type and detect pin */
907 regmap_write(es8326->regmap, ES8326_HPDET_TYPE, 0x83);
908 regmap_write(es8326->regmap, ES8326_CLK_RESAMPLE, 0x05);
909
910 /* set internal oscillator as clock source of headpone cp */
911 regmap_write(es8326->regmap, ES8326_CLK_DIV_CPC, 0x89);
912 regmap_write(es8326->regmap, ES8326_CLK_CTL, ES8326_CLK_ON);
913 /* clock manager reset release */
914 regmap_write(es8326->regmap, ES8326_RESET, 0x17);
915 /* set headphone detection as half scan mode */
916 regmap_write(es8326->regmap, ES8326_HP_MISC, 0x3d);
917 regmap_write(es8326->regmap, ES8326_PULLUP_CTL, 0x00);
918
919 /* enable headphone driver */
920 regmap_write(es8326->regmap, ES8326_HP_VOL, 0xc4);
921 regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xa7);
922 usleep_range(2000, 5000);
923 regmap_write(es8326->regmap, ES8326_HP_DRIVER_REF, 0x23);
924 regmap_write(es8326->regmap, ES8326_HP_DRIVER_REF, 0x33);
925 regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xa1);
926
927 regmap_write(es8326->regmap, ES8326_CLK_INV, 0x00);
928 regmap_write(es8326->regmap, ES8326_CLK_VMIDS1, 0xc4);
929 regmap_write(es8326->regmap, ES8326_CLK_VMIDS2, 0x81);
930 regmap_write(es8326->regmap, ES8326_CLK_CAL_TIME, 0x00);
931 /* calibrate for B version */
932 es8326_calibrate(component);
933 regmap_write(es8326->regmap, ES8326_DAC_CROSSTALK, 0xaa);
934 regmap_write(es8326->regmap, ES8326_DAC_RAMPRATE, 0x00);
935 /* turn off headphone out */
936 regmap_write(es8326->regmap, ES8326_HP_CAL, 0x00);
937 /* set ADC and DAC in low power mode */
938 regmap_write(es8326->regmap, ES8326_ANA_LP, 0xf0);
939
940 regmap_write(es8326->regmap, ES8326_ANA_VSEL, 0x7F);
941 /* select vdda as micbias source */
942 regmap_write(es8326->regmap, ES8326_VMIDLOW, 0x23);
943 /* set dac dsmclip = 1 */
944 regmap_write(es8326->regmap, ES8326_DAC_DSM, 0x08);
945 regmap_write(es8326->regmap, ES8326_DAC_VPPSCALE, 0x15);
946
947 regmap_write(es8326->regmap, ES8326_HPDET_TYPE, 0x80 |
948 ((es8326->version == ES8326_VERSION_B) ?
949 (ES8326_HP_DET_SRC_PIN9 | es8326->jack_pol) :
950 (ES8326_HP_DET_SRC_PIN9 | es8326->jack_pol | 0x04)));
951 usleep_range(5000, 10000);
952 es8326_enable_micbias(es8326->component);
953 usleep_range(50000, 70000);
954 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x00);
955 regmap_write(es8326->regmap, ES8326_INT_SOURCE,
956 (ES8326_INT_SRC_PIN9 | ES8326_INT_SRC_BUTTON));
957 regmap_write(es8326->regmap, ES8326_INTOUT_IO,
958 es8326->interrupt_clk);
959 regmap_write(es8326->regmap, ES8326_SDINOUT1_IO,
960 (ES8326_IO_DMIC_CLK << ES8326_SDINOUT1_SHIFT));
961 regmap_write(es8326->regmap, ES8326_SDINOUT23_IO, ES8326_IO_INPUT);
962
963 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x00);
964 regmap_write(es8326->regmap, ES8326_RESET, ES8326_CSM_ON);
965 regmap_update_bits(es8326->regmap, ES8326_PGAGAIN, ES8326_MIC_SEL_MASK,
966 ES8326_MIC1_SEL);
967
968 regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE, ES8326_MUTE_MASK,
969 ES8326_MUTE);
970
971 regmap_write(es8326->regmap, ES8326_ADC_MUTE, 0x0f);
972
973 es8326->jack_remove_retry = 0;
974 es8326->hp = 0;
975 return 0;
976 }
977
es8326_suspend(struct snd_soc_component * component)978 static int es8326_suspend(struct snd_soc_component *component)
979 {
980 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
981
982 cancel_delayed_work_sync(&es8326->jack_detect_work);
983 es8326_disable_micbias(component);
984 es8326->calibrated = false;
985 regmap_write(es8326->regmap, ES8326_CLK_CTL, ES8326_CLK_OFF);
986 regcache_cache_only(es8326->regmap, true);
987 regcache_mark_dirty(es8326->regmap);
988
989 /* reset register value to default */
990 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x01);
991 usleep_range(1000, 3000);
992 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x00);
993 return 0;
994 }
995
es8326_probe(struct snd_soc_component * component)996 static int es8326_probe(struct snd_soc_component *component)
997 {
998 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
999 int ret;
1000
1001 es8326->component = component;
1002 es8326->jd_inverted = device_property_read_bool(component->dev,
1003 "everest,jack-detect-inverted");
1004
1005 ret = device_property_read_u8(component->dev, "everest,mic1-src", &es8326->mic1_src);
1006 if (ret != 0) {
1007 dev_dbg(component->dev, "mic1-src return %d", ret);
1008 es8326->mic1_src = ES8326_ADC_AMIC;
1009 }
1010 dev_dbg(component->dev, "mic1-src %x", es8326->mic1_src);
1011
1012 ret = device_property_read_u8(component->dev, "everest,mic2-src", &es8326->mic2_src);
1013 if (ret != 0) {
1014 dev_dbg(component->dev, "mic2-src return %d", ret);
1015 es8326->mic2_src = ES8326_ADC_DMIC;
1016 }
1017 dev_dbg(component->dev, "mic2-src %x", es8326->mic2_src);
1018
1019 ret = device_property_read_u8(component->dev, "everest,jack-pol", &es8326->jack_pol);
1020 if (ret != 0) {
1021 dev_dbg(component->dev, "jack-pol return %d", ret);
1022 es8326->jack_pol = ES8326_HP_TYPE_AUTO;
1023 }
1024 dev_dbg(component->dev, "jack-pol %x", es8326->jack_pol);
1025
1026 ret = device_property_read_u8(component->dev, "everest,interrupt-src",
1027 &es8326->interrupt_src);
1028 if (ret != 0) {
1029 dev_dbg(component->dev, "interrupt-src return %d", ret);
1030 es8326->interrupt_src = ES8326_HP_DET_SRC_PIN9;
1031 }
1032 dev_dbg(component->dev, "interrupt-src %x", es8326->interrupt_src);
1033
1034 ret = device_property_read_u8(component->dev, "everest,interrupt-clk",
1035 &es8326->interrupt_clk);
1036 if (ret != 0) {
1037 dev_dbg(component->dev, "interrupt-clk return %d", ret);
1038 es8326->interrupt_clk = 0x45;
1039 }
1040 dev_dbg(component->dev, "interrupt-clk %x", es8326->interrupt_clk);
1041
1042 es8326_resume(component);
1043 return 0;
1044 }
1045
es8326_enable_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * jack)1046 static void es8326_enable_jack_detect(struct snd_soc_component *component,
1047 struct snd_soc_jack *jack)
1048 {
1049 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
1050
1051 mutex_lock(&es8326->lock);
1052 if (es8326->jd_inverted)
1053 snd_soc_component_update_bits(component, ES8326_HPDET_TYPE,
1054 ES8326_HP_DET_JACK_POL, ~es8326->jack_pol);
1055 es8326->jack = jack;
1056
1057 mutex_unlock(&es8326->lock);
1058 es8326_irq(es8326->irq, es8326);
1059 }
1060
es8326_disable_jack_detect(struct snd_soc_component * component)1061 static void es8326_disable_jack_detect(struct snd_soc_component *component)
1062 {
1063 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
1064
1065 dev_dbg(component->dev, "Enter into %s\n", __func__);
1066 if (!es8326->jack)
1067 return; /* Already disabled (or never enabled) */
1068 cancel_delayed_work_sync(&es8326->jack_detect_work);
1069
1070 mutex_lock(&es8326->lock);
1071 if (es8326->jack->status & SND_JACK_MICROPHONE) {
1072 es8326_disable_micbias(component);
1073 snd_soc_jack_report(es8326->jack, 0, SND_JACK_HEADSET);
1074 }
1075 es8326->jack = NULL;
1076 mutex_unlock(&es8326->lock);
1077 }
1078
es8326_set_jack(struct snd_soc_component * component,struct snd_soc_jack * jack,void * data)1079 static int es8326_set_jack(struct snd_soc_component *component,
1080 struct snd_soc_jack *jack, void *data)
1081 {
1082 if (jack)
1083 es8326_enable_jack_detect(component, jack);
1084 else
1085 es8326_disable_jack_detect(component);
1086
1087 return 0;
1088 }
1089
es8326_remove(struct snd_soc_component * component)1090 static void es8326_remove(struct snd_soc_component *component)
1091 {
1092 es8326_disable_jack_detect(component);
1093 es8326_set_bias_level(component, SND_SOC_BIAS_OFF);
1094 }
1095
1096 static const struct snd_soc_component_driver soc_component_dev_es8326 = {
1097 .probe = es8326_probe,
1098 .remove = es8326_remove,
1099 .resume = es8326_resume,
1100 .suspend = es8326_suspend,
1101 .set_bias_level = es8326_set_bias_level,
1102 .set_jack = es8326_set_jack,
1103 .dapm_widgets = es8326_dapm_widgets,
1104 .num_dapm_widgets = ARRAY_SIZE(es8326_dapm_widgets),
1105 .dapm_routes = es8326_dapm_routes,
1106 .num_dapm_routes = ARRAY_SIZE(es8326_dapm_routes),
1107 .controls = es8326_snd_controls,
1108 .num_controls = ARRAY_SIZE(es8326_snd_controls),
1109 .use_pmdown_time = 1,
1110 .endianness = 1,
1111 };
1112
es8326_i2c_probe(struct i2c_client * i2c)1113 static int es8326_i2c_probe(struct i2c_client *i2c)
1114 {
1115 struct es8326_priv *es8326;
1116 int ret;
1117
1118 es8326 = devm_kzalloc(&i2c->dev, sizeof(struct es8326_priv), GFP_KERNEL);
1119 if (!es8326)
1120 return -ENOMEM;
1121
1122 i2c_set_clientdata(i2c, es8326);
1123 es8326->i2c = i2c;
1124 mutex_init(&es8326->lock);
1125 es8326->regmap = devm_regmap_init_i2c(i2c, &es8326_regmap_config);
1126 if (IS_ERR(es8326->regmap)) {
1127 ret = PTR_ERR(es8326->regmap);
1128 dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
1129 return ret;
1130 }
1131
1132 es8326->irq = i2c->irq;
1133 INIT_DELAYED_WORK(&es8326->jack_detect_work,
1134 es8326_jack_detect_handler);
1135 INIT_DELAYED_WORK(&es8326->button_press_work,
1136 es8326_jack_button_handler);
1137 /* ES8316 is level-based while ES8326 is edge-based */
1138 ret = devm_request_threaded_irq(&i2c->dev, es8326->irq, NULL, es8326_irq,
1139 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1140 "es8326", es8326);
1141 if (ret) {
1142 dev_warn(&i2c->dev, "Failed to request IRQ: %d: %d\n",
1143 es8326->irq, ret);
1144 es8326->irq = -ENXIO;
1145 }
1146
1147 es8326->mclk = devm_clk_get_optional(&i2c->dev, "mclk");
1148 if (IS_ERR(es8326->mclk)) {
1149 dev_err(&i2c->dev, "unable to get mclk\n");
1150 return PTR_ERR(es8326->mclk);
1151 }
1152 if (!es8326->mclk)
1153 dev_warn(&i2c->dev, "assuming static mclk\n");
1154
1155 ret = clk_prepare_enable(es8326->mclk);
1156 if (ret) {
1157 dev_err(&i2c->dev, "unable to enable mclk\n");
1158 return ret;
1159 }
1160 return devm_snd_soc_register_component(&i2c->dev,
1161 &soc_component_dev_es8326,
1162 &es8326_dai, 1);
1163 }
1164
1165 static const struct i2c_device_id es8326_i2c_id[] = {
1166 {"es8326", 0 },
1167 {}
1168 };
1169 MODULE_DEVICE_TABLE(i2c, es8326_i2c_id);
1170
1171 #ifdef CONFIG_OF
1172 static const struct of_device_id es8326_of_match[] = {
1173 { .compatible = "everest,es8326", },
1174 {}
1175 };
1176 MODULE_DEVICE_TABLE(of, es8326_of_match);
1177 #endif
1178
1179 #ifdef CONFIG_ACPI
1180 static const struct acpi_device_id es8326_acpi_match[] = {
1181 {"ESSX8326", 0},
1182 {},
1183 };
1184 MODULE_DEVICE_TABLE(acpi, es8326_acpi_match);
1185 #endif
1186
1187 static struct i2c_driver es8326_i2c_driver = {
1188 .driver = {
1189 .name = "es8326",
1190 .acpi_match_table = ACPI_PTR(es8326_acpi_match),
1191 .of_match_table = of_match_ptr(es8326_of_match),
1192 },
1193 .probe = es8326_i2c_probe,
1194 .id_table = es8326_i2c_id,
1195 };
1196 module_i2c_driver(es8326_i2c_driver);
1197
1198 MODULE_DESCRIPTION("ASoC es8326 driver");
1199 MODULE_AUTHOR("David Yang <yangxiaohua@everest-semi.com>");
1200 MODULE_LICENSE("GPL");
1201