1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HW_SEQUENCER_H__ 27 #define __DC_HW_SEQUENCER_H__ 28 #include "dc_types.h" 29 #include "inc/clock_source.h" 30 #include "inc/hw/timing_generator.h" 31 #include "inc/hw/opp.h" 32 #include "inc/hw/link_encoder.h" 33 #include "inc/core_status.h" 34 35 struct pipe_ctx; 36 struct dc_state; 37 struct dc_stream_status; 38 struct dc_writeback_info; 39 struct dchub_init_data; 40 struct dc_static_screen_params; 41 struct resource_pool; 42 struct dc_phy_addr_space_config; 43 struct dc_virtual_addr_space_config; 44 struct dpp; 45 struct dce_hwseq; 46 struct link_resource; 47 struct dc_dmub_cmd; 48 struct pg_block_update; 49 struct drr_params; 50 51 struct subvp_pipe_control_lock_fast_params { 52 struct dc *dc; 53 bool lock; 54 bool subvp_immediate_flip; 55 }; 56 57 struct pipe_control_lock_params { 58 struct dc *dc; 59 struct pipe_ctx *pipe_ctx; 60 bool lock; 61 }; 62 63 struct set_flip_control_gsl_params { 64 struct pipe_ctx *pipe_ctx; 65 bool flip_immediate; 66 }; 67 68 struct program_triplebuffer_params { 69 const struct dc *dc; 70 struct pipe_ctx *pipe_ctx; 71 bool enableTripleBuffer; 72 }; 73 74 struct update_plane_addr_params { 75 struct dc *dc; 76 struct pipe_ctx *pipe_ctx; 77 }; 78 79 struct set_input_transfer_func_params { 80 struct dc *dc; 81 struct pipe_ctx *pipe_ctx; 82 struct dc_plane_state *plane_state; 83 }; 84 85 struct program_gamut_remap_params { 86 struct pipe_ctx *pipe_ctx; 87 }; 88 89 struct program_manual_trigger_params { 90 struct pipe_ctx *pipe_ctx; 91 }; 92 93 struct send_dmcub_cmd_params { 94 struct dc_context *ctx; 95 union dmub_rb_cmd *cmd; 96 enum dm_dmub_wait_type wait_type; 97 }; 98 99 struct setup_dpp_params { 100 struct pipe_ctx *pipe_ctx; 101 }; 102 103 struct program_bias_and_scale_params { 104 struct pipe_ctx *pipe_ctx; 105 }; 106 107 struct set_output_transfer_func_params { 108 struct dc *dc; 109 struct pipe_ctx *pipe_ctx; 110 const struct dc_stream_state *stream; 111 }; 112 113 struct update_visual_confirm_params { 114 struct dc *dc; 115 struct pipe_ctx *pipe_ctx; 116 int mpcc_id; 117 }; 118 119 struct power_on_mpc_mem_pwr_params { 120 struct mpc *mpc; 121 int mpcc_id; 122 bool power_on; 123 }; 124 125 struct set_output_csc_params { 126 struct mpc *mpc; 127 int opp_id; 128 const uint16_t *regval; 129 enum mpc_output_csc_mode ocsc_mode; 130 }; 131 132 struct set_ocsc_default_params { 133 struct mpc *mpc; 134 int opp_id; 135 enum dc_color_space color_space; 136 enum mpc_output_csc_mode ocsc_mode; 137 }; 138 139 struct subvp_save_surf_addr { 140 struct dc_dmub_srv *dc_dmub_srv; 141 const struct dc_plane_address *addr; 142 uint8_t subvp_index; 143 }; 144 145 struct wait_for_dcc_meta_propagation_params { 146 const struct dc *dc; 147 const struct pipe_ctx *top_pipe_to_program; 148 }; 149 150 struct fams2_global_control_lock_fast_params { 151 struct dc *dc; 152 bool is_required; 153 bool lock; 154 }; 155 156 union block_sequence_params { 157 struct update_plane_addr_params update_plane_addr_params; 158 struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params; 159 struct pipe_control_lock_params pipe_control_lock_params; 160 struct set_flip_control_gsl_params set_flip_control_gsl_params; 161 struct program_triplebuffer_params program_triplebuffer_params; 162 struct set_input_transfer_func_params set_input_transfer_func_params; 163 struct program_gamut_remap_params program_gamut_remap_params; 164 struct program_manual_trigger_params program_manual_trigger_params; 165 struct send_dmcub_cmd_params send_dmcub_cmd_params; 166 struct setup_dpp_params setup_dpp_params; 167 struct program_bias_and_scale_params program_bias_and_scale_params; 168 struct set_output_transfer_func_params set_output_transfer_func_params; 169 struct update_visual_confirm_params update_visual_confirm_params; 170 struct power_on_mpc_mem_pwr_params power_on_mpc_mem_pwr_params; 171 struct set_output_csc_params set_output_csc_params; 172 struct set_ocsc_default_params set_ocsc_default_params; 173 struct subvp_save_surf_addr subvp_save_surf_addr; 174 struct wait_for_dcc_meta_propagation_params wait_for_dcc_meta_propagation_params; 175 struct fams2_global_control_lock_fast_params fams2_global_control_lock_fast_params; 176 }; 177 178 enum block_sequence_func { 179 DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST = 0, 180 OPTC_PIPE_CONTROL_LOCK, 181 HUBP_SET_FLIP_CONTROL_GSL, 182 HUBP_PROGRAM_TRIPLEBUFFER, 183 HUBP_UPDATE_PLANE_ADDR, 184 DPP_SET_INPUT_TRANSFER_FUNC, 185 DPP_PROGRAM_GAMUT_REMAP, 186 OPTC_PROGRAM_MANUAL_TRIGGER, 187 DMUB_SEND_DMCUB_CMD, 188 DPP_SETUP_DPP, 189 DPP_PROGRAM_BIAS_AND_SCALE, 190 DPP_SET_OUTPUT_TRANSFER_FUNC, 191 MPC_UPDATE_VISUAL_CONFIRM, 192 MPC_POWER_ON_MPC_MEM_PWR, 193 MPC_SET_OUTPUT_CSC, 194 MPC_SET_OCSC_DEFAULT, 195 DMUB_SUBVP_SAVE_SURF_ADDR, 196 HUBP_WAIT_FOR_DCC_META_PROP, 197 DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST, 198 /* This must be the last value in this enum, add new ones above */ 199 HWSS_BLOCK_SEQUENCE_FUNC_COUNT 200 }; 201 202 struct block_sequence { 203 union block_sequence_params params; 204 enum block_sequence_func func; 205 }; 206 207 #define MAX_HWSS_BLOCK_SEQUENCE_SIZE (HWSS_BLOCK_SEQUENCE_FUNC_COUNT * MAX_PIPES) 208 209 struct hw_sequencer_funcs { 210 void (*hardware_release)(struct dc *dc); 211 /* Embedded Display Related */ 212 void (*edp_power_control)(struct dc_link *link, bool enable); 213 void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); 214 void (*edp_wait_for_T12)(struct dc_link *link); 215 216 /* Pipe Programming Related */ 217 void (*init_hw)(struct dc *dc); 218 void (*power_down_on_boot)(struct dc *dc); 219 void (*enable_accelerated_mode)(struct dc *dc, 220 struct dc_state *context); 221 enum dc_status (*apply_ctx_to_hw)(struct dc *dc, 222 struct dc_state *context); 223 void (*disable_plane)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx); 224 void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank); 225 void (*apply_ctx_for_surface)(struct dc *dc, 226 const struct dc_stream_state *stream, 227 int num_planes, struct dc_state *context); 228 void (*program_front_end_for_ctx)(struct dc *dc, 229 struct dc_state *context); 230 void (*wait_for_pending_cleared)(struct dc *dc, 231 struct dc_state *context); 232 void (*post_unlock_program_front_end)(struct dc *dc, 233 struct dc_state *context); 234 void (*update_plane_addr)(const struct dc *dc, 235 struct pipe_ctx *pipe_ctx); 236 void (*update_dchub)(struct dce_hwseq *hws, 237 struct dchub_init_data *dh_data); 238 void (*wait_for_mpcc_disconnect)(struct dc *dc, 239 struct resource_pool *res_pool, 240 struct pipe_ctx *pipe_ctx); 241 void (*edp_backlight_control)( 242 struct dc_link *link, 243 bool enable); 244 void (*program_triplebuffer)(const struct dc *dc, 245 struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); 246 void (*update_pending_status)(struct pipe_ctx *pipe_ctx); 247 void (*update_dsc_pg)(struct dc *dc, struct dc_state *context, bool safe_to_disable); 248 void (*clear_surface_dcc_and_tiling)(struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state, bool clear_tiling); 249 250 /* Pipe Lock Related */ 251 void (*pipe_control_lock)(struct dc *dc, 252 struct pipe_ctx *pipe, bool lock); 253 void (*interdependent_update_lock)(struct dc *dc, 254 struct dc_state *context, bool lock); 255 void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx, 256 bool flip_immediate); 257 void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock); 258 259 /* Timing Related */ 260 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, 261 struct crtc_position *position); 262 int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx); 263 void (*calc_vupdate_position)( 264 struct dc *dc, 265 struct pipe_ctx *pipe_ctx, 266 uint32_t *start_line, 267 uint32_t *end_line); 268 void (*enable_per_frame_crtc_position_reset)(struct dc *dc, 269 int group_size, struct pipe_ctx *grouped_pipes[]); 270 void (*enable_timing_synchronization)(struct dc *dc, 271 struct dc_state *state, 272 int group_index, int group_size, 273 struct pipe_ctx *grouped_pipes[]); 274 void (*enable_vblanks_synchronization)(struct dc *dc, 275 int group_index, int group_size, 276 struct pipe_ctx *grouped_pipes[]); 277 void (*setup_periodic_interrupt)(struct dc *dc, 278 struct pipe_ctx *pipe_ctx); 279 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, 280 struct dc_crtc_timing_adjust adjust); 281 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, 282 int num_pipes, 283 const struct dc_static_screen_params *events); 284 285 /* Stream Related */ 286 void (*enable_stream)(struct pipe_ctx *pipe_ctx); 287 void (*disable_stream)(struct pipe_ctx *pipe_ctx); 288 void (*blank_stream)(struct pipe_ctx *pipe_ctx); 289 void (*unblank_stream)(struct pipe_ctx *pipe_ctx, 290 struct dc_link_settings *link_settings); 291 292 /* Bandwidth Related */ 293 void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context); 294 bool (*update_bandwidth)(struct dc *dc, struct dc_state *context); 295 void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context); 296 297 /* Infopacket Related */ 298 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); 299 void (*send_immediate_sdp_message)( 300 struct pipe_ctx *pipe_ctx, 301 const uint8_t *custom_sdp_message, 302 unsigned int sdp_message_size); 303 void (*update_info_frame)(struct pipe_ctx *pipe_ctx); 304 void (*set_dmdata_attributes)(struct pipe_ctx *pipe); 305 void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx); 306 bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx); 307 308 /* Cursor Related */ 309 void (*set_cursor_position)(struct pipe_ctx *pipe); 310 void (*set_cursor_attribute)(struct pipe_ctx *pipe); 311 void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe); 312 313 /* Colour Related */ 314 void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx); 315 void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx, 316 enum dc_color_space colorspace, 317 uint16_t *matrix, int opp_id); 318 void (*trigger_3dlut_dma_load)(struct dc *dc, struct pipe_ctx *pipe_ctx); 319 320 /* VM Related */ 321 int (*init_sys_ctx)(struct dce_hwseq *hws, 322 struct dc *dc, 323 struct dc_phy_addr_space_config *pa_config); 324 void (*init_vm_ctx)(struct dce_hwseq *hws, 325 struct dc *dc, 326 struct dc_virtual_addr_space_config *va_config, 327 int vmid); 328 329 /* Writeback Related */ 330 void (*update_writeback)(struct dc *dc, 331 struct dc_writeback_info *wb_info, 332 struct dc_state *context); 333 void (*enable_writeback)(struct dc *dc, 334 struct dc_writeback_info *wb_info, 335 struct dc_state *context); 336 void (*disable_writeback)(struct dc *dc, 337 unsigned int dwb_pipe_inst); 338 339 /* Clock Related */ 340 enum dc_status (*set_clock)(struct dc *dc, 341 enum dc_clock_type clock_type, 342 uint32_t clk_khz, uint32_t stepping); 343 void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type, 344 struct dc_clock_config *clock_cfg); 345 void (*optimize_pwr_state)(const struct dc *dc, 346 struct dc_state *context); 347 void (*exit_optimized_pwr_state)(const struct dc *dc, 348 struct dc_state *context); 349 void (*calculate_pix_rate_divider)(struct dc *dc, 350 struct dc_state *context, 351 const struct dc_stream_state *stream); 352 353 /* Audio Related */ 354 void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx); 355 void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx); 356 357 /* Stereo 3D Related */ 358 void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc); 359 360 /* HW State Logging Related */ 361 void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx); 362 void (*log_color_state)(struct dc *dc, 363 struct dc_log_buffer_ctx *log_ctx); 364 void (*get_hw_state)(struct dc *dc, char *pBuf, 365 unsigned int bufSize, unsigned int mask); 366 void (*clear_status_bits)(struct dc *dc, unsigned int mask); 367 368 bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx, 369 struct set_backlight_level_params *params); 370 371 void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx); 372 373 void (*set_pipe)(struct pipe_ctx *pipe_ctx); 374 375 void (*enable_dp_link_output)(struct dc_link *link, 376 const struct link_resource *link_res, 377 enum signal_type signal, 378 enum clock_source_id clock_source, 379 const struct dc_link_settings *link_settings); 380 void (*enable_tmds_link_output)(struct dc_link *link, 381 const struct link_resource *link_res, 382 enum signal_type signal, 383 enum clock_source_id clock_source, 384 enum dc_color_depth color_depth, 385 uint32_t pixel_clock); 386 void (*enable_lvds_link_output)(struct dc_link *link, 387 const struct link_resource *link_res, 388 enum clock_source_id clock_source, 389 uint32_t pixel_clock); 390 void (*disable_link_output)(struct dc_link *link, 391 const struct link_resource *link_res, 392 enum signal_type signal); 393 394 void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits); 395 396 /* Idle Optimization Related */ 397 bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable); 398 399 bool (*does_plane_fit_in_mall)(struct dc *dc, 400 unsigned int pitch, 401 unsigned int height, 402 enum surface_pixel_format format, 403 struct dc_cursor_attributes *cursor_attr); 404 void (*commit_subvp_config)(struct dc *dc, struct dc_state *context); 405 void (*enable_phantom_streams)(struct dc *dc, struct dc_state *context); 406 void (*disable_phantom_streams)(struct dc *dc, struct dc_state *context); 407 void (*subvp_pipe_control_lock)(struct dc *dc, 408 struct dc_state *context, 409 bool lock, 410 bool should_lock_all_pipes, 411 struct pipe_ctx *top_pipe_to_program, 412 bool subvp_prev_use); 413 void (*subvp_pipe_control_lock_fast)(union block_sequence_params *params); 414 415 void (*z10_restore)(const struct dc *dc); 416 void (*z10_save_init)(struct dc *dc); 417 bool (*is_abm_supported)(struct dc *dc, 418 struct dc_state *context, struct dc_stream_state *stream); 419 420 void (*set_disp_pattern_generator)(const struct dc *dc, 421 struct pipe_ctx *pipe_ctx, 422 enum controller_dp_test_pattern test_pattern, 423 enum controller_dp_color_space color_space, 424 enum dc_color_depth color_depth, 425 const struct tg_color *solid_color, 426 int width, int height, int offset); 427 void (*blank_phantom)(struct dc *dc, 428 struct timing_generator *tg, 429 int width, 430 int height); 431 void (*update_visual_confirm_color)(struct dc *dc, 432 struct pipe_ctx *pipe_ctx, 433 int mpcc_id); 434 void (*update_phantom_vp_position)(struct dc *dc, 435 struct dc_state *context, 436 struct pipe_ctx *phantom_pipe); 437 void (*apply_update_flags_for_phantom)(struct pipe_ctx *phantom_pipe); 438 439 void (*calc_blocks_to_gate)(struct dc *dc, struct dc_state *context, 440 struct pg_block_update *update_state); 441 void (*calc_blocks_to_ungate)(struct dc *dc, struct dc_state *context, 442 struct pg_block_update *update_state); 443 void (*hw_block_power_up)(struct dc *dc, 444 struct pg_block_update *update_state); 445 void (*hw_block_power_down)(struct dc *dc, 446 struct pg_block_update *update_state); 447 void (*root_clock_control)(struct dc *dc, 448 struct pg_block_update *update_state, bool power_on); 449 bool (*is_pipe_topology_transition_seamless)(struct dc *dc, 450 const struct dc_state *cur_ctx, 451 const struct dc_state *new_ctx); 452 void (*wait_for_dcc_meta_propagation)(const struct dc *dc, 453 const struct pipe_ctx *top_pipe_to_program); 454 void (*fams2_global_control_lock)(struct dc *dc, 455 struct dc_state *context, 456 bool lock); 457 void (*fams2_update_config)(struct dc *dc, 458 struct dc_state *context, 459 bool enable); 460 void (*fams2_global_control_lock_fast)(union block_sequence_params *params); 461 void (*set_long_vtotal)(struct pipe_ctx **pipe_ctx, int num_pipes, uint32_t v_total_min, uint32_t v_total_max); 462 void (*program_outstanding_updates)(struct dc *dc, 463 struct dc_state *context); 464 void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable); 465 void (*wait_for_all_pending_updates)(const struct pipe_ctx *pipe_ctx); 466 void (*detect_pipe_changes)(struct dc_state *old_state, 467 struct dc_state *new_state, 468 struct pipe_ctx *old_pipe, 469 struct pipe_ctx *new_pipe); 470 void (*enable_plane)(struct dc *dc, 471 struct pipe_ctx *pipe_ctx, 472 struct dc_state *context); 473 void (*update_dchubp_dpp)(struct dc *dc, 474 struct pipe_ctx *pipe_ctx, 475 struct dc_state *context); 476 void (*post_unlock_reset_opp)(struct dc *dc, 477 struct pipe_ctx *opp_head); 478 }; 479 480 void color_space_to_black_color( 481 const struct dc *dc, 482 enum dc_color_space colorspace, 483 struct tg_color *black_color); 484 485 bool hwss_wait_for_blank_complete( 486 struct timing_generator *tg); 487 488 const uint16_t *find_color_matrix( 489 enum dc_color_space color_space, 490 uint32_t *array_size); 491 492 void get_surface_tile_visual_confirm_color( 493 struct pipe_ctx *pipe_ctx, 494 struct tg_color *color); 495 void get_surface_visual_confirm_color( 496 const struct pipe_ctx *pipe_ctx, 497 struct tg_color *color); 498 499 void get_hdr_visual_confirm_color( 500 struct pipe_ctx *pipe_ctx, 501 struct tg_color *color); 502 void get_mpctree_visual_confirm_color( 503 struct pipe_ctx *pipe_ctx, 504 struct tg_color *color); 505 void get_smartmux_visual_confirm_color( 506 struct dc *dc, 507 struct tg_color *color); 508 void get_vabc_visual_confirm_color( 509 struct pipe_ctx *pipe_ctx, 510 struct tg_color *color); 511 void get_subvp_visual_confirm_color( 512 struct pipe_ctx *pipe_ctx, 513 struct tg_color *color); 514 void get_fams2_visual_confirm_color( 515 struct dc *dc, 516 struct dc_state *context, 517 struct pipe_ctx *pipe_ctx, 518 struct tg_color *color); 519 520 void get_mclk_switch_visual_confirm_color( 521 struct pipe_ctx *pipe_ctx, 522 struct tg_color *color); 523 524 void get_cursor_visual_confirm_color( 525 struct pipe_ctx *pipe_ctx, 526 struct tg_color *color); 527 528 void get_dcc_visual_confirm_color( 529 struct dc *dc, 530 struct pipe_ctx *pipe_ctx, 531 struct tg_color *color); 532 533 void set_p_state_switch_method( 534 struct dc *dc, 535 struct dc_state *context, 536 struct pipe_ctx *pipe_ctx); 537 538 void set_drr_and_clear_adjust_pending( 539 struct pipe_ctx *pipe_ctx, 540 struct dc_stream_state *stream, 541 struct drr_params *params); 542 543 void hwss_execute_sequence(struct dc *dc, 544 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], 545 int num_steps); 546 547 void hwss_build_fast_sequence(struct dc *dc, 548 struct dc_dmub_cmd *dc_dmub_cmd, 549 unsigned int dmub_cmd_count, 550 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], 551 unsigned int *num_steps, 552 struct pipe_ctx *pipe_ctx, 553 struct dc_stream_status *stream_status, 554 struct dc_state *context); 555 556 void hwss_wait_for_all_blank_complete(struct dc *dc, 557 struct dc_state *context); 558 559 void hwss_wait_for_odm_update_pending_complete(struct dc *dc, 560 struct dc_state *context); 561 562 void hwss_wait_for_no_pipes_pending(struct dc *dc, 563 struct dc_state *context); 564 565 void hwss_wait_for_outstanding_hw_updates(struct dc *dc, 566 struct dc_state *dc_context); 567 568 void hwss_process_outstanding_hw_updates(struct dc *dc, 569 struct dc_state *dc_context); 570 571 void hwss_send_dmcub_cmd(union block_sequence_params *params); 572 573 void hwss_program_manual_trigger(union block_sequence_params *params); 574 575 void hwss_setup_dpp(union block_sequence_params *params); 576 577 void hwss_program_bias_and_scale(union block_sequence_params *params); 578 579 void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params); 580 581 void hwss_set_output_csc(union block_sequence_params *params); 582 583 void hwss_set_ocsc_default(union block_sequence_params *params); 584 585 void hwss_subvp_save_surf_addr(union block_sequence_params *params); 586 587 #endif /* __DC_HW_SEQUENCER_H__ */ 588