1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2025 AIROHA Inc
4  * Author: Lorenzo Bianconi <lorenzo@kernel.org>
5  */
6 
7 #define NPU_NUM_CORES		8
8 
9 struct airoha_npu {
10 	struct device *dev;
11 	struct regmap *regmap;
12 
13 	struct airoha_npu_core {
14 		struct airoha_npu *npu;
15 		/* protect concurrent npu memory accesses */
16 		spinlock_t lock;
17 		struct work_struct wdt_work;
18 	} cores[NPU_NUM_CORES];
19 
20 	struct {
21 		int (*ppe_init)(struct airoha_npu *npu);
22 		int (*ppe_deinit)(struct airoha_npu *npu);
23 		int (*ppe_flush_sram_entries)(struct airoha_npu *npu,
24 					      dma_addr_t foe_addr,
25 					      int sram_num_entries);
26 		int (*ppe_foe_commit_entry)(struct airoha_npu *npu,
27 					    dma_addr_t foe_addr,
28 					    u32 entry_size, u32 hash,
29 					    bool ppe2);
30 	} ops;
31 };
32 
33 struct airoha_npu *airoha_npu_get(struct device *dev);
34 void airoha_npu_put(struct airoha_npu *npu);
35