1 /*
2 * QEMU PowerPC e500-based platforms
3 *
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
5 *
6 * Author: Yu Liu, <yu.liu@freescale.com>
7 *
8 * This file is derived from hw/ppc440_bamboo.c,
9 * the copyright for that material belongs to the original owners.
10 *
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17 #include "qemu/osdep.h"
18 #include "qemu/datadir.h"
19 #include "qemu/units.h"
20 #include "qemu/guest-random.h"
21 #include "exec/target_page.h"
22 #include "qapi/error.h"
23 #include "e500.h"
24 #include "e500-ccsr.h"
25 #include "net/net.h"
26 #include "qemu/config-file.h"
27 #include "hw/block/flash.h"
28 #include "hw/char/serial-mm.h"
29 #include "hw/pci/pci.h"
30 #include "system/block-backend-io.h"
31 #include "system/system.h"
32 #include "system/kvm.h"
33 #include "system/reset.h"
34 #include "system/runstate.h"
35 #include "kvm_ppc.h"
36 #include "system/device_tree.h"
37 #include "hw/ppc/openpic.h"
38 #include "hw/ppc/openpic_kvm.h"
39 #include "hw/ppc/ppc.h"
40 #include "hw/qdev-properties.h"
41 #include "hw/loader.h"
42 #include "elf.h"
43 #include "hw/sysbus.h"
44 #include "qemu/host-utils.h"
45 #include "qemu/option.h"
46 #include "hw/pci-host/ppce500.h"
47 #include "qemu/error-report.h"
48 #include "hw/platform-bus.h"
49 #include "hw/net/fsl_etsec/etsec.h"
50 #include "hw/i2c/i2c.h"
51 #include "hw/irq.h"
52 #include "hw/sd/sdhci.h"
53 #include "hw/misc/unimp.h"
54
55 #define EPAPR_MAGIC (0x45504150)
56 #define DTC_LOAD_PAD 0x1800000
57 #define DTC_PAD_MASK 0xFFFFF
58 #define DTB_MAX_SIZE (8 * MiB)
59 #define INITRD_LOAD_PAD 0x2000000
60 #define INITRD_PAD_MASK 0xFFFFFF
61
62 #define RAM_SIZES_ALIGN (64 * MiB)
63
64 /* TODO: parameterize */
65 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL
66 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL
67 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL
68 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
69 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
70 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL
71 #define MPC8544_PCI_REGS_SIZE 0x1000ULL
72 #define MPC85XX_ESDHC_REGS_OFFSET 0x2e000ULL
73 #define MPC85XX_ESDHC_REGS_SIZE 0x1000ULL
74 #define MPC8544_UTIL_OFFSET 0xe0000ULL
75 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL
76 #define MPC8544_I2C_REGS_OFFSET 0x3000ULL
77 #define MPC8XXX_GPIO_IRQ 47
78 #define MPC8544_I2C_IRQ 43
79 #define MPC85XX_ESDHC_IRQ 72
80 #define RTC_REGS_OFFSET 0x68
81
82 #define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000)
83
84 struct boot_info
85 {
86 uint32_t dt_base;
87 uint32_t dt_size;
88 uint32_t entry;
89 };
90
pci_map_create(void * fdt,uint32_t mpic,int first_slot,int nr_slots,int * len)91 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
92 int nr_slots, int *len)
93 {
94 int i = 0;
95 int slot;
96 int pci_irq;
97 int host_irq;
98 int last_slot = first_slot + nr_slots;
99 uint32_t *pci_map;
100
101 *len = nr_slots * 4 * 7 * sizeof(uint32_t);
102 pci_map = g_malloc(*len);
103
104 for (slot = first_slot; slot < last_slot; slot++) {
105 for (pci_irq = 0; pci_irq < 4; pci_irq++) {
106 pci_map[i++] = cpu_to_be32(slot << 11);
107 pci_map[i++] = cpu_to_be32(0x0);
108 pci_map[i++] = cpu_to_be32(0x0);
109 pci_map[i++] = cpu_to_be32(pci_irq + 1);
110 pci_map[i++] = cpu_to_be32(mpic);
111 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq);
112 pci_map[i++] = cpu_to_be32(host_irq + 1);
113 pci_map[i++] = cpu_to_be32(0x1);
114 }
115 }
116
117 assert((i * sizeof(uint32_t)) == *len);
118
119 return pci_map;
120 }
121
dt_serial_create(void * fdt,unsigned long long offset,const char * soc,const char * mpic,const char * alias,int idx,bool defcon)122 static void dt_serial_create(void *fdt, unsigned long long offset,
123 const char *soc, const char *mpic,
124 const char *alias, int idx, bool defcon)
125 {
126 char *ser;
127
128 ser = g_strdup_printf("%s/serial@%llx", soc, offset);
129 qemu_fdt_add_subnode(fdt, ser);
130 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial");
131 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550");
132 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100);
133 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx);
134 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", PLATFORM_CLK_FREQ_HZ);
135 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2);
136 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
137 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser);
138
139 if (defcon) {
140 /*
141 * "linux,stdout-path" and "stdout" properties are deprecated by linux
142 * kernel. New platforms should only use the "stdout-path" property. Set
143 * the new property and continue using older property to remain
144 * compatible with the existing firmware.
145 */
146 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser);
147 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser);
148 }
149 g_free(ser);
150 }
151
create_dt_mpc8xxx_gpio(void * fdt,const char * soc,const char * mpic)152 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic)
153 {
154 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET;
155 int irq0 = MPC8XXX_GPIO_IRQ;
156 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0);
157 gchar *poweroff = g_strdup_printf("%s/power-off", soc);
158 int gpio_ph;
159
160 qemu_fdt_add_subnode(fdt, node);
161 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio");
162 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000);
163 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2);
164 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic);
165 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2);
166 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0);
167 gpio_ph = qemu_fdt_alloc_phandle(fdt);
168 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph);
169 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph);
170
171 /* Power Off Pin */
172 qemu_fdt_add_subnode(fdt, poweroff);
173 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff");
174 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0);
175
176 g_free(node);
177 g_free(poweroff);
178 }
179
dt_rtc_create(void * fdt,const char * i2c,const char * alias)180 static void dt_rtc_create(void *fdt, const char *i2c, const char *alias)
181 {
182 int offset = RTC_REGS_OFFSET;
183
184 gchar *rtc = g_strdup_printf("%s/rtc@%"PRIx32, i2c, offset);
185 qemu_fdt_add_subnode(fdt, rtc);
186 qemu_fdt_setprop_string(fdt, rtc, "compatible", "pericom,pt7c4338");
187 qemu_fdt_setprop_cells(fdt, rtc, "reg", offset);
188 qemu_fdt_setprop_string(fdt, "/aliases", alias, rtc);
189
190 g_free(rtc);
191 }
192
dt_i2c_create(void * fdt,const char * soc,const char * mpic,const char * alias)193 static void dt_i2c_create(void *fdt, const char *soc, const char *mpic,
194 const char *alias)
195 {
196 hwaddr mmio0 = MPC8544_I2C_REGS_OFFSET;
197 int irq0 = MPC8544_I2C_IRQ;
198
199 gchar *i2c = g_strdup_printf("%s/i2c@%"PRIx64, soc, mmio0);
200 qemu_fdt_add_subnode(fdt, i2c);
201 qemu_fdt_setprop_string(fdt, i2c, "device_type", "i2c");
202 qemu_fdt_setprop_string(fdt, i2c, "compatible", "fsl-i2c");
203 qemu_fdt_setprop_cells(fdt, i2c, "reg", mmio0, 0x14);
204 qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0);
205 qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2);
206 qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic);
207 qemu_fdt_setprop_cell(fdt, i2c, "#size-cells", 0);
208 qemu_fdt_setprop_cell(fdt, i2c, "#address-cells", 1);
209 qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c);
210
211 g_free(i2c);
212 }
213
dt_sdhc_create(void * fdt,const char * parent,const char * mpic)214 static void dt_sdhc_create(void *fdt, const char *parent, const char *mpic)
215 {
216 hwaddr mmio = MPC85XX_ESDHC_REGS_OFFSET;
217 hwaddr size = MPC85XX_ESDHC_REGS_SIZE;
218 int irq = MPC85XX_ESDHC_IRQ;
219 g_autofree char *name = NULL;
220
221 name = g_strdup_printf("%s/sdhc@%" PRIx64, parent, mmio);
222 qemu_fdt_add_subnode(fdt, name);
223 qemu_fdt_setprop(fdt, name, "sdhci,auto-cmd12", NULL, 0);
224 qemu_fdt_setprop_phandle(fdt, name, "interrupt-parent", mpic);
225 qemu_fdt_setprop_cells(fdt, name, "bus-width", 4);
226 qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x2);
227 qemu_fdt_setprop_cells(fdt, name, "reg", mmio, size);
228 qemu_fdt_setprop_string(fdt, name, "compatible", "fsl,esdhc");
229 }
230
231 typedef struct PlatformDevtreeData {
232 void *fdt;
233 const char *mpic;
234 int irq_start;
235 const char *node;
236 PlatformBusDevice *pbus;
237 } PlatformDevtreeData;
238
create_devtree_etsec(SysBusDevice * sbdev,PlatformDevtreeData * data)239 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data)
240 {
241 eTSEC *etsec = ETSEC_COMMON(sbdev);
242 PlatformBusDevice *pbus = data->pbus;
243 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0);
244 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0);
245 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1);
246 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2);
247 gchar *node = g_strdup_printf("%s/ethernet@%"PRIx64, data->node, mmio0);
248 gchar *group = g_strdup_printf("%s/queue-group", node);
249 void *fdt = data->fdt;
250
251 assert((int64_t)mmio0 >= 0);
252 assert(irq0 >= 0);
253 assert(irq1 >= 0);
254 assert(irq2 >= 0);
255
256 qemu_fdt_add_subnode(fdt, node);
257 qemu_fdt_setprop(fdt, node, "ranges", NULL, 0);
258 qemu_fdt_setprop_string(fdt, node, "device_type", "network");
259 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2");
260 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC");
261 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6);
262 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0);
263 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1);
264 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1);
265
266 qemu_fdt_add_subnode(fdt, group);
267 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000);
268 qemu_fdt_setprop_cells(fdt, group, "interrupts",
269 data->irq_start + irq0, 0x2,
270 data->irq_start + irq1, 0x2,
271 data->irq_start + irq2, 0x2);
272
273 g_free(node);
274 g_free(group);
275
276 return 0;
277 }
278
sysbus_device_create_devtree(SysBusDevice * sbdev,void * opaque)279 static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque)
280 {
281 PlatformDevtreeData *data = opaque;
282 bool matched = false;
283
284 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) {
285 create_devtree_etsec(sbdev, data);
286 matched = true;
287 }
288
289 if (!matched) {
290 error_report("Device %s is not supported by this machine yet.",
291 qdev_fw_name(DEVICE(sbdev)));
292 exit(1);
293 }
294 }
295
create_devtree_flash(SysBusDevice * sbdev,PlatformDevtreeData * data)296 static void create_devtree_flash(SysBusDevice *sbdev,
297 PlatformDevtreeData *data)
298 {
299 g_autofree char *name = NULL;
300 uint64_t num_blocks = object_property_get_uint(OBJECT(sbdev),
301 "num-blocks",
302 &error_fatal);
303 uint64_t sector_length = object_property_get_uint(OBJECT(sbdev),
304 "sector-length",
305 &error_fatal);
306 uint64_t bank_width = object_property_get_uint(OBJECT(sbdev),
307 "width",
308 &error_fatal);
309 hwaddr flashbase = 0;
310 hwaddr flashsize = num_blocks * sector_length;
311 void *fdt = data->fdt;
312
313 name = g_strdup_printf("%s/nor@%" PRIx64, data->node, flashbase);
314 qemu_fdt_add_subnode(fdt, name);
315 qemu_fdt_setprop_string(fdt, name, "compatible", "cfi-flash");
316 qemu_fdt_setprop_sized_cells(fdt, name, "reg",
317 1, flashbase, 1, flashsize);
318 qemu_fdt_setprop_cell(fdt, name, "bank-width", bank_width);
319 }
320
platform_bus_create_devtree(PPCE500MachineState * pms,void * fdt,const char * mpic)321 static void platform_bus_create_devtree(PPCE500MachineState *pms,
322 void *fdt, const char *mpic)
323 {
324 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
325 gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base);
326 const char platcomp[] = "qemu,platform\0simple-bus";
327 uint64_t addr = pmc->platform_bus_base;
328 uint64_t size = pmc->platform_bus_size;
329 int irq_start = pmc->platform_bus_first_irq;
330 SysBusDevice *sbdev;
331 bool ambiguous;
332
333 /* Create a /platform node that we can put all devices into */
334
335 qemu_fdt_add_subnode(fdt, node);
336 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp));
337
338 /* Our platform bus region is less than 32bit big, so 1 cell is enough for
339 address and size */
340 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1);
341 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1);
342 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size);
343
344 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic);
345
346 /* Create dt nodes for dynamic devices */
347 PlatformDevtreeData data = {
348 .fdt = fdt,
349 .mpic = mpic,
350 .irq_start = irq_start,
351 .node = node,
352 .pbus = pms->pbus_dev,
353 };
354
355 /* Loop through all dynamic sysbus devices and create nodes for them */
356 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data);
357
358 sbdev = SYS_BUS_DEVICE(object_resolve_path_type("", TYPE_PFLASH_CFI01,
359 &ambiguous));
360 if (sbdev) {
361 assert(!ambiguous);
362 create_devtree_flash(sbdev, &data);
363 }
364
365 g_free(node);
366 }
367
ppce500_load_device_tree(PPCE500MachineState * pms,hwaddr addr,hwaddr initrd_base,hwaddr initrd_size,hwaddr kernel_base,hwaddr kernel_size,bool dry_run)368 static int ppce500_load_device_tree(PPCE500MachineState *pms,
369 hwaddr addr,
370 hwaddr initrd_base,
371 hwaddr initrd_size,
372 hwaddr kernel_base,
373 hwaddr kernel_size,
374 bool dry_run)
375 {
376 MachineState *machine = MACHINE(pms);
377 unsigned int smp_cpus = machine->smp.cpus;
378 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
379 CPUPPCState *env = cpu_env(first_cpu);
380 int ret = -1;
381 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) };
382 int fdt_size;
383 void *fdt;
384 uint8_t hypercall[16];
385 uint32_t clock_freq = PLATFORM_CLK_FREQ_HZ;
386 uint32_t tb_freq = PLATFORM_CLK_FREQ_HZ;
387 int i;
388 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
389 char *soc;
390 char *mpic;
391 uint32_t mpic_ph;
392 uint32_t msi_ph;
393 char *gutil;
394 char *pci;
395 char *msi;
396 uint32_t *pci_map = NULL;
397 int len;
398 uint32_t pci_ranges[14] =
399 {
400 0x2000000, 0x0, pmc->pci_mmio_bus_base,
401 pmc->pci_mmio_base >> 32, pmc->pci_mmio_base,
402 0x0, 0x20000000,
403
404 0x1000000, 0x0, 0x0,
405 pmc->pci_pio_base >> 32, pmc->pci_pio_base,
406 0x0, 0x10000,
407 };
408 const char *dtb_file = machine->dtb;
409 const char *toplevel_compat = machine->dt_compatible;
410 uint8_t rng_seed[32];
411
412 if (dtb_file) {
413 char *filename;
414 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file);
415 if (!filename) {
416 goto out;
417 }
418
419 fdt = load_device_tree(filename, &fdt_size);
420 g_free(filename);
421 if (!fdt) {
422 goto out;
423 }
424 goto done;
425 }
426
427 fdt = create_device_tree(&fdt_size);
428 if (fdt == NULL) {
429 goto out;
430 }
431
432 /* Manipulate device tree in memory. */
433 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2);
434 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2);
435
436 qemu_fdt_add_subnode(fdt, "/memory");
437 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");
438 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
439 sizeof(mem_reg_property));
440
441 qemu_fdt_add_subnode(fdt, "/chosen");
442 if (initrd_size) {
443 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
444 initrd_base);
445 if (ret < 0) {
446 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
447 }
448
449 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
450 (initrd_base + initrd_size));
451 if (ret < 0) {
452 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
453 }
454
455 }
456
457 if (kernel_base != -1ULL) {
458 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel",
459 kernel_base >> 32, kernel_base,
460 kernel_size >> 32, kernel_size);
461 }
462
463 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
464 machine->kernel_cmdline);
465 if (ret < 0)
466 fprintf(stderr, "couldn't set /chosen/bootargs\n");
467
468 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
469 qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
470
471 if (kvm_enabled()) {
472 /* Read out host's frequencies */
473 clock_freq = kvmppc_get_clockfreq();
474 tb_freq = kvmppc_get_tbfreq();
475
476 /* indicate KVM hypercall interface */
477 qemu_fdt_add_subnode(fdt, "/hypervisor");
478 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible",
479 "linux,kvm");
480 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
481 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions",
482 hypercall, sizeof(hypercall));
483 /* if KVM supports the idle hcall, set property indicating this */
484 if (kvmppc_get_hasidle(env)) {
485 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0);
486 }
487 }
488
489 /* Create CPU nodes */
490 qemu_fdt_add_subnode(fdt, "/cpus");
491 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1);
492 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0);
493
494 /* We need to generate the cpu nodes in reverse order, so Linux can pick
495 the first node as boot node and be happy */
496 for (i = smp_cpus - 1; i >= 0; i--) {
497 CPUState *cpu;
498 char *cpu_name;
499 uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20);
500
501 cpu = qemu_get_cpu(i);
502 if (cpu == NULL) {
503 continue;
504 }
505 env = cpu_env(cpu);
506
507 cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i);
508 qemu_fdt_add_subnode(fdt, cpu_name);
509 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
510 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
511 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
512 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i);
513 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size",
514 env->dcache_line_size);
515 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size",
516 env->icache_line_size);
517 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
518 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
519 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
520 if (cpu->cpu_index) {
521 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled");
522 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method",
523 "spin-table");
524 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr",
525 cpu_release_addr);
526 } else {
527 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
528 }
529 g_free(cpu_name);
530 }
531
532 qemu_fdt_add_subnode(fdt, "/aliases");
533 /* XXX These should go into their respective devices' code */
534 soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base);
535 qemu_fdt_add_subnode(fdt, soc);
536 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc");
537 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb,
538 sizeof(compatible_sb));
539 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1);
540 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1);
541 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0,
542 pmc->ccsrbar_base >> 32, pmc->ccsrbar_base,
543 MPC8544_CCSRBAR_SIZE);
544 /* XXX should contain a reasonable value */
545 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0);
546
547 mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
548 qemu_fdt_add_subnode(fdt, mpic);
549 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic");
550 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic");
551 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
552 0x40000);
553 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0);
554 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
555 mpic_ph = qemu_fdt_alloc_phandle(fdt);
556 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph);
557 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
558 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
559
560 /*
561 * We have to generate ser1 first, because Linux takes the first
562 * device it finds in the dt as serial output device. And we generate
563 * devices in reverse order to the dt.
564 */
565 if (serial_hd(1)) {
566 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
567 soc, mpic, "serial1", 1, false);
568 }
569
570 if (serial_hd(0)) {
571 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
572 soc, mpic, "serial0", 0, true);
573 }
574
575 /* i2c */
576 dt_i2c_create(fdt, soc, mpic, "i2c");
577
578 dt_rtc_create(fdt, "i2c", "rtc");
579
580 /* sdhc */
581 if (pmc->has_esdhc) {
582 dt_sdhc_create(fdt, soc, mpic);
583 }
584
585 gutil = g_strdup_printf("%s/global-utilities@%llx", soc,
586 MPC8544_UTIL_OFFSET);
587 qemu_fdt_add_subnode(fdt, gutil);
588 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
589 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
590 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
591 g_free(gutil);
592
593 msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);
594 qemu_fdt_add_subnode(fdt, msi);
595 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");
596 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);
597 msi_ph = qemu_fdt_alloc_phandle(fdt);
598 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);
599 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic);
600 qemu_fdt_setprop_cells(fdt, msi, "interrupts",
601 0xe0, 0x0,
602 0xe1, 0x0,
603 0xe2, 0x0,
604 0xe3, 0x0,
605 0xe4, 0x0,
606 0xe5, 0x0,
607 0xe6, 0x0,
608 0xe7, 0x0);
609 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph);
610 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
611 g_free(msi);
612
613 pci = g_strdup_printf("/pci@%llx",
614 pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET);
615 qemu_fdt_add_subnode(fdt, pci);
616 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0);
617 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
618 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci");
619 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
620 0x0, 0x7);
621 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic),
622 pmc->pci_first_slot, pmc->pci_nr_slots,
623 &len);
624 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len);
625 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
626 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2);
627 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255);
628 for (i = 0; i < 14; i++) {
629 pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
630 }
631 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
632 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
633 qemu_fdt_setprop_cells(fdt, pci, "reg",
634 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32,
635 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET),
636 0, 0x1000);
637 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666);
638 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1);
639 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2);
640 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3);
641 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci);
642 g_free(pci);
643
644 if (pmc->has_mpc8xxx_gpio) {
645 create_dt_mpc8xxx_gpio(fdt, soc, mpic);
646 }
647 g_free(soc);
648
649 platform_bus_create_devtree(pms, fdt, mpic);
650
651 g_free(mpic);
652
653 pmc->fixup_devtree(fdt);
654
655 if (toplevel_compat) {
656 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat,
657 strlen(toplevel_compat) + 1);
658 }
659
660 done:
661 if (!dry_run) {
662 cpu_physical_memory_write(addr, fdt, fdt_size);
663
664 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
665 g_free(machine->fdt);
666 machine->fdt = fdt;
667 } else {
668 g_free(fdt);
669 }
670 ret = fdt_size;
671
672 out:
673 g_free(pci_map);
674
675 return ret;
676 }
677
678 typedef struct DeviceTreeParams {
679 PPCE500MachineState *machine;
680 hwaddr addr;
681 hwaddr initrd_base;
682 hwaddr initrd_size;
683 hwaddr kernel_base;
684 hwaddr kernel_size;
685 Notifier notifier;
686 } DeviceTreeParams;
687
ppce500_reset_device_tree(void * opaque)688 static void ppce500_reset_device_tree(void *opaque)
689 {
690 DeviceTreeParams *p = opaque;
691 ppce500_load_device_tree(p->machine, p->addr, p->initrd_base,
692 p->initrd_size, p->kernel_base, p->kernel_size,
693 false);
694 }
695
ppce500_init_notify(Notifier * notifier,void * data)696 static void ppce500_init_notify(Notifier *notifier, void *data)
697 {
698 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier);
699 ppce500_reset_device_tree(p);
700 }
701
ppce500_prep_device_tree(PPCE500MachineState * machine,hwaddr addr,hwaddr initrd_base,hwaddr initrd_size,hwaddr kernel_base,hwaddr kernel_size)702 static int ppce500_prep_device_tree(PPCE500MachineState *machine,
703 hwaddr addr,
704 hwaddr initrd_base,
705 hwaddr initrd_size,
706 hwaddr kernel_base,
707 hwaddr kernel_size)
708 {
709 DeviceTreeParams *p = g_new(DeviceTreeParams, 1);
710 p->machine = machine;
711 p->addr = addr;
712 p->initrd_base = initrd_base;
713 p->initrd_size = initrd_size;
714 p->kernel_base = kernel_base;
715 p->kernel_size = kernel_size;
716
717 qemu_register_reset_nosnapshotload(ppce500_reset_device_tree, p);
718 p->notifier.notify = ppce500_init_notify;
719 qemu_add_machine_init_done_notifier(&p->notifier);
720
721 /* Issue the device tree loader once, so that we get the size of the blob */
722 return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size,
723 kernel_base, kernel_size, true);
724 }
725
booke206_page_size_to_tlb(uint64_t size)726 static hwaddr booke206_page_size_to_tlb(uint64_t size)
727 {
728 return 63 - clz64(size / KiB);
729 }
730
booke206_set_tlb(ppcmas_tlb_t * tlb,target_ulong va,hwaddr pa,hwaddr len)731 void booke206_set_tlb(ppcmas_tlb_t *tlb, target_ulong va, hwaddr pa,
732 hwaddr len)
733 {
734 tlb->mas1 = booke206_page_size_to_tlb(len) << MAS1_TSIZE_SHIFT;
735 tlb->mas1 |= MAS1_VALID;
736 tlb->mas2 = va & TARGET_PAGE_MASK;
737 tlb->mas7_3 = pa & TARGET_PAGE_MASK;
738 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
739 }
740
booke206_initial_map_tsize(CPUPPCState * env)741 static int booke206_initial_map_tsize(CPUPPCState *env)
742 {
743 struct boot_info *bi = env->load_info;
744 hwaddr dt_end;
745 int ps;
746
747 /* Our initial TLB entry needs to cover everything from 0 to
748 the device tree top */
749 dt_end = bi->dt_base + bi->dt_size;
750 ps = booke206_page_size_to_tlb(dt_end) + 1;
751 if (ps & 1) {
752 /* e500v2 can only do even TLB size bits */
753 ps++;
754 }
755 return ps;
756 }
757
mmubooke_initial_mapsize(CPUPPCState * env)758 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env)
759 {
760 int tsize;
761
762 tsize = booke206_initial_map_tsize(env);
763 return (1ULL << 10 << tsize);
764 }
765
ppce500_cpu_reset_sec(void * opaque)766 static void ppce500_cpu_reset_sec(void *opaque)
767 {
768 PowerPCCPU *cpu = opaque;
769 CPUState *cs = CPU(cpu);
770
771 cpu_reset(cs);
772
773 cs->exception_index = EXCP_HLT;
774 }
775
ppce500_cpu_reset(void * opaque)776 static void ppce500_cpu_reset(void *opaque)
777 {
778 PowerPCCPU *cpu = opaque;
779 CPUState *cs = CPU(cpu);
780 CPUPPCState *env = &cpu->env;
781 struct boot_info *bi = env->load_info;
782 uint64_t map_size = mmubooke_initial_mapsize(env);
783 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
784
785 cpu_reset(cs);
786
787 /* Set initial guest state. */
788 cs->halted = 0;
789 env->gpr[1] = (16 * MiB) - 8;
790 env->gpr[3] = bi->dt_base;
791 env->gpr[4] = 0;
792 env->gpr[5] = 0;
793 env->gpr[6] = EPAPR_MAGIC;
794 env->gpr[7] = map_size;
795 env->gpr[8] = 0;
796 env->gpr[9] = 0;
797 env->nip = bi->entry;
798 /* create initial mapping */
799 booke206_set_tlb(tlb, 0, 0, map_size);
800 #ifdef CONFIG_KVM
801 env->tlb_dirty = true;
802 #endif
803 }
804
ppce500_init_mpic_qemu(PPCE500MachineState * pms,IrqLines * irqs)805 static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms,
806 IrqLines *irqs)
807 {
808 DeviceState *dev;
809 SysBusDevice *s;
810 int i, j, k;
811 MachineState *machine = MACHINE(pms);
812 unsigned int smp_cpus = machine->smp.cpus;
813 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
814
815 dev = qdev_new(TYPE_OPENPIC);
816 object_property_add_child(OBJECT(machine), "pic", OBJECT(dev));
817 qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
818 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
819
820 s = SYS_BUS_DEVICE(dev);
821 sysbus_realize_and_unref(s, &error_fatal);
822
823 k = 0;
824 for (i = 0; i < smp_cpus; i++) {
825 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
826 sysbus_connect_irq(s, k++, irqs[i].irq[j]);
827 }
828 }
829
830 return dev;
831 }
832
ppce500_init_mpic_kvm(const PPCE500MachineClass * pmc,Error ** errp)833 static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc,
834 Error **errp)
835 {
836 #ifdef CONFIG_KVM
837 DeviceState *dev;
838 CPUState *cs;
839
840 dev = qdev_new(TYPE_KVM_OPENPIC);
841 qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
842
843 if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
844 object_unparent(OBJECT(dev));
845 return NULL;
846 }
847
848 CPU_FOREACH(cs) {
849 if (kvm_openpic_connect_vcpu(dev, cs)) {
850 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n",
851 __func__);
852 abort();
853 }
854 }
855
856 return dev;
857 #else
858 g_assert_not_reached();
859 #endif
860 }
861
ppce500_init_mpic(PPCE500MachineState * pms,MemoryRegion * ccsr,IrqLines * irqs)862 static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms,
863 MemoryRegion *ccsr,
864 IrqLines *irqs)
865 {
866 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
867 DeviceState *dev = NULL;
868 SysBusDevice *s;
869
870 if (kvm_enabled()) {
871 Error *err = NULL;
872
873 if (kvm_kernel_irqchip_allowed()) {
874 dev = ppce500_init_mpic_kvm(pmc, &err);
875 }
876 if (kvm_kernel_irqchip_required() && !dev) {
877 error_reportf_err(err,
878 "kernel_irqchip requested but unavailable: ");
879 exit(1);
880 }
881 }
882
883 if (!dev) {
884 dev = ppce500_init_mpic_qemu(pms, irqs);
885 }
886
887 s = SYS_BUS_DEVICE(dev);
888 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET,
889 s->mmio[0].memory);
890
891 return dev;
892 }
893
ppce500_power_off(void * opaque,int line,int on)894 static void ppce500_power_off(void *opaque, int line, int on)
895 {
896 if (on) {
897 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
898 }
899 }
900
ppce500_init(MachineState * machine)901 void ppce500_init(MachineState *machine)
902 {
903 MemoryRegion *address_space_mem = get_system_memory();
904 PPCE500MachineState *pms = PPCE500_MACHINE(machine);
905 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine);
906 MachineClass *mc = MACHINE_CLASS(pmc);
907 PCIBus *pci_bus;
908 CPUPPCState *env = NULL;
909 uint64_t loadaddr;
910 hwaddr kernel_base = -1LL;
911 int kernel_size = 0;
912 hwaddr dt_base = 0;
913 hwaddr initrd_base = 0;
914 int initrd_size = 0;
915 hwaddr cur_base = 0;
916 char *filename;
917 const char *payload_name;
918 bool kernel_as_payload;
919 hwaddr bios_entry = 0;
920 target_long payload_size;
921 struct boot_info *boot_info = NULL;
922 int dt_size;
923 int i;
924 unsigned int smp_cpus = machine->smp.cpus;
925 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
926 * 4 respectively */
927 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
928 IrqLines *irqs;
929 DeviceState *dev, *mpicdev;
930 DriveInfo *dinfo;
931 CPUPPCState *firstenv = NULL;
932 MemoryRegion *ccsr_addr_space;
933 SysBusDevice *s;
934 PPCE500CCSRState *ccsr;
935 I2CBus *i2c;
936
937 irqs = g_new0(IrqLines, smp_cpus);
938 for (i = 0; i < smp_cpus; i++) {
939 PowerPCCPU *cpu;
940 CPUState *cs;
941
942 cpu = POWERPC_CPU(object_new(machine->cpu_type));
943 env = &cpu->env;
944 cs = CPU(cpu);
945
946 if (env->mmu_model != POWERPC_MMU_BOOKE206) {
947 error_report("MMU model %i not supported by this machine",
948 env->mmu_model);
949 exit(1);
950 }
951
952 /*
953 * Secondary CPU starts in halted state for now. Needs to change
954 * when implementing non-kernel boot.
955 */
956 object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0,
957 &error_abort);
958 qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal);
959
960 if (!firstenv) {
961 firstenv = env;
962 }
963
964 irqs[i].irq[OPENPIC_OUTPUT_INT] =
965 qdev_get_gpio_in(DEVICE(cpu), PPCE500_INPUT_INT);
966 irqs[i].irq[OPENPIC_OUTPUT_CINT] =
967 qdev_get_gpio_in(DEVICE(cpu), PPCE500_INPUT_CINT);
968 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
969 env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0;
970
971 ppc_booke_timers_init(cpu, PLATFORM_CLK_FREQ_HZ, PPC_TIMER_E500);
972
973 /* Register reset handler */
974 if (!i) {
975 /* Primary CPU */
976 boot_info = g_new0(struct boot_info, 1);
977 qemu_register_reset(ppce500_cpu_reset, cpu);
978 env->load_info = boot_info;
979 } else {
980 /* Secondary CPUs */
981 qemu_register_reset(ppce500_cpu_reset_sec, cpu);
982 }
983 }
984
985 env = firstenv;
986
987 if (!QEMU_IS_ALIGNED(machine->ram_size, RAM_SIZES_ALIGN)) {
988 error_report("RAM size must be multiple of %" PRIu64, RAM_SIZES_ALIGN);
989 exit(EXIT_FAILURE);
990 }
991
992 /* Register Memory */
993 memory_region_add_subregion(address_space_mem, 0, machine->ram);
994
995 dev = qdev_new("e500-ccsr");
996 object_property_add_child(OBJECT(machine), "e500-ccsr", OBJECT(dev));
997 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
998 ccsr = CCSR(dev);
999 ccsr_addr_space = &ccsr->ccsr_space;
1000 memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base,
1001 ccsr_addr_space);
1002
1003 mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs);
1004 g_free(irqs);
1005
1006 /* Serial */
1007 if (serial_hd(0)) {
1008 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
1009 0, qdev_get_gpio_in(mpicdev, 42), 399193,
1010 serial_hd(0), DEVICE_BIG_ENDIAN);
1011 }
1012
1013 if (serial_hd(1)) {
1014 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
1015 0, qdev_get_gpio_in(mpicdev, 42), 399193,
1016 serial_hd(1), DEVICE_BIG_ENDIAN);
1017 }
1018
1019 /* I2C */
1020 dev = qdev_new("mpc-i2c");
1021 s = SYS_BUS_DEVICE(dev);
1022 sysbus_realize_and_unref(s, &error_fatal);
1023 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ));
1024 memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET,
1025 sysbus_mmio_get_region(s, 0));
1026 i2c = I2C_BUS(qdev_get_child_bus(dev, "i2c"));
1027 i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET);
1028
1029 /* eSDHC */
1030 if (pmc->has_esdhc) {
1031 dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
1032 qdev_prop_set_string(dev, "name", "esdhc");
1033 qdev_prop_set_uint64(dev, "size", MPC85XX_ESDHC_REGS_SIZE);
1034 s = SYS_BUS_DEVICE(dev);
1035 sysbus_realize_and_unref(s, &error_fatal);
1036 memory_region_add_subregion(ccsr_addr_space, MPC85XX_ESDHC_REGS_OFFSET,
1037 sysbus_mmio_get_region(s, 0));
1038
1039 /*
1040 * Compatible with:
1041 * - SD Host Controller Specification Version 2.0 Part A2
1042 * (See MPC8569E Reference Manual)
1043 */
1044 dev = qdev_new(TYPE_SYSBUS_SDHCI);
1045 qdev_prop_set_uint8(dev, "sd-spec-version", 2);
1046 qdev_prop_set_uint8(dev, "endianness", DEVICE_BIG_ENDIAN);
1047 qdev_prop_set_uint8(dev, "vendor", SDHCI_VENDOR_FSL);
1048 s = SYS_BUS_DEVICE(dev);
1049 sysbus_realize_and_unref(s, &error_fatal);
1050 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC85XX_ESDHC_IRQ));
1051 memory_region_add_subregion(ccsr_addr_space, MPC85XX_ESDHC_REGS_OFFSET,
1052 sysbus_mmio_get_region(s, 0));
1053 }
1054
1055 /* General Utility device */
1056 dev = qdev_new("mpc8544-guts");
1057 s = SYS_BUS_DEVICE(dev);
1058 sysbus_realize_and_unref(s, &error_fatal);
1059 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
1060 sysbus_mmio_get_region(s, 0));
1061
1062 /* PCI */
1063 dev = qdev_new("e500-pcihost");
1064 object_property_add_child(OBJECT(machine), "pci-host", OBJECT(dev));
1065 qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot);
1066 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]);
1067 s = SYS_BUS_DEVICE(dev);
1068 sysbus_realize_and_unref(s, &error_fatal);
1069 for (i = 0; i < PCI_NUM_PINS; i++) {
1070 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i]));
1071 }
1072
1073 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
1074 sysbus_mmio_get_region(s, 0));
1075
1076 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
1077 if (!pci_bus)
1078 printf("couldn't create PCI controller!\n");
1079
1080 if (pci_bus) {
1081 /* Register network interfaces. */
1082 pci_init_nic_devices(pci_bus, mc->default_nic);
1083 }
1084
1085 /* Register spinning region */
1086 sysbus_create_simple("e500-spin", pmc->spin_base, NULL);
1087
1088 if (pmc->has_mpc8xxx_gpio) {
1089 qemu_irq poweroff_irq;
1090
1091 dev = qdev_new("mpc8xxx_gpio");
1092 s = SYS_BUS_DEVICE(dev);
1093 sysbus_realize_and_unref(s, &error_fatal);
1094 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ));
1095 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET,
1096 sysbus_mmio_get_region(s, 0));
1097
1098 /* Power Off GPIO at Pin 0 */
1099 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0);
1100 qdev_connect_gpio_out(dev, 0, poweroff_irq);
1101 }
1102
1103 /* Platform Bus Device */
1104 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1105 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1106 qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs);
1107 qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size);
1108 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1109 pms->pbus_dev = PLATFORM_BUS_DEVICE(dev);
1110
1111 s = SYS_BUS_DEVICE(pms->pbus_dev);
1112 for (i = 0; i < pmc->platform_bus_num_irqs; i++) {
1113 int irqn = pmc->platform_bus_first_irq + i;
1114 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn));
1115 }
1116
1117 memory_region_add_subregion(address_space_mem,
1118 pmc->platform_bus_base,
1119 &pms->pbus_dev->mmio);
1120
1121 dinfo = drive_get(IF_PFLASH, 0, 0);
1122 if (dinfo) {
1123 BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
1124 BlockDriverState *bs = blk_bs(blk);
1125 uint64_t mmio_size = memory_region_size(&pms->pbus_dev->mmio);
1126 uint64_t size = bdrv_getlength(bs);
1127 uint32_t sector_len = 64 * KiB;
1128
1129 if (!is_power_of_2(size)) {
1130 error_report("Size of pflash file must be a power of two.");
1131 exit(1);
1132 }
1133
1134 if (size > mmio_size) {
1135 error_report("Size of pflash file must not be bigger than %" PRIu64
1136 " bytes.", mmio_size);
1137 exit(1);
1138 }
1139
1140 if (!QEMU_IS_ALIGNED(size, sector_len)) {
1141 error_report("Size of pflash file must be a multiple of %" PRIu32
1142 ".", sector_len);
1143 exit(1);
1144 }
1145
1146 dev = qdev_new(TYPE_PFLASH_CFI01);
1147 qdev_prop_set_drive(dev, "drive", blk);
1148 qdev_prop_set_uint32(dev, "num-blocks", size / sector_len);
1149 qdev_prop_set_uint64(dev, "sector-length", sector_len);
1150 qdev_prop_set_uint8(dev, "width", 2);
1151 qdev_prop_set_bit(dev, "big-endian", true);
1152 qdev_prop_set_uint16(dev, "id0", 0x89);
1153 qdev_prop_set_uint16(dev, "id1", 0x18);
1154 qdev_prop_set_uint16(dev, "id2", 0x0000);
1155 qdev_prop_set_uint16(dev, "id3", 0x0);
1156 qdev_prop_set_string(dev, "name", "e500.flash");
1157 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1158
1159 memory_region_add_subregion(&pms->pbus_dev->mmio, 0,
1160 pflash_cfi01_get_memory(PFLASH_CFI01(dev)));
1161 }
1162
1163 /*
1164 * Smart firmware defaults ahead!
1165 *
1166 * We follow the following table to select which payload we execute.
1167 *
1168 * -kernel | -bios | payload
1169 * ---------+-------+---------
1170 * N | Y | u-boot
1171 * N | N | u-boot
1172 * Y | Y | u-boot
1173 * Y | N | kernel
1174 *
1175 * This ensures backwards compatibility with how we used to expose
1176 * -kernel to users but allows them to run through u-boot as well.
1177 */
1178 kernel_as_payload = false;
1179 if (machine->firmware == NULL) {
1180 if (machine->kernel_filename) {
1181 payload_name = machine->kernel_filename;
1182 kernel_as_payload = true;
1183 } else {
1184 payload_name = "u-boot.e500";
1185 }
1186 } else {
1187 payload_name = machine->firmware;
1188 }
1189
1190 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name);
1191 if (!filename) {
1192 error_report("could not find firmware/kernel file '%s'", payload_name);
1193 exit(1);
1194 }
1195
1196 payload_size = load_elf(filename, NULL, NULL, NULL,
1197 &bios_entry, &loadaddr, NULL, NULL,
1198 ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0);
1199 if (payload_size < 0) {
1200 /*
1201 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an
1202 * ePAPR compliant kernel
1203 */
1204 loadaddr = LOAD_UIMAGE_LOADADDR_INVALID;
1205 payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL,
1206 NULL, NULL);
1207 if (payload_size < 0) {
1208 error_report("could not load firmware '%s'", filename);
1209 exit(1);
1210 }
1211 }
1212
1213 g_free(filename);
1214
1215 if (kernel_as_payload) {
1216 kernel_base = loadaddr;
1217 kernel_size = payload_size;
1218 }
1219
1220 cur_base = loadaddr + payload_size;
1221 if (cur_base < 32 * MiB) {
1222 /* u-boot occupies memory up to 32MB, so load blobs above */
1223 cur_base = 32 * MiB;
1224 }
1225
1226 /* Load bare kernel only if no bios/u-boot has been provided */
1227 if (machine->kernel_filename && !kernel_as_payload) {
1228 kernel_base = cur_base;
1229 kernel_size = load_image_targphys(machine->kernel_filename,
1230 cur_base,
1231 machine->ram_size - cur_base);
1232 if (kernel_size < 0) {
1233 error_report("could not load kernel '%s'",
1234 machine->kernel_filename);
1235 exit(1);
1236 }
1237
1238 cur_base += kernel_size;
1239 }
1240
1241 /* Load initrd. */
1242 if (machine->initrd_filename) {
1243 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
1244 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base,
1245 machine->ram_size - initrd_base);
1246
1247 if (initrd_size < 0) {
1248 error_report("could not load initial ram disk '%s'",
1249 machine->initrd_filename);
1250 exit(1);
1251 }
1252
1253 cur_base = initrd_base + initrd_size;
1254 }
1255
1256 /*
1257 * Reserve space for dtb behind the kernel image because Linux has a bug
1258 * where it can only handle the dtb if it's within the first 64MB of where
1259 * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD
1260 * ensures enough space between kernel and initrd.
1261 */
1262 dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
1263 if (dt_base + DTB_MAX_SIZE > machine->ram_size) {
1264 error_report("not enough memory for device tree");
1265 exit(1);
1266 }
1267
1268 dt_size = ppce500_prep_device_tree(pms, dt_base,
1269 initrd_base, initrd_size,
1270 kernel_base, kernel_size);
1271 if (dt_size < 0) {
1272 error_report("couldn't load device tree");
1273 exit(1);
1274 }
1275 assert(dt_size < DTB_MAX_SIZE);
1276
1277 boot_info->entry = bios_entry;
1278 boot_info->dt_base = dt_base;
1279 boot_info->dt_size = dt_size;
1280 }
1281
e500_ccsr_initfn(Object * obj)1282 static void e500_ccsr_initfn(Object *obj)
1283 {
1284 PPCE500CCSRState *ccsr = CCSR(obj);
1285 memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr",
1286 MPC8544_CCSRBAR_SIZE);
1287 }
1288
1289 static const TypeInfo e500_ccsr_info = {
1290 .name = TYPE_CCSR,
1291 .parent = TYPE_SYS_BUS_DEVICE,
1292 .instance_size = sizeof(PPCE500CCSRState),
1293 .instance_init = e500_ccsr_initfn,
1294 };
1295
1296 static const TypeInfo ppce500_info = {
1297 .name = TYPE_PPCE500_MACHINE,
1298 .parent = TYPE_MACHINE,
1299 .abstract = true,
1300 .instance_size = sizeof(PPCE500MachineState),
1301 .class_size = sizeof(PPCE500MachineClass),
1302 };
1303
e500_register_types(void)1304 static void e500_register_types(void)
1305 {
1306 type_register_static(&e500_ccsr_info);
1307 type_register_static(&ppce500_info);
1308 }
1309
1310 type_init(e500_register_types)
1311