1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright(c) 2020-2021 Intel Corporation. */
3 #ifndef __CXL_MEM_H__
4 #define __CXL_MEM_H__
5 #include <uapi/linux/cxl_mem.h>
6 #include <linux/cdev.h>
7 #include <linux/uuid.h>
8 #include <linux/rcuwait.h>
9 #include <linux/cxl-event.h>
10 #include <linux/node.h>
11 #include "cxl.h"
12
13 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */
14 #define CXLMDEV_STATUS_OFFSET 0x0
15 #define CXLMDEV_DEV_FATAL BIT(0)
16 #define CXLMDEV_FW_HALT BIT(1)
17 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2)
18 #define CXLMDEV_MS_NOT_READY 0
19 #define CXLMDEV_MS_READY 1
20 #define CXLMDEV_MS_ERROR 2
21 #define CXLMDEV_MS_DISABLED 3
22 #define CXLMDEV_READY(status) \
23 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \
24 CXLMDEV_MS_READY)
25 #define CXLMDEV_MBOX_IF_READY BIT(4)
26 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5)
27 #define CXLMDEV_RESET_NEEDED_NOT 0
28 #define CXLMDEV_RESET_NEEDED_COLD 1
29 #define CXLMDEV_RESET_NEEDED_WARM 2
30 #define CXLMDEV_RESET_NEEDED_HOT 3
31 #define CXLMDEV_RESET_NEEDED_CXL 4
32 #define CXLMDEV_RESET_NEEDED(status) \
33 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \
34 CXLMDEV_RESET_NEEDED_NOT)
35
36 /**
37 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device
38 * @dev: driver core device object
39 * @cdev: char dev core object for ioctl operations
40 * @cxlds: The device state backing this device
41 * @detach_work: active memdev lost a port in its ancestry
42 * @cxl_nvb: coordinate removal of @cxl_nvd if present
43 * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem
44 * @endpoint: connection to the CXL port topology for this memory device
45 * @id: id number of this memdev instance.
46 * @depth: endpoint port depth
47 */
48 struct cxl_memdev {
49 struct device dev;
50 struct cdev cdev;
51 struct cxl_dev_state *cxlds;
52 struct work_struct detach_work;
53 struct cxl_nvdimm_bridge *cxl_nvb;
54 struct cxl_nvdimm *cxl_nvd;
55 struct cxl_port *endpoint;
56 int id;
57 int depth;
58 };
59
to_cxl_memdev(struct device * dev)60 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev)
61 {
62 return container_of(dev, struct cxl_memdev, dev);
63 }
64
cxled_to_port(struct cxl_endpoint_decoder * cxled)65 static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled)
66 {
67 return to_cxl_port(cxled->cxld.dev.parent);
68 }
69
cxlrd_to_port(struct cxl_root_decoder * cxlrd)70 static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd)
71 {
72 return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent);
73 }
74
75 static inline struct cxl_memdev *
cxled_to_memdev(struct cxl_endpoint_decoder * cxled)76 cxled_to_memdev(struct cxl_endpoint_decoder *cxled)
77 {
78 struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent);
79
80 return to_cxl_memdev(port->uport_dev);
81 }
82
83 bool is_cxl_memdev(const struct device *dev);
is_cxl_endpoint(struct cxl_port * port)84 static inline bool is_cxl_endpoint(struct cxl_port *port)
85 {
86 return is_cxl_memdev(port->uport_dev);
87 }
88
89 struct cxl_memdev *devm_cxl_add_memdev(struct device *host,
90 struct cxl_dev_state *cxlds);
91 int devm_cxl_sanitize_setup_notifier(struct device *host,
92 struct cxl_memdev *cxlmd);
93 struct cxl_memdev_state;
94 int devm_cxl_setup_fw_upload(struct device *host, struct cxl_memdev_state *mds);
95 int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled,
96 resource_size_t base, resource_size_t len,
97 resource_size_t skipped);
98
cxl_ep_load(struct cxl_port * port,struct cxl_memdev * cxlmd)99 static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port,
100 struct cxl_memdev *cxlmd)
101 {
102 if (!port)
103 return NULL;
104
105 return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev);
106 }
107
108 /**
109 * struct cxl_mbox_cmd - A command to be submitted to hardware.
110 * @opcode: (input) The command set and command submitted to hardware.
111 * @payload_in: (input) Pointer to the input payload.
112 * @payload_out: (output) Pointer to the output payload. Must be allocated by
113 * the caller.
114 * @size_in: (input) Number of bytes to load from @payload_in.
115 * @size_out: (input) Max number of bytes loaded into @payload_out.
116 * (output) Number of bytes generated by the device. For fixed size
117 * outputs commands this is always expected to be deterministic. For
118 * variable sized output commands, it tells the exact number of bytes
119 * written.
120 * @min_out: (input) internal command output payload size validation
121 * @poll_count: (input) Number of timeouts to attempt.
122 * @poll_interval_ms: (input) Time between mailbox background command polling
123 * interval timeouts.
124 * @return_code: (output) Error code returned from hardware.
125 *
126 * This is the primary mechanism used to send commands to the hardware.
127 * All the fields except @payload_* correspond exactly to the fields described in
128 * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and
129 * @payload_out are written to, and read from the Command Payload Registers
130 * defined in CXL 2.0 8.2.8.4.8.
131 */
132 struct cxl_mbox_cmd {
133 u16 opcode;
134 void *payload_in;
135 void *payload_out;
136 size_t size_in;
137 size_t size_out;
138 size_t min_out;
139 int poll_count;
140 int poll_interval_ms;
141 u16 return_code;
142 };
143
144 /*
145 * Per CXL 3.0 Section 8.2.8.4.5.1
146 */
147 #define CMD_CMD_RC_TABLE \
148 C(SUCCESS, 0, NULL), \
149 C(BACKGROUND, -ENXIO, "background cmd started successfully"), \
150 C(INPUT, -ENXIO, "cmd input was invalid"), \
151 C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \
152 C(INTERNAL, -ENXIO, "internal device error"), \
153 C(RETRY, -ENXIO, "temporary error, retry once"), \
154 C(BUSY, -ENXIO, "ongoing background operation"), \
155 C(MEDIADISABLED, -ENXIO, "media access is disabled"), \
156 C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \
157 C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \
158 C(FWAUTH, -ENXIO, "FW package authentication failed"), \
159 C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \
160 C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \
161 C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \
162 C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \
163 C(PADDR, -EFAULT, "physical address specified is invalid"), \
164 C(POISONLMT, -ENXIO, "poison injection limit has been reached"), \
165 C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \
166 C(ABORT, -ENXIO, "background cmd was aborted by device"), \
167 C(SECURITY, -ENXIO, "not valid in the current security state"), \
168 C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \
169 C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\
170 C(PAYLOADLEN, -ENXIO, "invalid payload length"), \
171 C(LOG, -ENXIO, "invalid or unsupported log page"), \
172 C(INTERRUPTED, -ENXIO, "asynchronous event occured"), \
173 C(FEATUREVERSION, -ENXIO, "unsupported feature version"), \
174 C(FEATURESELVALUE, -ENXIO, "unsupported feature selection value"), \
175 C(FEATURETRANSFERIP, -ENXIO, "feature transfer in progress"), \
176 C(FEATURETRANSFEROOO, -ENXIO, "feature transfer out of order"), \
177 C(RESOURCEEXHAUSTED, -ENXIO, "resources are exhausted"), \
178 C(EXTLIST, -ENXIO, "invalid Extent List"), \
179
180 #undef C
181 #define C(a, b, c) CXL_MBOX_CMD_RC_##a
182 enum { CMD_CMD_RC_TABLE };
183 #undef C
184 #define C(a, b, c) { b, c }
185 struct cxl_mbox_cmd_rc {
186 int err;
187 const char *desc;
188 };
189
190 static const
191 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE };
192 #undef C
193
cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd * mbox_cmd)194 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd)
195 {
196 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc;
197 }
198
cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd * mbox_cmd)199 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd)
200 {
201 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err;
202 }
203
204 /*
205 * CXL 2.0 - Memory capacity multiplier
206 * See Section 8.2.9.5
207 *
208 * Volatile, Persistent, and Partition capacities are specified to be in
209 * multiples of 256MB - define a multiplier to convert to/from bytes.
210 */
211 #define CXL_CAPACITY_MULTIPLIER SZ_256M
212
213 /*
214 * Event Interrupt Policy
215 *
216 * CXL rev 3.0 section 8.2.9.2.4; Table 8-52
217 */
218 enum cxl_event_int_mode {
219 CXL_INT_NONE = 0x00,
220 CXL_INT_MSI_MSIX = 0x01,
221 CXL_INT_FW = 0x02
222 };
223 struct cxl_event_interrupt_policy {
224 u8 info_settings;
225 u8 warn_settings;
226 u8 failure_settings;
227 u8 fatal_settings;
228 } __packed;
229
230 /**
231 * struct cxl_event_state - Event log driver state
232 *
233 * @buf: Buffer to receive event data
234 * @log_lock: Serialize event_buf and log use
235 */
236 struct cxl_event_state {
237 struct cxl_get_event_payload *buf;
238 struct mutex log_lock;
239 };
240
241 /* Device enabled poison commands */
242 enum poison_cmd_enabled_bits {
243 CXL_POISON_ENABLED_LIST,
244 CXL_POISON_ENABLED_INJECT,
245 CXL_POISON_ENABLED_CLEAR,
246 CXL_POISON_ENABLED_SCAN_CAPS,
247 CXL_POISON_ENABLED_SCAN_MEDIA,
248 CXL_POISON_ENABLED_SCAN_RESULTS,
249 CXL_POISON_ENABLED_MAX
250 };
251
252 /* Device enabled security commands */
253 enum security_cmd_enabled_bits {
254 CXL_SEC_ENABLED_SANITIZE,
255 CXL_SEC_ENABLED_SECURE_ERASE,
256 CXL_SEC_ENABLED_GET_SECURITY_STATE,
257 CXL_SEC_ENABLED_SET_PASSPHRASE,
258 CXL_SEC_ENABLED_DISABLE_PASSPHRASE,
259 CXL_SEC_ENABLED_UNLOCK,
260 CXL_SEC_ENABLED_FREEZE_SECURITY,
261 CXL_SEC_ENABLED_PASSPHRASE_SECURE_ERASE,
262 CXL_SEC_ENABLED_MAX
263 };
264
265 /**
266 * struct cxl_poison_state - Driver poison state info
267 *
268 * @max_errors: Maximum media error records held in device cache
269 * @enabled_cmds: All poison commands enabled in the CEL
270 * @list_out: The poison list payload returned by device
271 * @lock: Protect reads of the poison list
272 *
273 * Reads of the poison list are synchronized to ensure that a reader
274 * does not get an incomplete list because their request overlapped
275 * (was interrupted or preceded by) another read request of the same
276 * DPA range. CXL Spec 3.0 Section 8.2.9.8.4.1
277 */
278 struct cxl_poison_state {
279 u32 max_errors;
280 DECLARE_BITMAP(enabled_cmds, CXL_POISON_ENABLED_MAX);
281 struct cxl_mbox_poison_out *list_out;
282 struct mutex lock; /* Protect reads of poison list */
283 };
284
285 /*
286 * Get FW Info
287 * CXL rev 3.0 section 8.2.9.3.1; Table 8-56
288 */
289 struct cxl_mbox_get_fw_info {
290 u8 num_slots;
291 u8 slot_info;
292 u8 activation_cap;
293 u8 reserved[13];
294 char slot_1_revision[16];
295 char slot_2_revision[16];
296 char slot_3_revision[16];
297 char slot_4_revision[16];
298 } __packed;
299
300 #define CXL_FW_INFO_SLOT_INFO_CUR_MASK GENMASK(2, 0)
301 #define CXL_FW_INFO_SLOT_INFO_NEXT_MASK GENMASK(5, 3)
302 #define CXL_FW_INFO_SLOT_INFO_NEXT_SHIFT 3
303 #define CXL_FW_INFO_ACTIVATION_CAP_HAS_LIVE_ACTIVATE BIT(0)
304
305 /*
306 * Transfer FW Input Payload
307 * CXL rev 3.0 section 8.2.9.3.2; Table 8-57
308 */
309 struct cxl_mbox_transfer_fw {
310 u8 action;
311 u8 slot;
312 u8 reserved[2];
313 __le32 offset;
314 u8 reserved2[0x78];
315 u8 data[];
316 } __packed;
317
318 #define CXL_FW_TRANSFER_ACTION_FULL 0x0
319 #define CXL_FW_TRANSFER_ACTION_INITIATE 0x1
320 #define CXL_FW_TRANSFER_ACTION_CONTINUE 0x2
321 #define CXL_FW_TRANSFER_ACTION_END 0x3
322 #define CXL_FW_TRANSFER_ACTION_ABORT 0x4
323
324 /*
325 * CXL rev 3.0 section 8.2.9.3.2 mandates 128-byte alignment for FW packages
326 * and for each part transferred in a Transfer FW command.
327 */
328 #define CXL_FW_TRANSFER_ALIGNMENT 128
329
330 /*
331 * Activate FW Input Payload
332 * CXL rev 3.0 section 8.2.9.3.3; Table 8-58
333 */
334 struct cxl_mbox_activate_fw {
335 u8 action;
336 u8 slot;
337 } __packed;
338
339 #define CXL_FW_ACTIVATE_ONLINE 0x0
340 #define CXL_FW_ACTIVATE_OFFLINE 0x1
341
342 /* FW state bits */
343 #define CXL_FW_STATE_BITS 32
344 #define CXL_FW_CANCEL 0
345
346 /**
347 * struct cxl_fw_state - Firmware upload / activation state
348 *
349 * @state: fw_uploader state bitmask
350 * @oneshot: whether the fw upload fits in a single transfer
351 * @num_slots: Number of FW slots available
352 * @cur_slot: Slot number currently active
353 * @next_slot: Slot number for the new firmware
354 */
355 struct cxl_fw_state {
356 DECLARE_BITMAP(state, CXL_FW_STATE_BITS);
357 bool oneshot;
358 int num_slots;
359 int cur_slot;
360 int next_slot;
361 };
362
363 /**
364 * struct cxl_security_state - Device security state
365 *
366 * @state: state of last security operation
367 * @enabled_cmds: All security commands enabled in the CEL
368 * @poll_tmo_secs: polling timeout
369 * @sanitize_active: sanitize completion pending
370 * @poll_dwork: polling work item
371 * @sanitize_node: sanitation sysfs file to notify
372 */
373 struct cxl_security_state {
374 unsigned long state;
375 DECLARE_BITMAP(enabled_cmds, CXL_SEC_ENABLED_MAX);
376 int poll_tmo_secs;
377 bool sanitize_active;
378 struct delayed_work poll_dwork;
379 struct kernfs_node *sanitize_node;
380 };
381
382 /*
383 * enum cxl_devtype - delineate type-2 from a generic type-3 device
384 * @CXL_DEVTYPE_DEVMEM - Vendor specific CXL Type-2 device implementing HDM-D or
385 * HDM-DB, no requirement that this device implements a
386 * mailbox, or other memory-device-standard manageability
387 * flows.
388 * @CXL_DEVTYPE_CLASSMEM - Common class definition of a CXL Type-3 device with
389 * HDM-H and class-mandatory memory device registers
390 */
391 enum cxl_devtype {
392 CXL_DEVTYPE_DEVMEM,
393 CXL_DEVTYPE_CLASSMEM,
394 };
395
396 /**
397 * struct cxl_dpa_perf - DPA performance property entry
398 * @dpa_range - range for DPA address
399 * @coord - QoS performance data (i.e. latency, bandwidth)
400 * @qos_class - QoS Class cookies
401 */
402 struct cxl_dpa_perf {
403 struct range dpa_range;
404 struct access_coordinate coord;
405 int qos_class;
406 };
407
408 /**
409 * struct cxl_dev_state - The driver device state
410 *
411 * cxl_dev_state represents the CXL driver/device state. It provides an
412 * interface to mailbox commands as well as some cached data about the device.
413 * Currently only memory devices are represented.
414 *
415 * @dev: The device associated with this CXL state
416 * @cxlmd: The device representing the CXL.mem capabilities of @dev
417 * @reg_map: component and ras register mapping parameters
418 * @regs: Parsed register blocks
419 * @cxl_dvsec: Offset to the PCIe device DVSEC
420 * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
421 * @media_ready: Indicate whether the device media is usable
422 * @dpa_res: Overall DPA resource tree for the device
423 * @pmem_res: Active Persistent memory capacity configuration
424 * @ram_res: Active Volatile memory capacity configuration
425 * @serial: PCIe Device Serial Number
426 * @type: Generic Memory Class device or Vendor Specific Memory device
427 */
428 struct cxl_dev_state {
429 struct device *dev;
430 struct cxl_memdev *cxlmd;
431 struct cxl_register_map reg_map;
432 struct cxl_regs regs;
433 int cxl_dvsec;
434 bool rcd;
435 bool media_ready;
436 struct resource dpa_res;
437 struct resource pmem_res;
438 struct resource ram_res;
439 u64 serial;
440 enum cxl_devtype type;
441 };
442
443 /**
444 * struct cxl_memdev_state - Generic Type-3 Memory Device Class driver data
445 *
446 * CXL 8.1.12.1 PCI Header - Class Code Register Memory Device defines
447 * common memory device functionality like the presence of a mailbox and
448 * the functionality related to that like Identify Memory Device and Get
449 * Partition Info
450 * @cxlds: Core driver state common across Type-2 and Type-3 devices
451 * @payload_size: Size of space for payload
452 * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register)
453 * @lsa_size: Size of Label Storage Area
454 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device)
455 * @mbox_mutex: Mutex to synchronize mailbox access.
456 * @firmware_version: Firmware version for the memory device.
457 * @enabled_cmds: Hardware commands found enabled in CEL.
458 * @exclusive_cmds: Commands that are kernel-internal only
459 * @total_bytes: sum of all possible capacities
460 * @volatile_only_bytes: hard volatile capacity
461 * @persistent_only_bytes: hard persistent capacity
462 * @partition_align_bytes: alignment size for partition-able capacity
463 * @active_volatile_bytes: sum of hard + soft volatile
464 * @active_persistent_bytes: sum of hard + soft persistent
465 * @next_volatile_bytes: volatile capacity change pending device reset
466 * @next_persistent_bytes: persistent capacity change pending device reset
467 * @event: event log driver state
468 * @poison: poison driver state info
469 * @security: security driver state info
470 * @fw: firmware upload / activation state
471 * @mbox_send: @dev specific transport for transmitting mailbox commands
472 * @ram_perf: performance data entry matched to RAM partition
473 * @pmem_perf: performance data entry matched to PMEM partition
474 *
475 * See CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for
476 * details on capacity parameters.
477 */
478 struct cxl_memdev_state {
479 struct cxl_dev_state cxlds;
480 size_t payload_size;
481 size_t lsa_size;
482 struct mutex mbox_mutex; /* Protects device mailbox and firmware */
483 char firmware_version[0x10];
484 DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX);
485 DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX);
486 u64 total_bytes;
487 u64 volatile_only_bytes;
488 u64 persistent_only_bytes;
489 u64 partition_align_bytes;
490 u64 active_volatile_bytes;
491 u64 active_persistent_bytes;
492 u64 next_volatile_bytes;
493 u64 next_persistent_bytes;
494
495 struct cxl_dpa_perf ram_perf;
496 struct cxl_dpa_perf pmem_perf;
497
498 struct cxl_event_state event;
499 struct cxl_poison_state poison;
500 struct cxl_security_state security;
501 struct cxl_fw_state fw;
502
503 struct rcuwait mbox_wait;
504 int (*mbox_send)(struct cxl_memdev_state *mds,
505 struct cxl_mbox_cmd *cmd);
506 };
507
508 static inline struct cxl_memdev_state *
to_cxl_memdev_state(struct cxl_dev_state * cxlds)509 to_cxl_memdev_state(struct cxl_dev_state *cxlds)
510 {
511 if (cxlds->type != CXL_DEVTYPE_CLASSMEM)
512 return NULL;
513 return container_of(cxlds, struct cxl_memdev_state, cxlds);
514 }
515
516 enum cxl_opcode {
517 CXL_MBOX_OP_INVALID = 0x0000,
518 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID,
519 CXL_MBOX_OP_GET_EVENT_RECORD = 0x0100,
520 CXL_MBOX_OP_CLEAR_EVENT_RECORD = 0x0101,
521 CXL_MBOX_OP_GET_EVT_INT_POLICY = 0x0102,
522 CXL_MBOX_OP_SET_EVT_INT_POLICY = 0x0103,
523 CXL_MBOX_OP_GET_FW_INFO = 0x0200,
524 CXL_MBOX_OP_TRANSFER_FW = 0x0201,
525 CXL_MBOX_OP_ACTIVATE_FW = 0x0202,
526 CXL_MBOX_OP_GET_TIMESTAMP = 0x0300,
527 CXL_MBOX_OP_SET_TIMESTAMP = 0x0301,
528 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400,
529 CXL_MBOX_OP_GET_LOG = 0x0401,
530 CXL_MBOX_OP_IDENTIFY = 0x4000,
531 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100,
532 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101,
533 CXL_MBOX_OP_GET_LSA = 0x4102,
534 CXL_MBOX_OP_SET_LSA = 0x4103,
535 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200,
536 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201,
537 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202,
538 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203,
539 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204,
540 CXL_MBOX_OP_GET_POISON = 0x4300,
541 CXL_MBOX_OP_INJECT_POISON = 0x4301,
542 CXL_MBOX_OP_CLEAR_POISON = 0x4302,
543 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303,
544 CXL_MBOX_OP_SCAN_MEDIA = 0x4304,
545 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305,
546 CXL_MBOX_OP_SANITIZE = 0x4400,
547 CXL_MBOX_OP_SECURE_ERASE = 0x4401,
548 CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500,
549 CXL_MBOX_OP_SET_PASSPHRASE = 0x4501,
550 CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502,
551 CXL_MBOX_OP_UNLOCK = 0x4503,
552 CXL_MBOX_OP_FREEZE_SECURITY = 0x4504,
553 CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505,
554 CXL_MBOX_OP_MAX = 0x10000
555 };
556
557 #define DEFINE_CXL_CEL_UUID \
558 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \
559 0x3b, 0x3f, 0x17)
560
561 #define DEFINE_CXL_VENDOR_DEBUG_UUID \
562 UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \
563 0x40, 0x3d, 0x86)
564
565 struct cxl_mbox_get_supported_logs {
566 __le16 entries;
567 u8 rsvd[6];
568 struct cxl_gsl_entry {
569 uuid_t uuid;
570 __le32 size;
571 } __packed entry[];
572 } __packed;
573
574 struct cxl_cel_entry {
575 __le16 opcode;
576 __le16 effect;
577 } __packed;
578
579 struct cxl_mbox_get_log {
580 uuid_t uuid;
581 __le32 offset;
582 __le32 length;
583 } __packed;
584
585 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */
586 struct cxl_mbox_identify {
587 char fw_revision[0x10];
588 __le64 total_capacity;
589 __le64 volatile_capacity;
590 __le64 persistent_capacity;
591 __le64 partition_align;
592 __le16 info_event_log_size;
593 __le16 warning_event_log_size;
594 __le16 failure_event_log_size;
595 __le16 fatal_event_log_size;
596 __le32 lsa_size;
597 u8 poison_list_max_mer[3];
598 __le16 inject_poison_limit;
599 u8 poison_caps;
600 u8 qos_telemetry_caps;
601 } __packed;
602
603 /*
604 * General Media Event Record UUID
605 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
606 */
607 #define CXL_EVENT_GEN_MEDIA_UUID \
608 UUID_INIT(0xfbcd0a77, 0xc260, 0x417f, 0x85, 0xa9, 0x08, 0x8b, 0x16, \
609 0x21, 0xeb, 0xa6)
610
611 /*
612 * DRAM Event Record UUID
613 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44
614 */
615 #define CXL_EVENT_DRAM_UUID \
616 UUID_INIT(0x601dcbb3, 0x9c06, 0x4eab, 0xb8, 0xaf, 0x4e, 0x9b, 0xfb, \
617 0x5c, 0x96, 0x24)
618
619 /*
620 * Memory Module Event Record UUID
621 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45
622 */
623 #define CXL_EVENT_MEM_MODULE_UUID \
624 UUID_INIT(0xfe927475, 0xdd59, 0x4339, 0xa5, 0x86, 0x79, 0xba, 0xb1, \
625 0x13, 0xb7, 0x74)
626
627 /*
628 * Get Event Records output payload
629 * CXL rev 3.0 section 8.2.9.2.2; Table 8-50
630 */
631 #define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0)
632 #define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1)
633 struct cxl_get_event_payload {
634 u8 flags;
635 u8 reserved1;
636 __le16 overflow_err_count;
637 __le64 first_overflow_timestamp;
638 __le64 last_overflow_timestamp;
639 __le16 record_count;
640 u8 reserved2[10];
641 struct cxl_event_record_raw records[];
642 } __packed;
643
644 /*
645 * CXL rev 3.0 section 8.2.9.2.2; Table 8-49
646 */
647 enum cxl_event_log_type {
648 CXL_EVENT_TYPE_INFO = 0x00,
649 CXL_EVENT_TYPE_WARN,
650 CXL_EVENT_TYPE_FAIL,
651 CXL_EVENT_TYPE_FATAL,
652 CXL_EVENT_TYPE_MAX
653 };
654
655 /*
656 * Clear Event Records input payload
657 * CXL rev 3.0 section 8.2.9.2.3; Table 8-51
658 */
659 struct cxl_mbox_clear_event_payload {
660 u8 event_log; /* enum cxl_event_log_type */
661 u8 clear_flags;
662 u8 nr_recs;
663 u8 reserved[3];
664 __le16 handles[];
665 } __packed;
666 #define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX
667
668 struct cxl_mbox_get_partition_info {
669 __le64 active_volatile_cap;
670 __le64 active_persistent_cap;
671 __le64 next_volatile_cap;
672 __le64 next_persistent_cap;
673 } __packed;
674
675 struct cxl_mbox_get_lsa {
676 __le32 offset;
677 __le32 length;
678 } __packed;
679
680 struct cxl_mbox_set_lsa {
681 __le32 offset;
682 __le32 reserved;
683 u8 data[];
684 } __packed;
685
686 struct cxl_mbox_set_partition_info {
687 __le64 volatile_capacity;
688 u8 flags;
689 } __packed;
690
691 #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0)
692
693 /* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */
694 struct cxl_mbox_set_timestamp_in {
695 __le64 timestamp;
696
697 } __packed;
698
699 /* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */
700 struct cxl_mbox_poison_in {
701 __le64 offset;
702 __le64 length;
703 } __packed;
704
705 struct cxl_mbox_poison_out {
706 u8 flags;
707 u8 rsvd1;
708 __le64 overflow_ts;
709 __le16 count;
710 u8 rsvd2[20];
711 struct cxl_poison_record {
712 __le64 address;
713 __le32 length;
714 __le32 rsvd;
715 } __packed record[];
716 } __packed;
717
718 /*
719 * Get Poison List address field encodes the starting
720 * address of poison, and the source of the poison.
721 */
722 #define CXL_POISON_START_MASK GENMASK_ULL(63, 6)
723 #define CXL_POISON_SOURCE_MASK GENMASK(2, 0)
724
725 /* Get Poison List record length is in units of 64 bytes */
726 #define CXL_POISON_LEN_MULT 64
727
728 /* Kernel defined maximum for a list of poison errors */
729 #define CXL_POISON_LIST_MAX 1024
730
731 /* Get Poison List: Payload out flags */
732 #define CXL_POISON_FLAG_MORE BIT(0)
733 #define CXL_POISON_FLAG_OVERFLOW BIT(1)
734 #define CXL_POISON_FLAG_SCANNING BIT(2)
735
736 /* Get Poison List: Poison Source */
737 #define CXL_POISON_SOURCE_UNKNOWN 0
738 #define CXL_POISON_SOURCE_EXTERNAL 1
739 #define CXL_POISON_SOURCE_INTERNAL 2
740 #define CXL_POISON_SOURCE_INJECTED 3
741 #define CXL_POISON_SOURCE_VENDOR 7
742
743 /* Inject & Clear Poison CXL 3.0 Spec 8.2.9.8.4.2/3 */
744 struct cxl_mbox_inject_poison {
745 __le64 address;
746 };
747
748 /* Clear Poison CXL 3.0 Spec 8.2.9.8.4.3 */
749 struct cxl_mbox_clear_poison {
750 __le64 address;
751 u8 write_data[CXL_POISON_LEN_MULT];
752 } __packed;
753
754 /**
755 * struct cxl_mem_command - Driver representation of a memory device command
756 * @info: Command information as it exists for the UAPI
757 * @opcode: The actual bits used for the mailbox protocol
758 * @flags: Set of flags effecting driver behavior.
759 *
760 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag
761 * will be enabled by the driver regardless of what hardware may have
762 * advertised.
763 *
764 * The cxl_mem_command is the driver's internal representation of commands that
765 * are supported by the driver. Some of these commands may not be supported by
766 * the hardware. The driver will use @info to validate the fields passed in by
767 * the user then submit the @opcode to the hardware.
768 *
769 * See struct cxl_command_info.
770 */
771 struct cxl_mem_command {
772 struct cxl_command_info info;
773 enum cxl_opcode opcode;
774 u32 flags;
775 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0)
776 };
777
778 #define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01
779 #define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02
780 #define CXL_PMEM_SEC_STATE_LOCKED 0x04
781 #define CXL_PMEM_SEC_STATE_FROZEN 0x08
782 #define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10
783 #define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20
784
785 /* set passphrase input payload */
786 struct cxl_set_pass {
787 u8 type;
788 u8 reserved[31];
789 /* CXL field using NVDIMM define, same length */
790 u8 old_pass[NVDIMM_PASSPHRASE_LEN];
791 u8 new_pass[NVDIMM_PASSPHRASE_LEN];
792 } __packed;
793
794 /* disable passphrase input payload */
795 struct cxl_disable_pass {
796 u8 type;
797 u8 reserved[31];
798 u8 pass[NVDIMM_PASSPHRASE_LEN];
799 } __packed;
800
801 /* passphrase secure erase payload */
802 struct cxl_pass_erase {
803 u8 type;
804 u8 reserved[31];
805 u8 pass[NVDIMM_PASSPHRASE_LEN];
806 } __packed;
807
808 enum {
809 CXL_PMEM_SEC_PASS_MASTER = 0,
810 CXL_PMEM_SEC_PASS_USER,
811 };
812
813 int cxl_internal_send_cmd(struct cxl_memdev_state *mds,
814 struct cxl_mbox_cmd *cmd);
815 int cxl_dev_state_identify(struct cxl_memdev_state *mds);
816 int cxl_await_media_ready(struct cxl_dev_state *cxlds);
817 int cxl_enumerate_cmds(struct cxl_memdev_state *mds);
818 int cxl_mem_create_range_info(struct cxl_memdev_state *mds);
819 struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev);
820 void set_exclusive_cxl_commands(struct cxl_memdev_state *mds,
821 unsigned long *cmds);
822 void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds,
823 unsigned long *cmds);
824 void cxl_mem_get_event_records(struct cxl_memdev_state *mds, u32 status);
825 void cxl_event_trace_record(const struct cxl_memdev *cxlmd,
826 enum cxl_event_log_type type,
827 enum cxl_event_type event_type,
828 const uuid_t *uuid, union cxl_event *evt);
829 int cxl_set_timestamp(struct cxl_memdev_state *mds);
830 int cxl_poison_state_init(struct cxl_memdev_state *mds);
831 int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len,
832 struct cxl_region *cxlr);
833 int cxl_trigger_poison_list(struct cxl_memdev *cxlmd);
834 int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa);
835 int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa);
836
837 #ifdef CONFIG_CXL_SUSPEND
838 void cxl_mem_active_inc(void);
839 void cxl_mem_active_dec(void);
840 #else
cxl_mem_active_inc(void)841 static inline void cxl_mem_active_inc(void)
842 {
843 }
cxl_mem_active_dec(void)844 static inline void cxl_mem_active_dec(void)
845 {
846 }
847 #endif
848
849 int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd);
850
851 struct cxl_hdm {
852 struct cxl_component_regs regs;
853 unsigned int decoder_count;
854 unsigned int target_count;
855 unsigned int interleave_mask;
856 struct cxl_port *port;
857 };
858
859 struct seq_file;
860 struct dentry *cxl_debugfs_create_dir(const char *dir);
861 void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds);
862 #endif /* __CXL_MEM_H__ */
863