1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 *
4 * arch/xtensa/platform/xtavnet/setup.c
5 *
6 * ...
7 *
8 * Authors: Chris Zankel <chris@zankel.net>
9 * Joe Taylor <joe@tensilica.com>
10 *
11 * Copyright 2001 - 2006 Tensilica Inc.
12 */
13 #include <linux/stddef.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17 #include <linux/errno.h>
18 #include <linux/reboot.h>
19 #include <linux/kdev_t.h>
20 #include <linux/types.h>
21 #include <linux/major.h>
22 #include <linux/console.h>
23 #include <linux/delay.h>
24 #include <linux/of.h>
25 #include <linux/clk-provider.h>
26 #include <linux/of_address.h>
27 #include <linux/slab.h>
28
29 #include <asm/timex.h>
30 #include <asm/processor.h>
31 #include <asm/platform.h>
32 #include <asm/bootparam.h>
33 #include <platform/lcd.h>
34 #include <platform/hardware.h>
35
platform_halt(void)36 void platform_halt(void)
37 {
38 lcd_disp_at_pos(" HALT ", 0);
39 local_irq_disable();
40 while (1)
41 cpu_relax();
42 }
43
platform_power_off(void)44 void platform_power_off(void)
45 {
46 lcd_disp_at_pos("POWEROFF", 0);
47 local_irq_disable();
48 while (1)
49 cpu_relax();
50 }
51
platform_restart(void)52 void platform_restart(void)
53 {
54 /* Flush and reset the mmu, simulate a processor reset, and
55 * jump to the reset vector. */
56 cpu_reset();
57 /* control never gets here */
58 }
59
60 #ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT
61
platform_calibrate_ccount(void)62 void __init platform_calibrate_ccount(void)
63 {
64 ccount_freq = *(long *)XTFPGA_CLKFRQ_VADDR;
65 }
66
67 #endif
68
69 #ifdef CONFIG_OF
70
xtfpga_clk_setup(struct device_node * np)71 static void __init xtfpga_clk_setup(struct device_node *np)
72 {
73 void __iomem *base = of_iomap(np, 0);
74 struct clk *clk;
75 u32 freq;
76
77 if (!base) {
78 pr_err("%pOFn: invalid address\n", np);
79 return;
80 }
81
82 freq = __raw_readl(base);
83 iounmap(base);
84 clk = clk_register_fixed_rate(NULL, np->name, NULL, 0, freq);
85
86 if (IS_ERR(clk)) {
87 pr_err("%pOFn: clk registration failed\n", np);
88 return;
89 }
90
91 if (of_clk_add_provider(np, of_clk_src_simple_get, clk)) {
92 pr_err("%pOFn: clk provider registration failed\n", np);
93 return;
94 }
95 }
96 CLK_OF_DECLARE(xtfpga_clk, "cdns,xtfpga-clock", xtfpga_clk_setup);
97
98 #define MAC_LEN 6
update_local_mac(struct device_node * node)99 static void __init update_local_mac(struct device_node *node)
100 {
101 struct property *newmac;
102 const u8* macaddr;
103 int prop_len;
104
105 macaddr = of_get_property(node, "local-mac-address", &prop_len);
106 if (macaddr == NULL || prop_len != MAC_LEN)
107 return;
108
109 newmac = kzalloc(sizeof(*newmac) + MAC_LEN, GFP_KERNEL);
110 if (newmac == NULL)
111 return;
112
113 newmac->value = newmac + 1;
114 newmac->length = MAC_LEN;
115 newmac->name = kstrdup("local-mac-address", GFP_KERNEL);
116 if (newmac->name == NULL) {
117 kfree(newmac);
118 return;
119 }
120
121 memcpy(newmac->value, macaddr, MAC_LEN);
122 ((u8*)newmac->value)[5] = (*(u32*)DIP_SWITCHES_VADDR) & 0x3f;
123 of_update_property(node, newmac);
124 }
125
machine_setup(void)126 static int __init machine_setup(void)
127 {
128 struct device_node *eth = NULL;
129
130 if ((eth = of_find_compatible_node(eth, NULL, "opencores,ethoc")))
131 update_local_mac(eth);
132 return 0;
133 }
134 arch_initcall(machine_setup);
135
136 #else
137
138 #include <linux/serial_8250.h>
139 #include <linux/if.h>
140 #include <net/ethoc.h>
141 #include <linux/usb/c67x00.h>
142
143 /*----------------------------------------------------------------------------
144 * Ethernet -- OpenCores Ethernet MAC (ethoc driver)
145 */
146
147 static struct resource ethoc_res[] = {
148 [0] = { /* register space */
149 .start = OETH_REGS_PADDR,
150 .end = OETH_REGS_PADDR + OETH_REGS_SIZE - 1,
151 .flags = IORESOURCE_MEM,
152 },
153 [1] = { /* buffer space */
154 .start = OETH_SRAMBUFF_PADDR,
155 .end = OETH_SRAMBUFF_PADDR + OETH_SRAMBUFF_SIZE - 1,
156 .flags = IORESOURCE_MEM,
157 },
158 [2] = { /* IRQ number */
159 .start = XTENSA_PIC_LINUX_IRQ(OETH_IRQ),
160 .end = XTENSA_PIC_LINUX_IRQ(OETH_IRQ),
161 .flags = IORESOURCE_IRQ,
162 },
163 };
164
165 static struct ethoc_platform_data ethoc_pdata = {
166 /*
167 * The MAC address for these boards is 00:50:c2:13:6f:xx.
168 * The last byte (here as zero) is read from the DIP switches on the
169 * board.
170 */
171 .hwaddr = { 0x00, 0x50, 0xc2, 0x13, 0x6f, 0 },
172 .phy_id = -1,
173 .big_endian = XCHAL_HAVE_BE,
174 };
175
176 static struct platform_device ethoc_device = {
177 .name = "ethoc",
178 .id = -1,
179 .num_resources = ARRAY_SIZE(ethoc_res),
180 .resource = ethoc_res,
181 .dev = {
182 .platform_data = ðoc_pdata,
183 },
184 };
185
186 /*----------------------------------------------------------------------------
187 * USB Host/Device -- Cypress CY7C67300
188 */
189
190 static struct resource c67x00_res[] = {
191 [0] = { /* register space */
192 .start = C67X00_PADDR,
193 .end = C67X00_PADDR + C67X00_SIZE - 1,
194 .flags = IORESOURCE_MEM,
195 },
196 [1] = { /* IRQ number */
197 .start = XTENSA_PIC_LINUX_IRQ(C67X00_IRQ),
198 .end = XTENSA_PIC_LINUX_IRQ(C67X00_IRQ),
199 .flags = IORESOURCE_IRQ,
200 },
201 };
202
203 static struct c67x00_platform_data c67x00_pdata = {
204 .sie_config = C67X00_SIE1_HOST | C67X00_SIE2_UNUSED,
205 .hpi_regstep = 4,
206 };
207
208 static struct platform_device c67x00_device = {
209 .name = "c67x00",
210 .id = -1,
211 .num_resources = ARRAY_SIZE(c67x00_res),
212 .resource = c67x00_res,
213 .dev = {
214 .platform_data = &c67x00_pdata,
215 },
216 };
217
218 /*----------------------------------------------------------------------------
219 * UART
220 */
221
222 static struct resource serial_resource = {
223 .start = DUART16552_PADDR,
224 .end = DUART16552_PADDR + 0x1f,
225 .flags = IORESOURCE_MEM,
226 };
227
228 static struct plat_serial8250_port serial_platform_data[] = {
229 [0] = {
230 .mapbase = DUART16552_PADDR,
231 .irq = XTENSA_PIC_LINUX_IRQ(DUART16552_INTNUM),
232 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
233 UPF_IOREMAP,
234 .iotype = XCHAL_HAVE_BE ? UPIO_MEM32BE : UPIO_MEM32,
235 .regshift = 2,
236 .uartclk = 0, /* set in xtavnet_init() */
237 },
238 { },
239 };
240
241 static struct platform_device xtavnet_uart = {
242 .name = "serial8250",
243 .id = PLAT8250_DEV_PLATFORM,
244 .dev = {
245 .platform_data = serial_platform_data,
246 },
247 .num_resources = 1,
248 .resource = &serial_resource,
249 };
250
251 /* platform devices */
252 static struct platform_device *platform_devices[] __initdata = {
253 ðoc_device,
254 &c67x00_device,
255 &xtavnet_uart,
256 };
257
258
xtavnet_init(void)259 static int __init xtavnet_init(void)
260 {
261 /* Ethernet MAC address. */
262 ethoc_pdata.hwaddr[5] = *(u32 *)DIP_SWITCHES_VADDR;
263
264 /* Clock rate varies among FPGA bitstreams; board specific FPGA register
265 * reports the actual clock rate.
266 */
267 serial_platform_data[0].uartclk = *(long *)XTFPGA_CLKFRQ_VADDR;
268
269
270 /* register platform devices */
271 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
272
273 /* ETHOC driver is a bit quiet; at least display Ethernet MAC, so user
274 * knows whether they set it correctly on the DIP switches.
275 */
276 pr_info("XTFPGA: Ethernet MAC %pM\n", ethoc_pdata.hwaddr);
277 ethoc_pdata.eth_clkfreq = *(long *)XTFPGA_CLKFRQ_VADDR;
278
279 return 0;
280 }
281
282 /*
283 * Register to be done during do_initcalls().
284 */
285 arch_initcall(xtavnet_init);
286
287 #endif /* CONFIG_OF */
288