1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2012-2014, 2018-2025 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_fw_api_rx_h__ 8 #define __iwl_fw_api_rx_h__ 9 10 /* API for pre-9000 hardware */ 11 12 #define IWL_RX_INFO_PHY_CNT 8 13 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1 14 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 15 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 16 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0 17 #define IWL_RX_INFO_ENERGY_ANT_B_POS 8 18 #define IWL_RX_INFO_ENERGY_ANT_C_POS 16 19 20 enum iwl_mac_context_info { 21 MAC_CONTEXT_INFO_NONE, 22 MAC_CONTEXT_INFO_GSCAN, 23 }; 24 25 /** 26 * struct iwl_rx_phy_info - phy info 27 * (REPLY_RX_PHY_CMD = 0xc0) 28 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 29 * @cfg_phy_cnt: configurable DSP phy data byte count 30 * @stat_id: configurable DSP phy data set ID 31 * @reserved1: reserved 32 * @system_timestamp: GP2 at on air rise 33 * @timestamp: TSF at on air rise 34 * @beacon_time_stamp: beacon at on-air rise 35 * @phy_flags: general phy flags: band, modulation, ... 36 * @channel: channel number 37 * @non_cfg_phy: for various implementations of non_cfg_phy 38 * @rate_n_flags: RATE_MCS_* 39 * @byte_count: frame's byte-count 40 * @frame_time: frame's time on the air, based on byte count and frame rate 41 * calculation 42 * @mac_active_msk: what MACs were active when the frame was received 43 * @mac_context_info: additional info on the context in which the frame was 44 * received as defined in &enum iwl_mac_context_info 45 * 46 * Before each Rx, the device sends this data. It contains PHY information 47 * about the reception of the packet. 48 */ 49 struct iwl_rx_phy_info { 50 u8 non_cfg_phy_cnt; 51 u8 cfg_phy_cnt; 52 u8 stat_id; 53 u8 reserved1; 54 __le32 system_timestamp; 55 __le64 timestamp; 56 __le32 beacon_time_stamp; 57 __le16 phy_flags; 58 __le16 channel; 59 __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT]; 60 __le32 rate_n_flags; 61 __le32 byte_count; 62 u8 mac_active_msk; 63 u8 mac_context_info; 64 __le16 frame_time; 65 } __packed; 66 67 /* 68 * TCP offload Rx assist info 69 * 70 * bits 0:3 - reserved 71 * bits 4:7 - MIC CRC length 72 * bits 8:12 - MAC header length 73 * bit 13 - Padding indication 74 * bit 14 - A-AMSDU indication 75 * bit 15 - Offload enabled 76 */ 77 enum iwl_csum_rx_assist_info { 78 CSUM_RXA_RESERVED_MASK = 0x000f, 79 CSUM_RXA_MICSIZE_MASK = 0x00f0, 80 CSUM_RXA_HEADERLEN_MASK = 0x1f00, 81 CSUM_RXA_PADD = BIT(13), 82 CSUM_RXA_AMSDU = BIT(14), 83 CSUM_RXA_ENA = BIT(15) 84 }; 85 86 /** 87 * struct iwl_rx_mpdu_res_start - phy info 88 * @byte_count: byte count of the frame 89 * @assist: see &enum iwl_csum_rx_assist_info 90 */ 91 struct iwl_rx_mpdu_res_start { 92 __le16 byte_count; 93 __le16 assist; 94 } __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */ 95 96 /** 97 * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags 98 * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 99 * @RX_RES_PHY_FLAGS_MOD_CCK: modulation is CCK 100 * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 101 * @RX_RES_PHY_FLAGS_NARROW_BAND: narrow band (<20 MHz) receive 102 * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 103 * @RX_RES_PHY_FLAGS_ANTENNA_POS: antenna bit position 104 * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 105 * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 106 * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 107 * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 108 */ 109 enum iwl_rx_phy_flags { 110 RX_RES_PHY_FLAGS_BAND_24 = BIT(0), 111 RX_RES_PHY_FLAGS_MOD_CCK = BIT(1), 112 RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2), 113 RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3), 114 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 115 RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 116 RX_RES_PHY_FLAGS_AGG = BIT(7), 117 RX_RES_PHY_FLAGS_OFDM_HT = BIT(8), 118 RX_RES_PHY_FLAGS_OFDM_GF = BIT(9), 119 RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10), 120 }; 121 122 /** 123 * enum iwl_mvm_rx_status - written by fw for each Rx packet 124 * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 125 * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 126 * @RX_MPDU_RES_STATUS_SRC_STA_FOUND: station was found 127 * @RX_MPDU_RES_STATUS_KEY_VALID: key was valid 128 * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 129 * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 130 * in the driver. 131 * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 132 * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 133 * alg = CCM only. Checks replay attack for 11w frames. 134 * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 135 * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 136 * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 137 * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 138 * @RX_MPDU_RES_STATUS_SEC_EXT_ENC: this frame is encrypted using extension 139 * algorithm 140 * @RX_MPDU_RES_STATUS_SEC_CMAC_GMAC_ENC: this frame is protected using 141 * CMAC or GMAC 142 * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 143 * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 144 * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 145 * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw 146 * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors 147 * @RX_MPDU_RES_STATUS_STA_ID_MSK: station ID mask 148 * @RX_MDPU_RES_STATUS_STA_ID_SHIFT: station ID bit shift 149 */ 150 enum iwl_mvm_rx_status { 151 RX_MPDU_RES_STATUS_CRC_OK = BIT(0), 152 RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1), 153 RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2), 154 RX_MPDU_RES_STATUS_KEY_VALID = BIT(3), 155 RX_MPDU_RES_STATUS_ICV_OK = BIT(5), 156 RX_MPDU_RES_STATUS_MIC_OK = BIT(6), 157 RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 158 RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7), 159 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 160 RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 161 RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 162 RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 163 RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 164 RX_MPDU_RES_STATUS_SEC_CMAC_GMAC_ENC = (6 << 8), 165 RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 166 RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 167 RX_MPDU_RES_STATUS_DEC_DONE = BIT(11), 168 RX_MPDU_RES_STATUS_CSUM_DONE = BIT(16), 169 RX_MPDU_RES_STATUS_CSUM_OK = BIT(17), 170 RX_MDPU_RES_STATUS_STA_ID_SHIFT = 24, 171 RX_MPDU_RES_STATUS_STA_ID_MSK = 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT, 172 }; 173 174 /* 9000 series API */ 175 enum iwl_rx_mpdu_mac_flags1 { 176 IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK = 0x03, 177 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK = 0xf0, 178 /* shift should be 4, but the length is measured in 2-byte 179 * words, so shifting only by 3 gives a byte result 180 */ 181 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT = 3, 182 }; 183 184 enum iwl_rx_mpdu_mac_flags2 { 185 /* in 2-byte words */ 186 IWL_RX_MPDU_MFLG2_HDR_LEN_MASK = 0x1f, 187 IWL_RX_MPDU_MFLG2_PAD = 0x20, 188 IWL_RX_MPDU_MFLG2_AMSDU = 0x40, 189 }; 190 191 enum iwl_rx_mpdu_amsdu_info { 192 IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK = 0x7f, 193 IWL_RX_MPDU_AMSDU_LAST_SUBFRAME = 0x80, 194 }; 195 196 enum iwl_rx_mpdu_mac_phy_band { 197 /* whether or not this is MAC or LINK depends on the API */ 198 IWL_RX_MPDU_MAC_PHY_BAND_MAC_MASK = 0x0f, 199 IWL_RX_MPDU_MAC_PHY_BAND_LINK_MASK = 0x0f, 200 IWL_RX_MPDU_MAC_PHY_BAND_PHY_MASK = 0x30, 201 IWL_RX_MPDU_MAC_PHY_BAND_BAND_MASK = 0xc0, 202 }; 203 204 enum iwl_rx_l3_proto_values { 205 IWL_RX_L3_TYPE_NONE, 206 IWL_RX_L3_TYPE_IPV4, 207 IWL_RX_L3_TYPE_IPV4_FRAG, 208 IWL_RX_L3_TYPE_IPV6_FRAG, 209 IWL_RX_L3_TYPE_IPV6, 210 IWL_RX_L3_TYPE_IPV6_IN_IPV4, 211 IWL_RX_L3_TYPE_ARP, 212 IWL_RX_L3_TYPE_EAPOL, 213 }; 214 215 #define IWL_RX_L3_PROTO_POS 4 216 217 enum iwl_rx_l3l4_flags { 218 IWL_RX_L3L4_IP_HDR_CSUM_OK = BIT(0), 219 IWL_RX_L3L4_TCP_UDP_CSUM_OK = BIT(1), 220 IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH = BIT(2), 221 IWL_RX_L3L4_TCP_ACK = BIT(3), 222 IWL_RX_L3L4_L3_PROTO_MASK = 0xf << IWL_RX_L3_PROTO_POS, 223 IWL_RX_L3L4_L4_PROTO_MASK = 0xf << 8, 224 IWL_RX_L3L4_RSS_HASH_MASK = 0xf << 12, 225 }; 226 227 enum iwl_rx_mpdu_status { 228 IWL_RX_MPDU_STATUS_CRC_OK = BIT(0), 229 IWL_RX_MPDU_STATUS_OVERRUN_OK = BIT(1), 230 IWL_RX_MPDU_STATUS_SRC_STA_FOUND = BIT(2), 231 IWL_RX_MPDU_STATUS_KEY_VALID = BIT(3), 232 IWL_RX_MPDU_STATUS_ICV_OK = BIT(5), 233 IWL_RX_MPDU_STATUS_MIC_OK = BIT(6), 234 IWL_RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 235 /* overlayed since IWL_UCODE_TLV_API_DEPRECATE_TTAK */ 236 IWL_RX_MPDU_STATUS_REPLAY_ERROR = BIT(7), 237 IWL_RX_MPDU_STATUS_SEC_MASK = 0x7 << 8, 238 IWL_RX_MPDU_STATUS_SEC_UNKNOWN = IWL_RX_MPDU_STATUS_SEC_MASK, 239 IWL_RX_MPDU_STATUS_SEC_NONE = 0x0 << 8, 240 IWL_RX_MPDU_STATUS_SEC_WEP = 0x1 << 8, 241 IWL_RX_MPDU_STATUS_SEC_CCM = 0x2 << 8, 242 IWL_RX_MPDU_STATUS_SEC_TKIP = 0x3 << 8, 243 IWL_RX_MPDU_STATUS_SEC_EXT_ENC = 0x4 << 8, 244 IWL_RX_MPDU_STATUS_SEC_GCM = 0x5 << 8, 245 #if defined(__FreeBSD__) 246 IWL_RX_MPDU_STATUS_SEC_ENC_ERR = 0x7 << 8, 247 #endif 248 IWL_RX_MPDU_STATUS_DECRYPTED = BIT(11), 249 IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME = BIT(15), 250 251 IWL_RX_MPDU_STATUS_DUPLICATE = BIT(22), 252 253 IWL_RX_MPDU_STATUS_STA_ID = 0x1f000000, 254 }; 255 256 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f 257 258 enum iwl_rx_mpdu_reorder_data { 259 IWL_RX_MPDU_REORDER_NSSN_MASK = 0x00000fff, 260 IWL_RX_MPDU_REORDER_SN_MASK = 0x00fff000, 261 IWL_RX_MPDU_REORDER_SN_SHIFT = 12, 262 IWL_RX_MPDU_REORDER_BAID_MASK = 0x7f000000, 263 IWL_RX_MPDU_REORDER_BAID_SHIFT = 24, 264 IWL_RX_MPDU_REORDER_BA_OLD_SN = 0x80000000, 265 }; 266 267 enum iwl_rx_mpdu_phy_info { 268 IWL_RX_MPDU_PHY_EOF_INDICATION = BIT(0), 269 IWL_RX_MPDU_PHY_AMPDU = BIT(5), 270 IWL_RX_MPDU_PHY_AMPDU_TOGGLE = BIT(6), 271 IWL_RX_MPDU_PHY_SHORT_PREAMBLE = BIT(7), 272 /* short preamble is only for CCK, for non-CCK overridden by this */ 273 IWL_RX_MPDU_PHY_NCCK_ADDTL_NTFY = BIT(7), 274 IWL_RX_MPDU_PHY_TSF_OVERLOAD = BIT(8), 275 }; 276 277 enum iwl_rx_mpdu_mac_info { 278 IWL_RX_MPDU_PHY_MAC_INDEX_MASK = 0x0f, 279 IWL_RX_MPDU_PHY_PHY_INDEX_MASK = 0xf0, 280 }; 281 282 /* TSF overload low dword */ 283 enum iwl_rx_phy_he_data0 { 284 /* info type: HE any */ 285 IWL_RX_PHY_DATA0_HE_BEAM_CHNG = 0x00000001, 286 IWL_RX_PHY_DATA0_HE_UPLINK = 0x00000002, 287 IWL_RX_PHY_DATA0_HE_BSS_COLOR_MASK = 0x000000fc, 288 IWL_RX_PHY_DATA0_HE_SPATIAL_REUSE_MASK = 0x00000f00, 289 /* 1 bit reserved */ 290 IWL_RX_PHY_DATA0_HE_TXOP_DUR_MASK = 0x000fe000, 291 IWL_RX_PHY_DATA0_HE_LDPC_EXT_SYM = 0x00100000, 292 IWL_RX_PHY_DATA0_HE_PRE_FEC_PAD_MASK = 0x00600000, 293 IWL_RX_PHY_DATA0_HE_PE_DISAMBIG = 0x00800000, 294 IWL_RX_PHY_DATA0_HE_DOPPLER = 0x01000000, 295 /* 6 bits reserved */ 296 IWL_RX_PHY_DATA0_HE_DELIM_EOF = 0x80000000, 297 }; 298 299 /* TSF overload low dword */ 300 enum iwl_rx_phy_eht_data0 { 301 /* info type: EHT any */ 302 IWL_RX_PHY_DATA0_EHT_VALIDATE = BIT(0), 303 IWL_RX_PHY_DATA0_EHT_UPLINK = BIT(1), 304 IWL_RX_PHY_DATA0_EHT_BSS_COLOR_MASK = 0x000000fc, 305 IWL_RX_PHY_DATA0_ETH_SPATIAL_REUSE_MASK = 0x00000f00, 306 IWL_RX_PHY_DATA0_EHT_PS160 = BIT(12), 307 IWL_RX_PHY_DATA0_EHT_TXOP_DUR_MASK = 0x000fe000, 308 IWL_RX_PHY_DATA0_EHT_LDPC_EXT_SYM = BIT(20), 309 IWL_RX_PHY_DATA0_EHT_PRE_FEC_PAD_MASK = 0x00600000, 310 IWL_RX_PHY_DATA0_EHT_PE_DISAMBIG = BIT(23), 311 IWL_RX_PHY_DATA0_EHT_BW320_SLOT = BIT(24), 312 IWL_RX_PHY_DATA0_EHT_SIGA_CRC_OK = BIT(25), 313 IWL_RX_PHY_DATA0_EHT_PHY_VER = 0x1c000000, 314 /* 2 bits reserved */ 315 IWL_RX_PHY_DATA0_EHT_DELIM_EOF = BIT(31), 316 }; 317 318 enum iwl_rx_phy_info_type { 319 IWL_RX_PHY_INFO_TYPE_NONE = 0, 320 IWL_RX_PHY_INFO_TYPE_CCK = 1, 321 IWL_RX_PHY_INFO_TYPE_OFDM_LGCY = 2, 322 IWL_RX_PHY_INFO_TYPE_HT = 3, 323 IWL_RX_PHY_INFO_TYPE_VHT_SU = 4, 324 IWL_RX_PHY_INFO_TYPE_VHT_MU = 5, 325 IWL_RX_PHY_INFO_TYPE_HE_SU = 6, 326 IWL_RX_PHY_INFO_TYPE_HE_MU = 7, 327 IWL_RX_PHY_INFO_TYPE_HE_TB = 8, 328 IWL_RX_PHY_INFO_TYPE_HE_MU_EXT = 9, 329 IWL_RX_PHY_INFO_TYPE_HE_TB_EXT = 10, 330 IWL_RX_PHY_INFO_TYPE_EHT_MU = 11, 331 IWL_RX_PHY_INFO_TYPE_EHT_TB = 12, 332 IWL_RX_PHY_INFO_TYPE_EHT_MU_EXT = 13, 333 IWL_RX_PHY_INFO_TYPE_EHT_TB_EXT = 14, 334 }; 335 336 /* TSF overload high dword */ 337 enum iwl_rx_phy_common_data1 { 338 /* 339 * check this first - if TSF overload is set, 340 * see &enum iwl_rx_phy_info_type 341 */ 342 IWL_RX_PHY_DATA1_INFO_TYPE_MASK = 0xf0000000, 343 344 /* info type: HT/VHT/HE/EHT any */ 345 IWL_RX_PHY_DATA1_LSIG_LEN_MASK = 0x0fff0000, 346 }; 347 348 /* TSF overload high dword For HE rates*/ 349 enum iwl_rx_phy_he_data1 { 350 /* info type: HE MU/MU-EXT */ 351 IWL_RX_PHY_DATA1_HE_MU_SIGB_COMPRESSION = 0x00000001, 352 IWL_RX_PHY_DATA1_HE_MU_SIBG_SYM_OR_USER_NUM_MASK = 0x0000001e, 353 354 /* info type: HE any */ 355 IWL_RX_PHY_DATA1_HE_LTF_NUM_MASK = 0x000000e0, 356 IWL_RX_PHY_DATA1_HE_RU_ALLOC_SEC80 = 0x00000100, 357 /* trigger encoded */ 358 IWL_RX_PHY_DATA1_HE_RU_ALLOC_MASK = 0x0000fe00, 359 360 /* info type: HE TB/TX-EXT */ 361 IWL_RX_PHY_DATA1_HE_TB_PILOT_TYPE = 0x00000001, 362 IWL_RX_PHY_DATA1_HE_TB_LOW_SS_MASK = 0x0000000e, 363 }; 364 365 /* TSF overload high dword For EHT-MU/TB rates*/ 366 enum iwl_rx_phy_eht_data1 { 367 /* info type: EHT-MU */ 368 IWL_RX_PHY_DATA1_EHT_MU_NUM_SIG_SYM_USIGA2 = 0x0000001f, 369 /* info type: EHT-TB */ 370 IWL_RX_PHY_DATA1_EHT_TB_PILOT_TYPE = BIT(0), 371 IWL_RX_PHY_DATA1_EHT_TB_LOW_SS = 0x0000001e, 372 373 /* info type: EHT any */ 374 /* number of EHT-LTF symbols 0 - 1 EHT-LTF, 1 - 2 EHT-LTFs, 2 - 4 EHT-LTFs, 375 * 3 - 6 EHT-LTFs, 4 - 8 EHT-LTFs */ 376 IWL_RX_PHY_DATA1_EHT_SIG_LTF_NUM = 0x000000e0, 377 IWL_RX_PHY_DATA1_EHT_RU_ALLOC_B0 = 0x00000100, 378 IWL_RX_PHY_DATA1_EHT_RU_ALLOC_B1_B7 = 0x0000fe00, 379 }; 380 381 /* goes into Metadata DW 7 (Qu) or 8 (So or higher) */ 382 enum iwl_rx_phy_he_data2 { 383 /* info type: HE MU-EXT */ 384 /* the a1/a2/... is what the PHY/firmware calls the values */ 385 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU0 = 0x000000ff, /* a1 */ 386 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU2 = 0x0000ff00, /* a2 */ 387 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU0 = 0x00ff0000, /* b1 */ 388 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU2 = 0xff000000, /* b2 */ 389 390 /* info type: HE TB-EXT */ 391 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE1 = 0x0000000f, 392 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE2 = 0x000000f0, 393 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE3 = 0x00000f00, 394 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE4 = 0x0000f000, 395 }; 396 397 /* goes into Metadata DW 8 (Qu) or 7 (So or higher) */ 398 enum iwl_rx_phy_he_data3 { 399 /* info type: HE MU-EXT */ 400 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU1 = 0x000000ff, /* c1 */ 401 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU3 = 0x0000ff00, /* c2 */ 402 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU1 = 0x00ff0000, /* d1 */ 403 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU3 = 0xff000000, /* d2 */ 404 }; 405 406 /* goes into Metadata DW 4 high 16 bits */ 407 enum iwl_rx_phy_he_he_data4 { 408 /* info type: HE MU-EXT */ 409 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CTR_RU = 0x0001, 410 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CTR_RU = 0x0002, 411 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CRC_OK = 0x0004, 412 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CRC_OK = 0x0008, 413 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_MCS_MASK = 0x00f0, 414 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_DCM = 0x0100, 415 IWL_RX_PHY_DATA4_HE_MU_EXT_PREAMBLE_PUNC_TYPE_MASK = 0x0600, 416 }; 417 418 /* goes into Metadata DW 8 (Qu has no EHT) */ 419 enum iwl_rx_phy_eht_data2 { 420 /* info type: EHT-MU-EXT */ 421 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_A1 = 0x000001ff, 422 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_A2 = 0x0003fe00, 423 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_B1 = 0x07fc0000, 424 425 /* info type: EHT-TB-EXT */ 426 IWL_RX_PHY_DATA2_EHT_TB_EXT_TRIG_SIGA1 = 0xffffffff, 427 }; 428 429 /* goes into Metadata DW 7 (Qu has no EHT) */ 430 enum iwl_rx_phy_eht_data3 { 431 /* note: low 8 bits cannot be used */ 432 /* info type: EHT-MU-EXT */ 433 IWL_RX_PHY_DATA3_EHT_MU_EXT_RU_ALLOC_C1 = 0x0003fe00, 434 IWL_RX_PHY_DATA3_EHT_MU_EXT_RU_ALLOC_C2 = 0x07fc0000, 435 }; 436 437 /* goes into Metadata DW 4 */ 438 enum iwl_rx_phy_eht_data4 { 439 /* info type: EHT-MU-EXT */ 440 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_D1 = 0x000001ff, 441 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_D2 = 0x0003fe00, 442 IWL_RX_PHY_DATA4_EHT_MU_EXT_SIGB_MCS = 0x000c0000, 443 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_B2 = 0x1ff00000, 444 }; 445 446 /* goes into Metadata DW 16 */ 447 enum iwl_rx_phy_data5 { 448 /* info type: EHT any */ 449 IWL_RX_PHY_DATA5_EHT_TYPE_AND_COMP = 0x00000003, 450 /* info type: EHT-TB */ 451 IWL_RX_PHY_DATA5_EHT_TB_SPATIAL_REUSE1 = 0x0000003c, 452 IWL_RX_PHY_DATA5_EHT_TB_SPATIAL_REUSE2 = 0x000003c0, 453 /* info type: EHT-MU */ 454 IWL_RX_PHY_DATA5_EHT_MU_PUNC_CH_CODE = 0x0000007c, 455 IWL_RX_PHY_DATA5_EHT_MU_STA_ID_USR = 0x0003ff80, 456 IWL_RX_PHY_DATA5_EHT_MU_NUM_USR_NON_OFDMA = 0x001c0000, 457 IWL_RX_PHY_DATA5_EHT_MU_SPATIAL_CONF_USR_FIELD = 0x0fe00000, 458 }; 459 460 /** 461 * struct iwl_rx_mpdu_desc_v1 - RX MPDU descriptor 462 */ 463 struct iwl_rx_mpdu_desc_v1 { 464 /* DW7 - carries rss_hash only when rpa_en == 1 */ 465 union { 466 /** 467 * @rss_hash: RSS hash value 468 */ 469 __le32 rss_hash; 470 471 /** 472 * @phy_data2: depends on info type (see @phy_data1) 473 */ 474 __le32 phy_data2; 475 }; 476 477 /* DW8 - carries filter_match only when rpa_en == 1 */ 478 union { 479 /** 480 * @filter_match: filter match value 481 */ 482 __le32 filter_match; 483 484 /** 485 * @phy_data3: depends on info type (see @phy_data1) 486 */ 487 __le32 phy_data3; 488 }; 489 490 /* DW9 */ 491 /** 492 * @rate_n_flags: RX rate/flags encoding 493 */ 494 __le32 rate_n_flags; 495 /* DW10 */ 496 /** 497 * @energy_a: energy chain A 498 */ 499 u8 energy_a; 500 /** 501 * @energy_b: energy chain B 502 */ 503 u8 energy_b; 504 /** 505 * @channel: channel number 506 */ 507 u8 channel; 508 /** 509 * @mac_context: MAC context mask 510 */ 511 u8 mac_context; 512 /* DW11 */ 513 /** 514 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 515 */ 516 __le32 gp2_on_air_rise; 517 /* DW12 & DW13 */ 518 union { 519 /** 520 * @tsf_on_air_rise: 521 * TSF value on air rise (INA), only valid if 522 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 523 */ 524 __le64 tsf_on_air_rise; 525 526 struct { 527 /** 528 * @phy_data0: depends on info_type, see @phy_data1 529 */ 530 __le32 phy_data0; 531 /** 532 * @phy_data1: valid only if 533 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 534 * see &enum iwl_rx_phy_common_data1 or 535 * &enum iwl_rx_phy_he_data1 or 536 * &enum iwl_rx_phy_eht_data1. 537 */ 538 __le32 phy_data1; 539 }; 540 }; 541 } __packed; /* RX_MPDU_RES_START_API_S_VER_4 */ 542 543 /** 544 * struct iwl_rx_mpdu_desc_v3 - RX MPDU descriptor 545 */ 546 struct iwl_rx_mpdu_desc_v3 { 547 /* DW7 - carries filter_match only when rpa_en == 1 */ 548 union { 549 /** 550 * @filter_match: filter match value 551 */ 552 __le32 filter_match; 553 554 /** 555 * @phy_data3: depends on info type (see @phy_data1) 556 */ 557 __le32 phy_data3; 558 }; 559 560 /* DW8 - carries rss_hash only when rpa_en == 1 */ 561 union { 562 /** 563 * @rss_hash: RSS hash value 564 */ 565 __le32 rss_hash; 566 567 /** 568 * @phy_data2: depends on info type (see @phy_data1) 569 */ 570 __le32 phy_data2; 571 }; 572 /* DW9 */ 573 /** 574 * @partial_hash: 31:0 ip/tcp header hash 575 * w/o some fields (such as IP SRC addr) 576 */ 577 __le32 partial_hash; 578 /* DW10 */ 579 /** 580 * @raw_xsum: raw xsum value 581 */ 582 __be16 raw_xsum; 583 /** 584 * @reserved_xsum: reserved high bits in the raw checksum 585 */ 586 __le16 reserved_xsum; 587 /* DW11 */ 588 /** 589 * @rate_n_flags: RX rate/flags encoding 590 */ 591 __le32 rate_n_flags; 592 /* DW12 */ 593 /** 594 * @energy_a: energy chain A 595 */ 596 u8 energy_a; 597 /** 598 * @energy_b: energy chain B 599 */ 600 u8 energy_b; 601 /** 602 * @channel: channel number 603 */ 604 u8 channel; 605 /** 606 * @mac_context: MAC context mask 607 */ 608 u8 mac_context; 609 /* DW13 */ 610 /** 611 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 612 */ 613 __le32 gp2_on_air_rise; 614 /* DW14 & DW15 */ 615 union { 616 /** 617 * @tsf_on_air_rise: 618 * TSF value on air rise (INA), only valid if 619 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 620 */ 621 __le64 tsf_on_air_rise; 622 623 struct { 624 /** 625 * @phy_data0: depends on info_type, see @phy_data1 626 */ 627 __le32 phy_data0; 628 /** 629 * @phy_data1: valid only if 630 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 631 * see &enum iwl_rx_phy_data1. 632 */ 633 __le32 phy_data1; 634 }; 635 }; 636 /* DW16 */ 637 /** 638 * @phy_data5: valid only if 639 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 640 * see &enum iwl_rx_phy_data5. 641 */ 642 __le32 phy_data5; 643 /* DW17 */ 644 /** 645 * @reserved: reserved 646 */ 647 __le32 reserved[1]; 648 } __packed; /* RX_MPDU_RES_START_API_S_VER_3, 649 * RX_MPDU_RES_START_API_S_VER_5, 650 * RX_MPDU_RES_START_API_S_VER_6 651 */ 652 653 /** 654 * struct iwl_rx_mpdu_desc - RX MPDU descriptor 655 */ 656 struct iwl_rx_mpdu_desc { 657 /* DW2 */ 658 /** 659 * @mpdu_len: MPDU length 660 */ 661 __le16 mpdu_len; 662 /** 663 * @mac_flags1: &enum iwl_rx_mpdu_mac_flags1 664 */ 665 u8 mac_flags1; 666 /** 667 * @mac_flags2: &enum iwl_rx_mpdu_mac_flags2 668 */ 669 u8 mac_flags2; 670 /* DW3 */ 671 /** 672 * @amsdu_info: &enum iwl_rx_mpdu_amsdu_info 673 */ 674 u8 amsdu_info; 675 /** 676 * @phy_info: &enum iwl_rx_mpdu_phy_info 677 */ 678 __le16 phy_info; 679 /** 680 * @mac_phy_band: MAC/link ID, PHY ID, band; 681 * see &enum iwl_rx_mpdu_mac_phy_band 682 */ 683 u8 mac_phy_band; 684 /* DW4 */ 685 union { 686 struct { 687 /* carries csum data only when rpa_en == 1 */ 688 /** 689 * @raw_csum: raw checksum (alledgedly unreliable) 690 */ 691 __le16 raw_csum; 692 693 union { 694 /** 695 * @l3l4_flags: &enum iwl_rx_l3l4_flags 696 */ 697 __le16 l3l4_flags; 698 699 /** 700 * @phy_data4: depends on info type, see phy_data1 701 */ 702 __le16 phy_data4; 703 }; 704 }; 705 /** 706 * @phy_eht_data4: depends on info type, see phy_data1 707 */ 708 __le32 phy_eht_data4; 709 }; 710 /* DW5 */ 711 /** 712 * @status: &enum iwl_rx_mpdu_status 713 */ 714 __le32 status; 715 716 /* DW6 */ 717 /** 718 * @reorder_data: &enum iwl_rx_mpdu_reorder_data 719 */ 720 __le32 reorder_data; 721 722 union { 723 /** 724 * @v1: version 1 of the remaining RX descriptor, 725 * see &struct iwl_rx_mpdu_desc_v1 726 */ 727 struct iwl_rx_mpdu_desc_v1 v1; 728 /** 729 * @v3: version 3 of the remaining RX descriptor, 730 * see &struct iwl_rx_mpdu_desc_v3 731 */ 732 struct iwl_rx_mpdu_desc_v3 v3; 733 }; 734 } __packed; /* RX_MPDU_RES_START_API_S_VER_3, 735 * RX_MPDU_RES_START_API_S_VER_4, 736 * RX_MPDU_RES_START_API_S_VER_5, 737 * RX_MPDU_RES_START_API_S_VER_6 738 */ 739 740 #define IWL_RX_DESC_SIZE_V1 offsetofend(struct iwl_rx_mpdu_desc, v1) 741 742 #define RX_NO_DATA_CHAIN_A_POS 0 743 #define RX_NO_DATA_CHAIN_A_MSK (0xff << RX_NO_DATA_CHAIN_A_POS) 744 #define RX_NO_DATA_CHAIN_B_POS 8 745 #define RX_NO_DATA_CHAIN_B_MSK (0xff << RX_NO_DATA_CHAIN_B_POS) 746 #define RX_NO_DATA_CHANNEL_POS 16 747 #define RX_NO_DATA_CHANNEL_MSK (0xff << RX_NO_DATA_CHANNEL_POS) 748 749 #define RX_NO_DATA_INFO_TYPE_POS 0 750 #define RX_NO_DATA_INFO_TYPE_MSK (0xff << RX_NO_DATA_INFO_TYPE_POS) 751 #define RX_NO_DATA_INFO_TYPE_NONE 0 752 #define RX_NO_DATA_INFO_TYPE_RX_ERR 1 753 #define RX_NO_DATA_INFO_TYPE_NDP 2 754 #define RX_NO_DATA_INFO_TYPE_MU_UNMATCHED 3 755 #define RX_NO_DATA_INFO_TYPE_TB_UNMATCHED 4 756 757 #define RX_NO_DATA_INFO_ERR_POS 8 758 #define RX_NO_DATA_INFO_ERR_MSK (0xff << RX_NO_DATA_INFO_ERR_POS) 759 #define RX_NO_DATA_INFO_ERR_NONE 0 760 #define RX_NO_DATA_INFO_ERR_BAD_PLCP 1 761 #define RX_NO_DATA_INFO_ERR_UNSUPPORTED_RATE 2 762 #define RX_NO_DATA_INFO_ERR_NO_DELIM 3 763 #define RX_NO_DATA_INFO_ERR_BAD_MAC_HDR 4 764 #define RX_NO_DATA_INFO_LOW_ENERGY 5 765 766 #define RX_NO_DATA_FRAME_TIME_POS 0 767 #define RX_NO_DATA_FRAME_TIME_MSK (0xfffff << RX_NO_DATA_FRAME_TIME_POS) 768 769 #define RX_NO_DATA_RX_VEC0_HE_NSTS_MSK 0x03800000 770 #define RX_NO_DATA_RX_VEC0_VHT_NSTS_MSK 0x38000000 771 #define RX_NO_DATA_RX_VEC2_EHT_NSTS_MSK 0x00f00000 772 773 /* content of OFDM_RX_VECTOR_USIG_A1_OUT */ 774 enum iwl_rx_usig_a1 { 775 IWL_RX_USIG_A1_ENHANCED_WIFI_VER_ID = 0x00000007, 776 IWL_RX_USIG_A1_BANDWIDTH = 0x00000038, 777 IWL_RX_USIG_A1_UL_FLAG = 0x00000040, 778 IWL_RX_USIG_A1_BSS_COLOR = 0x00001f80, 779 IWL_RX_USIG_A1_TXOP_DURATION = 0x000fe000, 780 IWL_RX_USIG_A1_DISREGARD = 0x01f00000, 781 IWL_RX_USIG_A1_VALIDATE = 0x02000000, 782 IWL_RX_USIG_A1_EHT_BW320_SLOT = 0x04000000, 783 IWL_RX_USIG_A1_EHT_TYPE = 0x18000000, 784 IWL_RX_USIG_A1_RDY = 0x80000000, 785 }; 786 787 /* content of OFDM_RX_VECTOR_USIG_A2_EHT_OUT */ 788 enum iwl_rx_usig_a2_eht { 789 IWL_RX_USIG_A2_EHT_PPDU_TYPE = 0x00000003, 790 IWL_RX_USIG_A2_EHT_USIG2_VALIDATE_B2 = 0x00000004, 791 IWL_RX_USIG_A2_EHT_PUNC_CHANNEL = 0x000000f8, 792 IWL_RX_USIG_A2_EHT_USIG2_VALIDATE_B8 = 0x00000100, 793 IWL_RX_USIG_A2_EHT_SIG_MCS = 0x00000600, 794 IWL_RX_USIG_A2_EHT_SIG_SYM_NUM = 0x0000f800, 795 IWL_RX_USIG_A2_EHT_TRIG_SPATIAL_REUSE_1 = 0x000f0000, 796 IWL_RX_USIG_A2_EHT_TRIG_SPATIAL_REUSE_2 = 0x00f00000, 797 IWL_RX_USIG_A2_EHT_TRIG_USIG2_DISREGARD = 0x1f000000, 798 IWL_RX_USIG_A2_EHT_CRC_OK = 0x40000000, 799 IWL_RX_USIG_A2_EHT_RDY = 0x80000000, 800 }; 801 802 /** 803 * struct iwl_rx_no_data - RX no data descriptor 804 * @info: 7:0 frame type, 15:8 RX error type 805 * @rssi: 7:0 energy chain-A, 806 * 15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel 807 * @on_air_rise_time: GP2 during on air rise 808 * @fr_time: frame time 809 * @rate: rate/mcs of frame 810 * @phy_info: &enum iwl_rx_phy_he_data0 or &enum iwl_rx_phy_eht_data0 811 * based on &enum iwl_rx_phy_info_type 812 * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type. 813 * for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT 814 * for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT 815 */ 816 struct iwl_rx_no_data { 817 __le32 info; 818 __le32 rssi; 819 __le32 on_air_rise_time; 820 __le32 fr_time; 821 __le32 rate; 822 __le32 phy_info[2]; 823 __le32 rx_vec[2]; 824 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_1, 825 RX_NO_DATA_NTFY_API_S_VER_2 */ 826 827 /** 828 * struct iwl_rx_no_data_ver_3 - RX no data descriptor 829 * @info: 7:0 frame type, 15:8 RX error type 830 * @rssi: 7:0 energy chain-A, 831 * 15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel 832 * @on_air_rise_time: GP2 during on air rise 833 * @fr_time: frame time 834 * @rate: rate/mcs of frame, format depends on the notification version 835 * @phy_info: &enum iwl_rx_phy_eht_data0 and &enum iwl_rx_phy_info_type 836 * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type. 837 * for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT 838 * for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT 839 * for EHT: OFDM_RX_VECTOR_USIG_A1_OUT, OFDM_RX_VECTOR_USIG_A2_EHT_OUT, 840 * OFDM_RX_VECTOR_EHT_OUT, OFDM_RX_VECTOR_EHT_USER_FIELD_OUT 841 */ 842 struct iwl_rx_no_data_ver_3 { 843 __le32 info; 844 __le32 rssi; 845 __le32 on_air_rise_time; 846 __le32 fr_time; 847 __le32 rate; 848 __le32 phy_info[2]; 849 __le32 rx_vec[4]; 850 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_3, _VER_4 */ 851 852 struct iwl_frame_release { 853 u8 baid; 854 u8 reserved; 855 __le16 nssn; 856 }; 857 858 /** 859 * enum iwl_bar_frame_release_sta_tid - STA/TID information for BAR release 860 * @IWL_BAR_FRAME_RELEASE_TID_MASK: TID mask 861 * @IWL_BAR_FRAME_RELEASE_STA_MASK: STA mask 862 */ 863 enum iwl_bar_frame_release_sta_tid { 864 IWL_BAR_FRAME_RELEASE_TID_MASK = 0x0000000f, 865 IWL_BAR_FRAME_RELEASE_STA_MASK = 0x000001f0, 866 }; 867 868 /** 869 * enum iwl_bar_frame_release_ba_info - BA information for BAR release 870 * @IWL_BAR_FRAME_RELEASE_NSSN_MASK: NSSN mask 871 * @IWL_BAR_FRAME_RELEASE_SN_MASK: SN mask (ignored by driver) 872 * @IWL_BAR_FRAME_RELEASE_BAID_MASK: BAID mask 873 */ 874 enum iwl_bar_frame_release_ba_info { 875 IWL_BAR_FRAME_RELEASE_NSSN_MASK = 0x00000fff, 876 IWL_BAR_FRAME_RELEASE_SN_MASK = 0x00fff000, 877 IWL_BAR_FRAME_RELEASE_BAID_MASK = 0x3f000000, 878 }; 879 880 /** 881 * struct iwl_bar_frame_release - frame release from BAR info 882 * @sta_tid: STA & TID information, see &enum iwl_bar_frame_release_sta_tid. 883 * @ba_info: BA information, see &enum iwl_bar_frame_release_ba_info. 884 */ 885 struct iwl_bar_frame_release { 886 __le32 sta_tid; 887 __le32 ba_info; 888 } __packed; /* RX_BAR_TO_FRAME_RELEASE_API_S_VER_1 */ 889 890 enum iwl_rss_hash_func_en { 891 IWL_RSS_HASH_TYPE_IPV4_TCP, 892 IWL_RSS_HASH_TYPE_IPV4_UDP, 893 IWL_RSS_HASH_TYPE_IPV4_PAYLOAD, 894 IWL_RSS_HASH_TYPE_IPV6_TCP, 895 IWL_RSS_HASH_TYPE_IPV6_UDP, 896 IWL_RSS_HASH_TYPE_IPV6_PAYLOAD, 897 }; 898 899 #define IWL_RSS_HASH_KEY_CNT 10 900 #define IWL_RSS_INDIRECTION_TABLE_SIZE 128 901 #define IWL_RSS_ENABLE 1 902 903 /** 904 * struct iwl_rss_config_cmd - RSS (Receive Side Scaling) configuration 905 * 906 * @flags: 1 - enable, 0 - disable 907 * @hash_mask: Type of RSS to use. Values are from %iwl_rss_hash_func_en 908 * @reserved: reserved 909 * @secret_key: 320 bit input of random key configuration from driver 910 * @indirection_table: indirection table 911 */ 912 struct iwl_rss_config_cmd { 913 __le32 flags; 914 u8 hash_mask; 915 u8 reserved[3]; 916 __le32 secret_key[IWL_RSS_HASH_KEY_CNT]; 917 u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE]; 918 } __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */ 919 920 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0 921 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf 922 923 /** 924 * struct iwl_rxq_sync_cmd - RXQ notification trigger 925 * 926 * @flags: flags of the notification. bit 0:3 are the sender queue 927 * @rxq_mask: rx queues to send the notification on 928 * @count: number of bytes in payload, should be DWORD aligned 929 * @payload: data to send to rx queues 930 */ 931 struct iwl_rxq_sync_cmd { 932 __le32 flags; 933 __le32 rxq_mask; 934 __le32 count; 935 #if defined(__linux__) 936 u8 payload[]; 937 #elif defined(__FreeBSD__) 938 u8 payload[0]; 939 #endif 940 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 941 942 /** 943 * struct iwl_rxq_sync_notification - Notification triggered by RXQ 944 * sync command 945 * 946 * @count: number of bytes in payload 947 * @payload: data to send to rx queues 948 */ 949 struct iwl_rxq_sync_notification { 950 __le32 count; 951 #if defined(__linux__) 952 u8 payload[]; 953 #elif defined(__FreeBSD__) 954 u8 payload[0]; 955 #endif 956 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 957 958 /** 959 * enum iwl_mvm_pm_event - type of station PM event 960 * @IWL_MVM_PM_EVENT_AWAKE: station woke up 961 * @IWL_MVM_PM_EVENT_ASLEEP: station went to sleep 962 * @IWL_MVM_PM_EVENT_UAPSD: station sent uAPSD trigger 963 * @IWL_MVM_PM_EVENT_PS_POLL: station sent PS-Poll 964 */ 965 enum iwl_mvm_pm_event { 966 IWL_MVM_PM_EVENT_AWAKE, 967 IWL_MVM_PM_EVENT_ASLEEP, 968 IWL_MVM_PM_EVENT_UAPSD, 969 IWL_MVM_PM_EVENT_PS_POLL, 970 }; /* PEER_PM_NTFY_API_E_VER_1 */ 971 972 /** 973 * struct iwl_mvm_pm_state_notification - station PM state notification 974 * @sta_id: station ID of the station changing state 975 * @type: the new powersave state, see &enum iwl_mvm_pm_event 976 */ 977 struct iwl_mvm_pm_state_notification { 978 u8 sta_id; 979 u8 type; 980 /* private: */ 981 __le16 reserved; 982 } __packed; /* PEER_PM_NTFY_API_S_VER_1 */ 983 984 #define BA_WINDOW_STREAMS_MAX 16 985 #define BA_WINDOW_STATUS_TID_MSK 0x000F 986 #define BA_WINDOW_STATUS_STA_ID_POS 4 987 #define BA_WINDOW_STATUS_STA_ID_MSK 0x01F0 988 #define BA_WINDOW_STATUS_VALID_MSK BIT(9) 989 990 /** 991 * struct iwl_ba_window_status_notif - reordering window's status notification 992 * @bitmap: bitmap of received frames [start_seq_num + 0]..[start_seq_num + 63] 993 * @ra_tid: bit 3:0 - TID, bit 8:4 - STA_ID, bit 9 - valid 994 * @start_seq_num: the start sequence number of the bitmap 995 * @mpdu_rx_count: the number of received MPDUs since entering D0i3 996 */ 997 struct iwl_ba_window_status_notif { 998 __le64 bitmap[BA_WINDOW_STREAMS_MAX]; 999 __le16 ra_tid[BA_WINDOW_STREAMS_MAX]; 1000 __le32 start_seq_num[BA_WINDOW_STREAMS_MAX]; 1001 __le16 mpdu_rx_count[BA_WINDOW_STREAMS_MAX]; 1002 } __packed; /* BA_WINDOW_STATUS_NTFY_API_S_VER_1 */ 1003 1004 /** 1005 * struct iwl_rfh_queue_data - RX queue configuration 1006 * @q_num: Q num 1007 * @enable: enable queue 1008 * @reserved: alignment 1009 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 1010 * @fr_bd_cb: DMA address of freeRB table 1011 * @ur_bd_cb: DMA address of used RB table 1012 * @fr_bd_wid: Initial index of the free table 1013 */ 1014 struct iwl_rfh_queue_data { 1015 u8 q_num; 1016 u8 enable; 1017 __le16 reserved; 1018 __le64 urbd_stts_wrptr; 1019 __le64 fr_bd_cb; 1020 __le64 ur_bd_cb; 1021 __le32 fr_bd_wid; 1022 } __packed; /* RFH_QUEUE_CONFIG_S_VER_1 */ 1023 1024 /** 1025 * struct iwl_rfh_queue_config - RX queue configuration 1026 * @num_queues: number of queues configured 1027 * @reserved: alignment 1028 * @data: DMA addresses per-queue 1029 */ 1030 struct iwl_rfh_queue_config { 1031 u8 num_queues; 1032 u8 reserved[3]; 1033 #if defined(__linux__) 1034 struct iwl_rfh_queue_data data[]; 1035 #elif defined(__FreeBSD__) 1036 struct iwl_rfh_queue_data data[0]; 1037 #endif 1038 } __packed; /* RFH_QUEUE_CONFIG_API_S_VER_1 */ 1039 1040 /** 1041 * struct iwl_beacon_filter_notif_v1 - beacon filter notification 1042 * @average_energy: average energy for the received beacon 1043 * @mac_id: MAC ID the beacon was received for 1044 */ 1045 struct iwl_beacon_filter_notif_v1 { 1046 __le32 average_energy; 1047 __le32 mac_id; 1048 } __packed; /* BEACON_FILTER_IN_NTFY_API_S_VER_1 */ 1049 1050 /** 1051 * struct iwl_beacon_filter_notif - beacon filter notification 1052 * @average_energy: average energy for the received beacon 1053 * @link_id: link ID the beacon was received for 1054 */ 1055 struct iwl_beacon_filter_notif { 1056 __le32 average_energy; 1057 __le32 link_id; 1058 } __packed; /* BEACON_FILTER_IN_NTFY_API_S_VER_2 */ 1059 1060 union iwl_legacy_sig { 1061 #define OFDM_RX_LEGACY_LENGTH 0x00000fff 1062 #define OFDM_RX_RATE 0x0000f000 1063 __le32 ofdm; 1064 #define CCK_CRFR_SHORT_PREAMBLE 0x00000040 1065 __le32 cck; 1066 }; 1067 1068 struct iwl_ht_sigs { 1069 #define OFDM_RX_FRAME_HT_MCS 0x0000007f 1070 #define OFDM_RX_FRAME_HT_BANDWIDTH 0x00000080 1071 #define OFDM_RX_FRAME_HT_LENGTH 0x03ffff00 1072 __le32 a1; 1073 __le32 a2; 1074 }; 1075 1076 struct iwl_vht_sigs { 1077 #define OFDM_RX_FRAME_VHT_NUM_OF_DATA_SYM 0x000007ff 1078 #define OFDM_RX_FRAME_VHT_NUM_OF_DATA_SYM_VALID 0x80000000 1079 __le32 a0; 1080 __le32 a1, a2; 1081 }; 1082 1083 struct iwl_he_sigs { 1084 #define OFDM_RX_FRAME_HE_BEAM_CHANGE 0x00000001 1085 #define OFDM_RX_FRAME_HE_UL_FLAG 0x00000002 1086 #define OFDM_RX_FRAME_HE_MCS 0x0000003c 1087 #define OFDM_RX_FRAME_HE_DCM 0x00000040 1088 #define OFDM_RX_FRAME_HE_BSS_COLOR 0x00001f80 1089 #define OFDM_RX_FRAME_HE_SPATIAL_REUSE 0x0001e000 1090 #define OFDM_RX_FRAME_HE_BANDWIDTH 0x00060000 1091 #define OFDM_RX_FRAME_HE_SU_EXT_BW10 0x00080000 1092 #define OFDM_RX_FRAME_HE_GI_LTF_TYPE 0x00700000 1093 #define OFDM_RX_FRAME_HE_NSTS 0x03800000 1094 #define OFDM_RX_FRAME_HE_PRMBL_PUNC_TYPE 0x0c000000 1095 __le32 a1; 1096 #define OFDM_RX_FRAME_HE_TXOP_DURATION 0x0000007f 1097 #define OFDM_RX_FRAME_HE_CODING 0x00000080 1098 #define OFDM_RX_FRAME_HE_CODING_EXTRA_SYM 0x00000100 1099 #define OFDM_RX_FRAME_HE_STBC 0x00000200 1100 #define OFDM_RX_FRAME_HE_BF 0x00000400 1101 #define OFDM_RX_FRAME_HE_PRE_FEC_PAD_FACTOR 0x00001800 1102 #define OFDM_RX_FRAME_HE_PE_DISAMBIG 0x00002000 1103 #define OFDM_RX_FRAME_HE_DOPPLER 0x00004000 1104 #define OFDM_RX_FRAME_HE_TYPE 0x00038000 1105 #define OFDM_RX_FRAME_HE_MU_NUM_OF_SIGB_SYM_OR_USER_NUM 0x003c0000 1106 #define OFDM_RX_FRAME_HE_MU_SIGB_COMP 0x00400000 1107 #define OFDM_RX_FRAME_HE_MU_NUM_OF_LTF_SYM 0x03800000 1108 __le32 a2; 1109 #define OFDM_RX_FRAME_HE_NUM_OF_DATA_SYM 0x000007ff 1110 #define OFDM_RX_FRAME_HE_PE_DURATION 0x00003800 1111 #define OFDM_RX_FRAME_HE_NUM_OF_DATA_SYM_VALID 0x80000000 1112 __le32 a3; 1113 #define OFDM_RX_FRAME_HE_SIGB_STA_ID_FOUND 0x00000001 1114 #define OFDM_RX_FRAME_HE_SIGB_STA_ID_INDX 0x0000000e 1115 #define OFDM_RX_FRAME_HE_SIGB_NSTS 0x00000070 1116 #define OFDM_RX_FRAME_HE_SIGB_BF 0x00000080 1117 #define OFDM_RX_FRAME_HE_SIGB_MCS 0x00000f00 1118 #define OFDM_RX_FRAME_HE_SIGB_DCM 0x00001000 1119 #define OFDM_RX_FRAME_HE_SIGB_CODING 0x00002000 1120 #define OFDM_RX_FRAME_HE_SIGB_SPATIAL_CONFIG 0x0003c000 1121 #define OFDM_RX_FRAME_HE_SIGB_STA_RU 0x03fc0000 1122 #define OFDM_RX_FRAME_HE_SIGB_NUM_OF_SYM 0x3c000000 1123 #define OFDM_RX_FRAME_HE_SIGB_CRC_OK 0x40000000 1124 __le32 b; 1125 /* index 0 */ 1126 #define OFDM_RX_FRAME_HE_RU_ALLOC_0_A1 0x000000ff 1127 #define OFDM_RX_FRAME_HE_RU_ALLOC_0_A2 0x0000ff00 1128 #define OFDM_RX_FRAME_HE_RU_ALLOC_0_B1 0x00ff0000 1129 #define OFDM_RX_FRAME_HE_RU_ALLOC_0_B2 0xff000000 1130 /* index 1 */ 1131 #define OFDM_RX_FRAME_HE_RU_ALLOC_1_C1 0x000000ff 1132 #define OFDM_RX_FRAME_HE_RU_ALLOC_1_C2 0x0000ff00 1133 #define OFDM_RX_FRAME_HE_RU_ALLOC_1_D1 0x00ff0000 1134 #define OFDM_RX_FRAME_HE_RU_ALLOC_1_D2 0xff000000 1135 /* index 2 */ 1136 #define OFDM_RX_FRAME_HE_CENTER_RU_CC1 0x00000001 1137 #define OFDM_RX_FRAME_HE_CENTER_RU_CC2 0x00000002 1138 #define OFDM_RX_FRAME_HE_COMMON_CC1_CRC_OK 0x00000004 1139 #define OFDM_RX_FRAME_HE_COMMON_CC2_CRC_OK 0x00000008 1140 __le32 cmn[3]; 1141 }; 1142 1143 struct iwl_he_tb_sigs { 1144 #define OFDM_RX_HE_TRIG_FORMAT 0x00000001 1145 #define OFDM_RX_HE_TRIG_BSS_COLOR 0x0000007e 1146 #define OFDM_RX_HE_TRIG_SPATIAL_REUSE_1 0x00000780 1147 #define OFDM_RX_HE_TRIG_SPATIAL_REUSE_2 0x00007800 1148 #define OFDM_RX_HE_TRIG_SPATIAL_REUSE_3 0x00078000 1149 #define OFDM_RX_HE_TRIG_SPATIAL_REUSE_4 0x00780000 1150 #define OFDM_RX_HE_TRIG_BANDWIDTH 0x03000000 1151 __le32 a1; 1152 #define OFDM_RX_HE_TRIG_TXOP_DURATION 0x0000007f 1153 #define OFDM_RX_HE_TRIG_SIG2_RESERVED 0x0000ff80 1154 #define OFDM_RX_HE_TRIG_FORMAT_ERR 0x08000000 1155 #define OFDM_RX_HE_TRIG_BW_ERR 0x10000000 1156 #define OFDM_RX_HE_TRIG_LEGACY_LENGTH_ERR 0x20000000 1157 #define OFDM_RX_HE_TRIG_CRC_OK 0x40000000 1158 __le32 a2; 1159 #define OFDM_UCODE_TRIG_BASE_RX_LGCY_LENGTH 0x00000fff 1160 #define OFDM_UCODE_TRIG_BASE_RX_BANDWIDTH 0x00007000 1161 #define OFDM_UCODE_TRIG_BASE_PS160 0x00008000 1162 #define OFDM_UCODE_EHT_TRIG_CONTROL_CHANNEL 0x000f0000 1163 __le32 tb_rx0; 1164 #define OFDM_UCODE_TRIG_BASE_RX_MCS 0x0000000f 1165 #define OFDM_UCODE_TRIG_BASE_RX_DCM 0x00000010 1166 #define OFDM_UCODE_TRIG_BASE_RX_GI_LTF_TYPE 0x00000060 1167 #define OFDM_UCODE_TRIG_BASE_RX_NSTS 0x00000380 1168 #define OFDM_UCODE_TRIG_BASE_RX_CODING 0x00000400 1169 #define OFDM_UCODE_TRIG_BASE_RX_CODING_EXTRA_SYM 0x00000800 1170 #define OFDM_UCODE_TRIG_BASE_RX_STBC 0x00001000 1171 #define OFDM_UCODE_TRIG_BASE_RX_PRE_FEC_PAD_FACTOR 0x00006000 1172 #define OFDM_UCODE_TRIG_BASE_RX_PE_DISAMBIG 0x00008000 1173 #define OFDM_UCODE_TRIG_BASE_RX_DOPPLER 0x00010000 1174 #define OFDM_UCODE_TRIG_BASE_RX_RU 0x01fe0000 1175 #define OFDM_UCODE_TRIG_BASE_RX_RU_P80 0x00020000 1176 #define OFDM_UCODE_TRIG_BASE_RX_NUM_OF_LTF_SYM 0x0e000000 1177 #define OFDM_UCODE_TRIG_BASE_RX_LTF_PILOT_TYPE 0x10000000 1178 #define OFDM_UCODE_TRIG_BASE_RX_LOWEST_SS_ALLOCATION 0xe0000000 1179 __le32 tb_rx1; 1180 }; 1181 1182 struct iwl_eht_sigs { 1183 #define OFDM_RX_FRAME_ENHANCED_WIFI_VER_ID 0x00000007 1184 #define OFDM_RX_FRAME_ENHANCED_WIFI_BANDWIDTH 0x00000038 1185 #define OFDM_RX_FRAME_ENHANCED_WIFI_UL_FLAG 0x00000040 1186 #define OFDM_RX_FRAME_ENHANCED_WIFI_BSS_COLOR 0x00001f80 1187 #define OFDM_RX_FRAME_ENHANCED_WIFI_TXOP_DURATION 0x000fe000 1188 #define OFDM_RX_FRAME_EHT_USIG1_DISREGARD 0x01f00000 1189 #define OFDM_RX_FRAME_EHT_USIG1_VALIDATE 0x02000000 1190 #define OFDM_RX_FRAME_EHT_BW320_SLOT 0x04000000 1191 #define OFDM_RX_FRAME_EHT_TYPE 0x18000000 1192 #define OFDM_RX_FRAME_ENHANCED_ER_NO_STREAMS 0x20000000 1193 __le32 usig_a1; 1194 #define OFDM_RX_FRAME_EHT_PPDU_TYPE 0x00000003 1195 #define OFDM_RX_FRAME_EHT_USIG2_VALIDATE_B2 0x00000004 1196 #define OFDM_RX_FRAME_EHT_PUNC_CHANNEL 0x000000f8 1197 #define OFDM_RX_FRAME_EHT_USIG2_VALIDATE_B8 0x00000100 1198 #define OFDM_RX_FRAME_EHT_SIG_MCS 0x00000600 1199 #define OFDM_RX_FRAME_EHT_SIG_SYM_NUM 0x0000f800 1200 #define OFDM_RX_FRAME_EHT_TRIG_SPATIAL_REUSE_1 0x000f0000 1201 #define OFDM_RX_FRAME_EHT_TRIG_SPATIAL_REUSE_2 0x00f00000 1202 #define OFDM_RX_FRAME_EHT_TRIG_USIG2_DISREGARD 0x1f000000 1203 #define OFDM_RX_FRAME_EHT_TRIG_NO_STREAMS 0x20000000 1204 #define OFDM_RX_USIG_CRC_OK 0x40000000 1205 __le32 usig_a2_eht; 1206 #define OFDM_RX_FRAME_EHT_SPATIAL_REUSE 0x0000000f 1207 #define OFDM_RX_FRAME_EHT_GI_LTF_TYPE 0x00000030 1208 #define OFDM_RX_FRAME_EHT_NUM_OF_LTF_SYM 0x000001c0 1209 #define OFDM_RX_FRAME_EHT_CODING_EXTRA_SYM 0x00000200 1210 #define OFDM_RX_FRAME_EHT_PRE_FEC_PAD_FACTOR 0x00000c00 1211 #define OFDM_RX_FRAME_EHT_PE_DISAMBIG 0x00001000 1212 #define OFDM_RX_FRAME_EHT_USIG_OVF_DISREGARD 0x0001e000 1213 #define OFDM_RX_FRAME_EHT_NUM_OF_USERS 0x000e0000 1214 #define OFDM_RX_FRAME_EHT_NSTS 0x00f00000 1215 #define OFDM_RX_FRAME_EHT_BF 0x01000000 1216 #define OFDM_RX_FRAME_EHT_USIG_OVF_NDP_DISREGARD 0x06000000 1217 #define OFDM_RX_FRAME_EHTSIG_COMM_CC1_CRC_OK 0x08000000 1218 #define OFDM_RX_FRAME_EHTSIG_COMM_CC2_CRC_OK 0x10000000 1219 #define OFDM_RX_FRAME_EHT_NON_VALID_RU_ALLOC 0x20000000 1220 #define OFDM_RX_FRAME_EHT_NO_STREAMS 0x40000000 1221 __le32 b1; 1222 #define OFDM_RX_FRAME_EHT_MATCH_ID_FOUND 0x00000001 1223 #define OFDM_RX_FRAME_EHT_ID_INDX 0x0000000e 1224 #define OFDM_RX_FRAME_EHT_MCS 0x000000f0 1225 #define OFDM_RX_FRAME_EHT_CODING 0x00000100 1226 #define OFDM_RX_FRAME_EHT_SPATIAL_CONFIG 0x00007e00 1227 #define OFDM_RX_FRAME_EHT_STA_RU 0x007f8000 1228 #define OFDM_RX_FRAME_EHT_STA_RU_P80 0x00008000 1229 #define OFDM_RX_FRAME_EHT_STA_RU_PS160 0x00800000 1230 #define OFDM_RX_FRAME_EHT_USER_FIELD_CRC_OK 0x40000000 1231 __le32 b2; 1232 #define OFDM_RX_FRAME_EHT_NUM_OF_DATA_SYM 0x000007ff 1233 #define OFDM_RX_FRAME_EHT_PE_DURATION 0x00003800 1234 #define OFDM_RX_FRAME_EHT_NUM_OF_DATA_SYM_VALID 0x80000000 1235 __le32 sig2; 1236 #define OFDM_RX_FRAME_EHT_RU_ALLOC_0_A1 0x000001ff 1237 #define OFDM_RX_FRAME_EHT_RU_ALLOC_0_A2 0x0003fe00 1238 #define OFDM_RX_FRAME_EHT_RU_ALLOC_0_A3 0x07fc0000 1239 #define OFDM_RX_FRAME_EHT_RU_ALLOC_1_B1 0x000001ff 1240 #define OFDM_RX_FRAME_EHT_RU_ALLOC_1_B2 0x0003fe00 1241 #define OFDM_RX_FRAME_EHT_RU_ALLOC_1_B3 0x07fc0000 1242 #define OFDM_RX_FRAME_EHT_RU_ALLOC_2_C1 0x000001ff 1243 #define OFDM_RX_FRAME_EHT_RU_ALLOC_2_C2 0x0003fe00 1244 #define OFDM_RX_FRAME_EHT_RU_ALLOC_2_C3 0x07fc0000 1245 #define OFDM_RX_FRAME_EHT_RU_ALLOC_3_D1 0x000001ff 1246 #define OFDM_RX_FRAME_EHT_RU_ALLOC_3_D2 0x0003fe00 1247 #define OFDM_RX_FRAME_EHT_RU_ALLOC_3_D3 0x07fc0000 1248 #define OFDM_RX_FRAME_EHT_RU_ALLOC_4_A4 0x000001ff 1249 #define OFDM_RX_FRAME_EHT_RU_ALLOC_4_B4 0x0003fe00 1250 #define OFDM_RX_FRAME_EHT_RU_ALLOC_5_C4 0x000001ff 1251 #define OFDM_RX_FRAME_EHT_RU_ALLOC_5_D4 0x0003fe00 1252 __le32 cmn[6]; 1253 #define OFDM_RX_FRAME_EHT_USER_FIELD_ID 0x000007ff 1254 __le32 user_id; 1255 }; 1256 1257 struct iwl_eht_tb_sigs { 1258 /* same as non-TB above */ 1259 __le32 usig_a1, usig_a2_eht; 1260 /* same as HE TB above */ 1261 __le32 tb_rx0, tb_rx1; 1262 }; 1263 1264 struct iwl_uhr_sigs { 1265 __le32 usig_a1, usig_a1_uhr, usig_a2_uhr, b1, b2; 1266 __le32 sig2; 1267 __le32 cmn[6]; 1268 __le32 user_id; 1269 }; 1270 1271 struct iwl_uhr_tb_sigs { 1272 __le32 usig_a1, usig_a2_uhr, tb_rx0, tb_rx1; 1273 }; 1274 1275 struct iwl_uhr_elr_sigs { 1276 __le32 usig_a1, usig_a2_uhr; 1277 __le32 uhr_sig_elr1, uhr_sig_elr2; 1278 }; 1279 1280 union iwl_sigs { 1281 struct iwl_ht_sigs ht; 1282 struct iwl_vht_sigs vht; 1283 struct iwl_he_sigs he; 1284 struct iwl_he_tb_sigs he_tb; 1285 struct iwl_eht_sigs eht; 1286 struct iwl_eht_tb_sigs eht_tb; 1287 struct iwl_uhr_sigs uhr; 1288 struct iwl_uhr_tb_sigs uhr_tb; 1289 struct iwl_uhr_elr_sigs uhr_elr; 1290 }; 1291 1292 enum iwl_sniffer_status { 1293 IWL_SNIF_STAT_PLCP_RX_OK = 0, 1294 IWL_SNIF_STAT_AID_NOT_FOR_US = 1, 1295 IWL_SNIF_STAT_PLCP_RX_LSIG_ERR = 2, 1296 IWL_SNIF_STAT_PLCP_RX_SIGA_ERR = 3, 1297 IWL_SNIF_STAT_PLCP_RX_SIGB_ERR = 4, 1298 IWL_SNIF_STAT_UNEXPECTED_TB = 5, 1299 IWL_SNIF_STAT_UNSUPPORTED_RATE = 6, 1300 IWL_SNIF_STAT_UNKNOWN_ERROR = 7, 1301 }; /* AIR_SNIFFER_STATUS_E_VER_1 */ 1302 1303 enum iwl_sniffer_flags { 1304 IWL_SNIF_FLAG_VALID_TB_RX = BIT(0), 1305 IWL_SNIF_FLAG_VALID_RU = BIT(1), 1306 }; /* AIR_SNIFFER_FLAGS_E_VER_1 */ 1307 1308 /** 1309 * struct iwl_rx_phy_air_sniffer_ntfy - air sniffer notification 1310 * 1311 * @status: &enum iwl_sniffer_status 1312 * @flags: &enum iwl_sniffer_flags 1313 * @reserved1: reserved 1314 * @rssi_a: energy chain-A in negative dBm, measured at FINA time 1315 * @rssi_b: energy chain-B in negative dBm, measured at FINA time 1316 * @channel: channel number 1317 * @band: band information, PHY_BAND_* 1318 * @on_air_rise_time: GP2 at on air rise 1319 * @frame_time: frame time in us 1320 * @rate: RATE_MCS_* 1321 * @bytecount: byte count for legay and HT, otherwise number of symbols 1322 * @legacy_sig: CCK signal information if %RATE_MCS_MOD_TYPE_MSK in @rate is 1323 * %RATE_MCS_MOD_TYPE_CCK, otherwise OFDM signal information 1324 * @sigs: PHY signal information, depending on %RATE_MCS_MOD_TYPE_MSK in @rate 1325 * @reserved2: reserved 1326 * 1327 * Sent for every frame and before the normal RX command if data is included. 1328 */ 1329 struct iwl_rx_phy_air_sniffer_ntfy { 1330 u8 status; 1331 u8 flags; 1332 u8 reserved1[2]; 1333 u8 rssi_a, rssi_b; 1334 u8 channel, band; 1335 __le32 on_air_rise_time; 1336 __le32 frame_time; 1337 /* note: MCS in rate is not valid for MU-VHT */ 1338 __le32 rate; 1339 __le32 bytecount; 1340 union iwl_legacy_sig legacy_sig; 1341 union iwl_sigs sigs; 1342 __le32 reserved2; 1343 }; /* RX_PHY_AIR_SNIFFER_NTFY_API_S_VER_1 */ 1344 1345 #endif /* __iwl_fw_api_rx_h__ */ 1346