1 /*
2 * QEMU PowerPC PowerNV Proxy PHB model
3 *
4 * Copyright (c) 2022, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
8 */
9
10 #include "qemu/osdep.h"
11 #include "qemu/log.h"
12 #include "qapi/visitor.h"
13 #include "qapi/error.h"
14 #include "hw/pci-host/pnv_phb.h"
15 #include "hw/pci-host/pnv_phb3.h"
16 #include "hw/pci-host/pnv_phb4.h"
17 #include "hw/ppc/pnv.h"
18 #include "hw/qdev-properties.h"
19 #include "qom/object.h"
20 #include "system/system.h"
21
22
23 /*
24 * Set the QOM parent and parent bus of an object child. If the device
25 * state associated with the child has an id, use it as QOM id.
26 * Otherwise use object_typename[index] as QOM id.
27 *
28 * This helper does both operations at the same time because setting
29 * a new QOM child will erase the bus parent of the device. This happens
30 * because object_unparent() will call object_property_del_child(),
31 * which in turn calls the property release callback prop->release if
32 * it's defined. In our case this callback is set to
33 * object_finalize_child_property(), which was assigned during the
34 * first object_property_add_child() call. This callback will end up
35 * calling device_unparent(), and this function removes the device
36 * from its parent bus.
37 *
38 * The QOM and parent bus to be set aren´t necessarily related, so
39 * let's receive both as arguments.
40 */
pnv_parent_fixup(Object * parent,BusState * parent_bus,Object * child,int index,Error ** errp)41 static bool pnv_parent_fixup(Object *parent, BusState *parent_bus,
42 Object *child, int index,
43 Error **errp)
44 {
45 g_autofree char *default_id =
46 g_strdup_printf("%s[%d]", object_get_typename(child), index);
47 const char *dev_id = DEVICE(child)->id;
48
49 if (child->parent == parent) {
50 return true;
51 }
52
53 object_ref(child);
54 object_unparent(child);
55 object_property_add_child(parent, dev_id ? dev_id : default_id, child);
56 object_unref(child);
57
58 if (!qdev_set_parent_bus(DEVICE(child), parent_bus, errp)) {
59 return false;
60 }
61
62 return true;
63 }
64
pnv_phb_user_get_parent(PnvChip * chip,PnvPHB * phb,Error ** errp)65 static Object *pnv_phb_user_get_parent(PnvChip *chip, PnvPHB *phb, Error **errp)
66 {
67 if (phb->version == 3) {
68 return OBJECT(pnv_chip_add_phb(chip, phb));
69 } else {
70 return OBJECT(pnv_pec_add_phb(chip, phb, errp));
71 }
72 }
73
74 /*
75 * User created devices won't have the initial setup that default
76 * devices have. This setup consists of assigning a parent device
77 * (chip for PHB3, PEC for PHB4/5) that will be the QOM/bus parent
78 * of the PHB.
79 */
pnv_phb_user_device_init(PnvPHB * phb,Error ** errp)80 static bool pnv_phb_user_device_init(PnvPHB *phb, Error **errp)
81 {
82 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
83 PnvChip *chip = pnv_get_chip(pnv, phb->chip_id);
84 Object *parent = NULL;
85
86 if (!chip) {
87 error_setg(errp, "invalid chip id: %d", phb->chip_id);
88 return false;
89 }
90
91 parent = pnv_phb_user_get_parent(chip, phb, errp);
92 if (!parent) {
93 return false;
94 }
95
96 /*
97 * Reparent user created devices to the chip to build
98 * correctly the device tree. pnv_xscom_dt() needs every
99 * PHB to be a child of the chip to build the DT correctly.
100 */
101 if (!pnv_parent_fixup(parent, qdev_get_parent_bus(DEVICE(chip)),
102 OBJECT(phb), phb->phb_id, errp)) {
103 return false;
104 }
105
106 return true;
107 }
108
pnv_phb_realize(DeviceState * dev,Error ** errp)109 static void pnv_phb_realize(DeviceState *dev, Error **errp)
110 {
111 PnvPHB *phb = PNV_PHB(dev);
112 PCIHostState *pci = PCI_HOST_BRIDGE(dev);
113 g_autofree char *phb_typename = NULL;
114
115 if (!phb->version) {
116 error_setg(errp, "version not specified");
117 return;
118 }
119
120 switch (phb->version) {
121 case 3:
122 phb_typename = g_strdup(TYPE_PNV_PHB3);
123 break;
124 case 4:
125 phb_typename = g_strdup(TYPE_PNV_PHB4);
126 break;
127 case 5:
128 phb_typename = g_strdup(TYPE_PNV_PHB5);
129 break;
130 default:
131 g_assert_not_reached();
132 }
133
134 phb->backend = object_new(phb_typename);
135 object_property_add_child(OBJECT(dev), "phb-backend", phb->backend);
136
137 /* Passthrough child device properties to the proxy device */
138 object_property_set_uint(phb->backend, "index", phb->phb_id, errp);
139 object_property_set_uint(phb->backend, "chip-id", phb->chip_id, errp);
140 object_property_set_link(phb->backend, "phb-base", OBJECT(phb), errp);
141
142 /*
143 * Handle user created devices. User devices will not have a
144 * pointer to a chip (PHB3) and a PEC (PHB4/5).
145 */
146 if (!phb->chip && !phb->pec) {
147 if (!pnv_phb_user_device_init(phb, errp)) {
148 return;
149 }
150 }
151
152 if (phb->version == 3) {
153 object_property_set_link(phb->backend, "chip",
154 OBJECT(phb->chip), errp);
155 } else {
156 object_property_set_link(phb->backend, "pec", OBJECT(phb->pec), errp);
157 }
158
159 if (!qdev_realize(DEVICE(phb->backend), NULL, errp)) {
160 return;
161 }
162
163 if (phb->version == 3) {
164 pnv_phb3_bus_init(dev, PNV_PHB3(phb->backend));
165 } else {
166 pnv_phb4_bus_init(dev, PNV_PHB4(phb->backend));
167 }
168
169 if (defaults_enabled()) {
170 PCIDevice *root = pci_new(PCI_DEVFN(0, 0), TYPE_PNV_PHB_ROOT_PORT);
171
172 pci_realize_and_unref(root, pci->bus, errp);
173 }
174 }
175
pnv_phb_root_bus_path(PCIHostState * host_bridge,PCIBus * rootbus)176 static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge,
177 PCIBus *rootbus)
178 {
179 PnvPHB *phb = PNV_PHB(host_bridge);
180
181 snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x",
182 phb->chip_id, phb->phb_id);
183 return phb->bus_path;
184 }
185
186 static const Property pnv_phb_properties[] = {
187 DEFINE_PROP_UINT32("index", PnvPHB, phb_id, 0),
188 DEFINE_PROP_UINT32("chip-id", PnvPHB, chip_id, 0),
189 DEFINE_PROP_UINT32("version", PnvPHB, version, 0),
190
191 DEFINE_PROP_LINK("chip", PnvPHB, chip, TYPE_PNV_CHIP, PnvChip *),
192
193 DEFINE_PROP_LINK("pec", PnvPHB, pec, TYPE_PNV_PHB4_PEC,
194 PnvPhb4PecState *),
195 };
196
pnv_phb_class_init(ObjectClass * klass,const void * data)197 static void pnv_phb_class_init(ObjectClass *klass, const void *data)
198 {
199 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
200 DeviceClass *dc = DEVICE_CLASS(klass);
201
202 hc->root_bus_path = pnv_phb_root_bus_path;
203 dc->realize = pnv_phb_realize;
204 device_class_set_props(dc, pnv_phb_properties);
205 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
206 dc->user_creatable = true;
207 }
208
pnv_phb_root_port_reset_hold(Object * obj,ResetType type)209 static void pnv_phb_root_port_reset_hold(Object *obj, ResetType type)
210 {
211 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj);
212 PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(obj);
213 PCIDevice *d = PCI_DEVICE(obj);
214 uint8_t *conf = d->config;
215
216 if (rpc->parent_phases.hold) {
217 rpc->parent_phases.hold(obj, type);
218 }
219
220 if (phb_rp->version == 3) {
221 return;
222 }
223
224 /* PHB4 and later requires these extra reset steps */
225 pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
226 PCI_IO_RANGE_MASK & 0xff);
227 pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
228 PCI_IO_RANGE_MASK & 0xff);
229 pci_set_word(conf + PCI_MEMORY_BASE, 0);
230 pci_set_word(conf + PCI_MEMORY_LIMIT, 0xfff0);
231 pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0x1);
232 pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1);
233 pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */
234 pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff);
235 pci_config_set_interrupt_pin(conf, 0);
236 }
237
pnv_phb_root_port_realize(DeviceState * dev,Error ** errp)238 static void pnv_phb_root_port_realize(DeviceState *dev, Error **errp)
239 {
240 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
241 PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev);
242 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(dev));
243 PCIDevice *pci = PCI_DEVICE(dev);
244 uint16_t device_id = 0;
245 Error *local_err = NULL;
246 int chip_id, index;
247
248 /*
249 * 'index' will be used both as a PCIE slot value and to calculate
250 * QOM id. 'chip_id' is going to be used as PCIE chassis for the
251 * root port.
252 */
253 chip_id = object_property_get_int(OBJECT(bus), "chip-id", &local_err);
254 if (local_err) {
255 error_propagate(errp, local_err);
256 return;
257 }
258 index = object_property_get_int(OBJECT(bus), "phb-id", &local_err);
259 if (local_err) {
260 error_propagate(errp, local_err);
261 return;
262 }
263
264 /* Set unique chassis/slot values for the root port */
265 qdev_prop_set_uint8(dev, "chassis", chip_id);
266 qdev_prop_set_uint16(dev, "slot", index);
267
268 /*
269 * User created root ports are QOM parented to one of
270 * the peripheral containers but it's already at the right
271 * parent bus. Change the QOM parent to be the same as the
272 * parent bus it's already assigned to.
273 */
274 if (!pnv_parent_fixup(OBJECT(bus), BUS(bus), OBJECT(dev),
275 index, errp)) {
276 return;
277 }
278
279 rpc->parent_realize(dev, &local_err);
280 if (local_err) {
281 error_propagate(errp, local_err);
282 return;
283 }
284
285 switch (phb_rp->version) {
286 case 3:
287 device_id = PNV_PHB3_DEVICE_ID;
288 break;
289 case 4:
290 device_id = PNV_PHB4_DEVICE_ID;
291 break;
292 case 5:
293 device_id = PNV_PHB5_DEVICE_ID;
294 break;
295 default:
296 g_assert_not_reached();
297 }
298
299 pci_config_set_device_id(pci->config, device_id);
300 pci_config_set_interrupt_pin(pci->config, 0);
301 }
302
303 static const Property pnv_phb_root_port_properties[] = {
304 DEFINE_PROP_UINT32("version", PnvPHBRootPort, version, 0),
305 };
306
pnv_phb_root_port_class_init(ObjectClass * klass,const void * data)307 static void pnv_phb_root_port_class_init(ObjectClass *klass, const void *data)
308 {
309 DeviceClass *dc = DEVICE_CLASS(klass);
310 ResettableClass *rc = RESETTABLE_CLASS(klass);
311 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
312 PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
313
314 dc->desc = "IBM PHB PCIE Root Port";
315
316 device_class_set_props(dc, pnv_phb_root_port_properties);
317 device_class_set_parent_realize(dc, pnv_phb_root_port_realize,
318 &rpc->parent_realize);
319 resettable_class_set_parent_phases(rc, NULL, pnv_phb_root_port_reset_hold,
320 NULL, &rpc->parent_phases);
321 dc->user_creatable = true;
322
323 k->vendor_id = PCI_VENDOR_ID_IBM;
324 /* device_id will be written during realize() */
325 k->device_id = 0;
326 k->revision = 0;
327
328 rpc->exp_offset = 0x48;
329 rpc->aer_offset = 0x100;
330 }
331
332 static const TypeInfo pnv_phb_type_info = {
333 .name = TYPE_PNV_PHB,
334 .parent = TYPE_PCIE_HOST_BRIDGE,
335 .instance_size = sizeof(PnvPHB),
336 .class_init = pnv_phb_class_init,
337 };
338
339 static const TypeInfo pnv_phb_root_port_info = {
340 .name = TYPE_PNV_PHB_ROOT_PORT,
341 .parent = TYPE_PCIE_ROOT_PORT,
342 .instance_size = sizeof(PnvPHBRootPort),
343 .class_init = pnv_phb_root_port_class_init,
344 };
345
pnv_phb_register_types(void)346 static void pnv_phb_register_types(void)
347 {
348 type_register_static(&pnv_phb_type_info);
349 type_register_static(&pnv_phb_root_port_info);
350 }
351
352 type_init(pnv_phb_register_types)
353