1 /*
2 * Performance events x86 architecture header
3 *
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
11 *
12 * For licencing details see kernel-base/COPYING
13 */
14
15 #include <linux/perf_event.h>
16
17 /*
18 * | NHM/WSM | SNB |
19 * register -------------------------------
20 * | HT | no HT | HT | no HT |
21 *-----------------------------------------
22 * offcore | core | core | cpu | core |
23 * lbr_sel | core | core | cpu | core |
24 * ld_lat | cpu | core | cpu | core |
25 *-----------------------------------------
26 *
27 * Given that there is a small number of shared regs,
28 * we can pre-allocate their slot in the per-cpu
29 * per-core reg tables.
30 */
31 enum extra_reg_type {
32 EXTRA_REG_NONE = -1, /* not used */
33
34 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
35 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
36
37 EXTRA_REG_MAX /* number of entries needed */
38 };
39
40 struct event_constraint {
41 union {
42 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
43 u64 idxmsk64;
44 };
45 u64 code;
46 u64 cmask;
47 int weight;
48 int overlap;
49 };
50
51 struct amd_nb {
52 int nb_id; /* NorthBridge id */
53 int refcnt; /* reference count */
54 struct perf_event *owners[X86_PMC_IDX_MAX];
55 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
56 };
57
58 /* The maximal number of PEBS events: */
59 #define MAX_PEBS_EVENTS 4
60
61 /*
62 * A debug store configuration.
63 *
64 * We only support architectures that use 64bit fields.
65 */
66 struct debug_store {
67 u64 bts_buffer_base;
68 u64 bts_index;
69 u64 bts_absolute_maximum;
70 u64 bts_interrupt_threshold;
71 u64 pebs_buffer_base;
72 u64 pebs_index;
73 u64 pebs_absolute_maximum;
74 u64 pebs_interrupt_threshold;
75 u64 pebs_event_reset[MAX_PEBS_EVENTS];
76 };
77
78 /*
79 * Per register state.
80 */
81 struct er_account {
82 raw_spinlock_t lock; /* per-core: protect structure */
83 u64 config; /* extra MSR config */
84 u64 reg; /* extra MSR number */
85 atomic_t ref; /* reference count */
86 };
87
88 /*
89 * Per core/cpu state
90 *
91 * Used to coordinate shared registers between HT threads or
92 * among events on a single PMU.
93 */
94 struct intel_shared_regs {
95 struct er_account regs[EXTRA_REG_MAX];
96 int refcnt; /* per-core: #HT threads */
97 unsigned core_id; /* per-core: core id */
98 };
99
100 #define MAX_LBR_ENTRIES 16
101
102 struct cpu_hw_events {
103 /*
104 * Generic x86 PMC bits
105 */
106 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
107 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
108 unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
109 int enabled;
110
111 int n_events;
112 int n_added;
113 int n_txn;
114 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
115 u64 tags[X86_PMC_IDX_MAX];
116 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
117
118 unsigned int group_flag;
119
120 /*
121 * Intel DebugStore bits
122 */
123 struct debug_store *ds;
124 u64 pebs_enabled;
125
126 /*
127 * Intel LBR bits
128 */
129 int lbr_users;
130 void *lbr_context;
131 struct perf_branch_stack lbr_stack;
132 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
133
134 /*
135 * Intel host/guest exclude bits
136 */
137 u64 intel_ctrl_guest_mask;
138 u64 intel_ctrl_host_mask;
139 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
140
141 /*
142 * manage shared (per-core, per-cpu) registers
143 * used on Intel NHM/WSM/SNB
144 */
145 struct intel_shared_regs *shared_regs;
146
147 /*
148 * AMD specific bits
149 */
150 struct amd_nb *amd_nb;
151 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
152 u64 perf_ctr_virt_mask;
153
154 void *kfree_on_online;
155 };
156
157 #define __EVENT_CONSTRAINT(c, n, m, w, o) {\
158 { .idxmsk64 = (n) }, \
159 .code = (c), \
160 .cmask = (m), \
161 .weight = (w), \
162 .overlap = (o), \
163 }
164
165 #define EVENT_CONSTRAINT(c, n, m) \
166 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0)
167
168 /*
169 * The overlap flag marks event constraints with overlapping counter
170 * masks. This is the case if the counter mask of such an event is not
171 * a subset of any other counter mask of a constraint with an equal or
172 * higher weight, e.g.:
173 *
174 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
175 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
176 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
177 *
178 * The event scheduler may not select the correct counter in the first
179 * cycle because it needs to know which subsequent events will be
180 * scheduled. It may fail to schedule the events then. So we set the
181 * overlap flag for such constraints to give the scheduler a hint which
182 * events to select for counter rescheduling.
183 *
184 * Care must be taken as the rescheduling algorithm is O(n!) which
185 * will increase scheduling cycles for an over-commited system
186 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
187 * and its counter masks must be kept at a minimum.
188 */
189 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
190 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1)
191
192 /*
193 * Constraint on the Event code.
194 */
195 #define INTEL_EVENT_CONSTRAINT(c, n) \
196 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
197
198 /*
199 * Constraint on the Event code + UMask + fixed-mask
200 *
201 * filter mask to validate fixed counter events.
202 * the following filters disqualify for fixed counters:
203 * - inv
204 * - edge
205 * - cnt-mask
206 * The other filters are supported by fixed counters.
207 * The any-thread option is supported starting with v3.
208 */
209 #define FIXED_EVENT_CONSTRAINT(c, n) \
210 EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
211
212 /*
213 * Constraint on the Event code + UMask
214 */
215 #define INTEL_UEVENT_CONSTRAINT(c, n) \
216 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
217
218 #define EVENT_CONSTRAINT_END \
219 EVENT_CONSTRAINT(0, 0, 0)
220
221 #define for_each_event_constraint(e, c) \
222 for ((e) = (c); (e)->weight; (e)++)
223
224 /*
225 * Extra registers for specific events.
226 *
227 * Some events need large masks and require external MSRs.
228 * Those extra MSRs end up being shared for all events on
229 * a PMU and sometimes between PMU of sibling HT threads.
230 * In either case, the kernel needs to handle conflicting
231 * accesses to those extra, shared, regs. The data structure
232 * to manage those registers is stored in cpu_hw_event.
233 */
234 struct extra_reg {
235 unsigned int event;
236 unsigned int msr;
237 u64 config_mask;
238 u64 valid_mask;
239 int idx; /* per_xxx->regs[] reg index */
240 };
241
242 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
243 .event = (e), \
244 .msr = (ms), \
245 .config_mask = (m), \
246 .valid_mask = (vm), \
247 .idx = EXTRA_REG_##i \
248 }
249
250 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
251 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
252
253 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
254
255 union perf_capabilities {
256 struct {
257 u64 lbr_format:6;
258 u64 pebs_trap:1;
259 u64 pebs_arch_reg:1;
260 u64 pebs_format:4;
261 u64 smm_freeze:1;
262 };
263 u64 capabilities;
264 };
265
266 struct x86_pmu_quirk {
267 struct x86_pmu_quirk *next;
268 void (*func)(void);
269 };
270
271 /*
272 * struct x86_pmu - generic x86 pmu
273 */
274 struct x86_pmu {
275 /*
276 * Generic x86 PMC bits
277 */
278 const char *name;
279 int version;
280 int (*handle_irq)(struct pt_regs *);
281 void (*disable_all)(void);
282 void (*enable_all)(int added);
283 void (*enable)(struct perf_event *);
284 void (*disable)(struct perf_event *);
285 int (*hw_config)(struct perf_event *event);
286 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
287 unsigned eventsel;
288 unsigned perfctr;
289 u64 (*event_map)(int);
290 int max_events;
291 int num_counters;
292 int num_counters_fixed;
293 int cntval_bits;
294 u64 cntval_mask;
295 union {
296 unsigned long events_maskl;
297 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
298 };
299 int events_mask_len;
300 int apic;
301 u64 max_period;
302 struct event_constraint *
303 (*get_event_constraints)(struct cpu_hw_events *cpuc,
304 struct perf_event *event);
305
306 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
307 struct perf_event *event);
308 struct event_constraint *event_constraints;
309 struct x86_pmu_quirk *quirks;
310 int perfctr_second_write;
311
312 int (*cpu_prepare)(int cpu);
313 void (*cpu_starting)(int cpu);
314 void (*cpu_dying)(int cpu);
315 void (*cpu_dead)(int cpu);
316
317 /*
318 * Intel Arch Perfmon v2+
319 */
320 u64 intel_ctrl;
321 union perf_capabilities intel_cap;
322
323 /*
324 * Intel DebugStore bits
325 */
326 int bts, pebs;
327 int bts_active, pebs_active;
328 int pebs_record_size;
329 void (*drain_pebs)(struct pt_regs *regs);
330 struct event_constraint *pebs_constraints;
331
332 /*
333 * Intel LBR
334 */
335 unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
336 int lbr_nr; /* hardware stack size */
337
338 /*
339 * Extra registers for events
340 */
341 struct extra_reg *extra_regs;
342 unsigned int er_flags;
343
344 /*
345 * Intel host/guest support (KVM)
346 */
347 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
348 };
349
350 #define x86_add_quirk(func_) \
351 do { \
352 static struct x86_pmu_quirk __quirk __initdata = { \
353 .func = func_, \
354 }; \
355 __quirk.next = x86_pmu.quirks; \
356 x86_pmu.quirks = &__quirk; \
357 } while (0)
358
359 #define ERF_NO_HT_SHARING 1
360 #define ERF_HAS_RSP_1 2
361
362 extern struct x86_pmu x86_pmu __read_mostly;
363
364 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
365
366 int x86_perf_event_set_period(struct perf_event *event);
367
368 /*
369 * Generalized hw caching related hw_event table, filled
370 * in on a per model basis. A value of 0 means
371 * 'not supported', -1 means 'hw_event makes no sense on
372 * this CPU', any other value means the raw hw_event
373 * ID.
374 */
375
376 #define C(x) PERF_COUNT_HW_CACHE_##x
377
378 extern u64 __read_mostly hw_cache_event_ids
379 [PERF_COUNT_HW_CACHE_MAX]
380 [PERF_COUNT_HW_CACHE_OP_MAX]
381 [PERF_COUNT_HW_CACHE_RESULT_MAX];
382 extern u64 __read_mostly hw_cache_extra_regs
383 [PERF_COUNT_HW_CACHE_MAX]
384 [PERF_COUNT_HW_CACHE_OP_MAX]
385 [PERF_COUNT_HW_CACHE_RESULT_MAX];
386
387 u64 x86_perf_event_update(struct perf_event *event);
388
x86_pmu_addr_offset(int index)389 static inline int x86_pmu_addr_offset(int index)
390 {
391 int offset;
392
393 /* offset = X86_FEATURE_PERFCTR_CORE ? index << 1 : index */
394 alternative_io(ASM_NOP2,
395 "shll $1, %%eax",
396 X86_FEATURE_PERFCTR_CORE,
397 "=a" (offset),
398 "a" (index));
399
400 return offset;
401 }
402
x86_pmu_config_addr(int index)403 static inline unsigned int x86_pmu_config_addr(int index)
404 {
405 return x86_pmu.eventsel + x86_pmu_addr_offset(index);
406 }
407
x86_pmu_event_addr(int index)408 static inline unsigned int x86_pmu_event_addr(int index)
409 {
410 return x86_pmu.perfctr + x86_pmu_addr_offset(index);
411 }
412
413 int x86_setup_perfctr(struct perf_event *event);
414
415 int x86_pmu_hw_config(struct perf_event *event);
416
417 void x86_pmu_disable_all(void);
418
__x86_pmu_enable_event(struct hw_perf_event * hwc,u64 enable_mask)419 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
420 u64 enable_mask)
421 {
422 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
423
424 if (hwc->extra_reg.reg)
425 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
426 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
427 }
428
429 void x86_pmu_enable_all(int added);
430
431 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
432
433 void x86_pmu_stop(struct perf_event *event, int flags);
434
x86_pmu_disable_event(struct perf_event * event)435 static inline void x86_pmu_disable_event(struct perf_event *event)
436 {
437 struct hw_perf_event *hwc = &event->hw;
438
439 wrmsrl(hwc->config_base, hwc->config);
440 }
441
442 void x86_pmu_enable_event(struct perf_event *event);
443
444 int x86_pmu_handle_irq(struct pt_regs *regs);
445
446 extern struct event_constraint emptyconstraint;
447
448 extern struct event_constraint unconstrained;
449
450 #ifdef CONFIG_CPU_SUP_AMD
451
452 int amd_pmu_init(void);
453
454 #else /* CONFIG_CPU_SUP_AMD */
455
amd_pmu_init(void)456 static inline int amd_pmu_init(void)
457 {
458 return 0;
459 }
460
461 #endif /* CONFIG_CPU_SUP_AMD */
462
463 #ifdef CONFIG_CPU_SUP_INTEL
464
465 int intel_pmu_save_and_restart(struct perf_event *event);
466
467 struct event_constraint *
468 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event);
469
470 struct intel_shared_regs *allocate_shared_regs(int cpu);
471
472 int intel_pmu_init(void);
473
474 void init_debug_store_on_cpu(int cpu);
475
476 void fini_debug_store_on_cpu(int cpu);
477
478 void release_ds_buffers(void);
479
480 void reserve_ds_buffers(void);
481
482 extern struct event_constraint bts_constraint;
483
484 void intel_pmu_enable_bts(u64 config);
485
486 void intel_pmu_disable_bts(void);
487
488 int intel_pmu_drain_bts_buffer(void);
489
490 extern struct event_constraint intel_core2_pebs_event_constraints[];
491
492 extern struct event_constraint intel_atom_pebs_event_constraints[];
493
494 extern struct event_constraint intel_nehalem_pebs_event_constraints[];
495
496 extern struct event_constraint intel_westmere_pebs_event_constraints[];
497
498 extern struct event_constraint intel_snb_pebs_event_constraints[];
499
500 struct event_constraint *intel_pebs_constraints(struct perf_event *event);
501
502 void intel_pmu_pebs_enable(struct perf_event *event);
503
504 void intel_pmu_pebs_disable(struct perf_event *event);
505
506 void intel_pmu_pebs_enable_all(void);
507
508 void intel_pmu_pebs_disable_all(void);
509
510 void intel_ds_init(void);
511
512 void intel_pmu_lbr_reset(void);
513
514 void intel_pmu_lbr_enable(struct perf_event *event);
515
516 void intel_pmu_lbr_disable(struct perf_event *event);
517
518 void intel_pmu_lbr_enable_all(void);
519
520 void intel_pmu_lbr_disable_all(void);
521
522 void intel_pmu_lbr_read(void);
523
524 void intel_pmu_lbr_init_core(void);
525
526 void intel_pmu_lbr_init_nhm(void);
527
528 void intel_pmu_lbr_init_atom(void);
529
530 int p4_pmu_init(void);
531
532 int p6_pmu_init(void);
533
534 #else /* CONFIG_CPU_SUP_INTEL */
535
reserve_ds_buffers(void)536 static inline void reserve_ds_buffers(void)
537 {
538 }
539
release_ds_buffers(void)540 static inline void release_ds_buffers(void)
541 {
542 }
543
intel_pmu_init(void)544 static inline int intel_pmu_init(void)
545 {
546 return 0;
547 }
548
allocate_shared_regs(int cpu)549 static inline struct intel_shared_regs *allocate_shared_regs(int cpu)
550 {
551 return NULL;
552 }
553
554 #endif /* CONFIG_CPU_SUP_INTEL */
555