1 /*
2 * QEMU PowerPC CHRP (Genesi/bPlan Pegasos II) hardware System Emulator
3 *
4 * Copyright (c) 2018-2021 BALATON Zoltan
5 *
6 * This work is licensed under the GNU GPL license version 2 or later.
7 *
8 */
9
10 #include "qemu/osdep.h"
11 #include "qemu/units.h"
12 #include "qapi/error.h"
13 #include "hw/ppc/ppc.h"
14 #include "hw/sysbus.h"
15 #include "hw/pci/pci_host.h"
16 #include "hw/irq.h"
17 #include "hw/or-irq.h"
18 #include "hw/pci-host/mv64361.h"
19 #include "hw/isa/vt82c686.h"
20 #include "hw/ide/pci.h"
21 #include "hw/i2c/smbus_eeprom.h"
22 #include "hw/qdev-properties.h"
23 #include "system/reset.h"
24 #include "system/runstate.h"
25 #include "system/qtest.h"
26 #include "hw/boards.h"
27 #include "hw/loader.h"
28 #include "hw/fw-path-provider.h"
29 #include "elf.h"
30 #include "qemu/log.h"
31 #include "qemu/error-report.h"
32 #include "system/kvm.h"
33 #include "kvm_ppc.h"
34 #include "system/address-spaces.h"
35 #include "qom/qom-qobject.h"
36 #include "qobject/qdict.h"
37 #include "trace.h"
38 #include "qemu/datadir.h"
39 #include "system/device_tree.h"
40 #include "hw/ppc/vof.h"
41
42 #include <libfdt.h>
43
44 #define PROM_FILENAME "vof.bin"
45 #define PROM_ADDR 0xfff00000
46 #define PROM_SIZE 0x80000
47
48 #define INITRD_MIN_ADDR 0x600000
49
50 #define KVMPPC_HCALL_BASE 0xf000
51 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
52 #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5)
53
54 #define H_SUCCESS 0
55 #define H_PRIVILEGE -3 /* Caller not privileged */
56 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
57
58 #define BUS_FREQ_HZ 133333333
59
60 #define PCI0_CFG_ADDR 0xcf8
61 #define PCI0_MEM_BASE 0xc0000000
62 #define PCI0_MEM_SIZE 0x20000000
63 #define PCI0_IO_BASE 0xf8000000
64 #define PCI0_IO_SIZE 0x10000
65
66 #define PCI1_CFG_ADDR 0xc78
67 #define PCI1_MEM_BASE 0x80000000
68 #define PCI1_MEM_SIZE 0x40000000
69 #define PCI1_IO_BASE 0xfe000000
70 #define PCI1_IO_SIZE 0x10000
71
72 #define TYPE_PEGASOS2_MACHINE MACHINE_TYPE_NAME("pegasos2")
73 OBJECT_DECLARE_TYPE(Pegasos2MachineState, MachineClass, PEGASOS2_MACHINE)
74
75 struct Pegasos2MachineState {
76 MachineState parent_obj;
77
78 PowerPCCPU *cpu;
79 DeviceState *mv;
80 IRQState pci_irqs[PCI_NUM_PINS];
81 OrIRQState orirq[PCI_NUM_PINS];
82 qemu_irq mv_pirq[PCI_NUM_PINS];
83 qemu_irq via_pirq[PCI_NUM_PINS];
84 Vof *vof;
85 void *fdt_blob;
86 uint64_t kernel_addr;
87 uint64_t kernel_entry;
88 uint64_t kernel_size;
89 uint64_t initrd_addr;
90 uint64_t initrd_size;
91 };
92
93 static void *build_fdt(MachineState *machine, int *fdt_size);
94
pegasos2_cpu_reset(void * opaque)95 static void pegasos2_cpu_reset(void *opaque)
96 {
97 PowerPCCPU *cpu = opaque;
98 Pegasos2MachineState *pm = PEGASOS2_MACHINE(current_machine);
99
100 cpu_reset(CPU(cpu));
101 cpu->env.spr[SPR_HID1] = 7ULL << 28;
102 if (pm->vof) {
103 cpu->env.gpr[1] = 2 * VOF_STACK_SIZE - 0x20;
104 cpu->env.nip = 0x100;
105 }
106 cpu_ppc_tb_reset(&cpu->env);
107 }
108
pegasos2_pci_irq(void * opaque,int n,int level)109 static void pegasos2_pci_irq(void *opaque, int n, int level)
110 {
111 Pegasos2MachineState *pm = opaque;
112
113 /* PCI interrupt lines are connected to both MV64361 and VT8231 */
114 qemu_set_irq(pm->mv_pirq[n], level);
115 qemu_set_irq(pm->via_pirq[n], level);
116 }
117
pegasos2_init(MachineState * machine)118 static void pegasos2_init(MachineState *machine)
119 {
120 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine);
121 CPUPPCState *env;
122 MemoryRegion *rom = g_new(MemoryRegion, 1);
123 PCIBus *pci_bus;
124 Object *via;
125 PCIDevice *dev;
126 I2CBus *i2c_bus;
127 const char *fwname = machine->firmware ?: PROM_FILENAME;
128 char *filename;
129 int i;
130 ssize_t sz;
131 uint8_t *spd_data;
132
133 /* init CPU */
134 pm->cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
135 env = &pm->cpu->env;
136 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
137 error_report("Incompatible CPU, only 6xx bus supported");
138 exit(1);
139 }
140
141 /* Set time-base frequency */
142 cpu_ppc_tb_init(env, BUS_FREQ_HZ / 4);
143 qemu_register_reset(pegasos2_cpu_reset, pm->cpu);
144
145 /* RAM */
146 if (machine->ram_size > 2 * GiB) {
147 error_report("RAM size more than 2 GiB is not supported");
148 exit(1);
149 }
150 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
151
152 /* allocate and load firmware */
153 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, fwname);
154 if (!filename) {
155 error_report("Could not find firmware '%s'", fwname);
156 exit(1);
157 }
158 if (!machine->firmware && !pm->vof) {
159 pm->vof = g_malloc0(sizeof(*pm->vof));
160 }
161 memory_region_init_rom(rom, NULL, "pegasos2.rom", PROM_SIZE, &error_fatal);
162 memory_region_add_subregion(get_system_memory(), PROM_ADDR, rom);
163 sz = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
164 ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0);
165 if (sz <= 0) {
166 sz = load_image_targphys(filename, pm->vof ? 0 : PROM_ADDR, PROM_SIZE);
167 }
168 if (sz <= 0 || sz > PROM_SIZE) {
169 error_report("Could not load firmware '%s'", filename);
170 exit(1);
171 }
172 g_free(filename);
173 if (pm->vof) {
174 pm->vof->fw_size = sz;
175 }
176
177 /* Marvell Discovery II system controller */
178 pm->mv = DEVICE(sysbus_create_simple(TYPE_MV64361, -1,
179 qdev_get_gpio_in(DEVICE(pm->cpu), PPC6xx_INPUT_INT)));
180 for (i = 0; i < PCI_NUM_PINS; i++) {
181 pm->mv_pirq[i] = qdev_get_gpio_in_named(pm->mv, "gpp", 12 + i);
182 }
183 pci_bus = mv64361_get_pci_bus(pm->mv, 1);
184
185 /* VIA VT8231 South Bridge (multifunction PCI device) */
186 via = OBJECT(pci_new_multifunction(PCI_DEVFN(12, 0), TYPE_VT8231_ISA));
187
188 /* Set properties on individual devices before realizing the south bridge */
189 if (machine->audiodev) {
190 dev = PCI_DEVICE(object_resolve_path_component(via, "ac97"));
191 qdev_prop_set_string(DEVICE(dev), "audiodev", machine->audiodev);
192 }
193
194 pci_realize_and_unref(PCI_DEVICE(via), pci_bus, &error_abort);
195 for (i = 0; i < PCI_NUM_PINS; i++) {
196 pm->via_pirq[i] = qdev_get_gpio_in_named(DEVICE(via), "pirq", i);
197 }
198 object_property_add_alias(OBJECT(machine), "rtc-time",
199 object_resolve_path_component(via, "rtc"),
200 "date");
201 qdev_connect_gpio_out_named(DEVICE(via), "intr", 0,
202 qdev_get_gpio_in_named(pm->mv, "gpp", 31));
203
204 dev = PCI_DEVICE(object_resolve_path_component(via, "ide"));
205 pci_ide_create_devs(dev);
206
207 dev = PCI_DEVICE(object_resolve_path_component(via, "pm"));
208 i2c_bus = I2C_BUS(qdev_get_child_bus(DEVICE(dev), "i2c"));
209 spd_data = spd_data_generate(DDR, machine->ram_size);
210 smbus_eeprom_init_one(i2c_bus, 0x57, spd_data);
211
212 /* other PC hardware */
213 pci_vga_init(pci_bus);
214
215 /* PCI interrupt routing: lines from pci.0 and pci.1 are ORed */
216 for (int h = 0; h < 2; h++) {
217 DeviceState *pd;
218 g_autofree const char *pn = g_strdup_printf("pcihost%d", h);
219
220 pd = DEVICE(object_resolve_path_component(OBJECT(pm->mv), pn));
221 assert(pd);
222 for (i = 0; i < PCI_NUM_PINS; i++) {
223 OrIRQState *ori = &pm->orirq[i];
224
225 if (h == 0) {
226 g_autofree const char *n = g_strdup_printf("pci-orirq[%d]", i);
227
228 object_initialize_child_with_props(OBJECT(pm), n,
229 ori, sizeof(*ori),
230 TYPE_OR_IRQ, &error_fatal,
231 "num-lines", "2", NULL);
232 qdev_realize(DEVICE(ori), NULL, &error_fatal);
233 qemu_init_irq(&pm->pci_irqs[i], pegasos2_pci_irq, pm, i);
234 qdev_connect_gpio_out(DEVICE(ori), 0, &pm->pci_irqs[i]);
235 }
236 qdev_connect_gpio_out(pd, i, qdev_get_gpio_in(DEVICE(ori), h));
237 }
238 }
239
240 if (machine->kernel_filename) {
241 sz = load_elf(machine->kernel_filename, NULL, NULL, NULL,
242 &pm->kernel_entry, &pm->kernel_addr, NULL, NULL,
243 ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0);
244 if (sz <= 0) {
245 error_report("Could not load kernel '%s'",
246 machine->kernel_filename);
247 exit(1);
248 }
249 pm->kernel_size = sz;
250 if (!pm->vof) {
251 warn_report("Option -kernel may be ineffective with -bios.");
252 }
253 } else if (pm->vof && !qtest_enabled()) {
254 warn_report("Using Virtual OpenFirmware but no -kernel option.");
255 }
256
257 if (machine->initrd_filename) {
258 pm->initrd_addr = pm->kernel_addr + pm->kernel_size + 64 * KiB;
259 pm->initrd_addr = ROUND_UP(pm->initrd_addr, 4);
260 pm->initrd_addr = MAX(pm->initrd_addr, INITRD_MIN_ADDR);
261 sz = load_image_targphys(machine->initrd_filename, pm->initrd_addr,
262 machine->ram_size - pm->initrd_addr);
263 if (sz <= 0) {
264 error_report("Could not load initrd '%s'",
265 machine->initrd_filename);
266 exit(1);
267 }
268 pm->initrd_size = sz;
269 }
270
271 if (!pm->vof && machine->kernel_cmdline && machine->kernel_cmdline[0]) {
272 warn_report("Option -append may be ineffective with -bios.");
273 }
274 }
275
pegasos2_mv_reg_read(Pegasos2MachineState * pm,uint32_t addr,uint32_t len)276 static uint32_t pegasos2_mv_reg_read(Pegasos2MachineState *pm,
277 uint32_t addr, uint32_t len)
278 {
279 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0);
280 uint64_t val = 0xffffffffULL;
281 memory_region_dispatch_read(r, addr, &val, size_memop(len) | MO_LE,
282 MEMTXATTRS_UNSPECIFIED);
283 return val;
284 }
285
pegasos2_mv_reg_write(Pegasos2MachineState * pm,uint32_t addr,uint32_t len,uint32_t val)286 static void pegasos2_mv_reg_write(Pegasos2MachineState *pm, uint32_t addr,
287 uint32_t len, uint32_t val)
288 {
289 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0);
290 memory_region_dispatch_write(r, addr, val, size_memop(len) | MO_LE,
291 MEMTXATTRS_UNSPECIFIED);
292 }
293
pegasos2_pci_config_read(Pegasos2MachineState * pm,int bus,uint32_t addr,uint32_t len)294 static uint32_t pegasos2_pci_config_read(Pegasos2MachineState *pm, int bus,
295 uint32_t addr, uint32_t len)
296 {
297 hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR;
298 uint64_t val = 0xffffffffULL;
299
300 if (len <= 4) {
301 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31));
302 val = pegasos2_mv_reg_read(pm, pcicfg + 4, len);
303 }
304 return val;
305 }
306
pegasos2_pci_config_write(Pegasos2MachineState * pm,int bus,uint32_t addr,uint32_t len,uint32_t val)307 static void pegasos2_pci_config_write(Pegasos2MachineState *pm, int bus,
308 uint32_t addr, uint32_t len, uint32_t val)
309 {
310 hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR;
311
312 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31));
313 pegasos2_mv_reg_write(pm, pcicfg + 4, len, val);
314 }
315
pegasos2_superio_write(uint8_t addr,uint8_t val)316 static void pegasos2_superio_write(uint8_t addr, uint8_t val)
317 {
318 cpu_physical_memory_write(PCI1_IO_BASE + 0x3f0, &addr, 1);
319 cpu_physical_memory_write(PCI1_IO_BASE + 0x3f1, &val, 1);
320 }
321
pegasos2_machine_reset(MachineState * machine,ResetType type)322 static void pegasos2_machine_reset(MachineState *machine, ResetType type)
323 {
324 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine);
325 void *fdt;
326 uint64_t d[2];
327 int sz;
328
329 qemu_devices_reset(type);
330 if (!pm->vof) {
331 return; /* Firmware should set up machine so nothing to do */
332 }
333
334 /* Otherwise, set up devices that board firmware would normally do */
335 pegasos2_mv_reg_write(pm, 0, 4, 0x28020ff);
336 pegasos2_mv_reg_write(pm, 0x278, 4, 0xa31fc);
337 pegasos2_mv_reg_write(pm, 0xf300, 4, 0x11ff0400);
338 pegasos2_mv_reg_write(pm, 0xf10c, 4, 0x80000000);
339 pegasos2_mv_reg_write(pm, 0x1c, 4, 0x8000000);
340 pegasos2_pci_config_write(pm, 0, PCI_COMMAND, 2, PCI_COMMAND_IO |
341 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
342 pegasos2_pci_config_write(pm, 1, PCI_COMMAND, 2, PCI_COMMAND_IO |
343 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
344
345 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
346 PCI_INTERRUPT_LINE, 2, 0x9);
347 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
348 0x50, 1, 0x6);
349 pegasos2_superio_write(0xf4, 0xbe);
350 pegasos2_superio_write(0xf6, 0xef);
351 pegasos2_superio_write(0xf7, 0xfc);
352 pegasos2_superio_write(0xf2, 0x14);
353 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
354 0x50, 1, 0x2);
355 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
356 0x55, 1, 0x90);
357 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
358 0x56, 1, 0x99);
359 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
360 0x57, 1, 0x90);
361
362 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
363 PCI_INTERRUPT_LINE, 2, 0x109);
364 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
365 PCI_CLASS_PROG, 1, 0xf);
366 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
367 0x40, 1, 0xb);
368 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
369 0x50, 4, 0x17171717);
370 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
371 PCI_COMMAND, 2, 0x87);
372
373 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) |
374 PCI_INTERRUPT_LINE, 2, 0x409);
375 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) |
376 PCI_COMMAND, 2, 0x7);
377
378 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) |
379 PCI_INTERRUPT_LINE, 2, 0x409);
380 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) |
381 PCI_COMMAND, 2, 0x7);
382
383 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
384 PCI_INTERRUPT_LINE, 2, 0x9);
385 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
386 0x48, 4, 0xf00);
387 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
388 0x40, 4, 0x558020);
389 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
390 0x90, 4, 0xd00);
391
392 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 5) << 8) |
393 PCI_INTERRUPT_LINE, 2, 0x309);
394
395 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 6) << 8) |
396 PCI_INTERRUPT_LINE, 2, 0x309);
397
398 /* Device tree and VOF set up */
399 vof_init(pm->vof, machine->ram_size, &error_fatal);
400 if (vof_claim(pm->vof, 0, VOF_STACK_SIZE, VOF_STACK_SIZE) == -1) {
401 error_report("Memory allocation for stack failed");
402 exit(1);
403 }
404 if (pm->kernel_size &&
405 vof_claim(pm->vof, pm->kernel_addr, pm->kernel_size, 0) == -1) {
406 error_report("Memory for kernel is in use");
407 exit(1);
408 }
409 if (pm->initrd_size &&
410 vof_claim(pm->vof, pm->initrd_addr, pm->initrd_size, 0) == -1) {
411 error_report("Memory for initrd is in use");
412 exit(1);
413 }
414 fdt = build_fdt(machine, &sz);
415 /* FIXME: VOF assumes entry is same as load address */
416 d[0] = cpu_to_be64(pm->kernel_entry);
417 d[1] = cpu_to_be64(pm->kernel_size - (pm->kernel_entry - pm->kernel_addr));
418 qemu_fdt_setprop(fdt, "/chosen", "qemu,boot-kernel", d, sizeof(d));
419
420 g_free(pm->fdt_blob);
421 pm->fdt_blob = fdt;
422
423 vof_build_dt(fdt, pm->vof);
424 vof_client_open_store(fdt, pm->vof, "/chosen", "stdout", "/failsafe");
425
426 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
427 machine->fdt = fdt;
428
429 pm->cpu->vhyp = PPC_VIRTUAL_HYPERVISOR(machine);
430 pm->cpu->vhyp_class = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(pm->cpu->vhyp);
431 }
432
433 enum pegasos2_rtas_tokens {
434 RTAS_RESTART_RTAS = 0,
435 RTAS_NVRAM_FETCH = 1,
436 RTAS_NVRAM_STORE = 2,
437 RTAS_GET_TIME_OF_DAY = 3,
438 RTAS_SET_TIME_OF_DAY = 4,
439 RTAS_EVENT_SCAN = 6,
440 RTAS_CHECK_EXCEPTION = 7,
441 RTAS_READ_PCI_CONFIG = 8,
442 RTAS_WRITE_PCI_CONFIG = 9,
443 RTAS_DISPLAY_CHARACTER = 10,
444 RTAS_SET_INDICATOR = 11,
445 RTAS_POWER_OFF = 17,
446 RTAS_SUSPEND = 18,
447 RTAS_HIBERNATE = 19,
448 RTAS_SYSTEM_REBOOT = 20,
449 };
450
pegasos2_rtas(PowerPCCPU * cpu,Pegasos2MachineState * pm,target_ulong args_real)451 static target_ulong pegasos2_rtas(PowerPCCPU *cpu, Pegasos2MachineState *pm,
452 target_ulong args_real)
453 {
454 AddressSpace *as = CPU(cpu)->as;
455 uint32_t token = ldl_be_phys(as, args_real);
456 uint32_t nargs = ldl_be_phys(as, args_real + 4);
457 uint32_t nrets = ldl_be_phys(as, args_real + 8);
458 uint32_t args = args_real + 12;
459 uint32_t rets = args_real + 12 + nargs * 4;
460
461 if (nrets < 1) {
462 qemu_log_mask(LOG_GUEST_ERROR, "Too few return values in RTAS call\n");
463 return H_PARAMETER;
464 }
465 switch (token) {
466 case RTAS_GET_TIME_OF_DAY:
467 {
468 QObject *qo = object_property_get_qobject(qdev_get_machine(),
469 "rtc-time", &error_fatal);
470 QDict *qd = qobject_to(QDict, qo);
471
472 if (nargs != 0 || nrets != 8 || !qd) {
473 stl_be_phys(as, rets, -1);
474 qobject_unref(qo);
475 return H_PARAMETER;
476 }
477
478 stl_be_phys(as, rets, 0);
479 stl_be_phys(as, rets + 4, qdict_get_int(qd, "tm_year") + 1900);
480 stl_be_phys(as, rets + 8, qdict_get_int(qd, "tm_mon") + 1);
481 stl_be_phys(as, rets + 12, qdict_get_int(qd, "tm_mday"));
482 stl_be_phys(as, rets + 16, qdict_get_int(qd, "tm_hour"));
483 stl_be_phys(as, rets + 20, qdict_get_int(qd, "tm_min"));
484 stl_be_phys(as, rets + 24, qdict_get_int(qd, "tm_sec"));
485 stl_be_phys(as, rets + 28, 0);
486 qobject_unref(qo);
487 return H_SUCCESS;
488 }
489 case RTAS_READ_PCI_CONFIG:
490 {
491 uint32_t addr, len, val;
492
493 if (nargs != 2 || nrets != 2) {
494 stl_be_phys(as, rets, -1);
495 return H_PARAMETER;
496 }
497 addr = ldl_be_phys(as, args);
498 len = ldl_be_phys(as, args + 4);
499 val = pegasos2_pci_config_read(pm, !(addr >> 24),
500 addr & 0x0fffffff, len);
501 stl_be_phys(as, rets, 0);
502 stl_be_phys(as, rets + 4, val);
503 return H_SUCCESS;
504 }
505 case RTAS_WRITE_PCI_CONFIG:
506 {
507 uint32_t addr, len, val;
508
509 if (nargs != 3 || nrets != 1) {
510 stl_be_phys(as, rets, -1);
511 return H_PARAMETER;
512 }
513 addr = ldl_be_phys(as, args);
514 len = ldl_be_phys(as, args + 4);
515 val = ldl_be_phys(as, args + 8);
516 pegasos2_pci_config_write(pm, !(addr >> 24),
517 addr & 0x0fffffff, len, val);
518 stl_be_phys(as, rets, 0);
519 return H_SUCCESS;
520 }
521 case RTAS_DISPLAY_CHARACTER:
522 if (nargs != 1 || nrets != 1) {
523 stl_be_phys(as, rets, -1);
524 return H_PARAMETER;
525 }
526 qemu_log_mask(LOG_UNIMP, "%c", ldl_be_phys(as, args));
527 stl_be_phys(as, rets, 0);
528 return H_SUCCESS;
529 case RTAS_POWER_OFF:
530 {
531 if (nargs != 2 || nrets != 1) {
532 stl_be_phys(as, rets, -1);
533 return H_PARAMETER;
534 }
535 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
536 stl_be_phys(as, rets, 0);
537 return H_SUCCESS;
538 }
539 default:
540 qemu_log_mask(LOG_UNIMP, "Unknown RTAS token %u (args=%u, rets=%u)\n",
541 token, nargs, nrets);
542 stl_be_phys(as, rets, 0);
543 return H_SUCCESS;
544 }
545 }
546
pegasos2_cpu_in_nested(PowerPCCPU * cpu)547 static bool pegasos2_cpu_in_nested(PowerPCCPU *cpu)
548 {
549 return false;
550 }
551
pegasos2_hypercall(PPCVirtualHypervisor * vhyp,PowerPCCPU * cpu)552 static void pegasos2_hypercall(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
553 {
554 Pegasos2MachineState *pm = PEGASOS2_MACHINE(vhyp);
555 CPUPPCState *env = &cpu->env;
556
557 /* The TCG path should also be holding the BQL at this point */
558 g_assert(bql_locked());
559
560 if (FIELD_EX64(env->msr, MSR, PR)) {
561 qemu_log_mask(LOG_GUEST_ERROR, "Hypercall made with MSR[PR]=1\n");
562 env->gpr[3] = H_PRIVILEGE;
563 } else if (env->gpr[3] == KVMPPC_H_RTAS) {
564 env->gpr[3] = pegasos2_rtas(cpu, pm, env->gpr[4]);
565 } else if (env->gpr[3] == KVMPPC_H_VOF_CLIENT) {
566 int ret = vof_client_call(MACHINE(pm), pm->vof, pm->fdt_blob,
567 env->gpr[4]);
568 env->gpr[3] = (ret ? H_PARAMETER : H_SUCCESS);
569 } else {
570 qemu_log_mask(LOG_GUEST_ERROR, "Unsupported hypercall " TARGET_FMT_lx
571 "\n", env->gpr[3]);
572 env->gpr[3] = -1;
573 }
574 }
575
vhyp_nop(PPCVirtualHypervisor * vhyp,PowerPCCPU * cpu)576 static void vhyp_nop(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
577 {
578 }
579
vhyp_encode_hpt_for_kvm_pr(PPCVirtualHypervisor * vhyp)580 static target_ulong vhyp_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
581 {
582 return POWERPC_CPU(current_cpu)->env.spr[SPR_SDR1];
583 }
584
pegasos2_setprop(MachineState * ms,const char * path,const char * propname,void * val,int vallen)585 static bool pegasos2_setprop(MachineState *ms, const char *path,
586 const char *propname, void *val, int vallen)
587 {
588 return true;
589 }
590
pegasos2_machine_class_init(ObjectClass * oc,const void * data)591 static void pegasos2_machine_class_init(ObjectClass *oc, const void *data)
592 {
593 MachineClass *mc = MACHINE_CLASS(oc);
594 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
595 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc);
596
597 mc->desc = "Genesi/bPlan Pegasos II";
598 mc->init = pegasos2_init;
599 mc->reset = pegasos2_machine_reset;
600 mc->block_default_type = IF_IDE;
601 mc->default_boot_order = "cd";
602 mc->default_display = "std";
603 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7457_v1.2");
604 mc->default_ram_id = "pegasos2.ram";
605 mc->default_ram_size = 512 * MiB;
606 machine_add_audiodev_property(mc);
607
608 vhc->cpu_in_nested = pegasos2_cpu_in_nested;
609 vhc->hypercall = pegasos2_hypercall;
610 vhc->cpu_exec_enter = vhyp_nop;
611 vhc->cpu_exec_exit = vhyp_nop;
612 vhc->encode_hpt_for_kvm_pr = vhyp_encode_hpt_for_kvm_pr;
613
614 vmc->setprop = pegasos2_setprop;
615 }
616
617 static const TypeInfo pegasos2_machine_info = {
618 .name = TYPE_PEGASOS2_MACHINE,
619 .parent = TYPE_MACHINE,
620 .class_init = pegasos2_machine_class_init,
621 .instance_size = sizeof(Pegasos2MachineState),
622 .interfaces = (const InterfaceInfo[]) {
623 { TYPE_PPC_VIRTUAL_HYPERVISOR },
624 { TYPE_VOF_MACHINE_IF },
625 { }
626 },
627 };
628
pegasos2_machine_register_types(void)629 static void pegasos2_machine_register_types(void)
630 {
631 type_register_static(&pegasos2_machine_info);
632 }
633
634 type_init(pegasos2_machine_register_types)
635
636 /* FDT creation for passing to firmware */
637
638 typedef struct {
639 void *fdt;
640 const char *path;
641 } FDTInfo;
642
643 /* We do everything in reverse order so it comes out right in the tree */
644
dt_ide(PCIBus * bus,PCIDevice * d,FDTInfo * fi)645 static void dt_ide(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
646 {
647 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "spi");
648 }
649
dt_usb(PCIBus * bus,PCIDevice * d,FDTInfo * fi)650 static void dt_usb(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
651 {
652 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 0);
653 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 1);
654 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "usb");
655 }
656
dt_isa(PCIBus * bus,PCIDevice * d,FDTInfo * fi)657 static void dt_isa(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
658 {
659 GString *name = g_string_sized_new(64);
660 uint32_t cells[3];
661
662 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 1);
663 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 2);
664 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "isa");
665 qemu_fdt_setprop_string(fi->fdt, fi->path, "name", "isa");
666
667 /* additional devices */
668 g_string_printf(name, "%s/lpt@i3bc", fi->path);
669 qemu_fdt_add_subnode(fi->fdt, name->str);
670 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
671 cells[0] = cpu_to_be32(7);
672 cells[1] = 0;
673 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
674 cells, 2 * sizeof(cells[0]));
675 cells[0] = cpu_to_be32(1);
676 cells[1] = cpu_to_be32(0x3bc);
677 cells[2] = cpu_to_be32(8);
678 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
679 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "lpt");
680 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "lpt");
681
682 g_string_printf(name, "%s/fdc@i3f0", fi->path);
683 qemu_fdt_add_subnode(fi->fdt, name->str);
684 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
685 cells[0] = cpu_to_be32(6);
686 cells[1] = 0;
687 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
688 cells, 2 * sizeof(cells[0]));
689 cells[0] = cpu_to_be32(1);
690 cells[1] = cpu_to_be32(0x3f0);
691 cells[2] = cpu_to_be32(8);
692 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
693 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "fdc");
694 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "fdc");
695
696 g_string_printf(name, "%s/timer@i40", fi->path);
697 qemu_fdt_add_subnode(fi->fdt, name->str);
698 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
699 cells[0] = cpu_to_be32(1);
700 cells[1] = cpu_to_be32(0x40);
701 cells[2] = cpu_to_be32(8);
702 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
703 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "timer");
704 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "timer");
705
706 g_string_printf(name, "%s/rtc@i70", fi->path);
707 qemu_fdt_add_subnode(fi->fdt, name->str);
708 qemu_fdt_setprop_string(fi->fdt, name->str, "compatible", "ds1385-rtc");
709 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
710 cells[0] = cpu_to_be32(8);
711 cells[1] = 0;
712 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
713 cells, 2 * sizeof(cells[0]));
714 cells[0] = cpu_to_be32(1);
715 cells[1] = cpu_to_be32(0x70);
716 cells[2] = cpu_to_be32(2);
717 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
718 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "rtc");
719 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "rtc");
720
721 g_string_printf(name, "%s/keyboard@i60", fi->path);
722 qemu_fdt_add_subnode(fi->fdt, name->str);
723 cells[0] = cpu_to_be32(1);
724 cells[1] = 0;
725 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
726 cells, 2 * sizeof(cells[0]));
727 cells[0] = cpu_to_be32(1);
728 cells[1] = cpu_to_be32(0x60);
729 cells[2] = cpu_to_be32(5);
730 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
731 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "keyboard");
732 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "keyboard");
733
734 g_string_printf(name, "%s/8042@i60", fi->path);
735 qemu_fdt_add_subnode(fi->fdt, name->str);
736 qemu_fdt_setprop_cell(fi->fdt, name->str, "#interrupt-cells", 2);
737 qemu_fdt_setprop_cell(fi->fdt, name->str, "#size-cells", 0);
738 qemu_fdt_setprop_cell(fi->fdt, name->str, "#address-cells", 1);
739 qemu_fdt_setprop_string(fi->fdt, name->str, "interrupt-controller", "");
740 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
741 cells[0] = cpu_to_be32(1);
742 cells[1] = cpu_to_be32(0x60);
743 cells[2] = cpu_to_be32(5);
744 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
745 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "");
746 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "8042");
747
748 g_string_printf(name, "%s/serial@i2f8", fi->path);
749 qemu_fdt_add_subnode(fi->fdt, name->str);
750 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
751 cells[0] = cpu_to_be32(3);
752 cells[1] = 0;
753 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
754 cells, 2 * sizeof(cells[0]));
755 cells[0] = cpu_to_be32(1);
756 cells[1] = cpu_to_be32(0x2f8);
757 cells[2] = cpu_to_be32(8);
758 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
759 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "serial");
760 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "serial");
761
762 g_string_free(name, TRUE);
763 }
764
765 static struct {
766 const char *id;
767 const char *name;
768 void (*dtf)(PCIBus *bus, PCIDevice *d, FDTInfo *fi);
769 } device_map[] = {
770 { "pci11ab,6460", "host", NULL },
771 { "pci1106,8231", "isa", dt_isa },
772 { "pci1106,571", "ide", dt_ide },
773 { "pci1106,3044", "firewire", NULL },
774 { "pci1106,3038", "usb", dt_usb },
775 { "pci1106,8235", "other", NULL },
776 { "pci1106,3058", "sound", NULL },
777 { NULL, NULL }
778 };
779
add_pci_device(PCIBus * bus,PCIDevice * d,void * opaque)780 static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque)
781 {
782 FDTInfo *fi = opaque;
783 GString *node = g_string_new(NULL);
784 uint32_t cells[(PCI_NUM_REGIONS + 1) * 5];
785 int i, j;
786 const char *name = NULL;
787 g_autofree const gchar *pn = g_strdup_printf("pci%x,%x",
788 pci_get_word(&d->config[PCI_VENDOR_ID]),
789 pci_get_word(&d->config[PCI_DEVICE_ID]));
790
791 if (pci_get_word(&d->config[PCI_CLASS_DEVICE]) ==
792 PCI_CLASS_NETWORK_ETHERNET) {
793 name = "ethernet";
794 } else if (pci_get_word(&d->config[PCI_CLASS_DEVICE]) >> 8 ==
795 PCI_BASE_CLASS_DISPLAY) {
796 name = "display";
797 }
798 for (i = 0; device_map[i].id; i++) {
799 if (!strcmp(pn, device_map[i].id)) {
800 name = device_map[i].name;
801 break;
802 }
803 }
804 g_string_printf(node, "%s/%s@%x", fi->path, (name ?: pn),
805 PCI_SLOT(d->devfn));
806 if (PCI_FUNC(d->devfn)) {
807 g_string_append_printf(node, ",%x", PCI_FUNC(d->devfn));
808 }
809
810 qemu_fdt_add_subnode(fi->fdt, node->str);
811 if (device_map[i].dtf) {
812 FDTInfo cfi = { fi->fdt, node->str };
813 device_map[i].dtf(bus, d, &cfi);
814 }
815 cells[0] = cpu_to_be32(d->devfn << 8);
816 cells[1] = 0;
817 cells[2] = 0;
818 cells[3] = 0;
819 cells[4] = 0;
820 j = 5;
821 for (i = 0; i < PCI_NUM_REGIONS; i++) {
822 if (!d->io_regions[i].size) {
823 continue;
824 }
825 cells[j] = PCI_BASE_ADDRESS_0 + i * 4;
826 if (cells[j] == 0x28) {
827 cells[j] = 0x30;
828 }
829 cells[j] = cpu_to_be32(d->devfn << 8 | cells[j]);
830 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
831 cells[j] |= cpu_to_be32(1 << 24);
832 } else {
833 if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
834 cells[j] |= cpu_to_be32(3 << 24);
835 } else {
836 cells[j] |= cpu_to_be32(2 << 24);
837 }
838 if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
839 cells[j] |= cpu_to_be32(4 << 28);
840 }
841 }
842 cells[j + 1] = 0;
843 cells[j + 2] = 0;
844 cells[j + 3] = cpu_to_be32(d->io_regions[i].size >> 32);
845 cells[j + 4] = cpu_to_be32(d->io_regions[i].size);
846 j += 5;
847 }
848 qemu_fdt_setprop(fi->fdt, node->str, "reg", cells, j * sizeof(cells[0]));
849 qemu_fdt_setprop_string(fi->fdt, node->str, "name", name ?: pn);
850 if (pci_get_byte(&d->config[PCI_INTERRUPT_PIN])) {
851 qemu_fdt_setprop_cell(fi->fdt, node->str, "interrupts",
852 pci_get_byte(&d->config[PCI_INTERRUPT_PIN]));
853 }
854 /* Pegasos2 firmware has subsystem-id amd subsystem-vendor-id swapped */
855 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-vendor-id",
856 pci_get_word(&d->config[PCI_SUBSYSTEM_ID]));
857 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-id",
858 pci_get_word(&d->config[PCI_SUBSYSTEM_VENDOR_ID]));
859 cells[0] = pci_get_long(&d->config[PCI_CLASS_REVISION]);
860 qemu_fdt_setprop_cell(fi->fdt, node->str, "class-code", cells[0] >> 8);
861 qemu_fdt_setprop_cell(fi->fdt, node->str, "revision-id", cells[0] & 0xff);
862 qemu_fdt_setprop_cell(fi->fdt, node->str, "device-id",
863 pci_get_word(&d->config[PCI_DEVICE_ID]));
864 qemu_fdt_setprop_cell(fi->fdt, node->str, "vendor-id",
865 pci_get_word(&d->config[PCI_VENDOR_ID]));
866
867 g_string_free(node, TRUE);
868 }
869
build_fdt(MachineState * machine,int * fdt_size)870 static void *build_fdt(MachineState *machine, int *fdt_size)
871 {
872 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine);
873 PowerPCCPU *cpu = pm->cpu;
874 PCIBus *pci_bus;
875 FDTInfo fi;
876 uint32_t cells[16];
877 void *fdt = create_device_tree(fdt_size);
878
879 fi.fdt = fdt;
880
881 /* root node */
882 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,description",
883 "Pegasos CHRP PowerPC System");
884 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,board", "Pegasos2");
885 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,vendor", "bplan GmbH");
886 qemu_fdt_setprop_string(fdt, "/", "revision", "2B");
887 qemu_fdt_setprop_string(fdt, "/", "model", "Pegasos2");
888 qemu_fdt_setprop_string(fdt, "/", "device_type", "chrp");
889 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 1);
890 qemu_fdt_setprop_string(fdt, "/", "name", "bplan,Pegasos2");
891
892 /* pci@c0000000 */
893 qemu_fdt_add_subnode(fdt, "/pci@c0000000");
894 cells[0] = 0;
895 cells[1] = 0;
896 qemu_fdt_setprop(fdt, "/pci@c0000000", "bus-range",
897 cells, 2 * sizeof(cells[0]));
898 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "pci-bridge-number", 1);
899 cells[0] = cpu_to_be32(PCI0_MEM_BASE);
900 cells[1] = cpu_to_be32(PCI0_MEM_SIZE);
901 qemu_fdt_setprop(fdt, "/pci@c0000000", "reg", cells, 2 * sizeof(cells[0]));
902 cells[0] = cpu_to_be32(0x01000000);
903 cells[1] = 0;
904 cells[2] = 0;
905 cells[3] = cpu_to_be32(PCI0_IO_BASE);
906 cells[4] = 0;
907 cells[5] = cpu_to_be32(PCI0_IO_SIZE);
908 cells[6] = cpu_to_be32(0x02000000);
909 cells[7] = 0;
910 cells[8] = cpu_to_be32(PCI0_MEM_BASE);
911 cells[9] = cpu_to_be32(PCI0_MEM_BASE);
912 cells[10] = 0;
913 cells[11] = cpu_to_be32(PCI0_MEM_SIZE);
914 qemu_fdt_setprop(fdt, "/pci@c0000000", "ranges",
915 cells, 12 * sizeof(cells[0]));
916 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#size-cells", 2);
917 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#address-cells", 3);
918 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "device_type", "pci");
919 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "name", "pci");
920
921 fi.path = "/pci@c0000000";
922 pci_bus = mv64361_get_pci_bus(pm->mv, 0);
923 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi);
924
925 /* pci@80000000 */
926 qemu_fdt_add_subnode(fdt, "/pci@80000000");
927 cells[0] = 0;
928 cells[1] = 0;
929 qemu_fdt_setprop(fdt, "/pci@80000000", "bus-range",
930 cells, 2 * sizeof(cells[0]));
931 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "pci-bridge-number", 0);
932 cells[0] = cpu_to_be32(PCI1_MEM_BASE);
933 cells[1] = cpu_to_be32(PCI1_MEM_SIZE);
934 qemu_fdt_setprop(fdt, "/pci@80000000", "reg", cells, 2 * sizeof(cells[0]));
935 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "8259-interrupt-acknowledge",
936 0xf1000cb4);
937 cells[0] = cpu_to_be32(0x01000000);
938 cells[1] = 0;
939 cells[2] = 0;
940 cells[3] = cpu_to_be32(PCI1_IO_BASE);
941 cells[4] = 0;
942 cells[5] = cpu_to_be32(PCI1_IO_SIZE);
943 cells[6] = cpu_to_be32(0x02000000);
944 cells[7] = 0;
945 cells[8] = cpu_to_be32(PCI1_MEM_BASE);
946 cells[9] = cpu_to_be32(PCI1_MEM_BASE);
947 cells[10] = 0;
948 cells[11] = cpu_to_be32(PCI1_MEM_SIZE);
949 qemu_fdt_setprop(fdt, "/pci@80000000", "ranges",
950 cells, 12 * sizeof(cells[0]));
951 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#size-cells", 2);
952 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#address-cells", 3);
953 qemu_fdt_setprop_string(fdt, "/pci@80000000", "device_type", "pci");
954 qemu_fdt_setprop_string(fdt, "/pci@80000000", "name", "pci");
955
956 fi.path = "/pci@80000000";
957 pci_bus = mv64361_get_pci_bus(pm->mv, 1);
958 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi);
959
960 qemu_fdt_add_subnode(fdt, "/failsafe");
961 qemu_fdt_setprop_string(fdt, "/failsafe", "device_type", "serial");
962 qemu_fdt_setprop_string(fdt, "/failsafe", "name", "failsafe");
963
964 qemu_fdt_add_subnode(fdt, "/rtas");
965 qemu_fdt_setprop_cell(fdt, "/rtas", "system-reboot", RTAS_SYSTEM_REBOOT);
966 qemu_fdt_setprop_cell(fdt, "/rtas", "hibernate", RTAS_HIBERNATE);
967 qemu_fdt_setprop_cell(fdt, "/rtas", "suspend", RTAS_SUSPEND);
968 qemu_fdt_setprop_cell(fdt, "/rtas", "power-off", RTAS_POWER_OFF);
969 qemu_fdt_setprop_cell(fdt, "/rtas", "set-indicator", RTAS_SET_INDICATOR);
970 qemu_fdt_setprop_cell(fdt, "/rtas", "display-character",
971 RTAS_DISPLAY_CHARACTER);
972 qemu_fdt_setprop_cell(fdt, "/rtas", "write-pci-config",
973 RTAS_WRITE_PCI_CONFIG);
974 qemu_fdt_setprop_cell(fdt, "/rtas", "read-pci-config",
975 RTAS_READ_PCI_CONFIG);
976 /* Pegasos2 firmware misspells check-exception and guests use that */
977 qemu_fdt_setprop_cell(fdt, "/rtas", "check-execption",
978 RTAS_CHECK_EXCEPTION);
979 qemu_fdt_setprop_cell(fdt, "/rtas", "event-scan", RTAS_EVENT_SCAN);
980 qemu_fdt_setprop_cell(fdt, "/rtas", "set-time-of-day",
981 RTAS_SET_TIME_OF_DAY);
982 qemu_fdt_setprop_cell(fdt, "/rtas", "get-time-of-day",
983 RTAS_GET_TIME_OF_DAY);
984 qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-store", RTAS_NVRAM_STORE);
985 qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-fetch", RTAS_NVRAM_FETCH);
986 qemu_fdt_setprop_cell(fdt, "/rtas", "restart-rtas", RTAS_RESTART_RTAS);
987 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-error-log-max", 0);
988 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-event-scan-rate", 0);
989 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-display-device", 0);
990 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-size", 20);
991 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-version", 1);
992 qemu_fdt_setprop_string(fdt, "/rtas", "name", "rtas");
993
994 /* cpus */
995 qemu_fdt_add_subnode(fdt, "/cpus");
996 qemu_fdt_setprop_cell(fdt, "/cpus", "#cpus", 1);
997 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1);
998 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0);
999 qemu_fdt_setprop_string(fdt, "/cpus", "name", "cpus");
1000
1001 /* FIXME Get CPU name from CPU object */
1002 const char *cp = "/cpus/PowerPC,G4";
1003 qemu_fdt_add_subnode(fdt, cp);
1004 qemu_fdt_setprop_cell(fdt, cp, "l2cr", 0);
1005 qemu_fdt_setprop_cell(fdt, cp, "d-cache-size", 0x8000);
1006 qemu_fdt_setprop_cell(fdt, cp, "d-cache-block-size",
1007 cpu->env.dcache_line_size);
1008 qemu_fdt_setprop_cell(fdt, cp, "d-cache-line-size",
1009 cpu->env.dcache_line_size);
1010 qemu_fdt_setprop_cell(fdt, cp, "i-cache-size", 0x8000);
1011 qemu_fdt_setprop_cell(fdt, cp, "i-cache-block-size",
1012 cpu->env.icache_line_size);
1013 qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size",
1014 cpu->env.icache_line_size);
1015 if (ppc_is_split_tlb(cpu)) {
1016 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-sets", cpu->env.nb_ways);
1017 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-size", cpu->env.tlb_per_way);
1018 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-sets", cpu->env.nb_ways);
1019 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-size", cpu->env.tlb_per_way);
1020 qemu_fdt_setprop_string(fdt, cp, "tlb-split", "");
1021 }
1022 qemu_fdt_setprop_cell(fdt, cp, "tlb-sets", cpu->env.nb_ways);
1023 qemu_fdt_setprop_cell(fdt, cp, "tlb-size", cpu->env.nb_tlb);
1024 qemu_fdt_setprop_string(fdt, cp, "state", "running");
1025 if (cpu->env.insns_flags & PPC_ALTIVEC) {
1026 qemu_fdt_setprop_string(fdt, cp, "altivec", "");
1027 qemu_fdt_setprop_string(fdt, cp, "data-streams", "");
1028 }
1029 /*
1030 * FIXME What flags do data-streams, external-control and
1031 * performance-monitor depend on?
1032 */
1033 qemu_fdt_setprop_string(fdt, cp, "external-control", "");
1034 if (cpu->env.insns_flags & PPC_FLOAT_FSQRT) {
1035 qemu_fdt_setprop_string(fdt, cp, "general-purpose", "");
1036 }
1037 qemu_fdt_setprop_string(fdt, cp, "performance-monitor", "");
1038 if (cpu->env.insns_flags & PPC_FLOAT_FRES) {
1039 qemu_fdt_setprop_string(fdt, cp, "graphics", "");
1040 }
1041 qemu_fdt_setprop_cell(fdt, cp, "reservation-granule-size", 4);
1042 qemu_fdt_setprop_cell(fdt, cp, "timebase-frequency",
1043 cpu->env.tb_env->tb_freq);
1044 qemu_fdt_setprop_cell(fdt, cp, "bus-frequency", BUS_FREQ_HZ);
1045 qemu_fdt_setprop_cell(fdt, cp, "clock-frequency", BUS_FREQ_HZ * 7.5);
1046 qemu_fdt_setprop_cell(fdt, cp, "cpu-version", cpu->env.spr[SPR_PVR]);
1047 cells[0] = 0;
1048 cells[1] = 0;
1049 qemu_fdt_setprop(fdt, cp, "reg", cells, 2 * sizeof(cells[0]));
1050 qemu_fdt_setprop_string(fdt, cp, "device_type", "cpu");
1051 qemu_fdt_setprop_string(fdt, cp, "name", strrchr(cp, '/') + 1);
1052
1053 /* memory */
1054 qemu_fdt_add_subnode(fdt, "/memory@0");
1055 cells[0] = 0;
1056 cells[1] = cpu_to_be32(machine->ram_size);
1057 qemu_fdt_setprop(fdt, "/memory@0", "reg", cells, 2 * sizeof(cells[0]));
1058 qemu_fdt_setprop_string(fdt, "/memory@0", "device_type", "memory");
1059 qemu_fdt_setprop_string(fdt, "/memory@0", "name", "memory");
1060
1061 qemu_fdt_add_subnode(fdt, "/chosen");
1062 if (pm->initrd_addr && pm->initrd_size) {
1063 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
1064 pm->initrd_addr + pm->initrd_size);
1065 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
1066 pm->initrd_addr);
1067 }
1068 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
1069 machine->kernel_cmdline ?: "");
1070 qemu_fdt_setprop_string(fdt, "/chosen", "name", "chosen");
1071
1072 qemu_fdt_add_subnode(fdt, "/openprom");
1073 qemu_fdt_setprop_string(fdt, "/openprom", "model", "Pegasos2,1.1");
1074
1075 return fdt;
1076 }
1077