1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3 */
4
5 #include "dpu_hwio.h"
6 #include "dpu_hw_catalog.h"
7 #include "dpu_hw_lm.h"
8 #include "dpu_hw_sspp.h"
9 #include "dpu_kms.h"
10
11 #include "msm_mdss.h"
12
13 #include <drm/drm_file.h>
14 #include <drm/drm_managed.h>
15
16 #define DPU_FETCH_CONFIG_RESET_VALUE 0x00000087
17
18 /* SSPP registers */
19 #define SSPP_SRC_SIZE 0x00
20 #define SSPP_SRC_XY 0x08
21 #define SSPP_OUT_SIZE 0x0c
22 #define SSPP_OUT_XY 0x10
23 #define SSPP_SRC0_ADDR 0x14
24 #define SSPP_SRC1_ADDR 0x18
25 #define SSPP_SRC2_ADDR 0x1C
26 #define SSPP_SRC3_ADDR 0x20
27 #define SSPP_SRC_YSTRIDE0 0x24
28 #define SSPP_SRC_YSTRIDE1 0x28
29 #define SSPP_SRC_FORMAT 0x30
30 #define SSPP_SRC_UNPACK_PATTERN 0x34
31 #define SSPP_SRC_OP_MODE 0x38
32 #define SSPP_SRC_CONSTANT_COLOR 0x3c
33 #define SSPP_EXCL_REC_CTL 0x40
34 #define SSPP_UBWC_STATIC_CTRL 0x44
35 #define SSPP_FETCH_CONFIG 0x48
36 #define SSPP_DANGER_LUT 0x60
37 #define SSPP_SAFE_LUT 0x64
38 #define SSPP_CREQ_LUT 0x68
39 #define SSPP_QOS_CTRL 0x6C
40 #define SSPP_SRC_ADDR_SW_STATUS 0x70
41 #define SSPP_CREQ_LUT_0 0x74
42 #define SSPP_CREQ_LUT_1 0x78
43 #define SSPP_DECIMATION_CONFIG 0xB4
44 #define SSPP_SW_PIX_EXT_C0_LR 0x100
45 #define SSPP_SW_PIX_EXT_C0_TB 0x104
46 #define SSPP_SW_PIX_EXT_C0_REQ_PIXELS 0x108
47 #define SSPP_SW_PIX_EXT_C1C2_LR 0x110
48 #define SSPP_SW_PIX_EXT_C1C2_TB 0x114
49 #define SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS 0x118
50 #define SSPP_SW_PIX_EXT_C3_LR 0x120
51 #define SSPP_SW_PIX_EXT_C3_TB 0x124
52 #define SSPP_SW_PIX_EXT_C3_REQ_PIXELS 0x128
53 #define SSPP_TRAFFIC_SHAPER 0x130
54 #define SSPP_CDP_CNTL 0x134
55 #define SSPP_UBWC_ERROR_STATUS 0x138
56 #define SSPP_CDP_CNTL_REC1 0x13c
57 #define SSPP_TRAFFIC_SHAPER_PREFILL 0x150
58 #define SSPP_TRAFFIC_SHAPER_REC1_PREFILL 0x154
59 #define SSPP_TRAFFIC_SHAPER_REC1 0x158
60 #define SSPP_OUT_SIZE_REC1 0x160
61 #define SSPP_OUT_XY_REC1 0x164
62 #define SSPP_SRC_XY_REC1 0x168
63 #define SSPP_SRC_SIZE_REC1 0x16C
64 #define SSPP_MULTIRECT_OPMODE 0x170
65 #define SSPP_SRC_FORMAT_REC1 0x174
66 #define SSPP_SRC_UNPACK_PATTERN_REC1 0x178
67 #define SSPP_SRC_OP_MODE_REC1 0x17C
68 #define SSPP_SRC_CONSTANT_COLOR_REC1 0x180
69 #define SSPP_EXCL_REC_SIZE_REC1 0x184
70 #define SSPP_EXCL_REC_XY_REC1 0x188
71 #define SSPP_EXCL_REC_SIZE 0x1B4
72 #define SSPP_EXCL_REC_XY 0x1B8
73 #define SSPP_CLK_CTRL 0x330
74
75 /* SSPP_SRC_OP_MODE & OP_MODE_REC1 */
76 #define MDSS_MDP_OP_DEINTERLACE BIT(22)
77 #define MDSS_MDP_OP_DEINTERLACE_ODD BIT(23)
78 #define MDSS_MDP_OP_IGC_ROM_1 BIT(18)
79 #define MDSS_MDP_OP_IGC_ROM_0 BIT(17)
80 #define MDSS_MDP_OP_IGC_EN BIT(16)
81 #define MDSS_MDP_OP_FLIP_UD BIT(14)
82 #define MDSS_MDP_OP_FLIP_LR BIT(13)
83 #define MDSS_MDP_OP_BWC_EN BIT(0)
84 #define MDSS_MDP_OP_PE_OVERRIDE BIT(31)
85 #define MDSS_MDP_OP_BWC_LOSSLESS (0 << 1)
86 #define MDSS_MDP_OP_BWC_Q_HIGH (1 << 1)
87 #define MDSS_MDP_OP_BWC_Q_MED (2 << 1)
88
89 /* SSPP_QOS_CTRL */
90 #define SSPP_QOS_CTRL_VBLANK_EN BIT(16)
91 #define SSPP_QOS_CTRL_DANGER_SAFE_EN BIT(0)
92 #define SSPP_QOS_CTRL_DANGER_VBLANK_MASK 0x3
93 #define SSPP_QOS_CTRL_DANGER_VBLANK_OFF 4
94 #define SSPP_QOS_CTRL_CREQ_VBLANK_MASK 0x3
95 #define SSPP_QOS_CTRL_CREQ_VBLANK_OFF 20
96
97 /* DPU_SSPP_SCALER_QSEED2 */
98 #define SSPP_VIG_OP_MODE 0x0
99 #define SCALE_CONFIG 0x04
100 #define COMP0_3_PHASE_STEP_X 0x10
101 #define COMP0_3_PHASE_STEP_Y 0x14
102 #define COMP1_2_PHASE_STEP_X 0x18
103 #define COMP1_2_PHASE_STEP_Y 0x1c
104 #define COMP0_3_INIT_PHASE_X 0x20
105 #define COMP0_3_INIT_PHASE_Y 0x24
106 #define COMP1_2_INIT_PHASE_X 0x28
107 #define COMP1_2_INIT_PHASE_Y 0x2C
108 #define VIG_0_QSEED2_SHARP 0x30
109
110 /* SSPP_TRAFFIC_SHAPER and _REC1 */
111 #define SSPP_TRAFFIC_SHAPER_BPC_MAX 0xFF
112
113 /*
114 * Definitions for ViG op modes
115 */
116 #define VIG_OP_CSC_DST_DATAFMT BIT(19)
117 #define VIG_OP_CSC_SRC_DATAFMT BIT(18)
118 #define VIG_OP_CSC_EN BIT(17)
119 #define VIG_OP_MEM_PROT_CONT BIT(15)
120 #define VIG_OP_MEM_PROT_VAL BIT(14)
121 #define VIG_OP_MEM_PROT_SAT BIT(13)
122 #define VIG_OP_MEM_PROT_HUE BIT(12)
123 #define VIG_OP_HIST BIT(8)
124 #define VIG_OP_SKY_COL BIT(7)
125 #define VIG_OP_FOIL BIT(6)
126 #define VIG_OP_SKIN_COL BIT(5)
127 #define VIG_OP_PA_EN BIT(4)
128 #define VIG_OP_PA_SAT_ZERO_EXP BIT(2)
129 #define VIG_OP_MEM_PROT_BLEND BIT(1)
130
131 /*
132 * Definitions for CSC 10 op modes
133 */
134 #define SSPP_VIG_CSC_10_OP_MODE 0x0
135 #define VIG_CSC_10_SRC_DATAFMT BIT(1)
136 #define VIG_CSC_10_EN BIT(0)
137 #define CSC_10BIT_OFFSET 4
138
139 /* traffic shaper clock in Hz */
140 #define TS_CLK 19200000
141
142
dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe * pipe)143 static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe)
144 {
145 struct dpu_hw_sspp *ctx = pipe->sspp;
146 u32 mode_mask;
147
148 if (!ctx)
149 return;
150
151 if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
152 /**
153 * if rect index is RECT_SOLO, we cannot expect a
154 * virtual plane sharing the same SSPP id. So we go
155 * and disable multirect
156 */
157 mode_mask = 0;
158 } else {
159 mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE);
160 mode_mask |= pipe->multirect_index;
161 if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_TIME_MX)
162 mode_mask |= BIT(2);
163 else
164 mode_mask &= ~BIT(2);
165 }
166
167 DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE, mode_mask);
168 }
169
_sspp_setup_opmode(struct dpu_hw_sspp * ctx,u32 mask,u8 en)170 static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx,
171 u32 mask, u8 en)
172 {
173 const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk;
174 u32 opmode;
175
176 if (!test_bit(DPU_SSPP_SCALER_QSEED2, &ctx->cap->features) ||
177 !test_bit(DPU_SSPP_CSC, &ctx->cap->features))
178 return;
179
180 opmode = DPU_REG_READ(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE);
181
182 if (en)
183 opmode |= mask;
184 else
185 opmode &= ~mask;
186
187 DPU_REG_WRITE(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE, opmode);
188 }
189
_sspp_setup_csc10_opmode(struct dpu_hw_sspp * ctx,u32 mask,u8 en)190 static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
191 u32 mask, u8 en)
192 {
193 const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk;
194 u32 opmode;
195
196 opmode = DPU_REG_READ(&ctx->hw, sblk->csc_blk.base + SSPP_VIG_CSC_10_OP_MODE);
197 if (en)
198 opmode |= mask;
199 else
200 opmode &= ~mask;
201
202 DPU_REG_WRITE(&ctx->hw, sblk->csc_blk.base + SSPP_VIG_CSC_10_OP_MODE, opmode);
203 }
204
205 /*
206 * Setup source pixel format, flip,
207 */
dpu_hw_sspp_setup_format(struct dpu_sw_pipe * pipe,const struct dpu_format * fmt,u32 flags)208 static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
209 const struct dpu_format *fmt, u32 flags)
210 {
211 struct dpu_hw_sspp *ctx = pipe->sspp;
212 struct dpu_hw_blk_reg_map *c;
213 u32 chroma_samp, unpack, src_format;
214 u32 opmode = 0;
215 u32 fast_clear = 0;
216 u32 op_mode_off, unpack_pat_off, format_off;
217
218 if (!ctx || !fmt)
219 return;
220
221 if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
222 pipe->multirect_index == DPU_SSPP_RECT_0) {
223 op_mode_off = SSPP_SRC_OP_MODE;
224 unpack_pat_off = SSPP_SRC_UNPACK_PATTERN;
225 format_off = SSPP_SRC_FORMAT;
226 } else {
227 op_mode_off = SSPP_SRC_OP_MODE_REC1;
228 unpack_pat_off = SSPP_SRC_UNPACK_PATTERN_REC1;
229 format_off = SSPP_SRC_FORMAT_REC1;
230 }
231
232 c = &ctx->hw;
233 opmode = DPU_REG_READ(c, op_mode_off);
234 opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD |
235 MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE);
236
237 if (flags & DPU_SSPP_FLIP_LR)
238 opmode |= MDSS_MDP_OP_FLIP_LR;
239 if (flags & DPU_SSPP_FLIP_UD)
240 opmode |= MDSS_MDP_OP_FLIP_UD;
241
242 chroma_samp = fmt->chroma_sample;
243 if (flags & DPU_SSPP_SOURCE_ROTATED_90) {
244 if (chroma_samp == DPU_CHROMA_H2V1)
245 chroma_samp = DPU_CHROMA_H1V2;
246 else if (chroma_samp == DPU_CHROMA_H1V2)
247 chroma_samp = DPU_CHROMA_H2V1;
248 }
249
250 src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) |
251 (fmt->bits[C3_ALPHA] << 6) | (fmt->bits[C2_R_Cr] << 4) |
252 (fmt->bits[C1_B_Cb] << 2) | (fmt->bits[C0_G_Y] << 0);
253
254 if (flags & DPU_SSPP_ROT_90)
255 src_format |= BIT(11); /* ROT90 */
256
257 if (fmt->alpha_enable && fmt->fetch_planes == DPU_PLANE_INTERLEAVED)
258 src_format |= BIT(8); /* SRCC3_EN */
259
260 if (flags & DPU_SSPP_SOLID_FILL)
261 src_format |= BIT(22);
262
263 unpack = (fmt->element[3] << 24) | (fmt->element[2] << 16) |
264 (fmt->element[1] << 8) | (fmt->element[0] << 0);
265 src_format |= ((fmt->unpack_count - 1) << 12) |
266 (fmt->unpack_tight << 17) |
267 (fmt->unpack_align_msb << 18) |
268 ((fmt->bpp - 1) << 9);
269
270 if (fmt->fetch_mode != DPU_FETCH_LINEAR) {
271 if (DPU_FORMAT_IS_UBWC(fmt))
272 opmode |= MDSS_MDP_OP_BWC_EN;
273 src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
274 DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
275 DPU_FETCH_CONFIG_RESET_VALUE |
276 ctx->ubwc->highest_bank_bit << 18);
277 switch (ctx->ubwc->ubwc_enc_version) {
278 case UBWC_1_0:
279 fast_clear = fmt->alpha_enable ? BIT(31) : 0;
280 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
281 fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
282 BIT(8) |
283 (ctx->ubwc->highest_bank_bit << 4));
284 break;
285 case UBWC_2_0:
286 fast_clear = fmt->alpha_enable ? BIT(31) : 0;
287 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
288 fast_clear | (ctx->ubwc->ubwc_swizzle) |
289 (ctx->ubwc->highest_bank_bit << 4));
290 break;
291 case UBWC_3_0:
292 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
293 BIT(30) | (ctx->ubwc->ubwc_swizzle) |
294 (ctx->ubwc->highest_bank_bit << 4));
295 break;
296 case UBWC_4_0:
297 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
298 DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
299 break;
300 }
301 }
302
303 opmode |= MDSS_MDP_OP_PE_OVERRIDE;
304
305 /* if this is YUV pixel format, enable CSC */
306 if (DPU_FORMAT_IS_YUV(fmt))
307 src_format |= BIT(15);
308
309 if (DPU_FORMAT_IS_DX(fmt))
310 src_format |= BIT(14);
311
312 /* update scaler opmode, if appropriate */
313 if (test_bit(DPU_SSPP_CSC, &ctx->cap->features))
314 _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
315 DPU_FORMAT_IS_YUV(fmt));
316 else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features))
317 _sspp_setup_csc10_opmode(ctx,
318 VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
319 DPU_FORMAT_IS_YUV(fmt));
320
321 DPU_REG_WRITE(c, format_off, src_format);
322 DPU_REG_WRITE(c, unpack_pat_off, unpack);
323 DPU_REG_WRITE(c, op_mode_off, opmode);
324
325 /* clear previous UBWC error */
326 DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31));
327 }
328
dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp * ctx,struct dpu_hw_pixel_ext * pe_ext)329 static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
330 struct dpu_hw_pixel_ext *pe_ext)
331 {
332 struct dpu_hw_blk_reg_map *c;
333 u8 color;
334 u32 lr_pe[4], tb_pe[4], tot_req_pixels[4];
335 const u32 bytemask = 0xff;
336 const u32 shortmask = 0xffff;
337
338 if (!ctx || !pe_ext)
339 return;
340
341 c = &ctx->hw;
342
343 /* program SW pixel extension override for all pipes*/
344 for (color = 0; color < DPU_MAX_PLANES; color++) {
345 /* color 2 has the same set of registers as color 1 */
346 if (color == 2)
347 continue;
348
349 lr_pe[color] = ((pe_ext->right_ftch[color] & bytemask) << 24)|
350 ((pe_ext->right_rpt[color] & bytemask) << 16)|
351 ((pe_ext->left_ftch[color] & bytemask) << 8)|
352 (pe_ext->left_rpt[color] & bytemask);
353
354 tb_pe[color] = ((pe_ext->btm_ftch[color] & bytemask) << 24)|
355 ((pe_ext->btm_rpt[color] & bytemask) << 16)|
356 ((pe_ext->top_ftch[color] & bytemask) << 8)|
357 (pe_ext->top_rpt[color] & bytemask);
358
359 tot_req_pixels[color] = (((pe_ext->roi_h[color] +
360 pe_ext->num_ext_pxls_top[color] +
361 pe_ext->num_ext_pxls_btm[color]) & shortmask) << 16) |
362 ((pe_ext->roi_w[color] +
363 pe_ext->num_ext_pxls_left[color] +
364 pe_ext->num_ext_pxls_right[color]) & shortmask);
365 }
366
367 /* color 0 */
368 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_LR, lr_pe[0]);
369 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_TB, tb_pe[0]);
370 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_REQ_PIXELS,
371 tot_req_pixels[0]);
372
373 /* color 1 and color 2 */
374 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_LR, lr_pe[1]);
375 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_TB, tb_pe[1]);
376 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS,
377 tot_req_pixels[1]);
378
379 /* color 3 */
380 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_LR, lr_pe[3]);
381 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_TB, lr_pe[3]);
382 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_REQ_PIXELS,
383 tot_req_pixels[3]);
384 }
385
_dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp * ctx,struct dpu_hw_scaler3_cfg * scaler3_cfg,const struct dpu_format * format)386 static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
387 struct dpu_hw_scaler3_cfg *scaler3_cfg,
388 const struct dpu_format *format)
389 {
390 if (!ctx || !scaler3_cfg)
391 return;
392
393 dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg,
394 ctx->cap->sblk->scaler_blk.base,
395 ctx->cap->sblk->scaler_blk.version,
396 format);
397 }
398
399 /*
400 * dpu_hw_sspp_setup_rects()
401 */
dpu_hw_sspp_setup_rects(struct dpu_sw_pipe * pipe,struct dpu_sw_pipe_cfg * cfg)402 static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
403 struct dpu_sw_pipe_cfg *cfg)
404 {
405 struct dpu_hw_sspp *ctx = pipe->sspp;
406 struct dpu_hw_blk_reg_map *c;
407 u32 src_size, src_xy, dst_size, dst_xy;
408 u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
409
410 if (!ctx || !cfg)
411 return;
412
413 c = &ctx->hw;
414
415 if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
416 pipe->multirect_index == DPU_SSPP_RECT_0) {
417 src_size_off = SSPP_SRC_SIZE;
418 src_xy_off = SSPP_SRC_XY;
419 out_size_off = SSPP_OUT_SIZE;
420 out_xy_off = SSPP_OUT_XY;
421 } else {
422 src_size_off = SSPP_SRC_SIZE_REC1;
423 src_xy_off = SSPP_SRC_XY_REC1;
424 out_size_off = SSPP_OUT_SIZE_REC1;
425 out_xy_off = SSPP_OUT_XY_REC1;
426 }
427
428
429 /* src and dest rect programming */
430 src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1;
431 src_size = (drm_rect_height(&cfg->src_rect) << 16) |
432 drm_rect_width(&cfg->src_rect);
433 dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1;
434 dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
435 drm_rect_width(&cfg->dst_rect);
436
437 /* rectangle register programming */
438 DPU_REG_WRITE(c, src_size_off, src_size);
439 DPU_REG_WRITE(c, src_xy_off, src_xy);
440 DPU_REG_WRITE(c, out_size_off, dst_size);
441 DPU_REG_WRITE(c, out_xy_off, dst_xy);
442 }
443
dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe * pipe,struct dpu_hw_fmt_layout * layout)444 static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
445 struct dpu_hw_fmt_layout *layout)
446 {
447 struct dpu_hw_sspp *ctx = pipe->sspp;
448 u32 ystride0, ystride1;
449 int i;
450
451 if (!ctx)
452 return;
453
454 if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
455 for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++)
456 DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + i * 0x4,
457 layout->plane_addr[i]);
458 } else if (pipe->multirect_index == DPU_SSPP_RECT_0) {
459 DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR,
460 layout->plane_addr[0]);
461 DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR,
462 layout->plane_addr[2]);
463 } else {
464 DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR,
465 layout->plane_addr[0]);
466 DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR,
467 layout->plane_addr[2]);
468 }
469
470 if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
471 ystride0 = (layout->plane_pitch[0]) |
472 (layout->plane_pitch[1] << 16);
473 ystride1 = (layout->plane_pitch[2]) |
474 (layout->plane_pitch[3] << 16);
475 } else {
476 ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0);
477 ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1);
478
479 if (pipe->multirect_index == DPU_SSPP_RECT_0) {
480 ystride0 = (ystride0 & 0xFFFF0000) |
481 (layout->plane_pitch[0] & 0x0000FFFF);
482 ystride1 = (ystride1 & 0xFFFF0000)|
483 (layout->plane_pitch[2] & 0x0000FFFF);
484 } else {
485 ystride0 = (ystride0 & 0x0000FFFF) |
486 ((layout->plane_pitch[0] << 16) &
487 0xFFFF0000);
488 ystride1 = (ystride1 & 0x0000FFFF) |
489 ((layout->plane_pitch[2] << 16) &
490 0xFFFF0000);
491 }
492 }
493
494 DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE0, ystride0);
495 DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1, ystride1);
496 }
497
dpu_hw_sspp_setup_csc(struct dpu_hw_sspp * ctx,const struct dpu_csc_cfg * data)498 static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
499 const struct dpu_csc_cfg *data)
500 {
501 u32 offset;
502 bool csc10 = false;
503
504 if (!ctx || !data)
505 return;
506
507 offset = ctx->cap->sblk->csc_blk.base;
508
509 if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features)) {
510 offset += CSC_10BIT_OFFSET;
511 csc10 = true;
512 }
513
514 dpu_hw_csc_setup(&ctx->hw, offset, data, csc10);
515 }
516
dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe * pipe,u32 color)517 static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color)
518 {
519 struct dpu_hw_sspp *ctx = pipe->sspp;
520 struct dpu_hw_fmt_layout cfg;
521
522 if (!ctx)
523 return;
524
525 /* cleanup source addresses */
526 memset(&cfg, 0, sizeof(cfg));
527 ctx->ops.setup_sourceaddress(pipe, &cfg);
528
529 if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
530 pipe->multirect_index == DPU_SSPP_RECT_0)
531 DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR, color);
532 else
533 DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1,
534 color);
535 }
536
dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp * ctx,struct dpu_hw_qos_cfg * cfg)537 static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx,
538 struct dpu_hw_qos_cfg *cfg)
539 {
540 if (!ctx || !cfg)
541 return;
542
543 _dpu_hw_setup_qos_lut(&ctx->hw, SSPP_DANGER_LUT,
544 test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features),
545 cfg);
546 }
547
dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp * ctx,bool danger_safe_en)548 static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
549 bool danger_safe_en)
550 {
551 if (!ctx)
552 return;
553
554 DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL,
555 danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0);
556 }
557
dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe * pipe,const struct dpu_format * fmt,bool enable)558 static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
559 const struct dpu_format *fmt,
560 bool enable)
561 {
562 struct dpu_hw_sspp *ctx = pipe->sspp;
563 u32 cdp_cntl_offset = 0;
564
565 if (!ctx)
566 return;
567
568 if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
569 pipe->multirect_index == DPU_SSPP_RECT_0)
570 cdp_cntl_offset = SSPP_CDP_CNTL;
571 else
572 cdp_cntl_offset = SSPP_CDP_CNTL_REC1;
573
574 dpu_setup_cdp(&ctx->hw, cdp_cntl_offset, fmt, enable);
575 }
576
dpu_hw_sspp_setup_clk_force_ctrl(struct dpu_hw_sspp * ctx,bool enable)577 static bool dpu_hw_sspp_setup_clk_force_ctrl(struct dpu_hw_sspp *ctx, bool enable)
578 {
579 static const struct dpu_clk_ctrl_reg sspp_clk_ctrl = {
580 .reg_off = SSPP_CLK_CTRL,
581 .bit_off = 0
582 };
583
584 return dpu_hw_clk_force_ctrl(&ctx->hw, &sspp_clk_ctrl, enable);
585 }
586
_setup_layer_ops(struct dpu_hw_sspp * c,unsigned long features,const struct dpu_mdss_version * mdss_rev)587 static void _setup_layer_ops(struct dpu_hw_sspp *c,
588 unsigned long features, const struct dpu_mdss_version *mdss_rev)
589 {
590 c->ops.setup_format = dpu_hw_sspp_setup_format;
591 c->ops.setup_rects = dpu_hw_sspp_setup_rects;
592 c->ops.setup_sourceaddress = dpu_hw_sspp_setup_sourceaddress;
593 c->ops.setup_solidfill = dpu_hw_sspp_setup_solidfill;
594 c->ops.setup_pe = dpu_hw_sspp_setup_pe_config;
595
596 if (test_bit(DPU_SSPP_QOS, &features)) {
597 c->ops.setup_qos_lut = dpu_hw_sspp_setup_qos_lut;
598 c->ops.setup_qos_ctrl = dpu_hw_sspp_setup_qos_ctrl;
599 }
600
601 if (test_bit(DPU_SSPP_CSC, &features) ||
602 test_bit(DPU_SSPP_CSC_10BIT, &features))
603 c->ops.setup_csc = dpu_hw_sspp_setup_csc;
604
605 if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) ||
606 test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features))
607 c->ops.setup_multirect = dpu_hw_sspp_setup_multirect;
608
609 if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &features))
610 c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3;
611
612 if (test_bit(DPU_SSPP_CDP, &features))
613 c->ops.setup_cdp = dpu_hw_sspp_setup_cdp;
614
615 if (mdss_rev->core_major_ver >= 9)
616 c->ops.setup_clk_force_ctrl = dpu_hw_sspp_setup_clk_force_ctrl;
617 }
618
619 #ifdef CONFIG_DEBUG_FS
_dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp * hw_pipe,struct dpu_kms * kms,struct dentry * entry)620 int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,
621 struct dentry *entry)
622 {
623 const struct dpu_sspp_cfg *cfg = hw_pipe->cap;
624 const struct dpu_sspp_sub_blks *sblk = cfg->sblk;
625 struct dentry *debugfs_root;
626 char sspp_name[32];
627
628 snprintf(sspp_name, sizeof(sspp_name), "%d", hw_pipe->idx);
629
630 /* create overall sub-directory for the pipe */
631 debugfs_root =
632 debugfs_create_dir(sspp_name, entry);
633
634 /* don't error check these */
635 debugfs_create_xul("features", 0600,
636 debugfs_root, (unsigned long *)&hw_pipe->cap->features);
637
638 /* add register dump support */
639 dpu_debugfs_create_regset32("src_blk", 0400,
640 debugfs_root,
641 cfg->base,
642 cfg->len,
643 kms);
644
645 if (sblk->scaler_blk.len)
646 dpu_debugfs_create_regset32("scaler_blk", 0400,
647 debugfs_root,
648 sblk->scaler_blk.base + cfg->base,
649 sblk->scaler_blk.len,
650 kms);
651
652 if (cfg->features & BIT(DPU_SSPP_CSC) ||
653 cfg->features & BIT(DPU_SSPP_CSC_10BIT))
654 dpu_debugfs_create_regset32("csc_blk", 0400,
655 debugfs_root,
656 sblk->csc_blk.base + cfg->base,
657 sblk->csc_blk.len,
658 kms);
659
660 debugfs_create_u32("xin_id",
661 0400,
662 debugfs_root,
663 (u32 *) &cfg->xin_id);
664 debugfs_create_u32("clk_ctrl",
665 0400,
666 debugfs_root,
667 (u32 *) &cfg->clk_ctrl);
668
669 return 0;
670 }
671 #endif
672
dpu_hw_sspp_init(struct drm_device * dev,const struct dpu_sspp_cfg * cfg,void __iomem * addr,const struct msm_mdss_data * mdss_data,const struct dpu_mdss_version * mdss_rev)673 struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev,
674 const struct dpu_sspp_cfg *cfg,
675 void __iomem *addr,
676 const struct msm_mdss_data *mdss_data,
677 const struct dpu_mdss_version *mdss_rev)
678 {
679 struct dpu_hw_sspp *hw_pipe;
680
681 if (!addr)
682 return ERR_PTR(-EINVAL);
683
684 hw_pipe = drmm_kzalloc(dev, sizeof(*hw_pipe), GFP_KERNEL);
685 if (!hw_pipe)
686 return ERR_PTR(-ENOMEM);
687
688 hw_pipe->hw.blk_addr = addr + cfg->base;
689 hw_pipe->hw.log_mask = DPU_DBG_MASK_SSPP;
690
691 /* Assign ops */
692 hw_pipe->ubwc = mdss_data;
693 hw_pipe->idx = cfg->id;
694 hw_pipe->cap = cfg;
695 _setup_layer_ops(hw_pipe, hw_pipe->cap->features, mdss_rev);
696
697 return hw_pipe;
698 }
699