1 /*
2 * pcie_sriov.c:
3 *
4 * Implementation of SR/IOV emulation support.
5 *
6 * Copyright (c) 2015-2017 Knut Omang <knut.omang@oracle.com>
7 *
8 * This work is licensed under the terms of the GNU GPL, version 2 or later.
9 * See the COPYING file in the top-level directory.
10 *
11 */
12
13 #include "qemu/osdep.h"
14 #include "hw/pci/pci_device.h"
15 #include "hw/pci/pcie.h"
16 #include "hw/pci/pci_bus.h"
17 #include "hw/qdev-properties.h"
18 #include "qemu/range.h"
19 #include "qapi/error.h"
20 #include "trace.h"
21
22 static GHashTable *pfs;
23
unparent_vfs(PCIDevice * dev,uint16_t total_vfs)24 static void unparent_vfs(PCIDevice *dev, uint16_t total_vfs)
25 {
26 for (uint16_t i = 0; i < total_vfs; i++) {
27 PCIDevice *vf = dev->exp.sriov_pf.vf[i];
28 object_unparent(OBJECT(vf));
29 object_unref(OBJECT(vf));
30 }
31 g_free(dev->exp.sriov_pf.vf);
32 dev->exp.sriov_pf.vf = NULL;
33 }
34
register_vfs(PCIDevice * dev)35 static void register_vfs(PCIDevice *dev)
36 {
37 uint16_t num_vfs;
38 uint16_t i;
39 uint16_t sriov_cap = dev->exp.sriov_cap;
40
41 assert(sriov_cap > 0);
42 num_vfs = pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF);
43
44 trace_sriov_register_vfs(dev->name, PCI_SLOT(dev->devfn),
45 PCI_FUNC(dev->devfn), num_vfs);
46 for (i = 0; i < num_vfs; i++) {
47 pci_set_enabled(dev->exp.sriov_pf.vf[i], true);
48 }
49
50 pci_set_word(dev->wmask + sriov_cap + PCI_SRIOV_NUM_VF, 0);
51 }
52
unregister_vfs(PCIDevice * dev)53 static void unregister_vfs(PCIDevice *dev)
54 {
55 uint8_t *cfg = dev->config + dev->exp.sriov_cap;
56 uint16_t i;
57
58 trace_sriov_unregister_vfs(dev->name, PCI_SLOT(dev->devfn),
59 PCI_FUNC(dev->devfn));
60 for (i = 0; i < pci_get_word(cfg + PCI_SRIOV_TOTAL_VF); i++) {
61 pci_set_enabled(dev->exp.sriov_pf.vf[i], false);
62 }
63
64 pci_set_word(dev->wmask + dev->exp.sriov_cap + PCI_SRIOV_NUM_VF, 0xffff);
65 }
66
pcie_sriov_pf_init_common(PCIDevice * dev,uint16_t offset,uint16_t vf_dev_id,uint16_t init_vfs,uint16_t total_vfs,uint16_t vf_offset,uint16_t vf_stride,Error ** errp)67 static bool pcie_sriov_pf_init_common(PCIDevice *dev, uint16_t offset,
68 uint16_t vf_dev_id, uint16_t init_vfs,
69 uint16_t total_vfs, uint16_t vf_offset,
70 uint16_t vf_stride, Error **errp)
71 {
72 int32_t devfn = dev->devfn + vf_offset;
73 uint8_t *cfg = dev->config + offset;
74 uint8_t *wmask;
75
76 if (!pci_is_express(dev)) {
77 error_setg(errp, "PCI Express is required for SR-IOV PF");
78 return false;
79 }
80
81 if (pci_is_vf(dev)) {
82 error_setg(errp, "a device cannot be a SR-IOV PF and a VF at the same time");
83 return false;
84 }
85
86 if (total_vfs &&
87 (uint32_t)devfn + (uint32_t)(total_vfs - 1) * vf_stride >= PCI_DEVFN_MAX) {
88 error_setg(errp, "VF addr overflows");
89 return false;
90 }
91
92 pcie_add_capability(dev, PCI_EXT_CAP_ID_SRIOV, 1,
93 offset, PCI_EXT_CAP_SRIOV_SIZEOF);
94 dev->exp.sriov_cap = offset;
95 dev->exp.sriov_pf.vf = NULL;
96
97 pci_set_word(cfg + PCI_SRIOV_VF_OFFSET, vf_offset);
98 pci_set_word(cfg + PCI_SRIOV_VF_STRIDE, vf_stride);
99
100 /*
101 * Mandatory page sizes to support.
102 * Device implementations can call pcie_sriov_pf_add_sup_pgsize()
103 * to set more bits:
104 */
105 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, SRIOV_SUP_PGSIZE_MINREQ);
106
107 /*
108 * Default is to use 4K pages, software can modify it
109 * to any of the supported bits
110 */
111 pci_set_word(cfg + PCI_SRIOV_SYS_PGSIZE, 0x1);
112
113 /* Set up device ID and initial/total number of VFs available */
114 pci_set_word(cfg + PCI_SRIOV_VF_DID, vf_dev_id);
115 pci_set_word(cfg + PCI_SRIOV_INITIAL_VF, init_vfs);
116 pci_set_word(cfg + PCI_SRIOV_TOTAL_VF, total_vfs);
117 pci_set_word(cfg + PCI_SRIOV_NUM_VF, 0);
118
119 /* Write enable control bits */
120 wmask = dev->wmask + offset;
121 pci_set_word(wmask + PCI_SRIOV_CTRL,
122 PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI);
123 pci_set_word(wmask + PCI_SRIOV_NUM_VF, 0xffff);
124 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, 0x553);
125
126 qdev_prop_set_bit(&dev->qdev, "multifunction", true);
127
128 return true;
129 }
130
pcie_sriov_pf_init(PCIDevice * dev,uint16_t offset,const char * vfname,uint16_t vf_dev_id,uint16_t init_vfs,uint16_t total_vfs,uint16_t vf_offset,uint16_t vf_stride,Error ** errp)131 bool pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset,
132 const char *vfname, uint16_t vf_dev_id,
133 uint16_t init_vfs, uint16_t total_vfs,
134 uint16_t vf_offset, uint16_t vf_stride,
135 Error **errp)
136 {
137 BusState *bus = qdev_get_parent_bus(&dev->qdev);
138 int32_t devfn = dev->devfn + vf_offset;
139
140 if (pfs && g_hash_table_contains(pfs, dev->qdev.id)) {
141 error_setg(errp, "attaching user-created SR-IOV VF unsupported");
142 return false;
143 }
144
145 if (!pcie_sriov_pf_init_common(dev, offset, vf_dev_id, init_vfs,
146 total_vfs, vf_offset, vf_stride, errp)) {
147 return false;
148 }
149
150 dev->exp.sriov_pf.vf = g_new(PCIDevice *, total_vfs);
151
152 for (uint16_t i = 0; i < total_vfs; i++) {
153 PCIDevice *vf = pci_new(devfn, vfname);
154 vf->exp.sriov_vf.pf = dev;
155 vf->exp.sriov_vf.vf_number = i;
156
157 if (!qdev_realize(&vf->qdev, bus, errp)) {
158 object_unparent(OBJECT(vf));
159 object_unref(vf);
160 unparent_vfs(dev, i);
161 return false;
162 }
163
164 /* set vid/did according to sr/iov spec - they are not used */
165 pci_config_set_vendor_id(vf->config, 0xffff);
166 pci_config_set_device_id(vf->config, 0xffff);
167
168 dev->exp.sriov_pf.vf[i] = vf;
169 devfn += vf_stride;
170 }
171
172 return true;
173 }
174
pcie_sriov_pf_exit(PCIDevice * dev)175 void pcie_sriov_pf_exit(PCIDevice *dev)
176 {
177 uint8_t *cfg = dev->config + dev->exp.sriov_cap;
178
179 if (dev->exp.sriov_pf.vf_user_created) {
180 uint16_t ven_id = pci_get_word(dev->config + PCI_VENDOR_ID);
181 uint16_t total_vfs = pci_get_word(dev->config + PCI_SRIOV_TOTAL_VF);
182 uint16_t vf_dev_id = pci_get_word(dev->config + PCI_SRIOV_VF_DID);
183
184 unregister_vfs(dev);
185
186 for (uint16_t i = 0; i < total_vfs; i++) {
187 dev->exp.sriov_pf.vf[i]->exp.sriov_vf.pf = NULL;
188
189 pci_config_set_vendor_id(dev->exp.sriov_pf.vf[i]->config, ven_id);
190 pci_config_set_device_id(dev->exp.sriov_pf.vf[i]->config, vf_dev_id);
191 }
192 } else {
193 unparent_vfs(dev, pci_get_word(cfg + PCI_SRIOV_TOTAL_VF));
194 }
195 }
196
pcie_sriov_pf_init_vf_bar(PCIDevice * dev,int region_num,uint8_t type,dma_addr_t size)197 void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int region_num,
198 uint8_t type, dma_addr_t size)
199 {
200 uint32_t addr;
201 uint64_t wmask;
202 uint16_t sriov_cap = dev->exp.sriov_cap;
203
204 assert(sriov_cap > 0);
205 assert(region_num >= 0);
206 assert(region_num < PCI_NUM_REGIONS);
207 assert(region_num != PCI_ROM_SLOT);
208
209 wmask = ~(size - 1);
210 addr = sriov_cap + PCI_SRIOV_BAR + region_num * 4;
211
212 pci_set_long(dev->config + addr, type);
213 if (!(type & PCI_BASE_ADDRESS_SPACE_IO) &&
214 type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
215 pci_set_quad(dev->wmask + addr, wmask);
216 pci_set_quad(dev->cmask + addr, ~0ULL);
217 } else {
218 pci_set_long(dev->wmask + addr, wmask & 0xffffffff);
219 pci_set_long(dev->cmask + addr, 0xffffffff);
220 }
221 dev->exp.sriov_pf.vf_bar_type[region_num] = type;
222 }
223
pcie_sriov_vf_register_bar(PCIDevice * dev,int region_num,MemoryRegion * memory)224 void pcie_sriov_vf_register_bar(PCIDevice *dev, int region_num,
225 MemoryRegion *memory)
226 {
227 uint8_t type;
228
229 assert(dev->exp.sriov_vf.pf);
230 type = dev->exp.sriov_vf.pf->exp.sriov_pf.vf_bar_type[region_num];
231
232 return pci_register_bar(dev, region_num, type, memory);
233 }
234
compare_vf_devfns(gconstpointer a,gconstpointer b)235 static gint compare_vf_devfns(gconstpointer a, gconstpointer b)
236 {
237 return (*(PCIDevice **)a)->devfn - (*(PCIDevice **)b)->devfn;
238 }
239
pcie_sriov_pf_init_from_user_created_vfs(PCIDevice * dev,uint16_t offset,Error ** errp)240 int16_t pcie_sriov_pf_init_from_user_created_vfs(PCIDevice *dev,
241 uint16_t offset,
242 Error **errp)
243 {
244 GPtrArray *pf;
245 PCIDevice **vfs;
246 BusState *bus = qdev_get_parent_bus(DEVICE(dev));
247 uint16_t ven_id = pci_get_word(dev->config + PCI_VENDOR_ID);
248 uint16_t size = PCI_EXT_CAP_SRIOV_SIZEOF;
249 uint16_t vf_dev_id;
250 uint16_t vf_offset;
251 uint16_t vf_stride;
252 uint16_t i;
253
254 if (!pfs || !dev->qdev.id) {
255 return 0;
256 }
257
258 pf = g_hash_table_lookup(pfs, dev->qdev.id);
259 if (!pf) {
260 return 0;
261 }
262
263 if (pf->len > UINT16_MAX) {
264 error_setg(errp, "too many VFs");
265 return -1;
266 }
267
268 g_ptr_array_sort(pf, compare_vf_devfns);
269 vfs = (void *)pf->pdata;
270
271 if (vfs[0]->devfn <= dev->devfn) {
272 error_setg(errp, "a VF function number is less than the PF function number");
273 return -1;
274 }
275
276 vf_dev_id = pci_get_word(vfs[0]->config + PCI_DEVICE_ID);
277 vf_offset = vfs[0]->devfn - dev->devfn;
278 vf_stride = pf->len < 2 ? 0 : vfs[1]->devfn - vfs[0]->devfn;
279
280 for (i = 0; i < pf->len; i++) {
281 if (bus != qdev_get_parent_bus(&vfs[i]->qdev)) {
282 error_setg(errp, "SR-IOV VF parent bus mismatches with PF");
283 return -1;
284 }
285
286 if (ven_id != pci_get_word(vfs[i]->config + PCI_VENDOR_ID)) {
287 error_setg(errp, "SR-IOV VF vendor ID mismatches with PF");
288 return -1;
289 }
290
291 if (vf_dev_id != pci_get_word(vfs[i]->config + PCI_DEVICE_ID)) {
292 error_setg(errp, "inconsistent SR-IOV VF device IDs");
293 return -1;
294 }
295
296 for (size_t j = 0; j < PCI_NUM_REGIONS; j++) {
297 if (vfs[i]->io_regions[j].size != vfs[0]->io_regions[j].size ||
298 vfs[i]->io_regions[j].type != vfs[0]->io_regions[j].type) {
299 error_setg(errp, "inconsistent SR-IOV BARs");
300 return -1;
301 }
302 }
303
304 if (vfs[i]->devfn - vfs[0]->devfn != vf_stride * i) {
305 error_setg(errp, "inconsistent SR-IOV stride");
306 return -1;
307 }
308 }
309
310 if (!pcie_sriov_pf_init_common(dev, offset, vf_dev_id, pf->len,
311 pf->len, vf_offset, vf_stride, errp)) {
312 return -1;
313 }
314
315 if (!pcie_find_capability(dev, PCI_EXT_CAP_ID_ARI)) {
316 pcie_ari_init(dev, offset + size);
317 size += PCI_ARI_SIZEOF;
318 }
319
320 for (i = 0; i < pf->len; i++) {
321 vfs[i]->exp.sriov_vf.pf = dev;
322 vfs[i]->exp.sriov_vf.vf_number = i;
323
324 /* set vid/did according to sr/iov spec - they are not used */
325 pci_config_set_vendor_id(vfs[i]->config, 0xffff);
326 pci_config_set_device_id(vfs[i]->config, 0xffff);
327 }
328
329 dev->exp.sriov_pf.vf = vfs;
330 dev->exp.sriov_pf.vf_user_created = true;
331
332 for (i = 0; i < PCI_NUM_REGIONS; i++) {
333 PCIIORegion *region = &vfs[0]->io_regions[i];
334
335 if (region->size) {
336 pcie_sriov_pf_init_vf_bar(dev, i, region->type, region->size);
337 }
338 }
339
340 return size;
341 }
342
pcie_sriov_register_device(PCIDevice * dev,Error ** errp)343 bool pcie_sriov_register_device(PCIDevice *dev, Error **errp)
344 {
345 if (!dev->exp.sriov_pf.vf && dev->qdev.id &&
346 pfs && g_hash_table_contains(pfs, dev->qdev.id)) {
347 error_setg(errp, "attaching user-created SR-IOV VF unsupported");
348 return false;
349 }
350
351 if (dev->sriov_pf) {
352 PCIDevice *pci_pf;
353 GPtrArray *pf;
354
355 if (!PCI_DEVICE_GET_CLASS(dev)->sriov_vf_user_creatable) {
356 error_setg(errp, "user cannot create SR-IOV VF with this device type");
357 return false;
358 }
359
360 if (!pci_is_express(dev)) {
361 error_setg(errp, "PCI Express is required for SR-IOV VF");
362 return false;
363 }
364
365 if (!pci_qdev_find_device(dev->sriov_pf, &pci_pf)) {
366 error_setg(errp, "PCI device specified as SR-IOV PF already exists");
367 return false;
368 }
369
370 if (!pfs) {
371 pfs = g_hash_table_new_full(g_str_hash, g_str_equal, g_free, NULL);
372 }
373
374 pf = g_hash_table_lookup(pfs, dev->sriov_pf);
375 if (!pf) {
376 pf = g_ptr_array_new();
377 g_hash_table_insert(pfs, g_strdup(dev->sriov_pf), pf);
378 }
379
380 g_ptr_array_add(pf, dev);
381 }
382
383 return true;
384 }
385
pcie_sriov_unregister_device(PCIDevice * dev)386 void pcie_sriov_unregister_device(PCIDevice *dev)
387 {
388 if (dev->sriov_pf && pfs) {
389 GPtrArray *pf = g_hash_table_lookup(pfs, dev->sriov_pf);
390
391 if (pf) {
392 g_ptr_array_remove_fast(pf, dev);
393
394 if (!pf->len) {
395 g_hash_table_remove(pfs, dev->sriov_pf);
396 g_ptr_array_free(pf, FALSE);
397 }
398 }
399 }
400 }
401
pcie_sriov_config_write(PCIDevice * dev,uint32_t address,uint32_t val,int len)402 void pcie_sriov_config_write(PCIDevice *dev, uint32_t address,
403 uint32_t val, int len)
404 {
405 uint32_t off;
406 uint16_t sriov_cap = dev->exp.sriov_cap;
407
408 if (!sriov_cap || address < sriov_cap) {
409 return;
410 }
411 off = address - sriov_cap;
412 if (off >= PCI_EXT_CAP_SRIOV_SIZEOF) {
413 return;
414 }
415
416 trace_sriov_config_write(dev->name, PCI_SLOT(dev->devfn),
417 PCI_FUNC(dev->devfn), off, val, len);
418
419 if (range_covers_byte(off, len, PCI_SRIOV_CTRL)) {
420 if (val & PCI_SRIOV_CTRL_VFE) {
421 register_vfs(dev);
422 } else {
423 unregister_vfs(dev);
424 }
425 } else if (range_covers_byte(off, len, PCI_SRIOV_NUM_VF)) {
426 uint8_t *cfg = dev->config + sriov_cap;
427 uint8_t *wmask = dev->wmask + sriov_cap;
428 uint16_t num_vfs = pci_get_word(cfg + PCI_SRIOV_NUM_VF);
429 uint16_t wmask_val = PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI;
430
431 if (num_vfs <= pci_get_word(cfg + PCI_SRIOV_TOTAL_VF)) {
432 wmask_val |= PCI_SRIOV_CTRL_VFE;
433 }
434
435 pci_set_word(wmask + PCI_SRIOV_CTRL, wmask_val);
436 }
437 }
438
pcie_sriov_pf_post_load(PCIDevice * dev)439 void pcie_sriov_pf_post_load(PCIDevice *dev)
440 {
441 if (dev->exp.sriov_cap) {
442 register_vfs(dev);
443 }
444 }
445
446
447 /* Reset SR/IOV */
pcie_sriov_pf_reset(PCIDevice * dev)448 void pcie_sriov_pf_reset(PCIDevice *dev)
449 {
450 uint16_t sriov_cap = dev->exp.sriov_cap;
451 if (!sriov_cap) {
452 return;
453 }
454
455 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_CTRL, 0);
456 unregister_vfs(dev);
457
458 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF, 0);
459 pci_set_word(dev->wmask + sriov_cap + PCI_SRIOV_CTRL,
460 PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI);
461
462 /*
463 * Default is to use 4K pages, software can modify it
464 * to any of the supported bits
465 */
466 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_SYS_PGSIZE, 0x1);
467
468 for (uint16_t i = 0; i < PCI_NUM_REGIONS; i++) {
469 pci_set_quad(dev->config + sriov_cap + PCI_SRIOV_BAR + i * 4,
470 dev->exp.sriov_pf.vf_bar_type[i]);
471 }
472 }
473
474 /* Add optional supported page sizes to the mask of supported page sizes */
pcie_sriov_pf_add_sup_pgsize(PCIDevice * dev,uint16_t opt_sup_pgsize)475 void pcie_sriov_pf_add_sup_pgsize(PCIDevice *dev, uint16_t opt_sup_pgsize)
476 {
477 uint8_t *cfg = dev->config + dev->exp.sriov_cap;
478 uint8_t *wmask = dev->wmask + dev->exp.sriov_cap;
479
480 uint16_t sup_pgsize = pci_get_word(cfg + PCI_SRIOV_SUP_PGSIZE);
481
482 sup_pgsize |= opt_sup_pgsize;
483
484 /*
485 * Make sure the new bits are set, and that system page size
486 * also can be set to any of the new values according to spec:
487 */
488 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, sup_pgsize);
489 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, sup_pgsize);
490 }
491
492
pcie_sriov_vf_number(PCIDevice * dev)493 uint16_t pcie_sriov_vf_number(PCIDevice *dev)
494 {
495 assert(dev->exp.sriov_vf.pf);
496 return dev->exp.sriov_vf.vf_number;
497 }
498
pcie_sriov_get_pf(PCIDevice * dev)499 PCIDevice *pcie_sriov_get_pf(PCIDevice *dev)
500 {
501 return dev->exp.sriov_vf.pf;
502 }
503
pcie_sriov_get_vf_at_index(PCIDevice * dev,int n)504 PCIDevice *pcie_sriov_get_vf_at_index(PCIDevice *dev, int n)
505 {
506 assert(!pci_is_vf(dev));
507 if (n < pcie_sriov_num_vfs(dev)) {
508 return dev->exp.sriov_pf.vf[n];
509 }
510 return NULL;
511 }
512
pcie_sriov_num_vfs(PCIDevice * dev)513 uint16_t pcie_sriov_num_vfs(PCIDevice *dev)
514 {
515 uint16_t sriov_cap = dev->exp.sriov_cap;
516 uint8_t *cfg = dev->config + sriov_cap;
517
518 return sriov_cap &&
519 (pci_get_word(cfg + PCI_SRIOV_CTRL) & PCI_SRIOV_CTRL_VFE) ?
520 pci_get_word(cfg + PCI_SRIOV_NUM_VF) : 0;
521 }
522