1 /*
2 * QEMU PREP PCI host
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 * Copyright (c) 2011-2013 Andreas Färber
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "qemu/units.h"
28 #include "qemu/log.h"
29 #include "qapi/error.h"
30 #include "hw/pci/pci_device.h"
31 #include "hw/pci/pci_bus.h"
32 #include "hw/pci/pci_host.h"
33 #include "hw/qdev-properties.h"
34 #include "migration/vmstate.h"
35 #include "hw/intc/i8259.h"
36 #include "hw/irq.h"
37 #include "hw/or-irq.h"
38 #include "qom/object.h"
39
40 #define TYPE_RAVEN_PCI_DEVICE "raven"
41 #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
42
43 OBJECT_DECLARE_SIMPLE_TYPE(RavenPCIState, RAVEN_PCI_DEVICE)
44
45 struct RavenPCIState {
46 PCIDevice dev;
47 };
48
49 typedef struct PRePPCIState PREPPCIState;
50 DECLARE_INSTANCE_CHECKER(PREPPCIState, RAVEN_PCI_HOST_BRIDGE,
51 TYPE_RAVEN_PCI_HOST_BRIDGE)
52
53 struct PRePPCIState {
54 PCIHostState parent_obj;
55
56 OrIRQState *or_irq;
57 qemu_irq pci_irqs[PCI_NUM_PINS];
58 PCIBus pci_bus;
59 AddressSpace pci_io_as;
60 MemoryRegion pci_io;
61 MemoryRegion pci_io_non_contiguous;
62 MemoryRegion pci_memory;
63 MemoryRegion pci_intack;
64 MemoryRegion bm;
65 MemoryRegion bm_ram_alias;
66 MemoryRegion bm_pci_memory_alias;
67 AddressSpace bm_as;
68 RavenPCIState pci_dev;
69
70 int contiguous_map;
71 };
72
73 #define PCI_IO_BASE_ADDR 0x80000000 /* Physical address on main bus */
74
raven_pci_io_config(hwaddr addr)75 static inline uint32_t raven_pci_io_config(hwaddr addr)
76 {
77 int i;
78
79 for (i = 0; i < 11; i++) {
80 if ((addr & (1 << (11 + i))) != 0) {
81 break;
82 }
83 }
84 return (addr & 0x7ff) | (i << 11);
85 }
86
raven_pci_io_write(void * opaque,hwaddr addr,uint64_t val,unsigned int size)87 static void raven_pci_io_write(void *opaque, hwaddr addr,
88 uint64_t val, unsigned int size)
89 {
90 PREPPCIState *s = opaque;
91 PCIHostState *phb = PCI_HOST_BRIDGE(s);
92 pci_data_write(phb->bus, raven_pci_io_config(addr), val, size);
93 }
94
raven_pci_io_read(void * opaque,hwaddr addr,unsigned int size)95 static uint64_t raven_pci_io_read(void *opaque, hwaddr addr,
96 unsigned int size)
97 {
98 PREPPCIState *s = opaque;
99 PCIHostState *phb = PCI_HOST_BRIDGE(s);
100 return pci_data_read(phb->bus, raven_pci_io_config(addr), size);
101 }
102
103 static const MemoryRegionOps raven_pci_io_ops = {
104 .read = raven_pci_io_read,
105 .write = raven_pci_io_write,
106 .endianness = DEVICE_LITTLE_ENDIAN,
107 };
108
raven_intack_read(void * opaque,hwaddr addr,unsigned int size)109 static uint64_t raven_intack_read(void *opaque, hwaddr addr,
110 unsigned int size)
111 {
112 return pic_read_irq(isa_pic);
113 }
114
raven_intack_write(void * opaque,hwaddr addr,uint64_t data,unsigned size)115 static void raven_intack_write(void *opaque, hwaddr addr,
116 uint64_t data, unsigned size)
117 {
118 qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__);
119 }
120
121 static const MemoryRegionOps raven_intack_ops = {
122 .read = raven_intack_read,
123 .write = raven_intack_write,
124 .valid = {
125 .max_access_size = 1,
126 },
127 };
128
raven_io_address(PREPPCIState * s,hwaddr addr)129 static inline hwaddr raven_io_address(PREPPCIState *s,
130 hwaddr addr)
131 {
132 if (s->contiguous_map == 0) {
133 /* 64 KB contiguous space for IOs */
134 addr &= 0xFFFF;
135 } else {
136 /* 8 MB non-contiguous space for IOs */
137 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
138 }
139
140 /* FIXME: handle endianness switch */
141
142 return addr;
143 }
144
raven_io_read(void * opaque,hwaddr addr,unsigned int size)145 static uint64_t raven_io_read(void *opaque, hwaddr addr,
146 unsigned int size)
147 {
148 PREPPCIState *s = opaque;
149 uint8_t buf[4];
150
151 addr = raven_io_address(s, addr);
152 address_space_read(&s->pci_io_as, addr + PCI_IO_BASE_ADDR,
153 MEMTXATTRS_UNSPECIFIED, buf, size);
154
155 if (size == 1) {
156 return buf[0];
157 } else if (size == 2) {
158 return lduw_le_p(buf);
159 } else if (size == 4) {
160 return ldl_le_p(buf);
161 } else {
162 g_assert_not_reached();
163 }
164 }
165
raven_io_write(void * opaque,hwaddr addr,uint64_t val,unsigned int size)166 static void raven_io_write(void *opaque, hwaddr addr,
167 uint64_t val, unsigned int size)
168 {
169 PREPPCIState *s = opaque;
170 uint8_t buf[4];
171
172 addr = raven_io_address(s, addr);
173
174 if (size == 1) {
175 buf[0] = val;
176 } else if (size == 2) {
177 stw_le_p(buf, val);
178 } else if (size == 4) {
179 stl_le_p(buf, val);
180 } else {
181 g_assert_not_reached();
182 }
183
184 address_space_write(&s->pci_io_as, addr + PCI_IO_BASE_ADDR,
185 MEMTXATTRS_UNSPECIFIED, buf, size);
186 }
187
188 static const MemoryRegionOps raven_io_ops = {
189 .read = raven_io_read,
190 .write = raven_io_write,
191 .endianness = DEVICE_LITTLE_ENDIAN,
192 .impl.max_access_size = 4,
193 .impl.unaligned = true,
194 .valid.unaligned = true,
195 };
196
raven_map_irq(PCIDevice * pci_dev,int irq_num)197 static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
198 {
199 return (irq_num + (pci_dev->devfn >> 3)) & 1;
200 }
201
raven_set_irq(void * opaque,int irq_num,int level)202 static void raven_set_irq(void *opaque, int irq_num, int level)
203 {
204 PREPPCIState *s = opaque;
205
206 qemu_set_irq(s->pci_irqs[irq_num], level);
207 }
208
raven_pcihost_set_iommu(PCIBus * bus,void * opaque,int devfn)209 static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
210 int devfn)
211 {
212 PREPPCIState *s = opaque;
213
214 return &s->bm_as;
215 }
216
217 static const PCIIOMMUOps raven_iommu_ops = {
218 .get_address_space = raven_pcihost_set_iommu,
219 };
220
raven_change_gpio(void * opaque,int n,int level)221 static void raven_change_gpio(void *opaque, int n, int level)
222 {
223 PREPPCIState *s = opaque;
224
225 s->contiguous_map = level;
226 }
227
raven_pcihost_realizefn(DeviceState * d,Error ** errp)228 static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
229 {
230 SysBusDevice *dev = SYS_BUS_DEVICE(d);
231 PCIHostState *h = PCI_HOST_BRIDGE(dev);
232 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev);
233 MemoryRegion *address_space_mem = get_system_memory();
234 int i;
235
236 /*
237 * According to PReP specification section 6.1.6 "System Interrupt
238 * Assignments", all PCI interrupts are routed via IRQ 15
239 */
240 s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ));
241 object_property_set_int(OBJECT(s->or_irq), "num-lines", PCI_NUM_PINS,
242 &error_fatal);
243 qdev_realize(DEVICE(s->or_irq), NULL, &error_fatal);
244 sysbus_init_irq(dev, &s->or_irq->out_irq);
245
246 for (i = 0; i < PCI_NUM_PINS; i++) {
247 s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
248 }
249
250 qdev_init_gpio_in(d, raven_change_gpio, 1);
251
252 pci_bus_irqs(&s->pci_bus, raven_set_irq, s, PCI_NUM_PINS);
253 pci_bus_map_irqs(&s->pci_bus, raven_map_irq);
254
255 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s,
256 "pci-conf-idx", 4);
257 memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem);
258
259 memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s,
260 "pci-conf-data", 4);
261 memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem);
262
263 memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s,
264 "pciio", 0x00400000);
265 memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
266
267 memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s,
268 "pci-intack", 1);
269 memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack);
270
271 /* TODO Remove once realize propagates to child devices. */
272 qdev_realize(DEVICE(&s->pci_dev), BUS(&s->pci_bus), errp);
273 }
274
raven_pcihost_initfn(Object * obj)275 static void raven_pcihost_initfn(Object *obj)
276 {
277 PCIHostState *h = PCI_HOST_BRIDGE(obj);
278 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
279 MemoryRegion *address_space_mem = get_system_memory();
280 DeviceState *pci_dev;
281
282 memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000);
283 memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s,
284 "pci-io-non-contiguous", 0x00800000);
285 memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000);
286 address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");
287
288 /*
289 * Raven's raven_io_ops use the address-space API to access pci-conf-idx
290 * (which is also owned by the raven device). As such, mark the
291 * pci_io_non_contiguous as re-entrancy safe.
292 */
293 s->pci_io_non_contiguous.disable_reentrancy_guard = true;
294
295 /* CPU address space */
296 memory_region_add_subregion(address_space_mem, PCI_IO_BASE_ADDR,
297 &s->pci_io);
298 memory_region_add_subregion_overlap(address_space_mem, PCI_IO_BASE_ADDR,
299 &s->pci_io_non_contiguous, 1);
300 memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
301 pci_root_bus_init(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
302 &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
303
304 /* Bus master address space */
305 memory_region_init(&s->bm, obj, "bm-raven", 4 * GiB);
306 memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory",
307 &s->pci_memory, 0,
308 memory_region_size(&s->pci_memory));
309 memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system",
310 get_system_memory(), 0, 0x80000000);
311 memory_region_add_subregion(&s->bm, 0 , &s->bm_pci_memory_alias);
312 memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias);
313 address_space_init(&s->bm_as, &s->bm, "raven-bm");
314 pci_setup_iommu(&s->pci_bus, &raven_iommu_ops, s);
315
316 h->bus = &s->pci_bus;
317
318 object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);
319 pci_dev = DEVICE(&s->pci_dev);
320 object_property_set_int(OBJECT(&s->pci_dev), "addr", PCI_DEVFN(0, 0),
321 NULL);
322 qdev_prop_set_bit(pci_dev, "multifunction", false);
323 }
324
raven_realize(PCIDevice * d,Error ** errp)325 static void raven_realize(PCIDevice *d, Error **errp)
326 {
327 d->config[PCI_CACHE_LINE_SIZE] = 0x08;
328 d->config[PCI_LATENCY_TIMER] = 0x10;
329 d->config[PCI_CAPABILITY_LIST] = 0x00;
330 }
331
332 static const VMStateDescription vmstate_raven = {
333 .name = "raven",
334 .version_id = 0,
335 .minimum_version_id = 0,
336 .fields = (const VMStateField[]) {
337 VMSTATE_PCI_DEVICE(dev, RavenPCIState),
338 VMSTATE_END_OF_LIST()
339 },
340 };
341
raven_class_init(ObjectClass * klass,const void * data)342 static void raven_class_init(ObjectClass *klass, const void *data)
343 {
344 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
345 DeviceClass *dc = DEVICE_CLASS(klass);
346
347 k->realize = raven_realize;
348 k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
349 k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
350 k->revision = 0x00;
351 k->class_id = PCI_CLASS_BRIDGE_HOST;
352 dc->desc = "PReP Host Bridge - Motorola Raven";
353 dc->vmsd = &vmstate_raven;
354 /*
355 * Reason: PCI-facing part of the host bridge, not usable without
356 * the host-facing part, which can't be device_add'ed, yet.
357 */
358 dc->user_creatable = false;
359 }
360
361 static const TypeInfo raven_info = {
362 .name = TYPE_RAVEN_PCI_DEVICE,
363 .parent = TYPE_PCI_DEVICE,
364 .instance_size = sizeof(RavenPCIState),
365 .class_init = raven_class_init,
366 .interfaces = (const InterfaceInfo[]) {
367 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
368 { },
369 },
370 };
371
raven_pcihost_class_init(ObjectClass * klass,const void * data)372 static void raven_pcihost_class_init(ObjectClass *klass, const void *data)
373 {
374 DeviceClass *dc = DEVICE_CLASS(klass);
375
376 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
377 dc->realize = raven_pcihost_realizefn;
378 dc->fw_name = "pci";
379 }
380
381 static const TypeInfo raven_pcihost_info = {
382 .name = TYPE_RAVEN_PCI_HOST_BRIDGE,
383 .parent = TYPE_PCI_HOST_BRIDGE,
384 .instance_size = sizeof(PREPPCIState),
385 .instance_init = raven_pcihost_initfn,
386 .class_init = raven_pcihost_class_init,
387 };
388
raven_register_types(void)389 static void raven_register_types(void)
390 {
391 type_register_static(&raven_pcihost_info);
392 type_register_static(&raven_info);
393 }
394
395 type_init(raven_register_types)
396