1 /*
2 * vfio based device assignment support - PCI devices
3 *
4 * Copyright Red Hat, Inc. 2012-2015
5 *
6 * Authors:
7 * Alex Williamson <alex.williamson@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 */
12 #ifndef HW_VFIO_VFIO_PCI_H
13 #define HW_VFIO_VFIO_PCI_H
14
15 #include "system/memory.h"
16 #include "hw/pci/pci_device.h"
17 #include "hw/vfio/vfio-device.h"
18 #include "hw/vfio/vfio-region.h"
19 #include "qemu/event_notifier.h"
20 #include "qemu/queue.h"
21 #include "qemu/timer.h"
22 #include "qom/object.h"
23 #include "system/kvm.h"
24 #include "vfio-display.h"
25
26 #define PCI_ANY_ID (~0)
27
28 struct VFIOPCIDevice;
29
30 typedef struct VFIOIOEventFD {
31 QLIST_ENTRY(VFIOIOEventFD) next;
32 MemoryRegion *mr;
33 hwaddr addr;
34 unsigned size;
35 uint64_t data;
36 EventNotifier e;
37 VFIORegion *region;
38 hwaddr region_addr;
39 bool dynamic; /* Added runtime, removed on device reset */
40 bool vfio;
41 } VFIOIOEventFD;
42
43 typedef struct VFIOQuirk {
44 QLIST_ENTRY(VFIOQuirk) next;
45 void *data;
46 QLIST_HEAD(, VFIOIOEventFD) ioeventfds;
47 int nr_mem;
48 MemoryRegion *mem;
49 void (*reset)(struct VFIOPCIDevice *vdev, struct VFIOQuirk *quirk);
50 } VFIOQuirk;
51
52 typedef struct VFIOBAR {
53 VFIORegion region;
54 MemoryRegion *mr;
55 size_t size;
56 uint8_t type;
57 bool ioport;
58 bool mem64;
59 QLIST_HEAD(, VFIOQuirk) quirks;
60 } VFIOBAR;
61
62 typedef struct VFIOVGARegion {
63 MemoryRegion mem;
64 off_t offset;
65 int nr;
66 QLIST_HEAD(, VFIOQuirk) quirks;
67 } VFIOVGARegion;
68
69 typedef struct VFIOVGA {
70 off_t fd_offset;
71 int fd;
72 VFIOVGARegion region[QEMU_PCI_VGA_NUM_REGIONS];
73 } VFIOVGA;
74
75 typedef struct VFIOINTx {
76 bool pending; /* interrupt pending */
77 bool kvm_accel; /* set when QEMU bypass through KVM enabled */
78 uint8_t pin; /* which pin to pull for qemu_set_irq */
79 EventNotifier interrupt; /* eventfd triggered on interrupt */
80 EventNotifier unmask; /* eventfd for unmask on QEMU bypass */
81 PCIINTxRoute route; /* routing info for QEMU bypass */
82 uint32_t mmap_timeout; /* delay to re-enable mmaps after interrupt */
83 QEMUTimer *mmap_timer; /* enable mmaps after periods w/o interrupts */
84 } VFIOINTx;
85
86 typedef struct VFIOMSIVector {
87 /*
88 * Two interrupt paths are configured per vector. The first, is only used
89 * for interrupts injected via QEMU. This is typically the non-accel path,
90 * but may also be used when we want QEMU to handle masking and pending
91 * bits. The KVM path bypasses QEMU and is therefore higher performance,
92 * but requires masking at the device. virq is used to track the MSI route
93 * through KVM, thus kvm_interrupt is only available when virq is set to a
94 * valid (>= 0) value.
95 */
96 EventNotifier interrupt;
97 EventNotifier kvm_interrupt;
98 struct VFIOPCIDevice *vdev; /* back pointer to device */
99 int virq;
100 bool use;
101 } VFIOMSIVector;
102
103 enum {
104 VFIO_INT_NONE = 0,
105 VFIO_INT_INTx = 1,
106 VFIO_INT_MSI = 2,
107 VFIO_INT_MSIX = 3,
108 };
109
110 /* Cache of MSI-X setup */
111 typedef struct VFIOMSIXInfo {
112 uint8_t table_bar;
113 uint8_t pba_bar;
114 uint16_t entries;
115 uint32_t table_offset;
116 uint32_t pba_offset;
117 unsigned long *pending;
118 bool noresize;
119 MemoryRegion *pba_region;
120 } VFIOMSIXInfo;
121
122 /*
123 * TYPE_VFIO_PCI_BASE is an abstract type used to share code
124 * between VFIO implementations that use a kernel driver
125 * with those that use user sockets.
126 */
127 #define TYPE_VFIO_PCI_BASE "vfio-pci-base"
128 OBJECT_DECLARE_SIMPLE_TYPE(VFIOPCIDevice, VFIO_PCI_BASE)
129
130 #define TYPE_VFIO_PCI "vfio-pci"
131 /* TYPE_VFIO_PCI shares struct VFIOPCIDevice. */
132
133 struct VFIOPCIDevice {
134 PCIDevice pdev;
135 VFIODevice vbasedev;
136 VFIOINTx intx;
137 unsigned int config_size;
138 uint8_t *emulated_config_bits; /* QEMU emulated bits, little-endian */
139 off_t config_offset; /* Offset of config space region within device fd */
140 unsigned int rom_size;
141 off_t rom_offset; /* Offset of ROM region within device fd */
142 void *rom;
143 int msi_cap_size;
144 VFIOMSIVector *msi_vectors;
145 VFIOMSIXInfo *msix;
146 int nr_vectors; /* Number of MSI/MSIX vectors currently in use */
147 int interrupt; /* Current interrupt type */
148 VFIOBAR bars[PCI_NUM_REGIONS - 1]; /* No ROM */
149 VFIOVGA *vga; /* 0xa0000, 0x3b0, 0x3c0 */
150 void *igd_opregion;
151 PCIHostDeviceAddress host;
152 QemuUUID vf_token;
153 EventNotifier err_notifier;
154 EventNotifier req_notifier;
155 int (*resetfn)(struct VFIOPCIDevice *);
156 uint32_t vendor_id;
157 uint32_t device_id;
158 uint32_t sub_vendor_id;
159 uint32_t sub_device_id;
160 uint32_t features;
161 #define VFIO_FEATURE_ENABLE_VGA_BIT 0
162 #define VFIO_FEATURE_ENABLE_VGA (1 << VFIO_FEATURE_ENABLE_VGA_BIT)
163 #define VFIO_FEATURE_ENABLE_REQ_BIT 1
164 #define VFIO_FEATURE_ENABLE_REQ (1 << VFIO_FEATURE_ENABLE_REQ_BIT)
165 #define VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT 2
166 #define VFIO_FEATURE_ENABLE_IGD_OPREGION \
167 (1 << VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT)
168 #define VFIO_FEATURE_ENABLE_IGD_LPC_BIT 3
169 #define VFIO_FEATURE_ENABLE_IGD_LPC \
170 (1 << VFIO_FEATURE_ENABLE_IGD_LPC_BIT)
171 OnOffAuto display;
172 uint32_t display_xres;
173 uint32_t display_yres;
174 int32_t bootindex;
175 OnOffAuto igd_legacy_mode;
176 uint32_t igd_gms;
177 OffAutoPCIBAR msix_relo;
178 uint8_t nv_gpudirect_clique;
179 bool pci_aer;
180 bool req_enabled;
181 bool has_flr;
182 bool has_pm_reset;
183 bool rom_read_failed;
184 bool no_kvm_intx;
185 bool no_kvm_msi;
186 bool no_kvm_msix;
187 bool no_geforce_quirks;
188 bool no_kvm_ioeventfd;
189 bool no_vfio_ioeventfd;
190 bool enable_ramfb;
191 OnOffAuto ramfb_migrate;
192 bool defer_kvm_irq_routing;
193 bool clear_parent_atomics_on_exit;
194 bool skip_vsc_check;
195 VFIODisplay *dpy;
196 Notifier irqchip_change_notifier;
197 };
198
199 /* Use uin32_t for vendor & device so PCI_ANY_ID expands and cannot match hw */
vfio_pci_is(VFIOPCIDevice * vdev,uint32_t vendor,uint32_t device)200 static inline bool vfio_pci_is(VFIOPCIDevice *vdev, uint32_t vendor, uint32_t device)
201 {
202 return (vendor == PCI_ANY_ID || vendor == vdev->vendor_id) &&
203 (device == PCI_ANY_ID || device == vdev->device_id);
204 }
205
vfio_is_vga(VFIOPCIDevice * vdev)206 static inline bool vfio_is_vga(VFIOPCIDevice *vdev)
207 {
208 PCIDevice *pdev = &vdev->pdev;
209 uint16_t class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
210
211 return class == PCI_CLASS_DISPLAY_VGA;
212 }
213
214 /* MSI/MSI-X/INTx */
215 void vfio_pci_vector_init(VFIOPCIDevice *vdev, int nr);
216 void vfio_pci_add_kvm_msi_virq(VFIOPCIDevice *vdev, VFIOMSIVector *vector,
217 int vector_n, bool msix);
218 void vfio_pci_prepare_kvm_msi_virq_batch(VFIOPCIDevice *vdev);
219 void vfio_pci_commit_kvm_msi_virq_batch(VFIOPCIDevice *vdev);
220 bool vfio_pci_intx_enable(VFIOPCIDevice *vdev, Error **errp);
221 void vfio_pci_msix_set_notifiers(VFIOPCIDevice *vdev);
222 void vfio_pci_msi_set_handler(VFIOPCIDevice *vdev, int nr);
223
224 uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len);
225 void vfio_pci_write_config(PCIDevice *pdev,
226 uint32_t addr, uint32_t val, int len);
227
228 uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size);
229 void vfio_vga_write(void *opaque, hwaddr addr, uint64_t data, unsigned size);
230
231 bool vfio_opt_rom_in_denylist(VFIOPCIDevice *vdev);
232 bool vfio_config_quirk_setup(VFIOPCIDevice *vdev, Error **errp);
233 void vfio_vga_quirk_setup(VFIOPCIDevice *vdev);
234 void vfio_vga_quirk_exit(VFIOPCIDevice *vdev);
235 void vfio_vga_quirk_finalize(VFIOPCIDevice *vdev);
236 void vfio_bar_quirk_setup(VFIOPCIDevice *vdev, int nr);
237 void vfio_bar_quirk_exit(VFIOPCIDevice *vdev, int nr);
238 void vfio_bar_quirk_finalize(VFIOPCIDevice *vdev, int nr);
239 void vfio_setup_resetfn_quirk(VFIOPCIDevice *vdev);
240 bool vfio_add_virt_caps(VFIOPCIDevice *vdev, Error **errp);
241 void vfio_quirk_reset(VFIOPCIDevice *vdev);
242 VFIOQuirk *vfio_quirk_alloc(int nr_mem);
243 void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, int nr);
244 bool vfio_probe_igd_config_quirk(VFIOPCIDevice *vdev, Error **errp);
245
246 extern const PropertyInfo qdev_prop_nv_gpudirect_clique;
247
248 void vfio_pci_pre_reset(VFIOPCIDevice *vdev);
249 void vfio_pci_post_reset(VFIOPCIDevice *vdev);
250 bool vfio_pci_host_match(PCIHostDeviceAddress *addr, const char *name);
251 int vfio_pci_get_pci_hot_reset_info(VFIOPCIDevice *vdev,
252 struct vfio_pci_hot_reset_info **info_p);
253
254 bool vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp);
255
256 void vfio_display_reset(VFIOPCIDevice *vdev);
257 bool vfio_display_probe(VFIOPCIDevice *vdev, Error **errp);
258 void vfio_display_finalize(VFIOPCIDevice *vdev);
259
260 extern const VMStateDescription vfio_display_vmstate;
261
262 void vfio_pci_bars_exit(VFIOPCIDevice *vdev);
263 bool vfio_pci_add_capabilities(VFIOPCIDevice *vdev, Error **errp);
264 bool vfio_pci_config_setup(VFIOPCIDevice *vdev, Error **errp);
265 bool vfio_pci_interrupt_setup(VFIOPCIDevice *vdev, Error **errp);
266 void vfio_pci_intx_eoi(VFIODevice *vbasedev);
267 void vfio_pci_put_device(VFIOPCIDevice *vdev);
268 bool vfio_pci_populate_device(VFIOPCIDevice *vdev, Error **errp);
269 void vfio_pci_register_err_notifier(VFIOPCIDevice *vdev);
270 void vfio_pci_register_req_notifier(VFIOPCIDevice *vdev);
271 void vfio_pci_teardown_msi(VFIOPCIDevice *vdev);
272
273 #endif /* HW_VFIO_VFIO_PCI_H */
274