1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_MAIN_H_ 6 #define __RTK_MAIN_H_ 7 8 #include <net/mac80211.h> 9 #include <linux/vmalloc.h> 10 #include <linux/firmware.h> 11 #include <linux/average.h> 12 #include <linux/bitops.h> 13 #include <linux/bitfield.h> 14 #include <linux/iopoll.h> 15 #include <linux/interrupt.h> 16 #include <linux/workqueue.h> 17 18 #include "util.h" 19 20 #define RTW_MAX_MAC_ID_NUM 32 21 #define RTW_MAX_SEC_CAM_NUM 32 22 #define MAX_PG_CAM_BACKUP_NUM 8 23 24 #define RTW_SCAN_MAX_SSIDS 4 25 26 #define RTW_MAX_PATTERN_NUM 12 27 #define RTW_MAX_PATTERN_MASK_SIZE 16 28 #define RTW_MAX_PATTERN_SIZE 128 29 30 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2) 31 32 #define RFREG_MASK 0xfffff 33 #define INV_RF_DATA 0xffffffff 34 #define TX_PAGE_SIZE_SHIFT 7 35 #define TX_PAGE_SIZE (1 << TX_PAGE_SIZE_SHIFT) 36 37 #define RTW_CHANNEL_WIDTH_MAX 3 38 #define RTW_RF_PATH_MAX 4 39 #define HW_FEATURE_LEN 13 40 41 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */ 42 43 extern bool rtw_bf_support; 44 extern bool rtw_disable_lps_deep_mode; 45 extern unsigned int rtw_debug_mask; 46 extern bool rtw_edcca_enabled; 47 extern const struct ieee80211_ops rtw_ops; 48 49 #define RTW_MAX_CHANNEL_NUM_2G 14 50 #define RTW_MAX_CHANNEL_NUM_5G 49 51 52 struct rtw_dev; 53 struct rtw_debugfs; 54 55 enum rtw_hci_type { 56 RTW_HCI_TYPE_PCIE, 57 RTW_HCI_TYPE_USB, 58 RTW_HCI_TYPE_SDIO, 59 60 RTW_HCI_TYPE_UNDEFINE, 61 }; 62 63 struct rtw_hci { 64 const struct rtw_hci_ops *ops; 65 enum rtw_hci_type type; 66 67 u32 rpwm_addr; 68 u32 cpwm_addr; 69 70 u8 bulkout_num; 71 }; 72 73 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48)) 74 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64)) 75 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144)) 76 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177)) 77 78 #define IS_CH_5G_BAND_MID(channel) \ 79 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel)) 80 81 #define IS_CH_2G_BAND(channel) ((channel) <= 14) 82 #define IS_CH_5G_BAND(channel) \ 83 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \ 84 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel)) 85 86 enum rtw_supported_band { 87 RTW_BAND_2G = BIT(NL80211_BAND_2GHZ), 88 RTW_BAND_5G = BIT(NL80211_BAND_5GHZ), 89 RTW_BAND_60G = BIT(NL80211_BAND_60GHZ), 90 }; 91 92 /* now, support up to 80M bw */ 93 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80 94 95 enum rtw_bandwidth { 96 RTW_CHANNEL_WIDTH_20 = 0, 97 RTW_CHANNEL_WIDTH_40 = 1, 98 RTW_CHANNEL_WIDTH_80 = 2, 99 RTW_CHANNEL_WIDTH_160 = 3, 100 RTW_CHANNEL_WIDTH_80_80 = 4, 101 RTW_CHANNEL_WIDTH_5 = 5, 102 RTW_CHANNEL_WIDTH_10 = 6, 103 }; 104 105 enum rtw_sc_offset { 106 RTW_SC_DONT_CARE = 0, 107 RTW_SC_20_UPPER = 1, 108 RTW_SC_20_LOWER = 2, 109 RTW_SC_20_UPMOST = 3, 110 RTW_SC_20_LOWEST = 4, 111 RTW_SC_40_UPPER = 9, 112 RTW_SC_40_LOWER = 10, 113 }; 114 115 enum rtw_net_type { 116 RTW_NET_NO_LINK = 0, 117 RTW_NET_AD_HOC = 1, 118 RTW_NET_MGD_LINKED = 2, 119 RTW_NET_AP_MODE = 3, 120 }; 121 122 enum rtw_rf_type { 123 RF_1T1R = 0, 124 RF_1T2R = 1, 125 RF_2T2R = 2, 126 RF_2T3R = 3, 127 RF_2T4R = 4, 128 RF_3T3R = 5, 129 RF_3T4R = 6, 130 RF_4T4R = 7, 131 RF_TYPE_MAX, 132 }; 133 134 enum rtw_rf_path { 135 RF_PATH_A = 0, 136 RF_PATH_B = 1, 137 RF_PATH_C = 2, 138 RF_PATH_D = 3, 139 }; 140 141 enum rtw_bb_path { 142 BB_PATH_A = BIT(0), 143 BB_PATH_B = BIT(1), 144 BB_PATH_C = BIT(2), 145 BB_PATH_D = BIT(3), 146 147 BB_PATH_AB = (BB_PATH_A | BB_PATH_B), 148 BB_PATH_AC = (BB_PATH_A | BB_PATH_C), 149 BB_PATH_AD = (BB_PATH_A | BB_PATH_D), 150 BB_PATH_BC = (BB_PATH_B | BB_PATH_C), 151 BB_PATH_BD = (BB_PATH_B | BB_PATH_D), 152 BB_PATH_CD = (BB_PATH_C | BB_PATH_D), 153 154 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), 155 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), 156 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), 157 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), 158 159 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), 160 }; 161 162 enum rtw_rate_section { 163 RTW_RATE_SECTION_CCK = 0, 164 RTW_RATE_SECTION_OFDM, 165 RTW_RATE_SECTION_HT_1S, 166 RTW_RATE_SECTION_HT_2S, 167 RTW_RATE_SECTION_VHT_1S, 168 RTW_RATE_SECTION_VHT_2S, 169 __RTW_RATE_SECTION_2SS_MAX = RTW_RATE_SECTION_VHT_2S, 170 RTW_RATE_SECTION_HT_3S, 171 RTW_RATE_SECTION_HT_4S, 172 RTW_RATE_SECTION_VHT_3S, 173 RTW_RATE_SECTION_VHT_4S, 174 175 /* keep last */ 176 RTW_RATE_SECTION_NUM, 177 }; 178 179 enum rtw_wireless_set { 180 WIRELESS_CCK = 0x00000001, 181 WIRELESS_OFDM = 0x00000002, 182 WIRELESS_HT = 0x00000004, 183 WIRELESS_VHT = 0x00000008, 184 }; 185 186 #define HT_STBC_EN BIT(0) 187 #define VHT_STBC_EN BIT(1) 188 #define HT_LDPC_EN BIT(0) 189 #define VHT_LDPC_EN BIT(1) 190 191 enum rtw_chip_type { 192 RTW_CHIP_TYPE_8822B, 193 RTW_CHIP_TYPE_8822C, 194 RTW_CHIP_TYPE_8723D, 195 RTW_CHIP_TYPE_8821C, 196 RTW_CHIP_TYPE_8703B, 197 RTW_CHIP_TYPE_8821A, 198 RTW_CHIP_TYPE_8812A, 199 RTW_CHIP_TYPE_8814A, 200 }; 201 202 enum rtw_tx_queue_type { 203 /* the order of AC queues matters */ 204 RTW_TX_QUEUE_BK = 0x0, 205 RTW_TX_QUEUE_BE = 0x1, 206 RTW_TX_QUEUE_VI = 0x2, 207 RTW_TX_QUEUE_VO = 0x3, 208 209 RTW_TX_QUEUE_BCN = 0x4, 210 RTW_TX_QUEUE_MGMT = 0x5, 211 RTW_TX_QUEUE_HI0 = 0x6, 212 RTW_TX_QUEUE_H2C = 0x7, 213 /* keep it last */ 214 RTK_MAX_TX_QUEUE_NUM 215 }; 216 217 enum rtw_rx_queue_type { 218 RTW_RX_QUEUE_MPDU = 0x0, 219 RTW_RX_QUEUE_C2H = 0x1, 220 /* keep it last */ 221 RTK_MAX_RX_QUEUE_NUM 222 }; 223 224 enum rtw_fw_type { 225 RTW_NORMAL_FW = 0x0, 226 RTW_WOWLAN_FW = 0x1, 227 }; 228 229 enum rtw_rate_index { 230 RTW_RATEID_BGN_40M_2SS = 0, 231 RTW_RATEID_BGN_40M_1SS = 1, 232 RTW_RATEID_BGN_20M_2SS = 2, 233 RTW_RATEID_BGN_20M_1SS = 3, 234 RTW_RATEID_GN_N2SS = 4, 235 RTW_RATEID_GN_N1SS = 5, 236 RTW_RATEID_BG = 6, 237 RTW_RATEID_G = 7, 238 RTW_RATEID_B_20M = 8, 239 RTW_RATEID_ARFR0_AC_2SS = 9, 240 RTW_RATEID_ARFR1_AC_1SS = 10, 241 RTW_RATEID_ARFR2_AC_2G_1SS = 11, 242 RTW_RATEID_ARFR3_AC_2G_2SS = 12, 243 RTW_RATEID_ARFR4_AC_3SS = 13, 244 RTW_RATEID_ARFR5_N_3SS = 14, 245 RTW_RATEID_ARFR7_N_4SS = 15, 246 RTW_RATEID_ARFR6_AC_4SS = 16 247 }; 248 249 enum rtw_trx_desc_rate { 250 DESC_RATE1M = 0x00, 251 DESC_RATE2M = 0x01, 252 DESC_RATE5_5M = 0x02, 253 DESC_RATE11M = 0x03, 254 255 DESC_RATE6M = 0x04, 256 DESC_RATE9M = 0x05, 257 DESC_RATE12M = 0x06, 258 DESC_RATE18M = 0x07, 259 DESC_RATE24M = 0x08, 260 DESC_RATE36M = 0x09, 261 DESC_RATE48M = 0x0a, 262 DESC_RATE54M = 0x0b, 263 264 DESC_RATEMCS0 = 0x0c, 265 DESC_RATEMCS1 = 0x0d, 266 DESC_RATEMCS2 = 0x0e, 267 DESC_RATEMCS3 = 0x0f, 268 DESC_RATEMCS4 = 0x10, 269 DESC_RATEMCS5 = 0x11, 270 DESC_RATEMCS6 = 0x12, 271 DESC_RATEMCS7 = 0x13, 272 DESC_RATEMCS8 = 0x14, 273 DESC_RATEMCS9 = 0x15, 274 DESC_RATEMCS10 = 0x16, 275 DESC_RATEMCS11 = 0x17, 276 DESC_RATEMCS12 = 0x18, 277 DESC_RATEMCS13 = 0x19, 278 DESC_RATEMCS14 = 0x1a, 279 DESC_RATEMCS15 = 0x1b, 280 DESC_RATEMCS16 = 0x1c, 281 DESC_RATEMCS17 = 0x1d, 282 DESC_RATEMCS18 = 0x1e, 283 DESC_RATEMCS19 = 0x1f, 284 DESC_RATEMCS20 = 0x20, 285 DESC_RATEMCS21 = 0x21, 286 DESC_RATEMCS22 = 0x22, 287 DESC_RATEMCS23 = 0x23, 288 DESC_RATEMCS24 = 0x24, 289 DESC_RATEMCS25 = 0x25, 290 DESC_RATEMCS26 = 0x26, 291 DESC_RATEMCS27 = 0x27, 292 DESC_RATEMCS28 = 0x28, 293 DESC_RATEMCS29 = 0x29, 294 DESC_RATEMCS30 = 0x2a, 295 DESC_RATEMCS31 = 0x2b, 296 297 DESC_RATEVHT1SS_MCS0 = 0x2c, 298 DESC_RATEVHT1SS_MCS1 = 0x2d, 299 DESC_RATEVHT1SS_MCS2 = 0x2e, 300 DESC_RATEVHT1SS_MCS3 = 0x2f, 301 DESC_RATEVHT1SS_MCS4 = 0x30, 302 DESC_RATEVHT1SS_MCS5 = 0x31, 303 DESC_RATEVHT1SS_MCS6 = 0x32, 304 DESC_RATEVHT1SS_MCS7 = 0x33, 305 DESC_RATEVHT1SS_MCS8 = 0x34, 306 DESC_RATEVHT1SS_MCS9 = 0x35, 307 308 DESC_RATEVHT2SS_MCS0 = 0x36, 309 DESC_RATEVHT2SS_MCS1 = 0x37, 310 DESC_RATEVHT2SS_MCS2 = 0x38, 311 DESC_RATEVHT2SS_MCS3 = 0x39, 312 DESC_RATEVHT2SS_MCS4 = 0x3a, 313 DESC_RATEVHT2SS_MCS5 = 0x3b, 314 DESC_RATEVHT2SS_MCS6 = 0x3c, 315 DESC_RATEVHT2SS_MCS7 = 0x3d, 316 DESC_RATEVHT2SS_MCS8 = 0x3e, 317 DESC_RATEVHT2SS_MCS9 = 0x3f, 318 319 DESC_RATEVHT3SS_MCS0 = 0x40, 320 DESC_RATEVHT3SS_MCS1 = 0x41, 321 DESC_RATEVHT3SS_MCS2 = 0x42, 322 DESC_RATEVHT3SS_MCS3 = 0x43, 323 DESC_RATEVHT3SS_MCS4 = 0x44, 324 DESC_RATEVHT3SS_MCS5 = 0x45, 325 DESC_RATEVHT3SS_MCS6 = 0x46, 326 DESC_RATEVHT3SS_MCS7 = 0x47, 327 DESC_RATEVHT3SS_MCS8 = 0x48, 328 DESC_RATEVHT3SS_MCS9 = 0x49, 329 330 DESC_RATEVHT4SS_MCS0 = 0x4a, 331 DESC_RATEVHT4SS_MCS1 = 0x4b, 332 DESC_RATEVHT4SS_MCS2 = 0x4c, 333 DESC_RATEVHT4SS_MCS3 = 0x4d, 334 DESC_RATEVHT4SS_MCS4 = 0x4e, 335 DESC_RATEVHT4SS_MCS5 = 0x4f, 336 DESC_RATEVHT4SS_MCS6 = 0x50, 337 DESC_RATEVHT4SS_MCS7 = 0x51, 338 DESC_RATEVHT4SS_MCS8 = 0x52, 339 DESC_RATEVHT4SS_MCS9 = 0x53, 340 341 DESC_RATE_MAX, 342 }; 343 344 enum rtw_regulatory_domains { 345 RTW_REGD_FCC = 0, 346 RTW_REGD_MKK = 1, 347 RTW_REGD_ETSI = 2, 348 RTW_REGD_IC = 3, 349 RTW_REGD_KCC = 4, 350 RTW_REGD_ACMA = 5, 351 RTW_REGD_CHILE = 6, 352 RTW_REGD_UKRAINE = 7, 353 RTW_REGD_MEXICO = 8, 354 RTW_REGD_CN = 9, 355 RTW_REGD_QATAR = 10, 356 RTW_REGD_UK = 11, 357 358 RTW_REGD_WW, 359 RTW_REGD_MAX 360 }; 361 362 enum rtw_txq_flags { 363 RTW_TXQ_AMPDU, 364 RTW_TXQ_BLOCK_BA, 365 }; 366 367 enum rtw_flags { 368 RTW_FLAG_RUNNING, 369 RTW_FLAG_FW_RUNNING, 370 RTW_FLAG_SCANNING, 371 RTW_FLAG_POWERON, 372 RTW_FLAG_LEISURE_PS, 373 RTW_FLAG_LEISURE_PS_DEEP, 374 RTW_FLAG_DIG_DISABLE, 375 RTW_FLAG_BUSY_TRAFFIC, 376 RTW_FLAG_WOWLAN, 377 RTW_FLAG_RESTARTING, 378 RTW_FLAG_RESTART_TRIGGERING, 379 RTW_FLAG_FORCE_LOWEST_RATE, 380 381 NUM_OF_RTW_FLAGS, 382 }; 383 384 enum rtw_evm { 385 RTW_EVM_OFDM = 0, 386 RTW_EVM_1SS, 387 RTW_EVM_2SS_A, 388 RTW_EVM_2SS_B, 389 RTW_EVM_3SS_A, 390 RTW_EVM_3SS_B, 391 RTW_EVM_3SS_C, 392 /* keep it last */ 393 RTW_EVM_NUM 394 }; 395 396 enum rtw_snr { 397 RTW_SNR_OFDM_A = 0, 398 RTW_SNR_OFDM_B, 399 RTW_SNR_OFDM_C, 400 RTW_SNR_OFDM_D, 401 RTW_SNR_1SS_A, 402 RTW_SNR_1SS_B, 403 RTW_SNR_1SS_C, 404 RTW_SNR_1SS_D, 405 RTW_SNR_2SS_A, 406 RTW_SNR_2SS_B, 407 RTW_SNR_2SS_C, 408 RTW_SNR_2SS_D, 409 RTW_SNR_3SS_A, 410 RTW_SNR_3SS_B, 411 RTW_SNR_3SS_C, 412 RTW_SNR_3SS_D, 413 /* keep it last */ 414 RTW_SNR_NUM 415 }; 416 417 enum rtw_port { 418 RTW_PORT_0 = 0, 419 RTW_PORT_1 = 1, 420 RTW_PORT_2 = 2, 421 RTW_PORT_3 = 3, 422 RTW_PORT_4 = 4, 423 RTW_PORT_NUM 424 }; 425 426 enum rtw_wow_flags { 427 RTW_WOW_FLAG_EN_MAGIC_PKT, 428 RTW_WOW_FLAG_EN_REKEY_PKT, 429 RTW_WOW_FLAG_EN_DISCONNECT, 430 431 /* keep it last */ 432 RTW_WOW_FLAG_MAX, 433 }; 434 435 enum rtw_quirk_dis_caps { 436 QUIRK_DIS_CAP_PCI_ASPM, 437 QUIRK_DIS_CAP_LPS_DEEP, 438 }; 439 440 /* the power index is represented by differences, which cck-1s & ht40-1s are 441 * the base values, so for 1s's differences, there are only ht20 & ofdm 442 */ 443 struct rtw_2g_1s_pwr_idx_diff { 444 #ifdef __LITTLE_ENDIAN 445 s8 ofdm:4; 446 s8 bw20:4; 447 #else 448 s8 bw20:4; 449 s8 ofdm:4; 450 #endif 451 } __packed; 452 453 struct rtw_2g_ns_pwr_idx_diff { 454 #ifdef __LITTLE_ENDIAN 455 s8 bw20:4; 456 s8 bw40:4; 457 s8 cck:4; 458 s8 ofdm:4; 459 #else 460 s8 ofdm:4; 461 s8 cck:4; 462 s8 bw40:4; 463 s8 bw20:4; 464 #endif 465 } __packed; 466 467 struct rtw_2g_txpwr_idx { 468 u8 cck_base[6]; 469 u8 bw40_base[5]; 470 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff; 471 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff; 472 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff; 473 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff; 474 }; 475 476 struct rtw_5g_ht_1s_pwr_idx_diff { 477 #ifdef __LITTLE_ENDIAN 478 s8 ofdm:4; 479 s8 bw20:4; 480 #else 481 s8 bw20:4; 482 s8 ofdm:4; 483 #endif 484 } __packed; 485 486 struct rtw_5g_ht_ns_pwr_idx_diff { 487 #ifdef __LITTLE_ENDIAN 488 s8 bw20:4; 489 s8 bw40:4; 490 #else 491 s8 bw40:4; 492 s8 bw20:4; 493 #endif 494 } __packed; 495 496 struct rtw_5g_ofdm_ns_pwr_idx_diff { 497 #ifdef __LITTLE_ENDIAN 498 s8 ofdm_3s:4; 499 s8 ofdm_2s:4; 500 s8 ofdm_4s:4; 501 s8 res:4; 502 #else 503 s8 res:4; 504 s8 ofdm_4s:4; 505 s8 ofdm_2s:4; 506 s8 ofdm_3s:4; 507 #endif 508 } __packed; 509 510 struct rtw_5g_vht_ns_pwr_idx_diff { 511 #ifdef __LITTLE_ENDIAN 512 s8 bw160:4; 513 s8 bw80:4; 514 #else 515 s8 bw80:4; 516 s8 bw160:4; 517 #endif 518 } __packed; 519 520 struct rtw_5g_txpwr_idx { 521 u8 bw40_base[14]; 522 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff; 523 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff; 524 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff; 525 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff; 526 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff; 527 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff; 528 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff; 529 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff; 530 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff; 531 } __packed; 532 533 struct rtw_txpwr_idx { 534 struct rtw_2g_txpwr_idx pwr_idx_2g; 535 struct rtw_5g_txpwr_idx pwr_idx_5g; 536 } __packed; 537 538 struct rtw_channel_params { 539 u8 center_chan; 540 u8 primary_chan; 541 u8 bandwidth; 542 }; 543 544 struct rtw_hw_reg { 545 u32 addr; 546 u32 mask; 547 }; 548 549 struct rtw_hw_reg_desc { 550 u32 addr; 551 u32 mask; 552 const char *desc; 553 }; 554 555 struct rtw_ltecoex_addr { 556 u32 ctrl; 557 u32 wdata; 558 u32 rdata; 559 }; 560 561 struct rtw_reg_domain { 562 u32 addr; 563 u32 mask; 564 #define RTW_REG_DOMAIN_MAC32 0 565 #define RTW_REG_DOMAIN_MAC16 1 566 #define RTW_REG_DOMAIN_MAC8 2 567 #define RTW_REG_DOMAIN_RF_A 3 568 #define RTW_REG_DOMAIN_RF_B 4 569 #define RTW_REG_DOMAIN_NL 0xFF 570 u8 domain; 571 }; 572 573 struct rtw_rf_sipi_addr { 574 u32 hssi_1; 575 u32 hssi_2; 576 u32 lssi_read; 577 u32 lssi_read_pi; 578 }; 579 580 struct rtw_hw_reg_offset { 581 struct rtw_hw_reg hw_reg; 582 u8 offset; 583 }; 584 585 struct rtw_backup_info { 586 u8 len; 587 u32 reg; 588 u32 val; 589 }; 590 591 enum rtw_vif_port_set { 592 PORT_SET_MAC_ADDR = BIT(0), 593 PORT_SET_BSSID = BIT(1), 594 PORT_SET_NET_TYPE = BIT(2), 595 PORT_SET_AID = BIT(3), 596 PORT_SET_BCN_CTRL = BIT(4), 597 }; 598 599 struct rtw_vif_port { 600 struct rtw_hw_reg mac_addr; 601 struct rtw_hw_reg bssid; 602 struct rtw_hw_reg net_type; 603 struct rtw_hw_reg aid; 604 struct rtw_hw_reg bcn_ctrl; 605 }; 606 607 struct rtw_tx_pkt_info { 608 u32 tx_pkt_size; 609 u8 offset; 610 u8 pkt_offset; 611 u8 tim_offset; 612 u8 mac_id; 613 u8 rate_id; 614 u8 rate; 615 u8 qsel; 616 u8 bw; 617 u8 sec_type; 618 u8 sn; 619 bool ampdu_en; 620 u8 ampdu_factor; 621 u8 ampdu_density; 622 u16 seq; 623 bool stbc; 624 bool ldpc; 625 bool dis_rate_fallback; 626 bool bmc; 627 bool use_rate; 628 bool ls; 629 bool fs; 630 bool short_gi; 631 bool report; 632 bool rts; 633 bool dis_qselseq; 634 bool en_hwseq; 635 u8 hw_ssn_sel; 636 bool nav_use_hdr; 637 bool bt_null; 638 }; 639 640 struct rtw_rx_pkt_stat { 641 bool phy_status; 642 bool icv_err; 643 bool crc_err; 644 bool decrypted; 645 bool is_c2h; 646 bool channel_invalid; 647 648 s32 signal_power; 649 u16 pkt_len; 650 u8 bw; 651 u8 drv_info_sz; 652 u8 shift; 653 u8 rate; 654 u8 mac_id; 655 u8 cam_id; 656 u8 ppdu_cnt; 657 u32 tsf_low; 658 s8 rx_power[RTW_RF_PATH_MAX]; 659 u8 rssi; 660 u8 rxsc; 661 s8 rx_snr[RTW_RF_PATH_MAX]; 662 u8 rx_evm[RTW_RF_PATH_MAX]; 663 s8 cfo_tail[RTW_RF_PATH_MAX]; 664 u16 freq; 665 u8 band; 666 667 struct rtw_sta_info *si; 668 struct ieee80211_vif *vif; 669 struct ieee80211_hdr *hdr; 670 }; 671 672 DECLARE_EWMA(tp, 10, 2); 673 674 struct rtw_traffic_stats { 675 /* units in bytes */ 676 u64 tx_unicast; 677 u64 rx_unicast; 678 679 /* count for packets */ 680 u64 tx_cnt; 681 u64 rx_cnt; 682 683 /* units in Mbps */ 684 u32 tx_throughput; 685 u32 rx_throughput; 686 struct ewma_tp tx_ewma_tp; 687 struct ewma_tp rx_ewma_tp; 688 }; 689 690 enum rtw_lps_mode { 691 RTW_MODE_ACTIVE = 0, 692 RTW_MODE_LPS = 1, 693 RTW_MODE_WMM_PS = 2, 694 }; 695 696 enum rtw_lps_deep_mode { 697 LPS_DEEP_MODE_NONE = 0, 698 LPS_DEEP_MODE_LCLK = 1, 699 LPS_DEEP_MODE_PG = 2, 700 }; 701 702 enum rtw_pwr_state { 703 RTW_RF_OFF = 0x0, 704 RTW_RF_ON = 0x4, 705 RTW_ALL_ON = 0xc, 706 }; 707 708 struct rtw_lps_conf { 709 enum rtw_lps_mode mode; 710 enum rtw_lps_deep_mode deep_mode; 711 enum rtw_lps_deep_mode wow_deep_mode; 712 enum rtw_pwr_state state; 713 u8 awake_interval; 714 u8 rlbm; 715 u8 smart_ps; 716 u8 port_id; 717 bool sec_cam_backup; 718 bool pattern_cam_backup; 719 }; 720 721 enum rtw_hw_key_type { 722 RTW_CAM_NONE = 0, 723 RTW_CAM_WEP40 = 1, 724 RTW_CAM_TKIP = 2, 725 RTW_CAM_AES = 4, 726 RTW_CAM_WEP104 = 5, 727 }; 728 729 struct rtw_cam_entry { 730 bool valid; 731 bool group; 732 u8 addr[ETH_ALEN]; 733 u8 hw_key_type; 734 struct ieee80211_key_conf *key; 735 }; 736 737 struct rtw_sec_desc { 738 /* search strategy */ 739 bool default_key_search; 740 741 u32 total_cam_num; 742 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM]; 743 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM); 744 }; 745 746 struct rtw_tx_report { 747 /* protect the tx report queue */ 748 spinlock_t q_lock; 749 struct sk_buff_head queue; 750 atomic_t sn; 751 struct timer_list purge_timer; 752 }; 753 754 struct rtw_ra_report { 755 struct rate_info txrate; 756 u32 bit_rate; 757 u8 desc_rate; 758 }; 759 760 struct rtw_txq { 761 struct list_head list; 762 unsigned long flags; 763 }; 764 765 DECLARE_EWMA(rssi, 10, 16); 766 767 struct rtw_sta_info { 768 struct rtw_dev *rtwdev; 769 struct ieee80211_sta *sta; 770 struct ieee80211_vif *vif; 771 772 struct ewma_rssi avg_rssi; 773 u8 rssi_level; 774 775 u8 mac_id; 776 u8 rate_id; 777 enum rtw_bandwidth bw_mode; 778 u8 stbc_en:2; 779 u8 ldpc_en:2; 780 bool sgi_enable; 781 bool vht_enable; 782 u8 init_ra_lv; 783 u64 ra_mask; 784 785 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS); 786 787 struct rtw_ra_report ra_report; 788 789 bool use_cfg_mask; 790 struct cfg80211_bitrate_mask *mask; 791 792 struct work_struct rc_work; 793 }; 794 795 enum rtw_bfee_role { 796 RTW_BFEE_NONE, 797 RTW_BFEE_SU, 798 RTW_BFEE_MU 799 }; 800 801 struct rtw_bfee { 802 enum rtw_bfee_role role; 803 804 u16 p_aid; 805 u8 g_id; 806 u8 mac_addr[ETH_ALEN]; 807 u8 sound_dim; 808 809 /* SU-MIMO */ 810 u8 su_reg_index; 811 812 /* MU-MIMO */ 813 u16 aid; 814 }; 815 816 struct rtw_bf_info { 817 u8 bfer_mu_cnt; 818 u8 bfer_su_cnt; 819 DECLARE_BITMAP(bfer_su_reg_maping, 2); 820 u8 cur_csi_rpt_rate; 821 }; 822 823 struct rtw_vif { 824 enum rtw_net_type net_type; 825 u16 aid; 826 u8 mac_id; 827 u8 mac_addr[ETH_ALEN]; 828 u8 bssid[ETH_ALEN]; 829 u8 port; 830 u8 bcn_ctrl; 831 struct list_head rsvd_page_list; 832 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 833 const struct rtw_vif_port *conf; 834 struct cfg80211_scan_request *scan_req; 835 struct ieee80211_scan_ies *scan_ies; 836 837 struct rtw_traffic_stats stats; 838 839 struct rtw_bfee bfee; 840 }; 841 842 struct rtw_regulatory { 843 char alpha2[2] __nonstring; 844 u8 txpwr_regd_2g; 845 u8 txpwr_regd_5g; 846 }; 847 848 enum rtw_regd_state { 849 RTW_REGD_STATE_WORLDWIDE, 850 RTW_REGD_STATE_PROGRAMMED, 851 RTW_REGD_STATE_SETTING, 852 853 RTW_REGD_STATE_NR, 854 }; 855 856 struct rtw_regd { 857 enum rtw_regd_state state; 858 const struct rtw_regulatory *regulatory; 859 enum nl80211_dfs_regions dfs_region; 860 }; 861 862 struct rtw_chip_ops { 863 int (*power_on)(struct rtw_dev *rtwdev); 864 void (*power_off)(struct rtw_dev *rtwdev); 865 int (*mac_init)(struct rtw_dev *rtwdev); 866 int (*mac_postinit)(struct rtw_dev *rtwdev); 867 int (*dump_fw_crash)(struct rtw_dev *rtwdev); 868 void (*shutdown)(struct rtw_dev *rtwdev); 869 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map); 870 void (*phy_set_param)(struct rtw_dev *rtwdev); 871 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel, 872 u8 bandwidth, u8 primary_chan_idx); 873 void (*query_phy_status)(struct rtw_dev *rtwdev, u8 *phy_status, 874 struct rtw_rx_pkt_stat *pkt_stat); 875 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 876 u32 addr, u32 mask); 877 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 878 u32 addr, u32 mask, u32 data); 879 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 880 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset, 881 u32 size); 882 int (*set_antenna)(struct rtw_dev *rtwdev, int radio_idx, 883 u32 antenna_tx, 884 u32 antenna_rx); 885 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 886 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable); 887 void (*set_ampdu_factor)(struct rtw_dev *rtwdev, u8 factor); 888 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 889 void (*phy_calibration)(struct rtw_dev *rtwdev); 890 void (*dpk_track)(struct rtw_dev *rtwdev); 891 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level); 892 void (*pwr_track)(struct rtw_dev *rtwdev); 893 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif, 894 struct rtw_bfee *bfee, bool enable); 895 void (*set_gid_table)(struct rtw_dev *rtwdev, 896 struct ieee80211_vif *vif, 897 struct ieee80211_bss_conf *conf); 898 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate, 899 u8 fixrate_en, u8 *new_rate); 900 void (*adaptivity_init)(struct rtw_dev *rtwdev); 901 void (*adaptivity)(struct rtw_dev *rtwdev); 902 void (*cfo_init)(struct rtw_dev *rtwdev); 903 void (*cfo_track)(struct rtw_dev *rtwdev); 904 void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path, 905 enum rtw_bb_path tx_path_1ss, 906 enum rtw_bb_path tx_path_cck, 907 bool is_tx2_path); 908 void (*config_txrx_mode)(struct rtw_dev *rtwdev, u8 tx_path, 909 u8 rx_path, bool is_tx2_path); 910 void (*led_set)(struct led_classdev *led, enum led_brightness brightness); 911 /* for USB/SDIO only */ 912 void (*fill_txdesc_checksum)(struct rtw_dev *rtwdev, 913 struct rtw_tx_pkt_info *pkt_info, 914 u8 *txdesc); 915 916 /* for coex */ 917 void (*coex_set_init)(struct rtw_dev *rtwdev); 918 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev, 919 u8 ctrl_type, u8 pos_type); 920 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev); 921 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev); 922 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev); 923 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr); 924 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain); 925 }; 926 927 #define RTW_PWR_POLLING_CNT 20000 928 929 #define RTW_PWR_CMD_READ 0x00 930 #define RTW_PWR_CMD_WRITE 0x01 931 #define RTW_PWR_CMD_POLLING 0x02 932 #define RTW_PWR_CMD_DELAY 0x03 933 #define RTW_PWR_CMD_END 0x04 934 935 /* define the base address of each block */ 936 #define RTW_PWR_ADDR_MAC 0x00 937 #define RTW_PWR_ADDR_USB 0x01 938 #define RTW_PWR_ADDR_PCIE 0x02 939 #define RTW_PWR_ADDR_SDIO 0x03 940 941 #define RTW_PWR_INTF_SDIO_MSK BIT(0) 942 #define RTW_PWR_INTF_USB_MSK BIT(1) 943 #define RTW_PWR_INTF_PCI_MSK BIT(2) 944 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 945 946 #define RTW_PWR_CUT_TEST_MSK BIT(0) 947 #define RTW_PWR_CUT_A_MSK BIT(1) 948 #define RTW_PWR_CUT_B_MSK BIT(2) 949 #define RTW_PWR_CUT_C_MSK BIT(3) 950 #define RTW_PWR_CUT_D_MSK BIT(4) 951 #define RTW_PWR_CUT_E_MSK BIT(5) 952 #define RTW_PWR_CUT_F_MSK BIT(6) 953 #define RTW_PWR_CUT_G_MSK BIT(7) 954 #define RTW_PWR_CUT_ALL_MSK 0xFF 955 956 enum rtw_pwr_seq_cmd_delay_unit { 957 RTW_PWR_DELAY_US, 958 RTW_PWR_DELAY_MS, 959 }; 960 961 struct rtw_pwr_seq_cmd { 962 u16 offset; 963 u8 cut_mask; 964 u8 intf_mask; 965 u8 base:4; 966 u8 cmd:4; 967 u8 mask; 968 u8 value; 969 }; 970 971 enum rtw_chip_ver { 972 RTW_CHIP_VER_CUT_A = 0x00, 973 RTW_CHIP_VER_CUT_B = 0x01, 974 RTW_CHIP_VER_CUT_C = 0x02, 975 RTW_CHIP_VER_CUT_D = 0x03, 976 RTW_CHIP_VER_CUT_E = 0x04, 977 RTW_CHIP_VER_CUT_F = 0x05, 978 RTW_CHIP_VER_CUT_G = 0x06, 979 }; 980 981 #define RTW_INTF_PHY_PLATFORM_ALL 0 982 983 enum rtw_intf_phy_cut { 984 RTW_INTF_PHY_CUT_A = BIT(0), 985 RTW_INTF_PHY_CUT_B = BIT(1), 986 RTW_INTF_PHY_CUT_C = BIT(2), 987 RTW_INTF_PHY_CUT_D = BIT(3), 988 RTW_INTF_PHY_CUT_E = BIT(4), 989 RTW_INTF_PHY_CUT_F = BIT(5), 990 RTW_INTF_PHY_CUT_G = BIT(6), 991 RTW_INTF_PHY_CUT_ALL = 0xFFFF, 992 }; 993 994 enum rtw_ip_sel { 995 RTW_IP_SEL_PHY = 0, 996 RTW_IP_SEL_MAC = 1, 997 RTW_IP_SEL_DBI = 2, 998 999 RTW_IP_SEL_UNDEF = 0xFFFF 1000 }; 1001 1002 enum rtw_pq_map_id { 1003 RTW_PQ_MAP_VO = 0x0, 1004 RTW_PQ_MAP_VI = 0x1, 1005 RTW_PQ_MAP_BE = 0x2, 1006 RTW_PQ_MAP_BK = 0x3, 1007 RTW_PQ_MAP_MG = 0x4, 1008 RTW_PQ_MAP_HI = 0x5, 1009 RTW_PQ_MAP_NUM = 0x6, 1010 1011 RTW_PQ_MAP_UNDEF, 1012 }; 1013 1014 enum rtw_dma_mapping { 1015 RTW_DMA_MAPPING_EXTRA = 0, 1016 RTW_DMA_MAPPING_LOW = 1, 1017 RTW_DMA_MAPPING_NORMAL = 2, 1018 RTW_DMA_MAPPING_HIGH = 3, 1019 1020 RTW_DMA_MAPPING_MAX, 1021 RTW_DMA_MAPPING_UNDEF, 1022 }; 1023 1024 struct rtw_rqpn { 1025 enum rtw_dma_mapping dma_map_vo; 1026 enum rtw_dma_mapping dma_map_vi; 1027 enum rtw_dma_mapping dma_map_be; 1028 enum rtw_dma_mapping dma_map_bk; 1029 enum rtw_dma_mapping dma_map_mg; 1030 enum rtw_dma_mapping dma_map_hi; 1031 }; 1032 1033 struct rtw_prioq_addr { 1034 u32 rsvd; 1035 u32 avail; 1036 }; 1037 1038 struct rtw_prioq_addrs { 1039 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX]; 1040 bool wsize; 1041 }; 1042 1043 struct rtw_page_table { 1044 u16 hq_num; 1045 u16 nq_num; 1046 u16 lq_num; 1047 u16 exq_num; 1048 u16 gapq_num; 1049 }; 1050 1051 struct rtw_intf_phy_para { 1052 u16 offset; 1053 u16 value; 1054 u16 ip_sel; 1055 u16 cut_mask; 1056 u16 platform; 1057 }; 1058 1059 struct rtw_wow_pattern { 1060 u16 crc; 1061 u8 type; 1062 u8 valid; 1063 u8 mask[RTW_MAX_PATTERN_MASK_SIZE]; 1064 }; 1065 1066 struct rtw_pno_request { 1067 bool inited; 1068 u32 match_set_cnt; 1069 struct cfg80211_match_set *match_sets; 1070 u8 channel_cnt; 1071 struct ieee80211_channel *channels; 1072 struct cfg80211_sched_scan_plan scan_plan; 1073 }; 1074 1075 struct rtw_wow_param { 1076 struct ieee80211_vif *wow_vif; 1077 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX); 1078 u8 txpause; 1079 u8 pattern_cnt; 1080 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM]; 1081 1082 bool ips_enabled; 1083 struct rtw_pno_request pno_req; 1084 }; 1085 1086 struct rtw_intf_phy_para_table { 1087 const struct rtw_intf_phy_para *usb2_para; 1088 const struct rtw_intf_phy_para *usb3_para; 1089 const struct rtw_intf_phy_para *gen1_para; 1090 const struct rtw_intf_phy_para *gen2_para; 1091 u8 n_usb2_para; 1092 u8 n_usb3_para; 1093 u8 n_gen1_para; 1094 u8 n_gen2_para; 1095 }; 1096 1097 struct rtw_table { 1098 const void *data; 1099 const u32 size; 1100 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 1101 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1102 u32 addr, u32 data); 1103 enum rtw_rf_path rf_path; 1104 }; 1105 1106 static inline void rtw_load_table(struct rtw_dev *rtwdev, 1107 const struct rtw_table *tbl) 1108 { 1109 (*tbl->parse)(rtwdev, tbl); 1110 } 1111 1112 enum rtw_rfe_fem { 1113 RTW_RFE_IFEM, 1114 RTW_RFE_EFEM, 1115 RTW_RFE_IFEM2G_EFEM5G, 1116 RTW_RFE_NUM, 1117 }; 1118 1119 struct rtw_rfe_def { 1120 const struct rtw_table *phy_pg_tbl; 1121 const struct rtw_table *txpwr_lmt_tbl; 1122 const struct rtw_pwr_track_tbl *pwr_track_tbl; 1123 const struct rtw_table *agc_btg_tbl; 1124 }; 1125 1126 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt, track) { \ 1127 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1128 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1129 .pwr_track_tbl = &rtw ## chip ## _pwr_track_type ## track ## _tbl, \ 1130 } 1131 1132 #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, track, btg) { \ 1133 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1134 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1135 .pwr_track_tbl = &rtw ## chip ## _pwr_track_type ## track ## _tbl, \ 1136 .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \ 1137 } 1138 1139 #define RTW_PWR_TRK_5G_1 0 1140 #define RTW_PWR_TRK_5G_2 1 1141 #define RTW_PWR_TRK_5G_3 2 1142 #define RTW_PWR_TRK_5G_NUM 3 1143 1144 #define RTW_PWR_TRK_TBL_SZ 30 1145 1146 /* This table stores the values of TX power that will be adjusted by power 1147 * tracking. 1148 * 1149 * For 5G bands, there are 3 different settings. 1150 * For 2G there are cck rate and ofdm rate with different settings. 1151 */ 1152 struct rtw_pwr_track_tbl { 1153 const u8 *pwrtrk_5gd_n[RTW_PWR_TRK_5G_NUM]; 1154 const u8 *pwrtrk_5gd_p[RTW_PWR_TRK_5G_NUM]; 1155 const u8 *pwrtrk_5gc_n[RTW_PWR_TRK_5G_NUM]; 1156 const u8 *pwrtrk_5gc_p[RTW_PWR_TRK_5G_NUM]; 1157 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM]; 1158 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM]; 1159 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM]; 1160 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM]; 1161 const u8 *pwrtrk_2gd_n; 1162 const u8 *pwrtrk_2gd_p; 1163 const u8 *pwrtrk_2gc_n; 1164 const u8 *pwrtrk_2gc_p; 1165 const u8 *pwrtrk_2gb_n; 1166 const u8 *pwrtrk_2gb_p; 1167 const u8 *pwrtrk_2ga_n; 1168 const u8 *pwrtrk_2ga_p; 1169 const u8 *pwrtrk_2g_cckd_n; 1170 const u8 *pwrtrk_2g_cckd_p; 1171 const u8 *pwrtrk_2g_cckc_n; 1172 const u8 *pwrtrk_2g_cckc_p; 1173 const u8 *pwrtrk_2g_cckb_n; 1174 const u8 *pwrtrk_2g_cckb_p; 1175 const u8 *pwrtrk_2g_ccka_n; 1176 const u8 *pwrtrk_2g_ccka_p; 1177 const s8 *pwrtrk_xtal_n; 1178 const s8 *pwrtrk_xtal_p; 1179 }; 1180 1181 enum rtw_wlan_cpu { 1182 RTW_WCPU_3081, 1183 RTW_WCPU_8051, 1184 }; 1185 1186 enum rtw_fw_fifo_sel { 1187 RTW_FW_FIFO_SEL_TX, 1188 RTW_FW_FIFO_SEL_RX, 1189 RTW_FW_FIFO_SEL_RSVD_PAGE, 1190 RTW_FW_FIFO_SEL_REPORT, 1191 RTW_FW_FIFO_SEL_LLT, 1192 RTW_FW_FIFO_SEL_RXBUF_FW, 1193 1194 RTW_FW_FIFO_MAX, 1195 }; 1196 1197 enum rtw_fwcd_item { 1198 RTW_FWCD_TLV, 1199 RTW_FWCD_REG, 1200 RTW_FWCD_ROM, 1201 RTW_FWCD_IMEM, 1202 RTW_FWCD_DMEM, 1203 RTW_FWCD_EMEM, 1204 }; 1205 1206 /* hardware configuration for each IC */ 1207 struct rtw_chip_info { 1208 const struct rtw_chip_ops *ops; 1209 u8 id; 1210 1211 const char *fw_name; 1212 enum rtw_wlan_cpu wlan_cpu; 1213 u8 tx_pkt_desc_sz; 1214 u8 tx_buf_desc_sz; 1215 u8 rx_pkt_desc_sz; 1216 u8 rx_buf_desc_sz; 1217 u32 phy_efuse_size; 1218 u32 log_efuse_size; 1219 u32 ptct_efuse_size; 1220 u32 txff_size; 1221 u32 rxff_size; 1222 u32 fw_rxff_size; 1223 u16 rsvd_drv_pg_num; 1224 u8 band; 1225 u16 page_size; 1226 u8 csi_buf_pg_num; 1227 u8 dig_max; 1228 u8 dig_min; 1229 u8 txgi_factor; 1230 bool is_pwr_by_rate_dec; 1231 bool rx_ldpc; 1232 bool tx_stbc; 1233 u8 max_power_index; 1234 u8 ampdu_density; 1235 1236 u16 fw_fifo_addr[RTW_FW_FIFO_MAX]; 1237 const struct rtw_fwcd_segs *fwcd_segs; 1238 1239 bool amsdu_in_ampdu; 1240 u8 usb_tx_agg_desc_num; 1241 bool hw_feature_report; 1242 u8 c2h_ra_report_size; 1243 bool old_datarate_fb_limit; 1244 1245 u8 default_1ss_tx_path; 1246 1247 bool path_div_supported; 1248 bool ht_supported; 1249 bool vht_supported; 1250 u8 lps_deep_mode_supported; 1251 1252 /* init values */ 1253 u8 sys_func_en; 1254 const struct rtw_pwr_seq_cmd * const *pwr_on_seq; 1255 const struct rtw_pwr_seq_cmd * const *pwr_off_seq; 1256 const struct rtw_rqpn *rqpn_table; 1257 const struct rtw_prioq_addrs *prioq_addrs; 1258 const struct rtw_page_table *page_table; 1259 const struct rtw_intf_phy_para_table *intf_table; 1260 1261 const struct rtw_hw_reg *dig; 1262 const struct rtw_hw_reg *dig_cck; 1263 u32 rf_base_addr[RTW_RF_PATH_MAX]; 1264 u32 rf_sipi_addr[RTW_RF_PATH_MAX]; 1265 const struct rtw_rf_sipi_addr *rf_sipi_read_addr; 1266 u8 fix_rf_phy_num; 1267 const struct rtw_ltecoex_addr *ltecoex_addr; 1268 1269 const struct rtw_table *mac_tbl; 1270 const struct rtw_table *agc_tbl; 1271 const struct rtw_table *bb_tbl; 1272 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX]; 1273 const struct rtw_table *rfk_init_tbl; 1274 1275 const struct rtw_rfe_def *rfe_defs; 1276 u32 rfe_defs_size; 1277 1278 bool en_dis_dpd; 1279 u16 dpd_ratemask; 1280 u8 iqk_threshold; 1281 u8 lck_threshold; 1282 1283 u8 bfer_su_max_num; 1284 u8 bfer_mu_max_num; 1285 1286 const struct rtw_hw_reg_offset *edcca_th; 1287 s8 l2h_th_ini_cs; 1288 s8 l2h_th_ini_ad; 1289 1290 const char *wow_fw_name; 1291 const struct wiphy_wowlan_support *wowlan_stub; 1292 const u8 max_sched_scan_ssids; 1293 const u16 max_scan_ie_len; 1294 1295 /* coex paras */ 1296 u32 coex_para_ver; 1297 u8 bt_desired_ver; 1298 bool scbd_support; 1299 bool new_scbd10_def; /* true: fix 2M(8822c) */ 1300 bool ble_hid_profile_support; 1301 bool wl_mimo_ps_support; 1302 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */ 1303 u8 bt_rssi_type; 1304 u8 ant_isolation; 1305 u8 rssi_tolerance; 1306 u8 table_sant_num; 1307 u8 table_nsant_num; 1308 u8 tdma_sant_num; 1309 u8 tdma_nsant_num; 1310 u8 bt_afh_span_bw20; 1311 u8 bt_afh_span_bw40; 1312 u8 afh_5g_num; 1313 u8 wl_rf_para_num; 1314 u8 coex_info_hw_regs_num; 1315 const u8 *bt_rssi_step; 1316 const u8 *wl_rssi_step; 1317 const struct coex_table_para *table_nsant; 1318 const struct coex_table_para *table_sant; 1319 const struct coex_tdma_para *tdma_sant; 1320 const struct coex_tdma_para *tdma_nsant; 1321 const struct coex_rf_para *wl_rf_para_tx; 1322 const struct coex_rf_para *wl_rf_para_rx; 1323 const struct coex_5g_afh_map *afh_5g; 1324 const struct rtw_hw_reg *btg_reg; 1325 const struct rtw_reg_domain *coex_info_hw_regs; 1326 u32 wl_fw_desired_ver; 1327 }; 1328 1329 enum rtw_coex_bt_state_cnt { 1330 COEX_CNT_BT_RETRY, 1331 COEX_CNT_BT_REINIT, 1332 COEX_CNT_BT_REENABLE, 1333 COEX_CNT_BT_POPEVENT, 1334 COEX_CNT_BT_SETUPLINK, 1335 COEX_CNT_BT_IGNWLANACT, 1336 COEX_CNT_BT_INQ, 1337 COEX_CNT_BT_PAGE, 1338 COEX_CNT_BT_ROLESWITCH, 1339 COEX_CNT_BT_AFHUPDATE, 1340 COEX_CNT_BT_INFOUPDATE, 1341 COEX_CNT_BT_IQK, 1342 COEX_CNT_BT_IQKFAIL, 1343 1344 COEX_CNT_BT_MAX 1345 }; 1346 1347 enum rtw_coex_wl_state_cnt { 1348 COEX_CNT_WL_SCANAP, 1349 COEX_CNT_WL_CONNPKT, 1350 COEX_CNT_WL_COEXRUN, 1351 COEX_CNT_WL_NOISY0, 1352 COEX_CNT_WL_NOISY1, 1353 COEX_CNT_WL_NOISY2, 1354 COEX_CNT_WL_5MS_NOEXTEND, 1355 COEX_CNT_WL_FW_NOTIFY, 1356 1357 COEX_CNT_WL_MAX 1358 }; 1359 1360 struct rtw_coex_rfe { 1361 bool ant_switch_exist; 1362 bool ant_switch_diversity; 1363 bool ant_switch_with_bt; 1364 u8 rfe_module_type; 1365 u8 ant_switch_polarity; 1366 1367 /* true if WLG at BTG, else at WLAG */ 1368 bool wlg_at_btg; 1369 }; 1370 1371 #define COEX_WL_TDMA_PARA_LENGTH 5 1372 1373 struct rtw_coex_dm { 1374 bool cur_ps_tdma_on; 1375 bool cur_wl_rx_low_gain_en; 1376 bool ignore_wl_act; 1377 1378 u8 reason; 1379 u8 bt_rssi_state[4]; 1380 u8 wl_rssi_state[4]; 1381 u8 wl_ch_info[3]; 1382 u8 cur_ps_tdma; 1383 u8 cur_table; 1384 u8 ps_tdma_para[5]; 1385 u8 cur_bt_pwr_lvl; 1386 u8 cur_bt_lna_lvl; 1387 u8 cur_wl_pwr_lvl; 1388 u8 bt_status; 1389 u32 cur_ant_pos_type; 1390 u32 cur_switch_status; 1391 u32 setting_tdma; 1392 u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH]; 1393 }; 1394 1395 #define COEX_BTINFO_SRC_WL_FW 0x0 1396 #define COEX_BTINFO_SRC_BT_RSP 0x1 1397 #define COEX_BTINFO_SRC_BT_ACT 0x2 1398 #define COEX_BTINFO_SRC_BT_IQK 0x3 1399 #define COEX_BTINFO_SRC_BT_SCBD 0x4 1400 #define COEX_BTINFO_SRC_H2C60 0x5 1401 #define COEX_BTINFO_SRC_MAX 0x6 1402 1403 #define COEX_INFO_FTP BIT(7) 1404 #define COEX_INFO_A2DP BIT(6) 1405 #define COEX_INFO_HID BIT(5) 1406 #define COEX_INFO_SCO_BUSY BIT(4) 1407 #define COEX_INFO_ACL_BUSY BIT(3) 1408 #define COEX_INFO_INQ_PAGE BIT(2) 1409 #define COEX_INFO_SCO_ESCO BIT(1) 1410 #define COEX_INFO_CONNECTION BIT(0) 1411 #define COEX_BTINFO_LENGTH_MAX 10 1412 #define COEX_BTINFO_LENGTH 7 1413 1414 #define COEX_BT_HIDINFO_LIST 0x0 1415 #define COEX_BT_HIDINFO_A 0x1 1416 #define COEX_BT_HIDINFO_NAME 3 1417 1418 #define COEX_BT_HIDINFO_LENGTH 6 1419 #define COEX_BT_HIDINFO_HANDLE_NUM 4 1420 #define COEX_BT_HIDINFO_C2H_HANDLE 0 1421 #define COEX_BT_HIDINFO_C2H_VENDOR 1 1422 #define COEX_BT_BLE_HANDLE_THRS 0x10 1423 #define COEX_BT_HIDINFO_NOTCON 0xff 1424 1425 struct rtw_coex_hid { 1426 u8 hid_handle; 1427 u8 hid_vendor; 1428 u8 hid_name[COEX_BT_HIDINFO_NAME]; 1429 bool hid_info_completed; 1430 bool is_game_hid; 1431 }; 1432 1433 struct rtw_coex_hid_handle_list { 1434 u8 cmd_id; 1435 u8 len; 1436 u8 subid; 1437 u8 handle_cnt; 1438 u8 handle[COEX_BT_HIDINFO_HANDLE_NUM]; 1439 } __packed; 1440 1441 struct rtw_coex_hid_info_a { 1442 u8 cmd_id; 1443 u8 len; 1444 u8 subid; 1445 u8 handle; 1446 u8 vendor; 1447 u8 name[COEX_BT_HIDINFO_NAME]; 1448 } __packed; 1449 1450 struct rtw_coex_stat { 1451 bool bt_disabled; 1452 bool bt_disabled_pre; 1453 bool bt_link_exist; 1454 bool bt_whck_test; 1455 bool bt_inq_page; 1456 bool bt_inq_remain; 1457 bool bt_inq; 1458 bool bt_page; 1459 bool bt_ble_voice; 1460 bool bt_ble_exist; 1461 bool bt_hfp_exist; 1462 bool bt_a2dp_exist; 1463 bool bt_hid_exist; 1464 bool bt_pan_exist; /* PAN or OPP */ 1465 bool bt_opp_exist; /* OPP only */ 1466 bool bt_acl_busy; 1467 bool bt_fix_2M; 1468 bool bt_setup_link; 1469 bool bt_multi_link; 1470 bool bt_multi_link_pre; 1471 bool bt_multi_link_remain; 1472 bool bt_a2dp_sink; 1473 bool bt_a2dp_active; 1474 bool bt_reenable; 1475 bool bt_ble_scan_en; 1476 bool bt_init_scan; 1477 bool bt_slave; 1478 bool bt_418_hid_exist; 1479 bool bt_ble_hid_exist; 1480 bool bt_game_hid_exist; 1481 bool bt_hid_handle_cnt; 1482 bool bt_mailbox_reply; 1483 bool bt_ctr_ok; 1484 1485 bool wl_under_lps; 1486 bool wl_under_ips; 1487 bool wl_hi_pri_task1; 1488 bool wl_hi_pri_task2; 1489 bool wl_force_lps_ctrl; 1490 bool wl_gl_busy; 1491 bool wl_linkscan_proc; 1492 bool wl_ps_state_fail; 1493 bool wl_tx_limit_en; 1494 bool wl_ampdu_limit_en; 1495 bool wl_connected; 1496 bool wl_slot_extend; 1497 bool wl_cck_lock; 1498 bool wl_cck_lock_pre; 1499 bool wl_cck_lock_ever; 1500 bool wl_connecting; 1501 bool wl_slot_toggle; 1502 bool wl_slot_toggle_change; /* if toggle to no-toggle */ 1503 bool wl_mimo_ps; 1504 1505 u32 bt_supported_version; 1506 u32 bt_supported_feature; 1507 u32 hi_pri_tx; 1508 u32 hi_pri_rx; 1509 u32 lo_pri_tx; 1510 u32 lo_pri_rx; 1511 u32 patch_ver; 1512 u16 bt_reg_vendor_ae; 1513 u16 bt_reg_vendor_ac; 1514 s8 bt_rssi; 1515 u8 kt_ver; 1516 u8 gnt_workaround_state; 1517 u8 tdma_timer_base; 1518 u8 bt_profile_num; 1519 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX]; 1520 u8 bt_info_lb2; 1521 u8 bt_info_lb3; 1522 u8 bt_info_hb0; 1523 u8 bt_info_hb1; 1524 u8 bt_info_hb2; 1525 u8 bt_info_hb3; 1526 u8 bt_ble_scan_type; 1527 u8 bt_hid_pair_num; 1528 u8 bt_hid_slot; 1529 u8 bt_a2dp_bitpool; 1530 u8 bt_iqk_state; 1531 u8 bt_disable_cnt; 1532 1533 u16 wl_beacon_interval; 1534 u8 wl_noisy_level; 1535 u8 wl_fw_dbg_info[10]; 1536 u8 wl_fw_dbg_info_pre[10]; 1537 u8 wl_rx_rate; 1538 u8 wl_tx_rate; 1539 u8 wl_rts_rx_rate; 1540 u8 wl_coex_mode; 1541 u8 wl_iot_peer; 1542 u8 ampdu_max_time; 1543 u8 wl_tput_dir; 1544 1545 u8 wl_toggle_para[6]; 1546 u8 wl_toggle_interval; 1547 1548 u16 score_board; 1549 u16 retry_limit; 1550 1551 /* counters to record bt states */ 1552 u32 cnt_bt[COEX_CNT_BT_MAX]; 1553 1554 /* counters to record wifi states */ 1555 u32 cnt_wl[COEX_CNT_WL_MAX]; 1556 1557 /* counters to record bt c2h data */ 1558 u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX]; 1559 1560 u32 darfrc; 1561 u32 darfrch; 1562 1563 struct rtw_coex_hid hid_info[COEX_BT_HIDINFO_HANDLE_NUM]; 1564 struct rtw_coex_hid_handle_list hid_handle_list; 1565 }; 1566 1567 struct rtw_coex { 1568 struct sk_buff_head queue; 1569 wait_queue_head_t wait; 1570 1571 bool under_5g; 1572 bool stop_dm; 1573 bool freeze; 1574 bool freerun; 1575 bool wl_rf_off; 1576 bool manual_control; 1577 1578 struct rtw_coex_stat stat; 1579 struct rtw_coex_dm dm; 1580 struct rtw_coex_rfe rfe; 1581 1582 struct delayed_work bt_relink_work; 1583 struct delayed_work bt_reenable_work; 1584 struct delayed_work defreeze_work; 1585 struct delayed_work wl_remain_work; 1586 struct delayed_work bt_remain_work; 1587 struct delayed_work wl_connecting_work; 1588 struct delayed_work bt_multi_link_remain_work; 1589 struct delayed_work wl_ccklock_work; 1590 1591 }; 1592 1593 #define DPK_RF_REG_NUM 7 1594 #define DPK_RF_PATH_NUM 2 1595 #define DPK_BB_REG_NUM 18 1596 #define DPK_CHANNEL_WIDTH_80 1 1597 1598 DECLARE_EWMA(thermal, 10, 4); 1599 1600 struct rtw_dpk_info { 1601 bool is_dpk_pwr_on; 1602 bool is_reload; 1603 1604 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM); 1605 1606 u8 thermal_dpk[DPK_RF_PATH_NUM]; 1607 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM]; 1608 1609 u32 gnt_control; 1610 u32 gnt_value; 1611 1612 u8 result[RTW_RF_PATH_MAX]; 1613 u8 dpk_txagc[RTW_RF_PATH_MAX]; 1614 u32 coef[RTW_RF_PATH_MAX][20]; 1615 u16 dpk_gs[RTW_RF_PATH_MAX]; 1616 u8 thermal_dpk_delta[RTW_RF_PATH_MAX]; 1617 u8 pre_pwsf[RTW_RF_PATH_MAX]; 1618 1619 u8 dpk_band; 1620 u8 dpk_ch; 1621 u8 dpk_bw; 1622 }; 1623 1624 struct rtw_phy_cck_pd_reg { 1625 u32 reg_pd; 1626 u32 mask_pd; 1627 u32 reg_cs; 1628 u32 mask_cs; 1629 }; 1630 1631 #define DACK_MSBK_BACKUP_NUM 0xf 1632 #define DACK_DCK_BACKUP_NUM 0x2 1633 1634 struct rtw_swing_table { 1635 const u8 *p[RTW_RF_PATH_MAX]; 1636 const u8 *n[RTW_RF_PATH_MAX]; 1637 }; 1638 1639 struct rtw_pkt_count { 1640 u16 num_bcn_pkt; 1641 u16 num_qry_pkt[DESC_RATE_MAX]; 1642 }; 1643 1644 DECLARE_EWMA(evm, 10, 4); 1645 DECLARE_EWMA(snr, 10, 4); 1646 1647 struct rtw_iqk_info { 1648 bool done; 1649 struct { 1650 u32 s1_x; 1651 u32 s1_y; 1652 u32 s0_x; 1653 u32 s0_y; 1654 } result; 1655 }; 1656 1657 enum rtw_rf_band { 1658 RF_BAND_2G_CCK, 1659 RF_BAND_2G_OFDM, 1660 RF_BAND_5G_L, 1661 RF_BAND_5G_M, 1662 RF_BAND_5G_H, 1663 RF_BAND_MAX 1664 }; 1665 1666 #define RF_GAIN_NUM 11 1667 #define RF_HW_OFFSET_NUM 10 1668 1669 struct rtw_gapk_info { 1670 u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1671 u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM]; 1672 bool txgapk_bp_done; 1673 s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1674 s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1675 u8 read_txgain; 1676 u8 channel; 1677 }; 1678 1679 #define EDCCA_TH_L2H_IDX 0 1680 #define EDCCA_TH_H2L_IDX 1 1681 #define EDCCA_TH_L2H_LB 48 1682 #define EDCCA_ADC_BACKOFF 12 1683 #define EDCCA_IGI_BASE 50 1684 #define EDCCA_IGI_L2H_DIFF 8 1685 #define EDCCA_L2H_H2L_DIFF 7 1686 #define EDCCA_L2H_H2L_DIFF_NORMAL 8 1687 1688 enum rtw_edcca_mode { 1689 RTW_EDCCA_NORMAL = 0, 1690 RTW_EDCCA_ADAPTIVITY = 1, 1691 }; 1692 1693 struct rtw_cfo_track { 1694 bool is_adjust; 1695 u8 crystal_cap; 1696 s32 cfo_tail[RTW_RF_PATH_MAX]; 1697 s32 cfo_cnt[RTW_RF_PATH_MAX]; 1698 u32 packet_count; 1699 u32 packet_count_pre; 1700 }; 1701 1702 #define RRSR_INIT_2G 0x15f 1703 #define RRSR_INIT_5G 0x150 1704 1705 enum rtw_dm_cap { 1706 RTW_DM_CAP_NA, 1707 RTW_DM_CAP_TXGAPK, 1708 RTW_DM_CAP_NUM 1709 }; 1710 1711 struct rtw_dm_info { 1712 u32 cck_fa_cnt; 1713 u32 ofdm_fa_cnt; 1714 u32 total_fa_cnt; 1715 u32 cck_cca_cnt; 1716 u32 ofdm_cca_cnt; 1717 u32 total_cca_cnt; 1718 1719 u32 cck_ok_cnt; 1720 u32 cck_err_cnt; 1721 u32 ofdm_ok_cnt; 1722 u32 ofdm_err_cnt; 1723 u32 ht_ok_cnt; 1724 u32 ht_err_cnt; 1725 u32 vht_ok_cnt; 1726 u32 vht_err_cnt; 1727 1728 u8 min_rssi; 1729 u8 pre_min_rssi; 1730 u16 fa_history[4]; 1731 u8 igi_history[4]; 1732 u8 igi_bitmap; 1733 bool damping; 1734 u8 damping_cnt; 1735 u8 damping_rssi; 1736 1737 u8 cck_gi_u_bnd; 1738 u8 cck_gi_l_bnd; 1739 1740 u8 fix_rate; 1741 u8 tx_rate; 1742 u32 rrsr_val_init; 1743 u32 rrsr_mask_min; 1744 u8 thermal_avg[RTW_RF_PATH_MAX]; 1745 u8 thermal_meter_k; 1746 u8 thermal_meter_lck; 1747 s8 delta_power_index[RTW_RF_PATH_MAX]; 1748 s8 delta_power_index_last[RTW_RF_PATH_MAX]; 1749 u8 default_ofdm_index; 1750 u8 default_cck_index; 1751 bool pwr_trk_triggered; 1752 bool pwr_trk_init_trigger; 1753 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX]; 1754 s8 txagc_remnant_cck; 1755 s8 txagc_remnant_ofdm[RTW_RF_PATH_MAX]; 1756 u8 rx_cck_agc_report_type; 1757 1758 /* backup dack results for each path and I/Q */ 1759 u32 dack_adck[RTW_RF_PATH_MAX]; 1760 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM]; 1761 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM]; 1762 1763 struct rtw_dpk_info dpk_info; 1764 struct rtw_cfo_track cfo_track; 1765 1766 /* [bandwidth 0:20M/1:40M][number of path] */ 1767 u8 cck_pd_lv[2][RTW_RF_PATH_MAX]; 1768 u32 cck_fa_avg; 1769 u8 cck_pd_default; 1770 1771 /* save the last rx phy status for debug */ 1772 s8 rx_snr[RTW_RF_PATH_MAX]; 1773 u8 rx_evm_dbm[RTW_RF_PATH_MAX]; 1774 s16 cfo_tail[RTW_RF_PATH_MAX]; 1775 u8 rssi[RTW_RF_PATH_MAX]; 1776 u8 curr_rx_rate; 1777 struct rtw_pkt_count cur_pkt_count; 1778 struct rtw_pkt_count last_pkt_count; 1779 struct ewma_evm ewma_evm[RTW_EVM_NUM]; 1780 struct ewma_snr ewma_snr[RTW_SNR_NUM]; 1781 1782 u32 dm_flags; /* enum rtw_dm_cap */ 1783 struct rtw_iqk_info iqk; 1784 struct rtw_gapk_info gapk; 1785 bool is_bt_iqk_timeout; 1786 1787 s8 l2h_th_ini; 1788 enum rtw_edcca_mode edcca_mode; 1789 u8 scan_density; 1790 }; 1791 1792 struct rtw_efuse { 1793 u32 size; 1794 u32 physical_size; 1795 u32 logical_size; 1796 u32 protect_size; 1797 1798 u8 addr[ETH_ALEN]; 1799 u8 channel_plan; 1800 u8 country_code[2]; 1801 u8 rf_board_option; 1802 u8 rfe_option; 1803 u8 power_track_type; 1804 u8 thermal_meter[RTW_RF_PATH_MAX]; 1805 u8 thermal_meter_k; 1806 u8 crystal_cap; 1807 u8 ant_div_cfg; 1808 u8 ant_div_type; 1809 u8 regd; 1810 u8 afe; 1811 1812 u8 lna_type_2g; 1813 u8 lna_type_5g; 1814 u8 glna_type; 1815 u8 alna_type; 1816 bool ext_lna_2g; 1817 bool ext_lna_5g; 1818 u8 pa_type_2g; 1819 u8 pa_type_5g; 1820 u8 gpa_type; 1821 u8 apa_type; 1822 bool ext_pa_2g; 1823 bool ext_pa_5g; 1824 u8 tx_bb_swing_setting_2g; 1825 u8 tx_bb_swing_setting_5g; 1826 1827 bool btcoex; 1828 /* bt share antenna with wifi */ 1829 bool share_ant; 1830 u8 bt_setting; 1831 1832 u8 usb_mode_switch; 1833 1834 struct { 1835 u8 hci; 1836 u8 bw; 1837 u8 ptcl; 1838 u8 nss; 1839 u8 ant_num; 1840 } hw_cap; 1841 1842 struct rtw_txpwr_idx txpwr_idx_table[4]; 1843 }; 1844 1845 struct rtw_phy_cond { 1846 #ifdef __LITTLE_ENDIAN 1847 u32 rfe:8; 1848 u32 intf:4; 1849 u32 pkg:4; 1850 u32 plat:4; 1851 u32 intf_rsvd:4; 1852 u32 cut:4; 1853 u32 branch:2; 1854 u32 neg:1; 1855 u32 pos:1; 1856 #else 1857 u32 pos:1; 1858 u32 neg:1; 1859 u32 branch:2; 1860 u32 cut:4; 1861 u32 intf_rsvd:4; 1862 u32 plat:4; 1863 u32 pkg:4; 1864 u32 intf:4; 1865 u32 rfe:8; 1866 #endif 1867 /* for intf:4 */ 1868 #define INTF_PCIE BIT(0) 1869 #define INTF_USB BIT(1) 1870 #define INTF_SDIO BIT(2) 1871 /* for branch:2 */ 1872 #define BRANCH_IF 0 1873 #define BRANCH_ELIF 1 1874 #define BRANCH_ELSE 2 1875 #define BRANCH_ENDIF 3 1876 }; 1877 1878 struct rtw_phy_cond2 { 1879 #ifdef __LITTLE_ENDIAN 1880 u8 type_glna; 1881 u8 type_gpa; 1882 u8 type_alna; 1883 u8 type_apa; 1884 #else 1885 u8 type_apa; 1886 u8 type_alna; 1887 u8 type_gpa; 1888 u8 type_glna; 1889 #endif 1890 }; 1891 1892 struct rtw_fifo_conf { 1893 /* tx fifo information */ 1894 u16 rsvd_boundary; 1895 u16 rsvd_pg_num; 1896 u16 rsvd_drv_pg_num; 1897 u16 txff_pg_num; 1898 u16 acq_pg_num; 1899 u16 rsvd_drv_addr; 1900 u16 rsvd_h2c_info_addr; 1901 u16 rsvd_h2c_sta_info_addr; 1902 u16 rsvd_h2cq_addr; 1903 u16 rsvd_cpu_instr_addr; 1904 u16 rsvd_fw_txbuf_addr; 1905 u16 rsvd_csibuf_addr; 1906 const struct rtw_rqpn *rqpn; 1907 }; 1908 1909 struct rtw_fwcd_desc { 1910 u32 size; 1911 u8 *next; 1912 u8 *data; 1913 }; 1914 1915 struct rtw_fwcd_segs { 1916 const u32 *segs; 1917 u8 num; 1918 }; 1919 1920 #define FW_CD_TYPE 0xffff 1921 #define FW_CD_LEN 4 1922 #define FW_CD_VAL 0xaabbccdd 1923 struct rtw_fw_state { 1924 const struct firmware *firmware; 1925 struct rtw_dev *rtwdev; 1926 struct completion completion; 1927 struct rtw_fwcd_desc fwcd_desc; 1928 u16 version; 1929 u8 sub_version; 1930 u8 sub_index; 1931 u16 h2c_version; 1932 u32 feature; 1933 u32 feature_ext; 1934 enum rtw_fw_type type; 1935 }; 1936 1937 enum rtw_sar_sources { 1938 RTW_SAR_SOURCE_NONE, 1939 RTW_SAR_SOURCE_COMMON, 1940 }; 1941 1942 enum rtw_sar_bands { 1943 RTW_SAR_BAND_0, 1944 RTW_SAR_BAND_1, 1945 /* RTW_SAR_BAND_2, not used now */ 1946 RTW_SAR_BAND_3, 1947 RTW_SAR_BAND_4, 1948 1949 RTW_SAR_BAND_NR, 1950 }; 1951 1952 /* the union is reserved for other kinds of SAR sources 1953 * which might not re-use same format with array common. 1954 */ 1955 union rtw_sar_cfg { 1956 s8 common[RTW_SAR_BAND_NR]; 1957 }; 1958 1959 struct rtw_sar { 1960 enum rtw_sar_sources src; 1961 union rtw_sar_cfg cfg[RTW_RF_PATH_MAX][RTW_RATE_SECTION_NUM]; 1962 }; 1963 1964 struct rtw_hal { 1965 u32 rcr; 1966 1967 u32 chip_version; 1968 u8 cut_version; 1969 u8 mp_chip; 1970 u8 oem_id; 1971 u8 pkg_type; 1972 struct rtw_phy_cond phy_cond; 1973 struct rtw_phy_cond2 phy_cond2; 1974 bool rfe_btg; 1975 1976 u8 ps_mode; 1977 u8 current_channel; 1978 u8 current_primary_channel_index; 1979 u8 current_band_width; 1980 u8 current_band_type; 1981 u8 primary_channel; 1982 1983 /* center channel for different available bandwidth, 1984 * val of (bw > current_band_width) is invalid 1985 */ 1986 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 1987 1988 u8 sec_ch_offset; 1989 u8 rf_type; 1990 u8 rf_path_num; 1991 u8 rf_phy_num; 1992 u32 antenna_tx; 1993 u32 antenna_rx; 1994 u8 bfee_sts_cap; 1995 bool txrx_1ss; 1996 bool cck_high_power; 1997 1998 /* protect tx power section */ 1999 struct mutex tx_power_mutex; 2000 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX] 2001 [DESC_RATE_MAX]; 2002 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX] 2003 [DESC_RATE_MAX]; 2004 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX] 2005 [RTW_RATE_SECTION_NUM]; 2006 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX] 2007 [RTW_RATE_SECTION_NUM]; 2008 s8 tx_pwr_limit_2g[RTW_REGD_MAX] 2009 [RTW_CHANNEL_WIDTH_MAX] 2010 [RTW_RATE_SECTION_NUM] 2011 [RTW_MAX_CHANNEL_NUM_2G]; 2012 s8 tx_pwr_limit_5g[RTW_REGD_MAX] 2013 [RTW_CHANNEL_WIDTH_MAX] 2014 [RTW_RATE_SECTION_NUM] 2015 [RTW_MAX_CHANNEL_NUM_5G]; 2016 s8 tx_pwr_tbl[RTW_RF_PATH_MAX] 2017 [DESC_RATE_MAX]; 2018 2019 enum rtw_sar_bands sar_band; 2020 struct rtw_sar sar; 2021 2022 /* for 8821c set channel */ 2023 u32 ch_param[3]; 2024 }; 2025 2026 struct rtw_path_div { 2027 enum rtw_bb_path current_tx_path; 2028 u32 path_a_sum; 2029 u32 path_b_sum; 2030 u16 path_a_cnt; 2031 u16 path_b_cnt; 2032 }; 2033 2034 struct rtw_chan_info { 2035 int pri_ch_idx; 2036 int action_id; 2037 int bw; 2038 u8 extra_info; 2039 u8 channel; 2040 u16 timeout; 2041 }; 2042 2043 struct rtw_chan_list { 2044 u32 buf_size; 2045 u32 ch_num; 2046 u32 size; 2047 u16 addr; 2048 }; 2049 2050 struct rtw_hw_scan_info { 2051 struct ieee80211_vif *scanning_vif; 2052 u8 probe_pg_size; 2053 u8 op_pri_ch_idx; 2054 u8 op_pri_ch; 2055 u8 op_chan; 2056 u8 op_bw; 2057 }; 2058 2059 struct rtw_dev { 2060 struct ieee80211_hw *hw; 2061 struct device *dev; 2062 2063 struct rtw_hci hci; 2064 2065 struct rtw_hw_scan_info scan_info; 2066 const struct rtw_chip_info *chip; 2067 struct rtw_hal hal; 2068 struct rtw_fifo_conf fifo; 2069 struct rtw_fw_state fw; 2070 struct rtw_efuse efuse; 2071 struct rtw_sec_desc sec; 2072 struct rtw_traffic_stats stats; 2073 struct rtw_regd regd; 2074 struct rtw_bf_info bf_info; 2075 2076 struct rtw_dm_info dm_info; 2077 struct rtw_coex coex; 2078 2079 /* ensures exclusive access from mac80211 callbacks */ 2080 struct mutex mutex; 2081 2082 /* watch dog every 2 sec */ 2083 struct delayed_work watch_dog_work; 2084 u32 watch_dog_cnt; 2085 2086 struct list_head rsvd_page_list; 2087 2088 /* c2h cmd queue & handler work */ 2089 struct sk_buff_head c2h_queue; 2090 struct work_struct c2h_work; 2091 struct work_struct ips_work; 2092 struct work_struct fw_recovery_work; 2093 struct work_struct update_beacon_work; 2094 2095 /* used to protect txqs list */ 2096 spinlock_t txq_lock; 2097 struct list_head txqs; 2098 struct workqueue_struct *tx_wq; 2099 struct work_struct tx_work; 2100 struct work_struct ba_work; 2101 2102 struct rtw_tx_report tx_report; 2103 2104 struct { 2105 /* indicate the mail box to use with fw */ 2106 u8 last_box_num; 2107 u32 seq; 2108 } h2c; 2109 2110 /* lps power state & handler work */ 2111 struct rtw_lps_conf lps_conf; 2112 bool ps_enabled; 2113 bool beacon_loss; 2114 struct completion lps_leave_check; 2115 2116 struct rtw_debugfs *debugfs; 2117 2118 u8 sta_cnt; 2119 u32 rts_threshold; 2120 2121 DECLARE_BITMAP(hw_port, RTW_PORT_NUM); 2122 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM); 2123 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS); 2124 2125 u8 mp_mode; 2126 struct rtw_path_div dm_path_div; 2127 2128 struct rtw_fw_state wow_fw; 2129 struct rtw_wow_param wow; 2130 2131 bool need_rfk; 2132 struct completion fw_scan_density; 2133 bool ap_active; 2134 2135 bool led_registered; 2136 char led_name[32]; 2137 struct led_classdev led_cdev; 2138 2139 /* hci related data, must be last */ 2140 u8 priv[] __aligned(sizeof(void *)); 2141 }; 2142 2143 #include "hci.h" 2144 2145 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev) 2146 { 2147 return !!rtwdev->sta_cnt; 2148 } 2149 2150 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq) 2151 { 2152 void *p = rtwtxq; 2153 2154 return container_of(p, struct ieee80211_txq, drv_priv); 2155 } 2156 2157 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif) 2158 { 2159 void *p = rtwvif; 2160 2161 return container_of(p, struct ieee80211_vif, drv_priv); 2162 } 2163 2164 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev) 2165 { 2166 if (rtwdev->chip->ops->efuse_grant) 2167 rtwdev->chip->ops->efuse_grant(rtwdev, true); 2168 } 2169 2170 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev) 2171 { 2172 if (rtwdev->chip->ops->efuse_grant) 2173 rtwdev->chip->ops->efuse_grant(rtwdev, false); 2174 } 2175 2176 static inline bool rtw_chip_wcpu_8051(struct rtw_dev *rtwdev) 2177 { 2178 return rtwdev->chip->wlan_cpu == RTW_WCPU_8051; 2179 } 2180 2181 static inline bool rtw_chip_wcpu_3081(struct rtw_dev *rtwdev) 2182 { 2183 return rtwdev->chip->wlan_cpu == RTW_WCPU_3081; 2184 } 2185 2186 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev) 2187 { 2188 return rtwdev->chip->rx_ldpc; 2189 } 2190 2191 static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev) 2192 { 2193 return rtwdev->chip->tx_stbc; 2194 } 2195 2196 static inline u8 rtw_acquire_macid(struct rtw_dev *rtwdev) 2197 { 2198 unsigned long mac_id; 2199 2200 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM); 2201 if (mac_id < RTW_MAX_MAC_ID_NUM) 2202 set_bit(mac_id, rtwdev->mac_id_map); 2203 2204 return mac_id; 2205 } 2206 2207 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id) 2208 { 2209 clear_bit(mac_id, rtwdev->mac_id_map); 2210 } 2211 2212 static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev) 2213 { 2214 if (rtwdev->chip->ops->dump_fw_crash) 2215 return rtwdev->chip->ops->dump_fw_crash(rtwdev); 2216 2217 return 0; 2218 } 2219 2220 static inline 2221 enum nl80211_band rtw_hw_to_nl80211_band(enum rtw_supported_band hw_band) 2222 { 2223 switch (hw_band) { 2224 default: 2225 case RTW_BAND_2G: 2226 return NL80211_BAND_2GHZ; 2227 case RTW_BAND_5G: 2228 return NL80211_BAND_5GHZ; 2229 case RTW_BAND_60G: 2230 return NL80211_BAND_60GHZ; 2231 } 2232 } 2233 2234 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel); 2235 void rtw_set_dtim_period(struct rtw_dev *rtwdev, u8 dtim_period); 2236 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 2237 struct rtw_channel_params *ch_param); 2238 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); 2239 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); 2240 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value); 2241 void rtw_restore_reg(struct rtw_dev *rtwdev, 2242 struct rtw_backup_info *bckp, u32 num); 2243 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss); 2244 void rtw_set_channel(struct rtw_dev *rtwdev); 2245 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev); 2246 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 2247 u32 config); 2248 void rtw_tx_report_purge_timer(struct timer_list *t); 2249 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 2250 bool reset_ra_mask); 2251 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 2252 const u8 *mac_addr, bool hw_scan); 2253 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 2254 bool hw_scan); 2255 int rtw_core_start(struct rtw_dev *rtwdev); 2256 void rtw_power_off(struct rtw_dev *rtwdev); 2257 void rtw_core_stop(struct rtw_dev *rtwdev); 2258 int rtw_chip_info_setup(struct rtw_dev *rtwdev); 2259 int rtw_core_init(struct rtw_dev *rtwdev); 2260 void rtw_core_deinit(struct rtw_dev *rtwdev); 2261 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 2262 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 2263 u16 rtw_desc_to_bitrate(u8 desc_rate); 2264 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 2265 struct ieee80211_bss_conf *conf); 2266 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 2267 struct ieee80211_vif *vif); 2268 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 2269 bool fw_exist); 2270 void rtw_fw_recovery(struct rtw_dev *rtwdev); 2271 int rtw_wait_firmware_completion(struct rtw_dev *rtwdev); 2272 int rtw_power_on(struct rtw_dev *rtwdev); 2273 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start); 2274 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 2275 u32 fwcd_item); 2276 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size); 2277 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool config_1ss); 2278 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel, 2279 u8 primary_channel, enum rtw_supported_band band, 2280 enum rtw_bandwidth bandwidth); 2281 void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif); 2282 bool rtw_core_check_sta_active(struct rtw_dev *rtwdev); 2283 void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable); 2284 void rtw_set_ampdu_factor(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 2285 struct ieee80211_bss_conf *bss_conf); 2286 #endif 2287