xref: /linux/drivers/gpu/drm/i915/display/intel_dsi_vbt.c (revision ab93e0dd72c37d378dd936f031ffb83ff2bd87ce)
1 /*
2  * Copyright © 2014 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Author: Shobhit Kumar <shobhit.kumar@intel.com>
24  *
25  */
26 
27 #include <linux/gpio/consumer.h>
28 #include <linux/gpio/machine.h>
29 #include <linux/mfd/intel_soc_pmic.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/pinctrl/machine.h>
32 #include <linux/slab.h>
33 #include <linux/string_helpers.h>
34 #include <linux/unaligned.h>
35 
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_print.h>
39 #include <video/mipi_display.h>
40 
41 #include "i915_utils.h"
42 #include "intel_de.h"
43 #include "intel_display_regs.h"
44 #include "intel_display_types.h"
45 #include "intel_dsi.h"
46 #include "intel_dsi_vbt.h"
47 #include "intel_gmbus_regs.h"
48 #include "intel_pps_regs.h"
49 #include "vlv_dsi.h"
50 #include "vlv_dsi_regs.h"
51 #include "vlv_sideband.h"
52 
53 #define MIPI_TRANSFER_MODE_SHIFT	0
54 #define MIPI_VIRTUAL_CHANNEL_SHIFT	1
55 #define MIPI_PORT_SHIFT			3
56 
57 struct i2c_adapter_lookup {
58 	u16 target_addr;
59 	struct intel_dsi *intel_dsi;
60 	acpi_handle dev_handle;
61 };
62 
63 #define CHV_GPIO_IDX_START_N		0
64 #define CHV_GPIO_IDX_START_E		73
65 #define CHV_GPIO_IDX_START_SW		100
66 #define CHV_GPIO_IDX_START_SE		198
67 
68 /* ICL DSI Display GPIO Pins */
69 #define  ICL_GPIO_DDSP_HPD_A		0
70 #define  ICL_GPIO_L_VDDEN_1		1
71 #define  ICL_GPIO_L_BKLTEN_1		2
72 #define  ICL_GPIO_DDPA_CTRLCLK_1	3
73 #define  ICL_GPIO_DDPA_CTRLDATA_1	4
74 #define  ICL_GPIO_DDSP_HPD_B		5
75 #define  ICL_GPIO_L_VDDEN_2		6
76 #define  ICL_GPIO_L_BKLTEN_2		7
77 #define  ICL_GPIO_DDPA_CTRLCLK_2	8
78 #define  ICL_GPIO_DDPA_CTRLDATA_2	9
79 
intel_dsi_seq_port_to_port(struct intel_dsi * intel_dsi,u8 seq_port)80 static enum port intel_dsi_seq_port_to_port(struct intel_dsi *intel_dsi,
81 					    u8 seq_port)
82 {
83 	/*
84 	 * If single link DSI is being used on any port, the VBT sequence block
85 	 * send packet apparently always has 0 for the port. Just use the port
86 	 * we have configured, and ignore the sequence block port.
87 	 */
88 	if (hweight8(intel_dsi->ports) == 1)
89 		return ffs(intel_dsi->ports) - 1;
90 
91 	if (seq_port) {
92 		if (intel_dsi->ports & BIT(PORT_B))
93 			return PORT_B;
94 		if (intel_dsi->ports & BIT(PORT_C))
95 			return PORT_C;
96 	}
97 
98 	return PORT_A;
99 }
100 
mipi_exec_send_packet(struct intel_dsi * intel_dsi,const u8 * data)101 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
102 				       const u8 *data)
103 {
104 	struct intel_display *display = to_intel_display(&intel_dsi->base);
105 	struct mipi_dsi_device *dsi_device;
106 	u8 type, flags, seq_port;
107 	u16 len;
108 	enum port port;
109 
110 	drm_dbg_kms(display->drm, "\n");
111 
112 	flags = *data++;
113 	type = *data++;
114 
115 	len = *((u16 *) data);
116 	data += 2;
117 
118 	seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
119 
120 	port = intel_dsi_seq_port_to_port(intel_dsi, seq_port);
121 
122 	if (drm_WARN_ON(display->drm, !intel_dsi->dsi_hosts[port]))
123 		goto out;
124 
125 	dsi_device = intel_dsi->dsi_hosts[port]->device;
126 	if (!dsi_device) {
127 		drm_dbg_kms(display->drm, "no dsi device for port %c\n",
128 			    port_name(port));
129 		goto out;
130 	}
131 
132 	if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
133 		dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
134 	else
135 		dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
136 
137 	dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
138 
139 	switch (type) {
140 	case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
141 		mipi_dsi_generic_write(dsi_device, NULL, 0);
142 		break;
143 	case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
144 		mipi_dsi_generic_write(dsi_device, data, 1);
145 		break;
146 	case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
147 		mipi_dsi_generic_write(dsi_device, data, 2);
148 		break;
149 	case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
150 	case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
151 	case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
152 		drm_dbg_kms(display->drm, "Generic Read not yet implemented or used\n");
153 		break;
154 	case MIPI_DSI_GENERIC_LONG_WRITE:
155 		mipi_dsi_generic_write(dsi_device, data, len);
156 		break;
157 	case MIPI_DSI_DCS_SHORT_WRITE:
158 		mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
159 		break;
160 	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
161 		mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
162 		break;
163 	case MIPI_DSI_DCS_READ:
164 		drm_dbg_kms(display->drm, "DCS Read not yet implemented or used\n");
165 		break;
166 	case MIPI_DSI_DCS_LONG_WRITE:
167 		mipi_dsi_dcs_write_buffer(dsi_device, data, len);
168 		break;
169 	}
170 
171 	if (DISPLAY_VER(display) < 11)
172 		vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
173 
174 out:
175 	data += len;
176 
177 	return data;
178 }
179 
mipi_exec_delay(struct intel_dsi * intel_dsi,const u8 * data)180 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
181 {
182 	struct intel_display *display = to_intel_display(&intel_dsi->base);
183 	u32 delay = *((const u32 *) data);
184 
185 	drm_dbg_kms(display->drm, "%d usecs\n", delay);
186 
187 	usleep_range(delay, delay + 10);
188 	data += 4;
189 
190 	return data;
191 }
192 
soc_gpio_set_value(struct intel_connector * connector,u8 gpio_index,const char * con_id,u8 idx,bool value)193 static void soc_gpio_set_value(struct intel_connector *connector, u8 gpio_index,
194 			       const char *con_id, u8 idx, bool value)
195 {
196 	struct intel_display *display = to_intel_display(connector);
197 	/* XXX: this table is a quick ugly hack. */
198 	static struct gpio_desc *soc_gpio_table[U8_MAX + 1];
199 	struct gpio_desc *gpio_desc = soc_gpio_table[gpio_index];
200 
201 	if (gpio_desc) {
202 		gpiod_set_value(gpio_desc, value);
203 	} else {
204 		gpio_desc = devm_gpiod_get_index(display->drm->dev, con_id, idx,
205 						 value ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW);
206 		if (IS_ERR(gpio_desc)) {
207 			drm_err(display->drm,
208 				"GPIO index %u request failed (%pe)\n",
209 				gpio_index, gpio_desc);
210 			return;
211 		}
212 
213 		soc_gpio_table[gpio_index] = gpio_desc;
214 	}
215 }
216 
soc_opaque_gpio_set_value(struct intel_connector * connector,u8 gpio_index,const char * chip,const char * con_id,u8 idx,bool value)217 static void soc_opaque_gpio_set_value(struct intel_connector *connector,
218 				      u8 gpio_index, const char *chip,
219 				      const char *con_id, u8 idx, bool value)
220 {
221 	struct gpiod_lookup_table *lookup;
222 
223 	lookup = kzalloc(struct_size(lookup, table, 2), GFP_KERNEL);
224 	if (!lookup)
225 		return;
226 
227 	lookup->dev_id = "0000:00:02.0";
228 	lookup->table[0] =
229 		GPIO_LOOKUP_IDX(chip, idx, con_id, idx, GPIO_ACTIVE_HIGH);
230 
231 	gpiod_add_lookup_table(lookup);
232 
233 	soc_gpio_set_value(connector, gpio_index, con_id, idx, value);
234 
235 	gpiod_remove_lookup_table(lookup);
236 	kfree(lookup);
237 }
238 
vlv_gpio_set_value(struct intel_connector * connector,u8 gpio_source,u8 gpio_index,bool value)239 static void vlv_gpio_set_value(struct intel_connector *connector,
240 			       u8 gpio_source, u8 gpio_index, bool value)
241 {
242 	struct intel_display *display = to_intel_display(connector);
243 
244 	/* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
245 	if (connector->panel.vbt.dsi.seq_version < 3) {
246 		if (gpio_source == 1) {
247 			drm_dbg_kms(display->drm, "SC gpio not supported\n");
248 			return;
249 		}
250 		if (gpio_source > 1) {
251 			drm_dbg_kms(display->drm,
252 				    "unknown gpio source %u\n", gpio_source);
253 			return;
254 		}
255 	}
256 
257 	soc_opaque_gpio_set_value(connector, gpio_index,
258 				  "INT33FC:01", "Panel N", gpio_index, value);
259 }
260 
chv_gpio_set_value(struct intel_connector * connector,u8 gpio_source,u8 gpio_index,bool value)261 static void chv_gpio_set_value(struct intel_connector *connector,
262 			       u8 gpio_source, u8 gpio_index, bool value)
263 {
264 	struct intel_display *display = to_intel_display(connector);
265 
266 	if (connector->panel.vbt.dsi.seq_version >= 3) {
267 		if (gpio_index >= CHV_GPIO_IDX_START_SE) {
268 			/* XXX: it's unclear whether 255->57 is part of SE. */
269 			soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:03", "Panel SE",
270 						  gpio_index - CHV_GPIO_IDX_START_SE, value);
271 		} else if (gpio_index >= CHV_GPIO_IDX_START_SW) {
272 			soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:00", "Panel SW",
273 						  gpio_index - CHV_GPIO_IDX_START_SW, value);
274 		} else if (gpio_index >= CHV_GPIO_IDX_START_E) {
275 			soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:02", "Panel E",
276 						  gpio_index - CHV_GPIO_IDX_START_E, value);
277 		} else {
278 			soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:01", "Panel N",
279 						  gpio_index - CHV_GPIO_IDX_START_N, value);
280 		}
281 	} else {
282 		/* XXX: The spec is unclear about CHV GPIO on seq v2 */
283 		if (gpio_source != 0) {
284 			drm_dbg_kms(display->drm,
285 				    "unknown gpio source %u\n", gpio_source);
286 			return;
287 		}
288 
289 		if (gpio_index >= CHV_GPIO_IDX_START_E) {
290 			drm_dbg_kms(display->drm,
291 				    "invalid gpio index %u for GPIO N\n",
292 				    gpio_index);
293 			return;
294 		}
295 
296 		soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:01", "Panel N",
297 					  gpio_index - CHV_GPIO_IDX_START_N, value);
298 	}
299 }
300 
bxt_gpio_set_value(struct intel_connector * connector,u8 gpio_index,bool value)301 static void bxt_gpio_set_value(struct intel_connector *connector,
302 			       u8 gpio_index, bool value)
303 {
304 	soc_gpio_set_value(connector, gpio_index, NULL, gpio_index, value);
305 }
306 
307 enum {
308 	MIPI_RESET_1 = 0,
309 	MIPI_AVDD_EN_1,
310 	MIPI_BKLT_EN_1,
311 	MIPI_AVEE_EN_1,
312 	MIPI_VIO_EN_1,
313 	MIPI_RESET_2,
314 	MIPI_AVDD_EN_2,
315 	MIPI_BKLT_EN_2,
316 	MIPI_AVEE_EN_2,
317 	MIPI_VIO_EN_2,
318 };
319 
icl_native_gpio_set_value(struct intel_display * display,int gpio,bool value)320 static void icl_native_gpio_set_value(struct intel_display *display,
321 				      int gpio, bool value)
322 {
323 	int index;
324 
325 	if (drm_WARN_ON(display->drm, DISPLAY_VER(display) == 11 && gpio >= MIPI_RESET_2))
326 		return;
327 
328 	switch (gpio) {
329 	case MIPI_RESET_1:
330 	case MIPI_RESET_2:
331 		index = gpio == MIPI_RESET_1 ? HPD_PORT_A : HPD_PORT_B;
332 
333 		/*
334 		 * Disable HPD to set the pin to output, and set output
335 		 * value. The HPD pin should not be enabled for DSI anyway,
336 		 * assuming the board design and VBT are sane, and the pin isn't
337 		 * used by a non-DSI encoder.
338 		 *
339 		 * The locking protects against concurrent SHOTPLUG_CTL_DDI
340 		 * modifications in irq setup and handling.
341 		 */
342 		spin_lock_irq(&display->irq.lock);
343 		intel_de_rmw(display, SHOTPLUG_CTL_DDI,
344 			     SHOTPLUG_CTL_DDI_HPD_ENABLE(index) |
345 			     SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index),
346 			     value ? SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index) : 0);
347 		spin_unlock_irq(&display->irq.lock);
348 		break;
349 	case MIPI_AVDD_EN_1:
350 	case MIPI_AVDD_EN_2:
351 		index = gpio == MIPI_AVDD_EN_1 ? 0 : 1;
352 
353 		intel_de_rmw(display, PP_CONTROL(display, index), PANEL_POWER_ON,
354 			     value ? PANEL_POWER_ON : 0);
355 		break;
356 	case MIPI_BKLT_EN_1:
357 	case MIPI_BKLT_EN_2:
358 		index = gpio == MIPI_BKLT_EN_1 ? 0 : 1;
359 
360 		intel_de_rmw(display, PP_CONTROL(display, index), EDP_BLC_ENABLE,
361 			     value ? EDP_BLC_ENABLE : 0);
362 		break;
363 	case MIPI_AVEE_EN_1:
364 	case MIPI_AVEE_EN_2:
365 		index = gpio == MIPI_AVEE_EN_1 ? 1 : 2;
366 
367 		intel_de_rmw(display, GPIO(display, index),
368 			     GPIO_CLOCK_VAL_OUT,
369 			     GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT |
370 			     GPIO_CLOCK_VAL_MASK | (value ? GPIO_CLOCK_VAL_OUT : 0));
371 		break;
372 	case MIPI_VIO_EN_1:
373 	case MIPI_VIO_EN_2:
374 		index = gpio == MIPI_VIO_EN_1 ? 1 : 2;
375 
376 		intel_de_rmw(display, GPIO(display, index),
377 			     GPIO_DATA_VAL_OUT,
378 			     GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT |
379 			     GPIO_DATA_VAL_MASK | (value ? GPIO_DATA_VAL_OUT : 0));
380 		break;
381 	default:
382 		MISSING_CASE(gpio);
383 	}
384 }
385 
mipi_exec_gpio(struct intel_dsi * intel_dsi,const u8 * data)386 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
387 {
388 	struct intel_display *display = to_intel_display(&intel_dsi->base);
389 	struct intel_connector *connector = intel_dsi->attached_connector;
390 	u8 gpio_source = 0, gpio_index = 0, gpio_number;
391 	bool value;
392 	int size;
393 	bool native = DISPLAY_VER(display) >= 11;
394 
395 	if (connector->panel.vbt.dsi.seq_version >= 3) {
396 		size = 3;
397 
398 		gpio_index = data[0];
399 		gpio_number = data[1];
400 		value = data[2] & BIT(0);
401 
402 		if (connector->panel.vbt.dsi.seq_version >= 4 && data[2] & BIT(1))
403 			native = false;
404 	} else {
405 		size = 2;
406 
407 		gpio_number = data[0];
408 		value = data[1] & BIT(0);
409 
410 		if (connector->panel.vbt.dsi.seq_version == 2)
411 			gpio_source = (data[1] >> 1) & 3;
412 	}
413 
414 	drm_dbg_kms(display->drm, "GPIO index %u, number %u, source %u, native %s, set to %s\n",
415 		    gpio_index, gpio_number, gpio_source, str_yes_no(native), str_on_off(value));
416 
417 	if (native)
418 		icl_native_gpio_set_value(display, gpio_number, value);
419 	else if (DISPLAY_VER(display) >= 9)
420 		bxt_gpio_set_value(connector, gpio_index, value);
421 	else if (display->platform.valleyview)
422 		vlv_gpio_set_value(connector, gpio_source, gpio_number, value);
423 	else if (display->platform.cherryview)
424 		chv_gpio_set_value(connector, gpio_source, gpio_number, value);
425 
426 	return data + size;
427 }
428 
429 #ifdef CONFIG_ACPI
i2c_adapter_lookup(struct acpi_resource * ares,void * data)430 static int i2c_adapter_lookup(struct acpi_resource *ares, void *data)
431 {
432 	struct i2c_adapter_lookup *lookup = data;
433 	struct intel_dsi *intel_dsi = lookup->intel_dsi;
434 	struct acpi_resource_i2c_serialbus *sb;
435 	struct i2c_adapter *adapter;
436 	acpi_handle adapter_handle;
437 	acpi_status status;
438 
439 	if (!i2c_acpi_get_i2c_resource(ares, &sb))
440 		return 1;
441 
442 	if (lookup->target_addr != sb->slave_address)
443 		return 1;
444 
445 	status = acpi_get_handle(lookup->dev_handle,
446 				 sb->resource_source.string_ptr,
447 				 &adapter_handle);
448 	if (ACPI_FAILURE(status))
449 		return 1;
450 
451 	adapter = i2c_acpi_find_adapter_by_handle(adapter_handle);
452 	if (adapter)
453 		intel_dsi->i2c_bus_num = adapter->nr;
454 
455 	return 1;
456 }
457 
i2c_acpi_find_adapter(struct intel_dsi * intel_dsi,const u16 target_addr)458 static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
459 				  const u16 target_addr)
460 {
461 	struct intel_display *display = to_intel_display(&intel_dsi->base);
462 	struct acpi_device *adev = ACPI_COMPANION(display->drm->dev);
463 	struct i2c_adapter_lookup lookup = {
464 		.target_addr = target_addr,
465 		.intel_dsi = intel_dsi,
466 		.dev_handle = acpi_device_handle(adev),
467 	};
468 	LIST_HEAD(resource_list);
469 
470 	acpi_dev_get_resources(adev, &resource_list, i2c_adapter_lookup, &lookup);
471 	acpi_dev_free_resource_list(&resource_list);
472 }
473 #else
i2c_acpi_find_adapter(struct intel_dsi * intel_dsi,const u16 target_addr)474 static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
475 					 const u16 target_addr)
476 {
477 }
478 #endif
479 
mipi_exec_i2c(struct intel_dsi * intel_dsi,const u8 * data)480 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
481 {
482 	struct intel_display *display = to_intel_display(&intel_dsi->base);
483 	struct i2c_adapter *adapter;
484 	struct i2c_msg msg;
485 	int ret;
486 	u8 vbt_i2c_bus_num = *(data + 2);
487 	u16 target_addr = *(u16 *)(data + 3);
488 	u8 reg_offset = *(data + 5);
489 	u8 payload_size = *(data + 6);
490 	u8 *payload_data;
491 
492 	drm_dbg_kms(display->drm, "bus %d target-addr 0x%02x reg 0x%02x data %*ph\n",
493 		    vbt_i2c_bus_num, target_addr, reg_offset, payload_size, data + 7);
494 
495 	if (intel_dsi->i2c_bus_num < 0) {
496 		intel_dsi->i2c_bus_num = vbt_i2c_bus_num;
497 		i2c_acpi_find_adapter(intel_dsi, target_addr);
498 	}
499 
500 	adapter = i2c_get_adapter(intel_dsi->i2c_bus_num);
501 	if (!adapter) {
502 		drm_err(display->drm, "Cannot find a valid i2c bus for xfer\n");
503 		goto err_bus;
504 	}
505 
506 	payload_data = kzalloc(payload_size + 1, GFP_KERNEL);
507 	if (!payload_data)
508 		goto err_alloc;
509 
510 	payload_data[0] = reg_offset;
511 	memcpy(&payload_data[1], (data + 7), payload_size);
512 
513 	msg.addr = target_addr;
514 	msg.flags = 0;
515 	msg.len = payload_size + 1;
516 	msg.buf = payload_data;
517 
518 	ret = i2c_transfer(adapter, &msg, 1);
519 	if (ret < 0)
520 		drm_err(display->drm,
521 			"Failed to xfer payload of size (%u) to reg (%u)\n",
522 			payload_size, reg_offset);
523 
524 	kfree(payload_data);
525 err_alloc:
526 	i2c_put_adapter(adapter);
527 err_bus:
528 	return data + payload_size + 7;
529 }
530 
mipi_exec_spi(struct intel_dsi * intel_dsi,const u8 * data)531 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data)
532 {
533 	struct intel_display *display = to_intel_display(&intel_dsi->base);
534 
535 	drm_dbg_kms(display->drm, "Skipping SPI element execution\n");
536 
537 	return data + *(data + 5) + 6;
538 }
539 
mipi_exec_pmic(struct intel_dsi * intel_dsi,const u8 * data)540 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data)
541 {
542 	struct intel_display *display = to_intel_display(&intel_dsi->base);
543 #ifdef CONFIG_PMIC_OPREGION
544 	u32 value, mask, reg_address;
545 	u16 i2c_address;
546 	int ret;
547 
548 	/* byte 0 aka PMIC Flag is reserved */
549 	i2c_address	= get_unaligned_le16(data + 1);
550 	reg_address	= get_unaligned_le32(data + 3);
551 	value		= get_unaligned_le32(data + 7);
552 	mask		= get_unaligned_le32(data + 11);
553 
554 	ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address,
555 							reg_address,
556 							value, mask);
557 	if (ret)
558 		drm_err(display->drm, "%s failed, error: %d\n", __func__, ret);
559 #else
560 	drm_err(display->drm,
561 		"Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n");
562 #endif
563 
564 	return data + 15;
565 }
566 
567 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
568 					const u8 *data);
569 static const fn_mipi_elem_exec exec_elem[] = {
570 	[MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
571 	[MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
572 	[MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
573 	[MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
574 	[MIPI_SEQ_ELEM_SPI] = mipi_exec_spi,
575 	[MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic,
576 };
577 
578 /*
579  * MIPI Sequence from VBT #53 parsing logic
580  * We have already separated each sequence during bios parsing
581  * Following is generic execution function for any sequence
582  */
583 
584 static const char * const seq_name[] = {
585 	[MIPI_SEQ_END] = "MIPI_SEQ_END",
586 	[MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
587 	[MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
588 	[MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
589 	[MIPI_SEQ_DISPLAY_OFF]  = "MIPI_SEQ_DISPLAY_OFF",
590 	[MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
591 	[MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
592 	[MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
593 	[MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
594 	[MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF",
595 	[MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON",
596 	[MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF",
597 };
598 
sequence_name(enum mipi_seq seq_id)599 static const char *sequence_name(enum mipi_seq seq_id)
600 {
601 	if (seq_id < ARRAY_SIZE(seq_name))
602 		return seq_name[seq_id];
603 
604 	return "(unknown)";
605 }
606 
intel_dsi_vbt_exec(struct intel_dsi * intel_dsi,enum mipi_seq seq_id)607 static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,
608 			       enum mipi_seq seq_id)
609 {
610 	struct intel_display *display = to_intel_display(&intel_dsi->base);
611 	struct intel_connector *connector = intel_dsi->attached_connector;
612 	const u8 *data;
613 	fn_mipi_elem_exec mipi_elem_exec;
614 
615 	if (drm_WARN_ON(display->drm,
616 			seq_id >= ARRAY_SIZE(connector->panel.vbt.dsi.sequence)))
617 		return;
618 
619 	data = connector->panel.vbt.dsi.sequence[seq_id];
620 	if (!data)
621 		return;
622 
623 	drm_WARN_ON(display->drm, *data != seq_id);
624 
625 	drm_dbg_kms(display->drm, "Starting MIPI sequence %d - %s\n",
626 		    seq_id, sequence_name(seq_id));
627 
628 	/* Skip Sequence Byte. */
629 	data++;
630 
631 	/* Skip Size of Sequence. */
632 	if (connector->panel.vbt.dsi.seq_version >= 3)
633 		data += 4;
634 
635 	while (*data != MIPI_SEQ_ELEM_END) {
636 		u8 operation_byte = *data++;
637 		u8 operation_size = 0;
638 
639 		if (operation_byte < ARRAY_SIZE(exec_elem))
640 			mipi_elem_exec = exec_elem[operation_byte];
641 		else
642 			mipi_elem_exec = NULL;
643 
644 		/* Size of Operation. */
645 		if (connector->panel.vbt.dsi.seq_version >= 3)
646 			operation_size = *data++;
647 
648 		if (mipi_elem_exec) {
649 			const u8 *next = data + operation_size;
650 
651 			data = mipi_elem_exec(intel_dsi, data);
652 
653 			/* Consistency check if we have size. */
654 			if (operation_size && data != next) {
655 				drm_err(display->drm,
656 					"Inconsistent operation size\n");
657 				return;
658 			}
659 		} else if (operation_size) {
660 			/* We have size, skip. */
661 			drm_dbg_kms(display->drm,
662 				    "Unsupported MIPI operation byte %u\n",
663 				    operation_byte);
664 			data += operation_size;
665 		} else {
666 			/* No size, can't skip without parsing. */
667 			drm_err(display->drm,
668 				"Unsupported MIPI operation byte %u\n",
669 				operation_byte);
670 			return;
671 		}
672 	}
673 }
674 
intel_dsi_vbt_exec_sequence(struct intel_dsi * intel_dsi,enum mipi_seq seq_id)675 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
676 				 enum mipi_seq seq_id)
677 {
678 	if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel)
679 		gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
680 	if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight)
681 		gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1);
682 
683 	intel_dsi_vbt_exec(intel_dsi, seq_id);
684 
685 	if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel)
686 		gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
687 	if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight)
688 		gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0);
689 }
690 
intel_dsi_log_params(struct intel_dsi * intel_dsi)691 void intel_dsi_log_params(struct intel_dsi *intel_dsi)
692 {
693 	struct intel_display *display = to_intel_display(&intel_dsi->base);
694 	struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS,
695 					       "DSI parameters:");
696 
697 	drm_printf(&p, "Pclk %d\n", intel_dsi->pclk);
698 	drm_printf(&p, "Pixel overlap %d\n", intel_dsi->pixel_overlap);
699 	drm_printf(&p, "Lane count %d\n", intel_dsi->lane_count);
700 	drm_printf(&p, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg);
701 	drm_printf(&p, "Video mode format %s\n",
702 		   intel_dsi->video_mode == NON_BURST_SYNC_PULSE ?
703 		   "non-burst with sync pulse" :
704 		   intel_dsi->video_mode == NON_BURST_SYNC_EVENTS ?
705 		   "non-burst with sync events" :
706 		   intel_dsi->video_mode == BURST_MODE ?
707 		   "burst" : "<unknown>");
708 	drm_printf(&p, "Burst mode ratio %d\n", intel_dsi->burst_mode_ratio);
709 	drm_printf(&p, "Reset timer %d\n", intel_dsi->rst_timer_val);
710 	drm_printf(&p, "Eot %s\n", str_enabled_disabled(intel_dsi->eotp_pkt));
711 	drm_printf(&p, "Clockstop %s\n", str_enabled_disabled(!intel_dsi->clock_stop));
712 	drm_printf(&p, "Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
713 	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
714 		drm_printf(&p, "Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
715 	else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
716 		drm_printf(&p, "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
717 	else
718 		drm_printf(&p, "Dual link: NONE\n");
719 	drm_printf(&p, "Pixel Format %d\n", intel_dsi->pixel_format);
720 	drm_printf(&p, "TLPX %d\n", intel_dsi->escape_clk_div);
721 	drm_printf(&p, "LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
722 	drm_printf(&p, "Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
723 	drm_printf(&p, "Init Count 0x%x\n", intel_dsi->init_count);
724 	drm_printf(&p, "HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
725 	drm_printf(&p, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
726 	drm_printf(&p, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
727 	drm_printf(&p, "LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
728 	drm_printf(&p, "HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
729 	drm_printf(&p, "BTA %s\n",
730 		   str_enabled_disabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
731 }
732 
vbt_to_dsi_pixel_format(unsigned int format)733 static enum mipi_dsi_pixel_format vbt_to_dsi_pixel_format(unsigned int format)
734 {
735 	switch (format) {
736 	case PIXEL_FORMAT_RGB888:
737 		return MIPI_DSI_FMT_RGB888;
738 	case PIXEL_FORMAT_RGB666_LOOSELY_PACKED:
739 		return MIPI_DSI_FMT_RGB666;
740 	case PIXEL_FORMAT_RGB666:
741 		return MIPI_DSI_FMT_RGB666_PACKED;
742 	case PIXEL_FORMAT_RGB565:
743 		return MIPI_DSI_FMT_RGB565;
744 	default:
745 		MISSING_CASE(format);
746 		return MIPI_DSI_FMT_RGB666;
747 	}
748 }
749 
intel_dsi_vbt_init(struct intel_dsi * intel_dsi,u16 panel_id)750 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
751 {
752 	struct intel_display *display = to_intel_display(&intel_dsi->base);
753 	struct intel_connector *connector = intel_dsi->attached_connector;
754 	struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
755 	struct mipi_pps_data *pps = connector->panel.vbt.dsi.pps;
756 	struct drm_display_mode *mode = connector->panel.vbt.lfp_vbt_mode;
757 	u16 burst_mode_ratio;
758 	enum port port;
759 
760 	drm_dbg_kms(display->drm, "\n");
761 
762 	intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
763 	intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
764 	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
765 	intel_dsi->pixel_format =
766 		vbt_to_dsi_pixel_format(mipi_config->videomode_color_format);
767 
768 	intel_dsi->dual_link = mipi_config->dual_link;
769 	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
770 	intel_dsi->operation_mode = mipi_config->is_cmd_mode;
771 	intel_dsi->video_mode = mipi_config->video_transfer_mode;
772 	intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
773 	intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
774 	intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout;
775 	intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
776 	intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
777 	intel_dsi->init_count = mipi_config->master_init_timer;
778 	intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
779 	intel_dsi->video_frmt_cfg_bits =
780 		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
781 	intel_dsi->bgr_enabled = mipi_config->rgb_flip;
782 
783 	/* Starting point, adjusted depending on dual link and burst mode */
784 	intel_dsi->pclk = mode->clock;
785 
786 	/* In dual link mode each port needs half of pixel clock */
787 	if (intel_dsi->dual_link) {
788 		intel_dsi->pclk /= 2;
789 
790 		/* we can enable pixel_overlap if needed by panel. In this
791 		 * case we need to increase the pixelclock for extra pixels
792 		 */
793 		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
794 			intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
795 		}
796 	}
797 
798 	/* Burst Mode Ratio
799 	 * Target ddr frequency from VBT / non burst ddr freq
800 	 * multiply by 100 to preserve remainder
801 	 */
802 	if (intel_dsi->video_mode == BURST_MODE) {
803 		u32 bitrate;
804 
805 		if (mipi_config->target_burst_mode_freq == 0) {
806 			drm_err(display->drm, "Burst mode target is not set\n");
807 			return false;
808 		}
809 
810 		bitrate = intel_dsi_bitrate(intel_dsi);
811 
812 		/*
813 		 * Sometimes the VBT contains a slightly lower clock, then
814 		 * the bitrate we have calculated, in this case just replace it
815 		 * with the calculated bitrate.
816 		 */
817 		if (mipi_config->target_burst_mode_freq < bitrate &&
818 		    intel_fuzzy_clock_check(mipi_config->target_burst_mode_freq,
819 					    bitrate))
820 			mipi_config->target_burst_mode_freq = bitrate;
821 
822 		if (mipi_config->target_burst_mode_freq < bitrate) {
823 			drm_err(display->drm, "Burst mode freq is less than computed\n");
824 			return false;
825 		}
826 
827 		burst_mode_ratio =
828 			DIV_ROUND_UP(mipi_config->target_burst_mode_freq * 100, bitrate);
829 
830 		intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
831 	} else
832 		burst_mode_ratio = 100;
833 
834 	intel_dsi->burst_mode_ratio = burst_mode_ratio;
835 
836 	/* delays in VBT are in unit of 100us, so need to convert
837 	 * here in ms
838 	 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
839 	intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
840 	intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
841 	intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
842 	intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
843 	intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
844 
845 	intel_dsi->i2c_bus_num = -1;
846 
847 	/* a regular driver would get the device in probe */
848 	for_each_dsi_port(port, intel_dsi->ports) {
849 		mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
850 	}
851 
852 	return true;
853 }
854 
855 /*
856  * On some BYT/CHT devs some sequences are incomplete and we need to manually
857  * control some GPIOs. We need to add a GPIO lookup table before we get these.
858  * If the GOP did not initialize the panel (HDMI inserted) we may need to also
859  * change the pinmux for the SoC's PWM0 pin from GPIO to PWM.
860  */
861 static struct gpiod_lookup_table pmic_panel_gpio_table = {
862 	/* Intel GFX is consumer */
863 	.dev_id = "0000:00:02.0",
864 	.table = {
865 		/* Panel EN/DISABLE */
866 		GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH),
867 		{ }
868 	},
869 };
870 
871 static struct gpiod_lookup_table soc_panel_gpio_table = {
872 	.dev_id = "0000:00:02.0",
873 	.table = {
874 		GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH),
875 		GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH),
876 		{ }
877 	},
878 };
879 
880 static const struct pinctrl_map soc_pwm_pinctrl_map[] = {
881 	PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00",
882 			  "pwm0_grp", "pwm"),
883 };
884 
intel_dsi_vbt_gpio_init(struct intel_dsi * intel_dsi,bool panel_is_on)885 void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on)
886 {
887 	struct intel_display *display = to_intel_display(&intel_dsi->base);
888 	struct intel_connector *connector = intel_dsi->attached_connector;
889 	struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
890 	enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
891 	struct gpiod_lookup_table *gpiod_lookup_table = NULL;
892 	bool want_backlight_gpio = false;
893 	bool want_panel_gpio = false;
894 	struct pinctrl *pinctrl;
895 	int ret;
896 
897 	if ((display->platform.valleyview || display->platform.cherryview) &&
898 	    mipi_config->pwm_blc == PPS_BLC_PMIC) {
899 		gpiod_lookup_table = &pmic_panel_gpio_table;
900 		want_panel_gpio = true;
901 	}
902 
903 	if (display->platform.valleyview && mipi_config->pwm_blc == PPS_BLC_SOC) {
904 		gpiod_lookup_table = &soc_panel_gpio_table;
905 		want_panel_gpio = true;
906 		want_backlight_gpio = true;
907 
908 		/* Ensure PWM0 pin is muxed as PWM instead of GPIO */
909 		ret = pinctrl_register_mappings(soc_pwm_pinctrl_map,
910 					     ARRAY_SIZE(soc_pwm_pinctrl_map));
911 		if (ret)
912 			drm_err(display->drm,
913 				"Failed to register pwm0 pinmux mapping\n");
914 
915 		pinctrl = devm_pinctrl_get_select(display->drm->dev, "soc_pwm0");
916 		if (IS_ERR(pinctrl))
917 			drm_err(display->drm,
918 				"Failed to set pinmux to PWM\n");
919 	}
920 
921 	if (gpiod_lookup_table)
922 		gpiod_add_lookup_table(gpiod_lookup_table);
923 
924 	if (want_panel_gpio) {
925 		intel_dsi->gpio_panel = devm_gpiod_get(display->drm->dev, "panel", flags);
926 		if (IS_ERR(intel_dsi->gpio_panel)) {
927 			drm_err(display->drm,
928 				"Failed to own gpio for panel control\n");
929 			intel_dsi->gpio_panel = NULL;
930 		}
931 	}
932 
933 	if (want_backlight_gpio) {
934 		intel_dsi->gpio_backlight =
935 			devm_gpiod_get(display->drm->dev, "backlight", flags);
936 		if (IS_ERR(intel_dsi->gpio_backlight)) {
937 			drm_err(display->drm,
938 				"Failed to own gpio for backlight control\n");
939 			intel_dsi->gpio_backlight = NULL;
940 		}
941 	}
942 
943 	if (gpiod_lookup_table)
944 		gpiod_remove_lookup_table(gpiod_lookup_table);
945 }
946