xref: /qemu/target/sh4/helper.c (revision 7cef6d686309e2792186504ae17cf4f3eb57ef68)
1 /*
2  *  SH4 emulation
3  *
4  *  Copyright (c) 2005 Samuel Tardieu
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 
22 #include "cpu.h"
23 #include "exec/cputlb.h"
24 #include "exec/page-protection.h"
25 #include "exec/target_page.h"
26 #include "exec/log.h"
27 
28 #if !defined(CONFIG_USER_ONLY)
29 #include "hw/sh4/sh_intc.h"
30 #include "system/runstate.h"
31 #endif
32 
33 #define MMU_OK                   0
34 #define MMU_ITLB_MISS            (-1)
35 #define MMU_ITLB_MULTIPLE        (-2)
36 #define MMU_ITLB_VIOLATION       (-3)
37 #define MMU_DTLB_MISS_READ       (-4)
38 #define MMU_DTLB_MISS_WRITE      (-5)
39 #define MMU_DTLB_INITIAL_WRITE   (-6)
40 #define MMU_DTLB_VIOLATION_READ  (-7)
41 #define MMU_DTLB_VIOLATION_WRITE (-8)
42 #define MMU_DTLB_MULTIPLE        (-9)
43 #define MMU_DTLB_MISS            (-10)
44 #define MMU_IADDR_ERROR          (-11)
45 #define MMU_DADDR_ERROR_READ     (-12)
46 #define MMU_DADDR_ERROR_WRITE    (-13)
47 
48 #if defined(CONFIG_USER_ONLY)
49 
cpu_sh4_is_cached(CPUSH4State * env,target_ulong addr)50 int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr)
51 {
52     /* For user mode, only U0 area is cacheable. */
53     return !(addr & 0x80000000);
54 }
55 
56 #else /* !CONFIG_USER_ONLY */
57 
superh_cpu_do_interrupt(CPUState * cs)58 void superh_cpu_do_interrupt(CPUState *cs)
59 {
60     CPUSH4State *env = cpu_env(cs);
61     int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD;
62     int do_exp, irq_vector = cs->exception_index;
63 
64     /* prioritize exceptions over interrupts */
65 
66     do_exp = cs->exception_index != -1;
67     do_irq = do_irq && (cs->exception_index == -1);
68 
69     if (env->sr & (1u << SR_BL)) {
70         if (do_exp && cs->exception_index != 0x1e0) {
71             /* In theory a masked exception generates a reset exception,
72                which in turn jumps to the reset vector. However this only
73                works when using a bootloader. When using a kernel and an
74                initrd, they need to be reloaded and the program counter
75                should be loaded with the kernel entry point.
76                qemu_system_reset_request takes care of that.  */
77             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
78             return;
79         }
80         if (do_irq && !env->in_sleep) {
81             return; /* masked */
82         }
83     }
84     env->in_sleep = 0;
85 
86     if (do_irq) {
87         irq_vector = sh_intc_get_pending_vector(env->intc_handle,
88                                                 (env->sr >> 4) & 0xf);
89         if (irq_vector == -1) {
90             return; /* masked */
91         }
92     }
93 
94     if (qemu_loglevel_mask(CPU_LOG_INT)) {
95         const char *expname;
96         switch (cs->exception_index) {
97         case 0x0e0:
98             expname = "addr_error";
99             break;
100         case 0x040:
101             expname = "tlb_miss";
102             break;
103         case 0x0a0:
104             expname = "tlb_violation";
105             break;
106         case 0x180:
107             expname = "illegal_instruction";
108             break;
109         case 0x1a0:
110             expname = "slot_illegal_instruction";
111             break;
112         case 0x800:
113             expname = "fpu_disable";
114             break;
115         case 0x820:
116             expname = "slot_fpu";
117             break;
118         case 0x100:
119             expname = "data_write";
120             break;
121         case 0x060:
122             expname = "dtlb_miss_write";
123             break;
124         case 0x0c0:
125             expname = "dtlb_violation_write";
126             break;
127         case 0x120:
128             expname = "fpu_exception";
129             break;
130         case 0x080:
131             expname = "initial_page_write";
132             break;
133         case 0x160:
134             expname = "trapa";
135             break;
136         default:
137             expname = do_irq ? "interrupt" : "???";
138             break;
139         }
140         qemu_log("exception 0x%03x [%s] raised\n",
141                   irq_vector, expname);
142         log_cpu_state(cs, 0);
143     }
144 
145     env->ssr = cpu_read_sr(env);
146     env->spc = env->pc;
147     env->sgr = env->gregs[15];
148     env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB);
149     env->lock_addr = -1;
150 
151     if (env->flags & TB_FLAG_DELAY_SLOT_MASK) {
152         /* Branch instruction should be executed again before delay slot. */
153         env->spc -= 2;
154         /* Clear flags for exception/interrupt routine. */
155         env->flags &= ~TB_FLAG_DELAY_SLOT_MASK;
156     }
157 
158     if (do_exp) {
159         env->expevt = cs->exception_index;
160         switch (cs->exception_index) {
161         case 0x000:
162         case 0x020:
163         case 0x140:
164             env->sr &= ~(1u << SR_FD);
165             env->sr |= 0xf << 4; /* IMASK */
166             env->pc = 0xa0000000;
167             break;
168         case 0x040:
169         case 0x060:
170             env->pc = env->vbr + 0x400;
171             break;
172         case 0x160:
173             env->spc += 2; /* special case for TRAPA */
174             /* fall through */
175         default:
176             env->pc = env->vbr + 0x100;
177             break;
178         }
179         return;
180     }
181 
182     if (do_irq) {
183         env->intevt = irq_vector;
184         env->pc = env->vbr + 0x600;
185         return;
186     }
187 }
188 
update_itlb_use(CPUSH4State * env,int itlbnb)189 static void update_itlb_use(CPUSH4State * env, int itlbnb)
190 {
191     uint32_t or_mask = 0, and_mask = 0xff;
192 
193     switch (itlbnb) {
194     case 0:
195         and_mask = 0x1f;
196         break;
197     case 1:
198         and_mask = 0xe7;
199         or_mask = 0x80;
200         break;
201     case 2:
202         and_mask = 0xfb;
203         or_mask = 0x50;
204         break;
205     case 3:
206         or_mask = 0x2c;
207         break;
208     }
209 
210     env->mmucr &= (and_mask << 24) | 0x00ffffff;
211     env->mmucr |= (or_mask << 24);
212 }
213 
itlb_replacement(CPUSH4State * env)214 static int itlb_replacement(CPUSH4State * env)
215 {
216     if ((env->mmucr & 0xe0000000) == 0xe0000000) {
217         return 0;
218     }
219     if ((env->mmucr & 0x98000000) == 0x18000000) {
220         return 1;
221     }
222     if ((env->mmucr & 0x54000000) == 0x04000000) {
223         return 2;
224     }
225     if ((env->mmucr & 0x2c000000) == 0x00000000) {
226         return 3;
227     }
228     cpu_abort(env_cpu(env), "Unhandled itlb_replacement");
229 }
230 
231 /* Find the corresponding entry in the right TLB
232    Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
233 */
find_tlb_entry(CPUSH4State * env,target_ulong address,tlb_t * entries,uint8_t nbtlb,int use_asid)234 static int find_tlb_entry(CPUSH4State * env, target_ulong address,
235                           tlb_t * entries, uint8_t nbtlb, int use_asid)
236 {
237     int match = MMU_DTLB_MISS;
238     uint32_t start, end;
239     uint8_t asid;
240     int i;
241 
242     asid = env->pteh & 0xff;
243 
244     for (i = 0; i < nbtlb; i++) {
245         if (!entries[i].v)
246             continue; /* Invalid entry */
247         if (!entries[i].sh && use_asid && entries[i].asid != asid)
248             continue; /* Bad ASID */
249         start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
250         end = start + entries[i].size - 1;
251         if (address >= start && address <= end) { /* Match */
252             if (match != MMU_DTLB_MISS)
253                 return MMU_DTLB_MULTIPLE; /* Multiple match */
254             match = i;
255         }
256     }
257     return match;
258 }
259 
increment_urc(CPUSH4State * env)260 static void increment_urc(CPUSH4State * env)
261 {
262     uint8_t urb, urc;
263 
264     /* Increment URC */
265     urb = ((env->mmucr) >> 18) & 0x3f;
266     urc = ((env->mmucr) >> 10) & 0x3f;
267     urc++;
268     if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
269         urc = 0;
270     env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
271 }
272 
273 /* Copy and utlb entry into itlb
274    Return entry
275 */
copy_utlb_entry_itlb(CPUSH4State * env,int utlb)276 static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
277 {
278     int itlb;
279 
280     tlb_t * ientry;
281     itlb = itlb_replacement(env);
282     ientry = &env->itlb[itlb];
283     if (ientry->v) {
284         tlb_flush_page(env_cpu(env), ientry->vpn << 10);
285     }
286     *ientry = env->utlb[utlb];
287     update_itlb_use(env, itlb);
288     return itlb;
289 }
290 
291 /* Find itlb entry
292    Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
293 */
find_itlb_entry(CPUSH4State * env,target_ulong address,int use_asid)294 static int find_itlb_entry(CPUSH4State * env, target_ulong address,
295                            int use_asid)
296 {
297     int e;
298 
299     e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
300     if (e == MMU_DTLB_MULTIPLE) {
301         e = MMU_ITLB_MULTIPLE;
302     } else if (e == MMU_DTLB_MISS) {
303         e = MMU_ITLB_MISS;
304     } else if (e >= 0) {
305         update_itlb_use(env, e);
306     }
307     return e;
308 }
309 
310 /* Find utlb entry
311    Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
find_utlb_entry(CPUSH4State * env,target_ulong address,int use_asid)312 static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
313 {
314     /* per utlb access */
315     increment_urc(env);
316 
317     /* Return entry */
318     return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
319 }
320 
321 /* Match address against MMU
322    Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
323    MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
324    MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
325    MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
326    MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
327 */
get_mmu_address(CPUSH4State * env,target_ulong * physical,int * prot,target_ulong address,MMUAccessType access_type)328 static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
329                            int *prot, target_ulong address,
330                            MMUAccessType access_type)
331 {
332     int use_asid, n;
333     tlb_t *matching = NULL;
334 
335     use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
336 
337     if (access_type == MMU_INST_FETCH) {
338         n = find_itlb_entry(env, address, use_asid);
339         if (n >= 0) {
340             matching = &env->itlb[n];
341             if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
342                 n = MMU_ITLB_VIOLATION;
343             } else {
344                 *prot = PAGE_EXEC;
345             }
346         } else {
347             n = find_utlb_entry(env, address, use_asid);
348             if (n >= 0) {
349                 n = copy_utlb_entry_itlb(env, n);
350                 matching = &env->itlb[n];
351                 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
352                     n = MMU_ITLB_VIOLATION;
353                 } else {
354                     *prot = PAGE_READ | PAGE_EXEC;
355                     if ((matching->pr & 1) && matching->d) {
356                         *prot |= PAGE_WRITE;
357                     }
358                 }
359             } else if (n == MMU_DTLB_MULTIPLE) {
360                 n = MMU_ITLB_MULTIPLE;
361             } else if (n == MMU_DTLB_MISS) {
362                 n = MMU_ITLB_MISS;
363             }
364         }
365     } else {
366         n = find_utlb_entry(env, address, use_asid);
367         if (n >= 0) {
368             matching = &env->utlb[n];
369             if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
370                 n = (access_type == MMU_DATA_STORE)
371                     ? MMU_DTLB_VIOLATION_WRITE : MMU_DTLB_VIOLATION_READ;
372             } else if ((access_type == MMU_DATA_STORE) && !(matching->pr & 1)) {
373                 n = MMU_DTLB_VIOLATION_WRITE;
374             } else if ((access_type == MMU_DATA_STORE) && !matching->d) {
375                 n = MMU_DTLB_INITIAL_WRITE;
376             } else {
377                 *prot = PAGE_READ;
378                 if ((matching->pr & 1) && matching->d) {
379                     *prot |= PAGE_WRITE;
380                 }
381             }
382         } else if (n == MMU_DTLB_MISS) {
383             n = (access_type == MMU_DATA_STORE)
384                 ? MMU_DTLB_MISS_WRITE : MMU_DTLB_MISS_READ;
385         }
386     }
387     if (n >= 0) {
388         n = MMU_OK;
389         *physical = ((matching->ppn << 10) & ~(matching->size - 1))
390                     | (address & (matching->size - 1));
391     }
392     return n;
393 }
394 
get_physical_address(CPUSH4State * env,target_ulong * physical,int * prot,target_ulong address,MMUAccessType access_type)395 static int get_physical_address(CPUSH4State * env, target_ulong * physical,
396                                 int *prot, target_ulong address,
397                                 MMUAccessType access_type)
398 {
399     /* P1, P2 and P4 areas do not use translation */
400     if ((address >= 0x80000000 && address < 0xc0000000) || address >= 0xe0000000) {
401         if (!(env->sr & (1u << SR_MD))
402                 && (address < 0xe0000000 || address >= 0xe4000000)) {
403             /* Unauthorized access in user mode (only store queues are available) */
404             qemu_log_mask(LOG_GUEST_ERROR, "Unauthorized access\n");
405             if (access_type == MMU_DATA_LOAD) {
406                 return MMU_DADDR_ERROR_READ;
407             } else if (access_type == MMU_DATA_STORE) {
408                 return MMU_DADDR_ERROR_WRITE;
409             } else {
410                 return MMU_IADDR_ERROR;
411             }
412         }
413         if (address >= 0x80000000 && address < 0xc0000000) {
414             /* Mask upper 3 bits for P1 and P2 areas */
415             *physical = address & 0x1fffffff;
416         } else {
417             *physical = address;
418         }
419         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
420         return MMU_OK;
421     }
422 
423     /* If MMU is disabled, return the corresponding physical page */
424     if (!(env->mmucr & MMUCR_AT)) {
425         *physical = address & 0x1FFFFFFF;
426         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
427         return MMU_OK;
428     }
429 
430     /* We need to resort to the MMU */
431     return get_mmu_address(env, physical, prot, address, access_type);
432 }
433 
superh_cpu_get_phys_page_debug(CPUState * cs,vaddr addr)434 hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
435 {
436     target_ulong physical;
437     int prot;
438 
439     if (get_physical_address(cpu_env(cs), &physical, &prot, addr, MMU_DATA_LOAD)
440             == MMU_OK) {
441         return physical;
442     }
443 
444     return -1;
445 }
446 
cpu_load_tlb(CPUSH4State * env)447 void cpu_load_tlb(CPUSH4State * env)
448 {
449     CPUState *cs = env_cpu(env);
450     int n = cpu_mmucr_urc(env->mmucr);
451     tlb_t * entry = &env->utlb[n];
452 
453     if (entry->v) {
454         /* Overwriting valid entry in utlb. */
455         target_ulong address = entry->vpn << 10;
456         tlb_flush_page(cs, address);
457     }
458 
459     /* Take values into cpu status from registers. */
460     entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
461     entry->vpn  = cpu_pteh_vpn(env->pteh);
462     entry->v    = (uint8_t)cpu_ptel_v(env->ptel);
463     entry->ppn  = cpu_ptel_ppn(env->ptel);
464     entry->sz   = (uint8_t)cpu_ptel_sz(env->ptel);
465     switch (entry->sz) {
466     case 0: /* 00 */
467         entry->size = 1024; /* 1K */
468         break;
469     case 1: /* 01 */
470         entry->size = 1024 * 4; /* 4K */
471         break;
472     case 2: /* 10 */
473         entry->size = 1024 * 64; /* 64K */
474         break;
475     case 3: /* 11 */
476         entry->size = 1024 * 1024; /* 1M */
477         break;
478     default:
479         cpu_abort(cs, "Unhandled load_tlb");
480         break;
481     }
482     entry->sh   = (uint8_t)cpu_ptel_sh(env->ptel);
483     entry->c    = (uint8_t)cpu_ptel_c(env->ptel);
484     entry->pr   = (uint8_t)cpu_ptel_pr(env->ptel);
485     entry->d    = (uint8_t)cpu_ptel_d(env->ptel);
486     entry->wt   = (uint8_t)cpu_ptel_wt(env->ptel);
487     entry->sa   = (uint8_t)cpu_ptea_sa(env->ptea);
488     entry->tc   = (uint8_t)cpu_ptea_tc(env->ptea);
489 }
490 
cpu_sh4_invalidate_tlb(CPUSH4State * s)491  void cpu_sh4_invalidate_tlb(CPUSH4State *s)
492 {
493     int i;
494 
495     /* UTLB */
496     for (i = 0; i < UTLB_SIZE; i++) {
497         tlb_t * entry = &s->utlb[i];
498         entry->v = 0;
499     }
500     /* ITLB */
501     for (i = 0; i < ITLB_SIZE; i++) {
502         tlb_t * entry = &s->itlb[i];
503         entry->v = 0;
504     }
505 
506     tlb_flush(env_cpu(s));
507 }
508 
cpu_sh4_read_mmaped_itlb_addr(CPUSH4State * s,hwaddr addr)509 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
510                                        hwaddr addr)
511 {
512     int index = (addr & 0x00000300) >> 8;
513     tlb_t * entry = &s->itlb[index];
514 
515     return (entry->vpn  << 10) |
516            (entry->v    <<  8) |
517            (entry->asid);
518 }
519 
cpu_sh4_write_mmaped_itlb_addr(CPUSH4State * s,hwaddr addr,uint32_t mem_value)520 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
521                                     uint32_t mem_value)
522 {
523     uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
524     uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
525     uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
526 
527     int index = (addr & 0x00000300) >> 8;
528     tlb_t * entry = &s->itlb[index];
529     if (entry->v) {
530         /* Overwriting valid entry in itlb. */
531         target_ulong address = entry->vpn << 10;
532         tlb_flush_page(env_cpu(s), address);
533     }
534     entry->asid = asid;
535     entry->vpn = vpn;
536     entry->v = v;
537 }
538 
cpu_sh4_read_mmaped_itlb_data(CPUSH4State * s,hwaddr addr)539 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
540                                        hwaddr addr)
541 {
542     int array = (addr & 0x00800000) >> 23;
543     int index = (addr & 0x00000300) >> 8;
544     tlb_t * entry = &s->itlb[index];
545 
546     if (array == 0) {
547         /* ITLB Data Array 1 */
548         return (entry->ppn << 10) |
549                (entry->v   <<  8) |
550                (entry->pr  <<  5) |
551                ((entry->sz & 1) <<  6) |
552                ((entry->sz & 2) <<  4) |
553                (entry->c   <<  3) |
554                (entry->sh  <<  1);
555     } else {
556         /* ITLB Data Array 2 */
557         return (entry->tc << 1) |
558                (entry->sa);
559     }
560 }
561 
cpu_sh4_write_mmaped_itlb_data(CPUSH4State * s,hwaddr addr,uint32_t mem_value)562 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
563                                     uint32_t mem_value)
564 {
565     int array = (addr & 0x00800000) >> 23;
566     int index = (addr & 0x00000300) >> 8;
567     tlb_t * entry = &s->itlb[index];
568 
569     if (array == 0) {
570         /* ITLB Data Array 1 */
571         if (entry->v) {
572             /* Overwriting valid entry in utlb. */
573             target_ulong address = entry->vpn << 10;
574             tlb_flush_page(env_cpu(s), address);
575         }
576         entry->ppn = (mem_value & 0x1ffffc00) >> 10;
577         entry->v   = (mem_value & 0x00000100) >> 8;
578         entry->sz  = (mem_value & 0x00000080) >> 6 |
579                      (mem_value & 0x00000010) >> 4;
580         entry->pr  = (mem_value & 0x00000040) >> 5;
581         entry->c   = (mem_value & 0x00000008) >> 3;
582         entry->sh  = (mem_value & 0x00000002) >> 1;
583     } else {
584         /* ITLB Data Array 2 */
585         entry->tc  = (mem_value & 0x00000008) >> 3;
586         entry->sa  = (mem_value & 0x00000007);
587     }
588 }
589 
cpu_sh4_read_mmaped_utlb_addr(CPUSH4State * s,hwaddr addr)590 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
591                                        hwaddr addr)
592 {
593     int index = (addr & 0x00003f00) >> 8;
594     tlb_t * entry = &s->utlb[index];
595 
596     increment_urc(s); /* per utlb access */
597 
598     return (entry->vpn  << 10) |
599            (entry->v    <<  8) |
600            (entry->asid);
601 }
602 
cpu_sh4_write_mmaped_utlb_addr(CPUSH4State * s,hwaddr addr,uint32_t mem_value)603 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
604                                     uint32_t mem_value)
605 {
606     int associate = addr & 0x0000080;
607     uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
608     uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
609     uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
610     uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
611     int use_asid = !(s->mmucr & MMUCR_SV) || !(s->sr & (1u << SR_MD));
612 
613     if (associate) {
614         int i;
615         tlb_t * utlb_match_entry = NULL;
616         int needs_tlb_flush = 0;
617 
618         /* search UTLB */
619         for (i = 0; i < UTLB_SIZE; i++) {
620             tlb_t * entry = &s->utlb[i];
621             if (!entry->v)
622                 continue;
623 
624             if (entry->vpn == vpn
625                 && (!use_asid || entry->asid == asid || entry->sh)) {
626                 if (utlb_match_entry) {
627                     CPUState *cs = env_cpu(s);
628 
629                     /* Multiple TLB Exception */
630                     cs->exception_index = 0x140;
631                     s->tea = addr;
632                     break;
633                 }
634                 if (entry->v && !v)
635                     needs_tlb_flush = 1;
636                 entry->v = v;
637                 entry->d = d;
638                 utlb_match_entry = entry;
639             }
640             increment_urc(s); /* per utlb access */
641         }
642 
643         /* search ITLB */
644         for (i = 0; i < ITLB_SIZE; i++) {
645             tlb_t * entry = &s->itlb[i];
646             if (entry->vpn == vpn
647                 && (!use_asid || entry->asid == asid || entry->sh)) {
648                 if (entry->v && !v)
649                     needs_tlb_flush = 1;
650                 if (utlb_match_entry)
651                     *entry = *utlb_match_entry;
652                 else
653                     entry->v = v;
654                 break;
655             }
656         }
657 
658         if (needs_tlb_flush) {
659             tlb_flush_page(env_cpu(s), vpn << 10);
660         }
661     } else {
662         int index = (addr & 0x00003f00) >> 8;
663         tlb_t * entry = &s->utlb[index];
664         if (entry->v) {
665             CPUState *cs = env_cpu(s);
666 
667             /* Overwriting valid entry in utlb. */
668             target_ulong address = entry->vpn << 10;
669             tlb_flush_page(cs, address);
670         }
671         entry->asid = asid;
672         entry->vpn = vpn;
673         entry->d = d;
674         entry->v = v;
675         increment_urc(s);
676     }
677 }
678 
cpu_sh4_read_mmaped_utlb_data(CPUSH4State * s,hwaddr addr)679 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
680                                        hwaddr addr)
681 {
682     int array = (addr & 0x00800000) >> 23;
683     int index = (addr & 0x00003f00) >> 8;
684     tlb_t * entry = &s->utlb[index];
685 
686     increment_urc(s); /* per utlb access */
687 
688     if (array == 0) {
689         /* ITLB Data Array 1 */
690         return (entry->ppn << 10) |
691                (entry->v   <<  8) |
692                (entry->pr  <<  5) |
693                ((entry->sz & 1) <<  6) |
694                ((entry->sz & 2) <<  4) |
695                (entry->c   <<  3) |
696                (entry->d   <<  2) |
697                (entry->sh  <<  1) |
698                (entry->wt);
699     } else {
700         /* ITLB Data Array 2 */
701         return (entry->tc << 1) |
702                (entry->sa);
703     }
704 }
705 
cpu_sh4_write_mmaped_utlb_data(CPUSH4State * s,hwaddr addr,uint32_t mem_value)706 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
707                                     uint32_t mem_value)
708 {
709     int array = (addr & 0x00800000) >> 23;
710     int index = (addr & 0x00003f00) >> 8;
711     tlb_t * entry = &s->utlb[index];
712 
713     increment_urc(s); /* per utlb access */
714 
715     if (array == 0) {
716         /* UTLB Data Array 1 */
717         if (entry->v) {
718             /* Overwriting valid entry in utlb. */
719             target_ulong address = entry->vpn << 10;
720             tlb_flush_page(env_cpu(s), address);
721         }
722         entry->ppn = (mem_value & 0x1ffffc00) >> 10;
723         entry->v   = (mem_value & 0x00000100) >> 8;
724         entry->sz  = (mem_value & 0x00000080) >> 6 |
725                      (mem_value & 0x00000010) >> 4;
726         entry->pr  = (mem_value & 0x00000060) >> 5;
727         entry->c   = (mem_value & 0x00000008) >> 3;
728         entry->d   = (mem_value & 0x00000004) >> 2;
729         entry->sh  = (mem_value & 0x00000002) >> 1;
730         entry->wt  = (mem_value & 0x00000001);
731     } else {
732         /* UTLB Data Array 2 */
733         entry->tc = (mem_value & 0x00000008) >> 3;
734         entry->sa = (mem_value & 0x00000007);
735     }
736 }
737 
cpu_sh4_is_cached(CPUSH4State * env,target_ulong addr)738 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
739 {
740     int n;
741     int use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
742 
743     /* check area */
744     if (env->sr & (1u << SR_MD)) {
745         /* For privileged mode, P2 and P4 area is not cacheable. */
746         if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
747             return 0;
748     } else {
749         /* For user mode, only U0 area is cacheable. */
750         if (0x80000000 <= addr)
751             return 0;
752     }
753 
754     /*
755      * TODO : Evaluate CCR and check if the cache is on or off.
756      *        Now CCR is not in CPUSH4State, but in SH7750State.
757      *        When you move the ccr into CPUSH4State, the code will be
758      *        as follows.
759      */
760 #if 0
761     /* check if operand cache is enabled or not. */
762     if (!(env->ccr & 1))
763         return 0;
764 #endif
765 
766     /* if MMU is off, no check for TLB. */
767     if (env->mmucr & MMUCR_AT)
768         return 1;
769 
770     /* check TLB */
771     n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
772     if (n >= 0)
773         return env->itlb[n].c;
774 
775     n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
776     if (n >= 0)
777         return env->utlb[n].c;
778 
779     return 0;
780 }
781 
superh_cpu_exec_interrupt(CPUState * cs,int interrupt_request)782 bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
783 {
784     if (interrupt_request & CPU_INTERRUPT_HARD) {
785         /* Delay slots are indivisible, ignore interrupts */
786         if (cpu_env(cs)->flags & TB_FLAG_DELAY_SLOT_MASK) {
787             return false;
788         } else {
789             superh_cpu_do_interrupt(cs);
790             return true;
791         }
792     }
793     return false;
794 }
795 
superh_cpu_tlb_fill(CPUState * cs,vaddr address,int size,MMUAccessType access_type,int mmu_idx,bool probe,uintptr_t retaddr)796 bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
797                          MMUAccessType access_type, int mmu_idx,
798                          bool probe, uintptr_t retaddr)
799 {
800     CPUSH4State *env = cpu_env(cs);
801     int ret;
802 
803     target_ulong physical;
804     int prot;
805 
806     ret = get_physical_address(env, &physical, &prot, address, access_type);
807 
808     if (ret == MMU_OK) {
809         address &= TARGET_PAGE_MASK;
810         physical &= TARGET_PAGE_MASK;
811         tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
812         return true;
813     }
814     if (probe) {
815         return false;
816     }
817 
818     if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) {
819         env->pteh = (env->pteh & PTEH_ASID_MASK) | (address & PTEH_VPN_MASK);
820     }
821 
822     env->tea = address;
823     switch (ret) {
824     case MMU_ITLB_MISS:
825     case MMU_DTLB_MISS_READ:
826         cs->exception_index = 0x040;
827         break;
828     case MMU_DTLB_MULTIPLE:
829     case MMU_ITLB_MULTIPLE:
830         cs->exception_index = 0x140;
831         break;
832     case MMU_ITLB_VIOLATION:
833         cs->exception_index = 0x0a0;
834         break;
835     case MMU_DTLB_MISS_WRITE:
836         cs->exception_index = 0x060;
837         break;
838     case MMU_DTLB_INITIAL_WRITE:
839         cs->exception_index = 0x080;
840         break;
841     case MMU_DTLB_VIOLATION_READ:
842         cs->exception_index = 0x0a0;
843         break;
844     case MMU_DTLB_VIOLATION_WRITE:
845         cs->exception_index = 0x0c0;
846         break;
847     case MMU_IADDR_ERROR:
848     case MMU_DADDR_ERROR_READ:
849         cs->exception_index = 0x0e0;
850         break;
851     case MMU_DADDR_ERROR_WRITE:
852         cs->exception_index = 0x100;
853         break;
854     default:
855         cpu_abort(cs, "Unhandled MMU fault");
856     }
857     cpu_loop_exit_restore(cs, retaddr);
858 }
859 #endif /* !CONFIG_USER_ONLY */
860