1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "reg_helper.h" 28 #include "dcn10_optc.h" 29 #include "dc.h" 30 #include "dc_trace.h" 31 32 #define REG(reg)\ 33 optc1->tg_regs->reg 34 35 #define CTX \ 36 optc1->base.ctx 37 38 #undef FN 39 #define FN(reg_name, field_name) \ 40 optc1->tg_shift->field_name, optc1->tg_mask->field_name 41 42 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100 43 44 /** 45 * apply_front_porch_workaround() - This is a workaround for a bug that has 46 * existed since R5xx and has not been fixed 47 * keep Front porch at minimum 2 for Interlaced 48 * mode or 1 for progressive. 49 * 50 * @timing: Timing parameters used to configure DCN blocks. 51 */ 52 static void apply_front_porch_workaround(struct dc_crtc_timing *timing) 53 { 54 if (timing->flags.INTERLACE == 1) { 55 if (timing->v_front_porch < 2) 56 timing->v_front_porch = 2; 57 } else { 58 if (timing->v_front_porch < 1) 59 timing->v_front_porch = 1; 60 } 61 } 62 63 void optc1_program_global_sync( 64 struct timing_generator *optc, 65 int vready_offset, 66 int vstartup_start, 67 int vupdate_offset, 68 int vupdate_width, 69 int pstate_keepout) 70 { 71 struct optc *optc1 = DCN10TG_FROM_TG(optc); 72 73 optc1->vready_offset = vready_offset; 74 optc1->vstartup_start = vstartup_start; 75 optc1->vupdate_offset = vupdate_offset; 76 optc1->vupdate_width = vupdate_width; 77 optc1->pstate_keepout = pstate_keepout; 78 79 if (optc1->vstartup_start == 0) { 80 BREAK_TO_DEBUGGER(); 81 return; 82 } 83 84 REG_SET(OTG_VSTARTUP_PARAM, 0, 85 VSTARTUP_START, optc1->vstartup_start); 86 87 REG_SET_2(OTG_VUPDATE_PARAM, 0, 88 VUPDATE_OFFSET, optc1->vupdate_offset, 89 VUPDATE_WIDTH, optc1->vupdate_width); 90 91 REG_SET(OTG_VREADY_PARAM, 0, 92 VREADY_OFFSET, optc1->vready_offset); 93 } 94 95 static void optc1_disable_stereo(struct timing_generator *optc) 96 { 97 struct optc *optc1 = DCN10TG_FROM_TG(optc); 98 99 REG_SET(OTG_STEREO_CONTROL, 0, 100 OTG_STEREO_EN, 0); 101 102 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0, 103 OTG_3D_STRUCTURE_EN, 0, 104 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0); 105 } 106 107 void optc1_setup_vertical_interrupt0( 108 struct timing_generator *optc, 109 uint32_t start_line, 110 uint32_t end_line) 111 { 112 struct optc *optc1 = DCN10TG_FROM_TG(optc); 113 114 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0, 115 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line, 116 OTG_VERTICAL_INTERRUPT0_LINE_END, end_line); 117 } 118 119 void optc1_setup_vertical_interrupt1( 120 struct timing_generator *optc, 121 uint32_t start_line) 122 { 123 struct optc *optc1 = DCN10TG_FROM_TG(optc); 124 125 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0, 126 OTG_VERTICAL_INTERRUPT1_LINE_START, start_line); 127 } 128 129 void optc1_setup_vertical_interrupt2( 130 struct timing_generator *optc, 131 uint32_t start_line) 132 { 133 struct optc *optc1 = DCN10TG_FROM_TG(optc); 134 135 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0, 136 OTG_VERTICAL_INTERRUPT2_LINE_START, start_line); 137 } 138 139 /** 140 * optc1_program_timing() - used by mode timing set Program 141 * CRTC Timing Registers - OTG_H_*, 142 * OTG_V_*, Pixel repetition. 143 * Including SYNC. Call BIOS command table to program Timings. 144 * 145 * @optc: timing_generator instance. 146 * @dc_crtc_timing: Timing parameters used to configure DCN blocks. 147 * @vready_offset: Vready's starting position. 148 * @vstartup_start: Vstartup period. 149 * @vupdate_offset: Vupdate starting position. 150 * @vupdate_width: Vupdate duration. 151 * @pstate_keepout: determines low power mode timing during refresh 152 * @signal: DC signal types. 153 * @use_vbios: to program timings from BIOS command table. 154 * 155 */ 156 void optc1_program_timing( 157 struct timing_generator *optc, 158 const struct dc_crtc_timing *dc_crtc_timing, 159 int vready_offset, 160 int vstartup_start, 161 int vupdate_offset, 162 int vupdate_width, 163 int pstate_keepout, 164 const enum signal_type signal, 165 bool use_vbios) 166 { 167 (void)use_vbios; 168 struct dc_crtc_timing patched_crtc_timing; 169 uint32_t asic_blank_end; 170 uint32_t asic_blank_start; 171 uint32_t v_total; 172 uint32_t v_sync_end; 173 uint32_t h_sync_polarity, v_sync_polarity; 174 uint32_t start_point = 0; 175 uint32_t field_num = 0; 176 enum h_timing_div_mode h_div = H_TIMING_NO_DIV; 177 178 struct optc *optc1 = DCN10TG_FROM_TG(optc); 179 180 optc1->signal = signal; 181 optc1->vready_offset = vready_offset; 182 optc1->vstartup_start = vstartup_start; 183 optc1->vupdate_offset = vupdate_offset; 184 optc1->vupdate_width = vupdate_width; 185 optc1->pstate_keepout = pstate_keepout; 186 patched_crtc_timing = *dc_crtc_timing; 187 apply_front_porch_workaround(&patched_crtc_timing); 188 optc1->orginal_patched_timing = patched_crtc_timing; 189 190 /* Load horizontal timing */ 191 192 /* CRTC_H_TOTAL = vesa.h_total - 1 */ 193 REG_SET(OTG_H_TOTAL, 0, 194 OTG_H_TOTAL, patched_crtc_timing.h_total - 1); 195 196 /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */ 197 REG_UPDATE_2(OTG_H_SYNC_A, 198 OTG_H_SYNC_A_START, 0, 199 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width); 200 201 /* blank_start = line end - front porch */ 202 asic_blank_start = patched_crtc_timing.h_total - 203 patched_crtc_timing.h_front_porch; 204 205 /* blank_end = blank_start - active */ 206 asic_blank_end = asic_blank_start - 207 patched_crtc_timing.h_border_right - 208 patched_crtc_timing.h_addressable - 209 patched_crtc_timing.h_border_left; 210 211 REG_UPDATE_2(OTG_H_BLANK_START_END, 212 OTG_H_BLANK_START, asic_blank_start, 213 OTG_H_BLANK_END, asic_blank_end); 214 215 /* h_sync polarity */ 216 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? 217 0 : 1; 218 219 REG_UPDATE(OTG_H_SYNC_A_CNTL, 220 OTG_H_SYNC_A_POL, h_sync_polarity); 221 222 v_total = patched_crtc_timing.v_total - 1; 223 224 REG_SET(OTG_V_TOTAL, 0, 225 OTG_V_TOTAL, v_total); 226 227 /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and 228 * OTG_V_TOTAL_MIN are equal to V_TOTAL. 229 */ 230 optc->funcs->set_vtotal_min_max(optc, v_total, v_total); 231 232 /* v_sync_start = 0, v_sync_end = v_sync_width */ 233 v_sync_end = patched_crtc_timing.v_sync_width; 234 235 REG_UPDATE_2(OTG_V_SYNC_A, 236 OTG_V_SYNC_A_START, 0, 237 OTG_V_SYNC_A_END, v_sync_end); 238 239 /* blank_start = frame end - front porch */ 240 asic_blank_start = patched_crtc_timing.v_total - 241 patched_crtc_timing.v_front_porch; 242 243 /* blank_end = blank_start - active */ 244 asic_blank_end = asic_blank_start - 245 patched_crtc_timing.v_border_bottom - 246 patched_crtc_timing.v_addressable - 247 patched_crtc_timing.v_border_top; 248 249 REG_UPDATE_2(OTG_V_BLANK_START_END, 250 OTG_V_BLANK_START, asic_blank_start, 251 OTG_V_BLANK_END, asic_blank_end); 252 253 /* v_sync polarity */ 254 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ? 255 0 : 1; 256 257 REG_UPDATE(OTG_V_SYNC_A_CNTL, 258 OTG_V_SYNC_A_POL, v_sync_polarity); 259 260 if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT || 261 optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 262 optc1->signal == SIGNAL_TYPE_EDP) { 263 start_point = 1; 264 if (patched_crtc_timing.flags.INTERLACE == 1) 265 field_num = 1; 266 } 267 268 /* Interlace */ 269 if (REG(OTG_INTERLACE_CONTROL)) { 270 if (patched_crtc_timing.flags.INTERLACE == 1) 271 REG_UPDATE(OTG_INTERLACE_CONTROL, 272 OTG_INTERLACE_ENABLE, 1); 273 else 274 REG_UPDATE(OTG_INTERLACE_CONTROL, 275 OTG_INTERLACE_ENABLE, 0); 276 } 277 278 /* VTG enable set to 0 first VInit */ 279 REG_UPDATE(CONTROL, 280 VTG0_ENABLE, 0); 281 282 /* original code is using VTG offset to address OTG reg, seems wrong */ 283 REG_UPDATE_2(OTG_CONTROL, 284 OTG_START_POINT_CNTL, start_point, 285 OTG_FIELD_NUMBER_CNTL, field_num); 286 287 optc->funcs->program_global_sync(optc, 288 vready_offset, 289 vstartup_start, 290 vupdate_offset, 291 vupdate_width, 292 pstate_keepout); 293 294 optc->funcs->set_vtg_params(optc, dc_crtc_timing, true); 295 296 /* TODO 297 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1 298 * program_horz_count_by_2 299 * for DVI 30bpp mode, 0 otherwise 300 * program_horz_count_by_2(optc, &patched_crtc_timing); 301 */ 302 303 /* Enable stereo - only when we need to pack 3D frame. Other types 304 * of stereo handled in explicit call 305 */ 306 if (optc->funcs->is_two_pixels_per_container(&patched_crtc_timing) || optc1->opp_count == 2) 307 h_div = H_TIMING_DIV_BY2; 308 309 if (REG(OPTC_DATA_FORMAT_CONTROL) && optc1->tg_mask->OPTC_DATA_FORMAT != 0) { 310 uint32_t data_fmt = 0; 311 312 if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 313 data_fmt = 1; 314 else if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 315 data_fmt = 2; 316 317 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt); 318 } 319 320 if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) { 321 if (optc1->opp_count == 4) 322 h_div = H_TIMING_DIV_BY4; 323 324 REG_UPDATE(OTG_H_TIMING_CNTL, 325 OTG_H_TIMING_DIV_MODE, h_div); 326 } else { 327 REG_UPDATE(OTG_H_TIMING_CNTL, 328 OTG_H_TIMING_DIV_BY2, h_div); 329 } 330 } 331 332 /** 333 * optc1_set_vtg_params - Set Vertical Timing Generator (VTG) parameters 334 * 335 * @optc: timing_generator struct used to extract the optc parameters 336 * @dc_crtc_timing: Timing parameters configured 337 * @program_fp2: Boolean value indicating if FP2 will be programmed or not 338 * 339 * OTG is responsible for generating the global sync signals, including 340 * vertical timing information for each HUBP in the dcfclk domain. Each VTG is 341 * associated with one OTG that provides HUBP with vertical timing information 342 * (i.e., there is 1:1 correspondence between OTG and VTG). This function is 343 * responsible for setting the OTG parameters to the VTG during the pipe 344 * programming. 345 */ 346 void optc1_set_vtg_params(struct timing_generator *optc, 347 const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2) 348 { 349 struct dc_crtc_timing patched_crtc_timing; 350 uint32_t asic_blank_end; 351 uint32_t v_init; 352 uint32_t v_fp2 = 0; 353 int32_t vertical_line_start; 354 355 struct optc *optc1 = DCN10TG_FROM_TG(optc); 356 357 patched_crtc_timing = *dc_crtc_timing; 358 apply_front_porch_workaround(&patched_crtc_timing); 359 360 /* VCOUNT_INIT is the start of blank */ 361 v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch; 362 363 /* end of blank = v_init - active */ 364 asic_blank_end = v_init - 365 patched_crtc_timing.v_border_bottom - 366 patched_crtc_timing.v_addressable - 367 patched_crtc_timing.v_border_top; 368 369 /* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */ 370 vertical_line_start = asic_blank_end - optc1->vstartup_start + 1; 371 if (vertical_line_start < 0) 372 v_fp2 = -vertical_line_start; 373 374 /* Interlace */ 375 if (REG(OTG_INTERLACE_CONTROL)) { 376 if (patched_crtc_timing.flags.INTERLACE == 1) { 377 v_init = v_init / 2; 378 if ((optc1->vstartup_start/2)*2 > asic_blank_end) 379 v_fp2 = v_fp2 / 2; 380 } 381 } 382 383 if (program_fp2) 384 REG_UPDATE_2(CONTROL, 385 VTG0_FP2, v_fp2, 386 VTG0_VCOUNT_INIT, v_init); 387 else 388 REG_UPDATE(CONTROL, VTG0_VCOUNT_INIT, v_init); 389 } 390 391 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable) 392 { 393 struct optc *optc1 = DCN10TG_FROM_TG(optc); 394 395 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; 396 397 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 398 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable); 399 } 400 401 /** 402 * optc1_set_timing_double_buffer() - DRR double buffering control 403 * 404 * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN, 405 * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers. 406 * 407 * @optc: timing_generator instance. 408 * @enable: Enable DRR double buffering control if true, disable otherwise. 409 * 410 * Options: any time, start of frame, dp start of frame (range timing) 411 */ 412 void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable) 413 { 414 struct optc *optc1 = DCN10TG_FROM_TG(optc); 415 uint32_t mode = enable ? 2 : 0; 416 417 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 418 OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mode); 419 } 420 421 /** 422 * optc1_unblank_crtc() - Call ASIC Control Object to UnBlank CRTC. 423 * 424 * @optc: timing_generator instance. 425 */ 426 static void optc1_unblank_crtc(struct timing_generator *optc) 427 { 428 struct optc *optc1 = DCN10TG_FROM_TG(optc); 429 430 REG_UPDATE_2(OTG_BLANK_CONTROL, 431 OTG_BLANK_DATA_EN, 0, 432 OTG_BLANK_DE_MODE, 0); 433 434 /* W/A for automated testing 435 * Automated testing will fail underflow test as there 436 * sporadic underflows which occur during the optc blank 437 * sequence. As a w/a, clear underflow on unblank. 438 * This prevents the failure, but will not mask actual 439 * underflow that affect real use cases. 440 */ 441 optc1_clear_optc_underflow(optc); 442 } 443 444 /** 445 * optc1_blank_crtc() - Call ASIC Control Object to Blank CRTC. 446 * 447 * @optc: timing_generator instance. 448 */ 449 450 static void optc1_blank_crtc(struct timing_generator *optc) 451 { 452 struct optc *optc1 = DCN10TG_FROM_TG(optc); 453 454 REG_UPDATE_2(OTG_BLANK_CONTROL, 455 OTG_BLANK_DATA_EN, 1, 456 OTG_BLANK_DE_MODE, 0); 457 458 optc1_set_blank_data_double_buffer(optc, false); 459 } 460 461 void optc1_set_blank(struct timing_generator *optc, 462 bool enable_blanking) 463 { 464 if (enable_blanking) 465 optc1_blank_crtc(optc); 466 else 467 optc1_unblank_crtc(optc); 468 } 469 470 bool optc1_is_blanked(struct timing_generator *optc) 471 { 472 struct optc *optc1 = DCN10TG_FROM_TG(optc); 473 uint32_t blank_en; 474 uint32_t blank_state; 475 476 REG_GET_2(OTG_BLANK_CONTROL, 477 OTG_BLANK_DATA_EN, &blank_en, 478 OTG_CURRENT_BLANK_STATE, &blank_state); 479 480 return blank_en && blank_state; 481 } 482 483 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable) 484 { 485 struct optc *optc1 = DCN10TG_FROM_TG(optc); 486 487 if (enable) { 488 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 489 OPTC_INPUT_CLK_EN, 1, 490 OPTC_INPUT_CLK_GATE_DIS, 1); 491 492 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, 493 OPTC_INPUT_CLK_ON, 1, 494 1, 1000); 495 496 /* Enable clock */ 497 REG_UPDATE_2(OTG_CLOCK_CONTROL, 498 OTG_CLOCK_EN, 1, 499 OTG_CLOCK_GATE_DIS, 1); 500 REG_WAIT(OTG_CLOCK_CONTROL, 501 OTG_CLOCK_ON, 1, 502 1, 1000); 503 } else { 504 505 //last chance to clear underflow, otherwise, it will always there due to clock is off. 506 if (optc->funcs->is_optc_underflow_occurred(optc) == true) 507 optc->funcs->clear_optc_underflow(optc); 508 509 REG_UPDATE_2(OTG_CLOCK_CONTROL, 510 OTG_CLOCK_GATE_DIS, 0, 511 OTG_CLOCK_EN, 0); 512 513 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 514 OPTC_INPUT_CLK_GATE_DIS, 0, 515 OPTC_INPUT_CLK_EN, 0); 516 } 517 } 518 519 /** 520 * optc1_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator. 521 * 522 * @optc: timing_generator instance. 523 */ 524 static bool optc1_enable_crtc(struct timing_generator *optc) 525 { 526 /* TODO FPGA wait for answer 527 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE 528 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK 529 */ 530 struct optc *optc1 = DCN10TG_FROM_TG(optc); 531 532 /* opp instance for OTG. For DCN1.0, ODM is remoed. 533 * OPP and OPTC should 1:1 mapping 534 */ 535 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 536 OPTC_SRC_SEL, optc->inst); 537 538 /* VTG enable first is for HW workaround */ 539 REG_UPDATE(CONTROL, 540 VTG0_ENABLE, 1); 541 542 REG_SEQ_START(); 543 544 /* Enable CRTC */ 545 REG_UPDATE_2(OTG_CONTROL, 546 OTG_DISABLE_POINT_CNTL, 3, 547 OTG_MASTER_EN, 1); 548 549 REG_SEQ_SUBMIT(); 550 REG_SEQ_WAIT_DONE(); 551 552 return true; 553 } 554 555 /* disable_crtc - call ASIC Control Object to disable Timing generator. */ 556 bool optc1_disable_crtc(struct timing_generator *optc) 557 { 558 struct optc *optc1 = DCN10TG_FROM_TG(optc); 559 560 /* disable otg request until end of the first line 561 * in the vertical blank region 562 */ 563 REG_UPDATE_2(OTG_CONTROL, 564 OTG_DISABLE_POINT_CNTL, 3, 565 OTG_MASTER_EN, 0); 566 567 REG_UPDATE(CONTROL, 568 VTG0_ENABLE, 0); 569 570 /* CRTC disabled, so disable clock. */ 571 REG_WAIT(OTG_CLOCK_CONTROL, 572 OTG_BUSY, 0, 573 1, 100000); 574 575 return true; 576 } 577 578 579 void optc1_program_blank_color( 580 struct timing_generator *optc, 581 const struct tg_color *black_color) 582 { 583 struct optc *optc1 = DCN10TG_FROM_TG(optc); 584 585 REG_SET_3(OTG_BLACK_COLOR, 0, 586 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb, 587 OTG_BLACK_COLOR_G_Y, black_color->color_g_y, 588 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr); 589 } 590 591 bool optc1_validate_timing( 592 struct timing_generator *optc, 593 const struct dc_crtc_timing *timing) 594 { 595 uint32_t v_blank; 596 uint32_t h_blank; 597 uint32_t min_v_blank; 598 struct optc *optc1 = DCN10TG_FROM_TG(optc); 599 600 ASSERT(timing != NULL); 601 602 v_blank = (timing->v_total - timing->v_addressable - 603 timing->v_border_top - timing->v_border_bottom); 604 605 h_blank = (timing->h_total - timing->h_addressable - 606 timing->h_border_right - 607 timing->h_border_left); 608 609 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && 610 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING && 611 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && 612 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE && 613 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE && 614 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA) 615 return false; 616 617 /* Temporarily blocking interlacing mode until it's supported */ 618 if (timing->flags.INTERLACE == 1) 619 return false; 620 621 /* Check maximum number of pixels supported by Timing Generator 622 * (Currently will never fail, in order to fail needs display which 623 * needs more than 8192 horizontal and 624 * more than 8192 vertical total pixels) 625 */ 626 if (timing->h_total > optc1->max_h_total || 627 timing->v_total > optc1->max_v_total) 628 return false; 629 630 631 if (h_blank < optc1->min_h_blank) 632 return false; 633 634 if (timing->h_sync_width < optc1->min_h_sync_width || 635 timing->v_sync_width < optc1->min_v_sync_width) 636 return false; 637 638 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; 639 640 if (v_blank < min_v_blank) 641 return false; 642 643 return true; 644 645 } 646 647 /* 648 * get_vblank_counter 649 * 650 * @brief 651 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which 652 * holds the counter of frames. 653 * 654 * @param 655 * struct timing_generator *optc - [in] timing generator which controls the 656 * desired CRTC 657 * 658 * @return 659 * Counter of frames, which should equal to number of vblanks. 660 */ 661 uint32_t optc1_get_vblank_counter(struct timing_generator *optc) 662 { 663 struct optc *optc1 = DCN10TG_FROM_TG(optc); 664 uint32_t frame_count; 665 666 REG_GET(OTG_STATUS_FRAME_COUNT, 667 OTG_FRAME_COUNT, &frame_count); 668 669 return frame_count; 670 } 671 672 void optc1_lock(struct timing_generator *optc) 673 { 674 struct optc *optc1 = DCN10TG_FROM_TG(optc); 675 676 REG_SET(OTG_GLOBAL_CONTROL0, 0, 677 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); 678 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 679 OTG_MASTER_UPDATE_LOCK, 1); 680 681 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 682 UPDATE_LOCK_STATUS, 1, 683 1, 10); 684 685 TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true); 686 } 687 688 void optc1_unlock(struct timing_generator *optc) 689 { 690 struct optc *optc1 = DCN10TG_FROM_TG(optc); 691 692 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 693 OTG_MASTER_UPDATE_LOCK, 0); 694 695 TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, false); 696 } 697 698 void optc1_get_position(struct timing_generator *optc, 699 struct crtc_position *position) 700 { 701 struct optc *optc1 = DCN10TG_FROM_TG(optc); 702 703 REG_GET_2(OTG_STATUS_POSITION, 704 OTG_HORZ_COUNT, &position->horizontal_count, 705 OTG_VERT_COUNT, &position->vertical_count); 706 707 REG_GET(OTG_NOM_VERT_POSITION, 708 OTG_VERT_COUNT_NOM, &position->nominal_vcount); 709 } 710 711 bool optc1_is_counter_moving(struct timing_generator *optc) 712 { 713 struct crtc_position position1, position2; 714 715 optc->funcs->get_position(optc, &position1); 716 optc->funcs->get_position(optc, &position2); 717 718 if (position1.horizontal_count == position2.horizontal_count && 719 position1.vertical_count == position2.vertical_count) 720 return false; 721 else 722 return true; 723 } 724 725 bool optc1_did_triggered_reset_occur( 726 struct timing_generator *optc) 727 { 728 struct optc *optc1 = DCN10TG_FROM_TG(optc); 729 uint32_t occurred_force, occurred_vsync; 730 731 REG_GET(OTG_FORCE_COUNT_NOW_CNTL, 732 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force); 733 734 REG_GET(OTG_VERT_SYNC_CONTROL, 735 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync); 736 737 return occurred_vsync != 0 || occurred_force != 0; 738 } 739 740 void optc1_disable_reset_trigger(struct timing_generator *optc) 741 { 742 struct optc *optc1 = DCN10TG_FROM_TG(optc); 743 744 REG_WRITE(OTG_TRIGA_CNTL, 0); 745 746 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 747 OTG_FORCE_COUNT_NOW_CLEAR, 1); 748 749 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 750 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1); 751 } 752 753 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst) 754 { 755 struct optc *optc1 = DCN10TG_FROM_TG(optc); 756 uint32_t falling_edge; 757 758 REG_GET(OTG_V_SYNC_A_CNTL, 759 OTG_V_SYNC_A_POL, &falling_edge); 760 761 if (falling_edge) 762 REG_SET_3(OTG_TRIGA_CNTL, 0, 763 /* vsync signal from selected OTG pipe based 764 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 765 */ 766 OTG_TRIGA_SOURCE_SELECT, 20, 767 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 768 /* always detect falling edge */ 769 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1); 770 else 771 REG_SET_3(OTG_TRIGA_CNTL, 0, 772 /* vsync signal from selected OTG pipe based 773 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 774 */ 775 OTG_TRIGA_SOURCE_SELECT, 20, 776 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 777 /* always detect rising edge */ 778 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1); 779 780 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 781 /* force H count to H_TOTAL and V count to V_TOTAL in 782 * progressive mode and V_TOTAL-1 in interlaced mode 783 */ 784 OTG_FORCE_COUNT_NOW_MODE, 2); 785 } 786 787 void optc1_enable_crtc_reset( 788 struct timing_generator *optc, 789 int source_tg_inst, 790 struct crtc_trigger_info *crtc_tp) 791 { 792 struct optc *optc1 = DCN10TG_FROM_TG(optc); 793 uint32_t falling_edge = 0; 794 uint32_t rising_edge = 0; 795 796 switch (crtc_tp->event) { 797 798 case CRTC_EVENT_VSYNC_RISING: 799 rising_edge = 1; 800 break; 801 802 case CRTC_EVENT_VSYNC_FALLING: 803 falling_edge = 1; 804 break; 805 } 806 807 REG_SET_4(OTG_TRIGA_CNTL, 0, 808 /* vsync signal from selected OTG pipe based 809 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 810 */ 811 OTG_TRIGA_SOURCE_SELECT, 20, 812 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 813 /* always detect falling edge */ 814 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge, 815 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge); 816 817 switch (crtc_tp->delay) { 818 case TRIGGER_DELAY_NEXT_LINE: 819 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 820 OTG_AUTO_FORCE_VSYNC_MODE, 1); 821 break; 822 case TRIGGER_DELAY_NEXT_PIXEL: 823 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 824 /* force H count to H_TOTAL and V count to V_TOTAL in 825 * progressive mode and V_TOTAL-1 in interlaced mode 826 */ 827 OTG_FORCE_COUNT_NOW_MODE, 2); 828 break; 829 } 830 } 831 832 void optc1_wait_for_state(struct timing_generator *optc, 833 enum crtc_state state) 834 { 835 struct optc *optc1 = DCN10TG_FROM_TG(optc); 836 837 switch (state) { 838 case CRTC_STATE_VBLANK: 839 REG_WAIT(OTG_STATUS, 840 OTG_V_BLANK, 1, 841 1, 100000); /* 1 vupdate at 10hz */ 842 break; 843 844 case CRTC_STATE_VACTIVE: 845 REG_WAIT(OTG_STATUS, 846 OTG_V_ACTIVE_DISP, 1, 847 1, 100000); /* 1 vupdate at 10hz */ 848 break; 849 850 default: 851 break; 852 } 853 } 854 855 void optc1_set_early_control( 856 struct timing_generator *optc, 857 uint32_t early_cntl) 858 { 859 (void)optc; 860 (void)early_cntl; 861 /* asic design change, do not need this control 862 * empty for share caller logic 863 */ 864 } 865 866 867 void optc1_set_static_screen_control( 868 struct timing_generator *optc, 869 uint32_t event_triggers, 870 uint32_t num_frames) 871 { 872 struct optc *optc1 = DCN10TG_FROM_TG(optc); 873 874 // By register spec, it only takes 8 bit value 875 if (num_frames > 0xFF) 876 num_frames = 0xFF; 877 878 /* Bit 8 is no longer applicable in RV for PSR case, 879 * set bit 8 to 0 if given 880 */ 881 if ((event_triggers & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN) 882 != 0) 883 event_triggers = event_triggers & 884 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN; 885 886 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0, 887 OTG_STATIC_SCREEN_EVENT_MASK, event_triggers, 888 OTG_STATIC_SCREEN_FRAME_COUNT, num_frames); 889 } 890 891 static void optc1_setup_manual_trigger(struct timing_generator *optc) 892 { 893 struct optc *optc1 = DCN10TG_FROM_TG(optc); 894 895 REG_SET(OTG_GLOBAL_CONTROL2, 0, 896 MANUAL_FLOW_CONTROL_SEL, optc->inst); 897 898 REG_SET_8(OTG_TRIGA_CNTL, 0, 899 OTG_TRIGA_SOURCE_SELECT, 22, 900 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst, 901 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1, 902 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0, 903 OTG_TRIGA_POLARITY_SELECT, 0, 904 OTG_TRIGA_FREQUENCY_SELECT, 0, 905 OTG_TRIGA_DELAY, 0, 906 OTG_TRIGA_CLEAR, 1); 907 } 908 909 static void optc1_program_manual_trigger(struct timing_generator *optc) 910 { 911 struct optc *optc1 = DCN10TG_FROM_TG(optc); 912 913 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 914 MANUAL_FLOW_CONTROL, 1); 915 916 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 917 MANUAL_FLOW_CONTROL, 0); 918 } 919 920 /** 921 * optc1_set_drr() - Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*. 922 * 923 * @optc: timing_generator instance. 924 * @params: parameters used for Dynamic Refresh Rate. 925 */ 926 void optc1_set_drr( 927 struct timing_generator *optc, 928 const struct drr_params *params) 929 { 930 struct optc *optc1 = DCN10TG_FROM_TG(optc); 931 932 if (params != NULL && 933 params->vertical_total_max > 0 && 934 params->vertical_total_min > 0) { 935 936 if (params->vertical_total_mid != 0) { 937 938 REG_SET(OTG_V_TOTAL_MID, 0, 939 OTG_V_TOTAL_MID, params->vertical_total_mid - 1); 940 941 REG_UPDATE_2(OTG_V_TOTAL_CONTROL, 942 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1, 943 OTG_VTOTAL_MID_FRAME_NUM, 944 (uint8_t)params->vertical_total_mid_frame_num); 945 946 } 947 948 optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1); 949 950 REG_UPDATE_5(OTG_V_TOTAL_CONTROL, 951 OTG_V_TOTAL_MIN_SEL, 1, 952 OTG_V_TOTAL_MAX_SEL, 1, 953 OTG_FORCE_LOCK_ON_EVENT, 0, 954 OTG_SET_V_TOTAL_MIN_MASK_EN, 0, 955 OTG_SET_V_TOTAL_MIN_MASK, 0); 956 } 957 958 // Setup manual flow control for EOF via TRIG_A 959 optc->funcs->setup_manual_trigger(optc); 960 } 961 962 void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max) 963 { 964 struct optc *optc1 = DCN10TG_FROM_TG(optc); 965 966 REG_SET(OTG_V_TOTAL_MAX, 0, 967 OTG_V_TOTAL_MAX, vtotal_max); 968 969 REG_SET(OTG_V_TOTAL_MIN, 0, 970 OTG_V_TOTAL_MIN, vtotal_min); 971 } 972 973 static void optc1_set_test_pattern( 974 struct timing_generator *optc, 975 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' 976 * because this is not DP-specific (which is probably somewhere in DP 977 * encoder) */ 978 enum controller_dp_test_pattern test_pattern, 979 enum dc_color_depth color_depth) 980 { 981 struct optc *optc1 = DCN10TG_FROM_TG(optc); 982 enum test_pattern_color_format bit_depth; 983 enum test_pattern_dyn_range dyn_range; 984 enum test_pattern_mode mode; 985 uint32_t pattern_mask; 986 uint32_t pattern_data; 987 /* color ramp generator mixes 16-bits color */ 988 uint32_t src_bpc = 16; 989 /* requested bpc */ 990 uint32_t dst_bpc; 991 uint32_t index; 992 /* RGB values of the color bars. 993 * Produce two RGB colors: RGB0 - white (all Fs) 994 * and RGB1 - black (all 0s) 995 * (three RGB components for two colors) 996 */ 997 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000, 998 0x0000, 0x0000}; 999 /* dest color (converted to the specified color format) */ 1000 uint16_t dst_color[6]; 1001 uint32_t inc_base; 1002 1003 /* translate to bit depth */ 1004 switch (color_depth) { 1005 case COLOR_DEPTH_666: 1006 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; 1007 break; 1008 case COLOR_DEPTH_888: 1009 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 1010 break; 1011 case COLOR_DEPTH_101010: 1012 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10; 1013 break; 1014 case COLOR_DEPTH_121212: 1015 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12; 1016 break; 1017 default: 1018 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 1019 break; 1020 } 1021 1022 switch (test_pattern) { 1023 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES: 1024 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA: 1025 { 1026 dyn_range = (test_pattern == 1027 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ? 1028 TEST_PATTERN_DYN_RANGE_CEA : 1029 TEST_PATTERN_DYN_RANGE_VESA); 1030 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB; 1031 1032 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS, 1033 OTG_TEST_PATTERN_VRES, 6, 1034 OTG_TEST_PATTERN_HRES, 6); 1035 1036 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 1037 OTG_TEST_PATTERN_EN, 1, 1038 OTG_TEST_PATTERN_MODE, mode, 1039 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range, 1040 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1041 } 1042 break; 1043 1044 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS: 1045 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS: 1046 { 1047 mode = (test_pattern == 1048 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ? 1049 TEST_PATTERN_MODE_VERTICALBARS : 1050 TEST_PATTERN_MODE_HORIZONTALBARS); 1051 1052 switch (bit_depth) { 1053 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1054 dst_bpc = 6; 1055 break; 1056 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1057 dst_bpc = 8; 1058 break; 1059 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1060 dst_bpc = 10; 1061 break; 1062 default: 1063 dst_bpc = 8; 1064 break; 1065 } 1066 1067 /* adjust color to the required colorFormat */ 1068 for (index = 0; index < 6; index++) { 1069 /* dst = 2^dstBpc * src / 2^srcBpc = src >> 1070 * (srcBpc - dstBpc); 1071 */ 1072 dst_color[index] = 1073 src_color[index] >> (src_bpc - dst_bpc); 1074 /* CRTC_TEST_PATTERN_DATA has 16 bits, 1075 * lowest 6 are hardwired to ZERO 1076 * color bits should be left aligned to MSB 1077 * XXXXXXXXXX000000 for 10 bit, 1078 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6 1079 */ 1080 dst_color[index] <<= (16 - dst_bpc); 1081 } 1082 1083 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1084 1085 /* We have to write the mask before data, similar to pipeline. 1086 * For example, for 8 bpc, if we want RGB0 to be magenta, 1087 * and RGB1 to be cyan, 1088 * we need to make 7 writes: 1089 * MASK DATA 1090 * 000001 00000000 00000000 set mask to R0 1091 * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0 1092 * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0 1093 * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1 1094 * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1 1095 * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1 1096 * 100000 11111111 00000000 B1 255, 0xFF00 1097 * 1098 * we will make a loop of 6 in which we prepare the mask, 1099 * then write, then prepare the color for next write. 1100 * first iteration will write mask only, 1101 * but each next iteration color prepared in 1102 * previous iteration will be written within new mask, 1103 * the last component will written separately, 1104 * mask is not changing between 6th and 7th write 1105 * and color will be prepared by last iteration 1106 */ 1107 1108 /* write color, color values mask in CRTC_TEST_PATTERN_MASK 1109 * is B1, G1, R1, B0, G0, R0 1110 */ 1111 pattern_data = 0; 1112 for (index = 0; index < 6; index++) { 1113 /* prepare color mask, first write PATTERN_DATA 1114 * will have all zeros 1115 */ 1116 pattern_mask = (1 << index); 1117 1118 /* write color component */ 1119 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1120 OTG_TEST_PATTERN_MASK, pattern_mask, 1121 OTG_TEST_PATTERN_DATA, pattern_data); 1122 1123 /* prepare next color component, 1124 * will be written in the next iteration 1125 */ 1126 pattern_data = dst_color[index]; 1127 } 1128 /* write last color component, 1129 * it's been already prepared in the loop 1130 */ 1131 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1132 OTG_TEST_PATTERN_MASK, pattern_mask, 1133 OTG_TEST_PATTERN_DATA, pattern_data); 1134 1135 /* enable test pattern */ 1136 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 1137 OTG_TEST_PATTERN_EN, 1, 1138 OTG_TEST_PATTERN_MODE, mode, 1139 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1140 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1141 } 1142 break; 1143 1144 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP: 1145 { 1146 mode = (bit_depth == 1147 TEST_PATTERN_COLOR_FORMAT_BPC_10 ? 1148 TEST_PATTERN_MODE_DUALRAMP_RGB : 1149 TEST_PATTERN_MODE_SINGLERAMP_RGB); 1150 1151 switch (bit_depth) { 1152 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1153 dst_bpc = 6; 1154 break; 1155 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1156 dst_bpc = 8; 1157 break; 1158 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1159 dst_bpc = 10; 1160 break; 1161 default: 1162 dst_bpc = 8; 1163 break; 1164 } 1165 1166 /* increment for the first ramp for one color gradation 1167 * 1 gradation for 6-bit color is 2^10 1168 * gradations in 16-bit color 1169 */ 1170 inc_base = (src_bpc - dst_bpc); 1171 1172 switch (bit_depth) { 1173 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1174 { 1175 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1176 OTG_TEST_PATTERN_INC0, inc_base, 1177 OTG_TEST_PATTERN_INC1, 0, 1178 OTG_TEST_PATTERN_HRES, 6, 1179 OTG_TEST_PATTERN_VRES, 6, 1180 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1181 } 1182 break; 1183 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1184 { 1185 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1186 OTG_TEST_PATTERN_INC0, inc_base, 1187 OTG_TEST_PATTERN_INC1, 0, 1188 OTG_TEST_PATTERN_HRES, 8, 1189 OTG_TEST_PATTERN_VRES, 6, 1190 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1191 } 1192 break; 1193 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1194 { 1195 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1196 OTG_TEST_PATTERN_INC0, inc_base, 1197 OTG_TEST_PATTERN_INC1, inc_base + 2, 1198 OTG_TEST_PATTERN_HRES, 8, 1199 OTG_TEST_PATTERN_VRES, 5, 1200 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6); 1201 } 1202 break; 1203 default: 1204 break; 1205 } 1206 1207 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1208 1209 /* enable test pattern */ 1210 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1211 1212 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0, 1213 OTG_TEST_PATTERN_EN, 1, 1214 OTG_TEST_PATTERN_MODE, mode, 1215 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1216 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1217 } 1218 break; 1219 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE: 1220 { 1221 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1222 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1223 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1224 } 1225 break; 1226 default: 1227 break; 1228 1229 } 1230 } 1231 1232 void optc1_get_crtc_scanoutpos( 1233 struct timing_generator *optc, 1234 uint32_t *v_blank_start, 1235 uint32_t *v_blank_end, 1236 uint32_t *h_position, 1237 uint32_t *v_position) 1238 { 1239 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1240 struct crtc_position position; 1241 1242 REG_GET_2(OTG_V_BLANK_START_END, 1243 OTG_V_BLANK_START, v_blank_start, 1244 OTG_V_BLANK_END, v_blank_end); 1245 1246 optc1_get_position(optc, &position); 1247 1248 *h_position = position.horizontal_count; 1249 *v_position = position.vertical_count; 1250 } 1251 1252 static void optc1_enable_stereo(struct timing_generator *optc, 1253 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1254 { 1255 (void)timing; 1256 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1257 1258 if (flags) { 1259 uint32_t stereo_en; 1260 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0; 1261 1262 if (flags->PROGRAM_STEREO) 1263 REG_UPDATE_3(OTG_STEREO_CONTROL, 1264 OTG_STEREO_EN, stereo_en, 1265 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0, 1266 OTG_STEREO_SYNC_OUTPUT_POLARITY, flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1267 1268 if (flags->PROGRAM_POLARITY) 1269 REG_UPDATE(OTG_STEREO_CONTROL, 1270 OTG_STEREO_EYE_FLAG_POLARITY, 1271 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1272 1273 if (flags->DISABLE_STEREO_DP_SYNC) 1274 REG_UPDATE(OTG_STEREO_CONTROL, 1275 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1); 1276 1277 if (flags->PROGRAM_STEREO) 1278 REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL, 1279 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED, 1280 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED); 1281 1282 } 1283 } 1284 1285 void optc1_program_stereo(struct timing_generator *optc, 1286 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1287 { 1288 if (flags->PROGRAM_STEREO) 1289 optc1_enable_stereo(optc, timing, flags); 1290 else 1291 optc1_disable_stereo(optc); 1292 } 1293 1294 1295 bool optc1_is_stereo_left_eye(struct timing_generator *optc) 1296 { 1297 bool ret = false; 1298 uint32_t left_eye = 0; 1299 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1300 1301 REG_GET(OTG_STEREO_STATUS, 1302 OTG_STEREO_CURRENT_EYE, &left_eye); 1303 if (left_eye == 1) 1304 ret = true; 1305 else 1306 ret = false; 1307 1308 return ret; 1309 } 1310 1311 bool optc1_get_hw_timing(struct timing_generator *tg, 1312 struct dc_crtc_timing *hw_crtc_timing) 1313 { 1314 struct dcn_otg_state s = {0}; 1315 1316 if (tg == NULL || hw_crtc_timing == NULL) 1317 return false; 1318 1319 optc1_read_otg_state(tg, &s); 1320 1321 hw_crtc_timing->h_total = s.h_total + 1; 1322 hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end); 1323 hw_crtc_timing->h_front_porch = s.h_total + 1 - s.h_blank_start; 1324 hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start; 1325 1326 hw_crtc_timing->v_total = s.v_total + 1; 1327 hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end); 1328 hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start; 1329 hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start; 1330 1331 return true; 1332 } 1333 1334 1335 void optc1_read_otg_state(struct timing_generator *optc, 1336 struct dcn_otg_state *s) 1337 { 1338 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1339 1340 REG_GET(OTG_CONTROL, 1341 OTG_MASTER_EN, &s->otg_enabled); 1342 1343 REG_GET_2(OTG_V_BLANK_START_END, 1344 OTG_V_BLANK_START, &s->v_blank_start, 1345 OTG_V_BLANK_END, &s->v_blank_end); 1346 1347 REG_GET(OTG_V_SYNC_A_CNTL, 1348 OTG_V_SYNC_A_POL, &s->v_sync_a_pol); 1349 1350 REG_GET(OTG_V_TOTAL, 1351 OTG_V_TOTAL, &s->v_total); 1352 1353 REG_GET(OTG_V_TOTAL_MAX, 1354 OTG_V_TOTAL_MAX, &s->v_total_max); 1355 1356 REG_GET(OTG_V_TOTAL_MIN, 1357 OTG_V_TOTAL_MIN, &s->v_total_min); 1358 1359 REG_GET(OTG_V_TOTAL_CONTROL, 1360 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel); 1361 1362 REG_GET(OTG_V_TOTAL_CONTROL, 1363 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel); 1364 1365 REG_GET_2(OTG_V_SYNC_A, 1366 OTG_V_SYNC_A_START, &s->v_sync_a_start, 1367 OTG_V_SYNC_A_END, &s->v_sync_a_end); 1368 1369 REG_GET_2(OTG_H_BLANK_START_END, 1370 OTG_H_BLANK_START, &s->h_blank_start, 1371 OTG_H_BLANK_END, &s->h_blank_end); 1372 1373 REG_GET_2(OTG_H_SYNC_A, 1374 OTG_H_SYNC_A_START, &s->h_sync_a_start, 1375 OTG_H_SYNC_A_END, &s->h_sync_a_end); 1376 1377 REG_GET(OTG_H_SYNC_A_CNTL, 1378 OTG_H_SYNC_A_POL, &s->h_sync_a_pol); 1379 1380 REG_GET(OTG_H_TOTAL, 1381 OTG_H_TOTAL, &s->h_total); 1382 1383 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1384 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); 1385 1386 REG_GET(OTG_VERTICAL_INTERRUPT1_CONTROL, 1387 OTG_VERTICAL_INTERRUPT1_INT_ENABLE, &s->vertical_interrupt1_en); 1388 1389 REG_GET(OTG_VERTICAL_INTERRUPT1_POSITION, 1390 OTG_VERTICAL_INTERRUPT1_LINE_START, &s->vertical_interrupt1_line); 1391 1392 REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL, 1393 OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &s->vertical_interrupt2_en); 1394 1395 REG_GET(OTG_VERTICAL_INTERRUPT2_POSITION, 1396 OTG_VERTICAL_INTERRUPT2_LINE_START, &s->vertical_interrupt2_line); 1397 1398 s->otg_master_update_lock = REG_READ(OTG_MASTER_UPDATE_LOCK); 1399 s->otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL); 1400 } 1401 1402 bool optc1_get_otg_active_size(struct timing_generator *optc, 1403 uint32_t *otg_active_width, 1404 uint32_t *otg_active_height) 1405 { 1406 uint32_t otg_enabled; 1407 uint32_t v_blank_start; 1408 uint32_t v_blank_end; 1409 uint32_t h_blank_start; 1410 uint32_t h_blank_end; 1411 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1412 1413 1414 REG_GET(OTG_CONTROL, 1415 OTG_MASTER_EN, &otg_enabled); 1416 1417 if (otg_enabled == 0) 1418 return false; 1419 1420 REG_GET_2(OTG_V_BLANK_START_END, 1421 OTG_V_BLANK_START, &v_blank_start, 1422 OTG_V_BLANK_END, &v_blank_end); 1423 1424 REG_GET_2(OTG_H_BLANK_START_END, 1425 OTG_H_BLANK_START, &h_blank_start, 1426 OTG_H_BLANK_END, &h_blank_end); 1427 1428 *otg_active_width = h_blank_start - h_blank_end; 1429 *otg_active_height = v_blank_start - v_blank_end; 1430 return true; 1431 } 1432 1433 void optc1_clear_optc_underflow(struct timing_generator *optc) 1434 { 1435 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1436 1437 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); 1438 } 1439 1440 void optc1_tg_init(struct timing_generator *optc) 1441 { 1442 optc1_set_blank_data_double_buffer(optc, true); 1443 optc1_set_timing_double_buffer(optc, true); 1444 optc1_clear_optc_underflow(optc); 1445 } 1446 1447 bool optc1_is_tg_enabled(struct timing_generator *optc) 1448 { 1449 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1450 uint32_t otg_enabled = 0; 1451 1452 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled); 1453 1454 return (otg_enabled != 0); 1455 1456 } 1457 1458 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc) 1459 { 1460 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1461 uint32_t underflow_occurred = 0; 1462 1463 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1464 OPTC_UNDERFLOW_OCCURRED_STATUS, 1465 &underflow_occurred); 1466 1467 return (underflow_occurred == 1); 1468 } 1469 1470 bool optc1_configure_crc(struct timing_generator *optc, 1471 const struct crc_params *params) 1472 { 1473 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1474 1475 /* Cannot configure crc on a CRTC that is disabled */ 1476 if (!optc1_is_tg_enabled(optc)) 1477 return false; 1478 1479 if (!params->enable || params->reset) 1480 REG_WRITE(OTG_CRC_CNTL, 0); 1481 1482 if (!params->enable) 1483 return true; 1484 1485 /* Program frame boundaries */ 1486 switch (params->crc_eng_inst) { 1487 case 0: 1488 /* Window A x axis start and end. */ 1489 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL, 1490 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start, 1491 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end); 1492 1493 /* Window A y axis start and end. */ 1494 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL, 1495 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start, 1496 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end); 1497 1498 /* Window B x axis start and end. */ 1499 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL, 1500 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start, 1501 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end); 1502 1503 /* Window B y axis start and end. */ 1504 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL, 1505 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start, 1506 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end); 1507 1508 /* Set crc mode and selection, and enable.*/ 1509 REG_UPDATE_3(OTG_CRC_CNTL, 1510 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0, 1511 OTG_CRC0_SELECT, params->selection, 1512 OTG_CRC_EN, 1); 1513 break; 1514 case 1: 1515 /* Window A x axis start and end. */ 1516 REG_UPDATE_2(OTG_CRC1_WINDOWA_X_CONTROL, 1517 OTG_CRC1_WINDOWA_X_START, params->windowa_x_start, 1518 OTG_CRC1_WINDOWA_X_END, params->windowa_x_end); 1519 1520 /* Window A y axis start and end. */ 1521 REG_UPDATE_2(OTG_CRC1_WINDOWA_Y_CONTROL, 1522 OTG_CRC1_WINDOWA_Y_START, params->windowa_y_start, 1523 OTG_CRC1_WINDOWA_Y_END, params->windowa_y_end); 1524 1525 /* Window B x axis start and end. */ 1526 REG_UPDATE_2(OTG_CRC1_WINDOWB_X_CONTROL, 1527 OTG_CRC1_WINDOWB_X_START, params->windowb_x_start, 1528 OTG_CRC1_WINDOWB_X_END, params->windowb_x_end); 1529 1530 /* Window B y axis start and end. */ 1531 REG_UPDATE_2(OTG_CRC1_WINDOWB_Y_CONTROL, 1532 OTG_CRC1_WINDOWB_Y_START, params->windowb_y_start, 1533 OTG_CRC1_WINDOWB_Y_END, params->windowb_y_end); 1534 1535 /* Set crc mode and selection, and enable.*/ 1536 REG_UPDATE_3(OTG_CRC_CNTL, 1537 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0, 1538 OTG_CRC1_SELECT, params->selection, 1539 OTG_CRC_EN, 1); 1540 break; 1541 default: 1542 return false; 1543 } 1544 1545 return true; 1546 } 1547 1548 /** 1549 * optc1_get_crc - Capture CRC result per component 1550 * 1551 * @optc: timing_generator instance. 1552 * @idx: index of crc engine to get CRC from 1553 * @r_cr: 16-bit primary CRC signature for red data. 1554 * @g_y: 16-bit primary CRC signature for green data. 1555 * @b_cb: 16-bit primary CRC signature for blue data. 1556 * 1557 * This function reads the CRC signature from the OPTC registers. Notice that 1558 * we have three registers to keep the CRC result per color component (RGB). 1559 * 1560 * Returns: 1561 * If CRC is disabled, return false; otherwise, return true, and the CRC 1562 * results in the parameters. 1563 */ 1564 bool optc1_get_crc(struct timing_generator *optc, uint8_t idx, 1565 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) 1566 { 1567 uint32_t field = 0; 1568 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1569 1570 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); 1571 1572 /* Early return if CRC is not enabled for this CRTC */ 1573 if (!field) 1574 return false; 1575 1576 switch (idx) { 1577 case 0: 1578 /* OTG_CRC0_DATA_RG has the CRC16 results for the red and green component */ 1579 REG_GET_2(OTG_CRC0_DATA_RG, 1580 CRC0_R_CR, r_cr, 1581 CRC0_G_Y, g_y); 1582 1583 /* OTG_CRC0_DATA_B has the CRC16 results for the blue component */ 1584 REG_GET(OTG_CRC0_DATA_B, 1585 CRC0_B_CB, b_cb); 1586 break; 1587 case 1: 1588 /* OTG_CRC1_DATA_RG has the CRC16 results for the red and green component */ 1589 REG_GET_2(OTG_CRC1_DATA_RG, 1590 CRC1_R_CR, r_cr, 1591 CRC1_G_Y, g_y); 1592 1593 /* OTG_CRC1_DATA_B has the CRC16 results for the blue component */ 1594 REG_GET(OTG_CRC1_DATA_B, 1595 CRC1_B_CB, b_cb); 1596 break; 1597 default: 1598 return false; 1599 } 1600 1601 return true; 1602 } 1603 1604 /* "Container" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this: 1605 * 1606 * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as 1607 * container rate. 1608 * 1609 * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be 1610 * halved to maintain the correct pixel rate. 1611 * 1612 * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied 1613 * to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well. 1614 * 1615 */ 1616 bool optc1_is_two_pixels_per_container(const struct dc_crtc_timing *timing) 1617 { 1618 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; 1619 1620 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 1621 && !timing->dsc_cfg.ycbcr422_simple); 1622 return two_pix; 1623 } 1624 1625 static const struct timing_generator_funcs dcn10_tg_funcs = { 1626 .validate_timing = optc1_validate_timing, 1627 .program_timing = optc1_program_timing, 1628 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 1629 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 1630 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 1631 .program_global_sync = optc1_program_global_sync, 1632 .enable_crtc = optc1_enable_crtc, 1633 .disable_crtc = optc1_disable_crtc, 1634 /* used by enable_timing_synchronization. Not need for FPGA */ 1635 .is_counter_moving = optc1_is_counter_moving, 1636 .get_position = optc1_get_position, 1637 .get_frame_count = optc1_get_vblank_counter, 1638 .get_scanoutpos = optc1_get_crtc_scanoutpos, 1639 .get_otg_active_size = optc1_get_otg_active_size, 1640 .set_early_control = optc1_set_early_control, 1641 /* used by enable_timing_synchronization. Not need for FPGA */ 1642 .wait_for_state = optc1_wait_for_state, 1643 .set_blank = optc1_set_blank, 1644 .is_blanked = optc1_is_blanked, 1645 .set_blank_color = optc1_program_blank_color, 1646 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 1647 .enable_reset_trigger = optc1_enable_reset_trigger, 1648 .enable_crtc_reset = optc1_enable_crtc_reset, 1649 .disable_reset_trigger = optc1_disable_reset_trigger, 1650 .lock = optc1_lock, 1651 .unlock = optc1_unlock, 1652 .enable_optc_clock = optc1_enable_optc_clock, 1653 .set_drr = optc1_set_drr, 1654 .get_last_used_drr_vtotal = NULL, 1655 .set_vtotal_min_max = optc1_set_vtotal_min_max, 1656 .set_static_screen_control = optc1_set_static_screen_control, 1657 .set_test_pattern = optc1_set_test_pattern, 1658 .program_stereo = optc1_program_stereo, 1659 .is_stereo_left_eye = optc1_is_stereo_left_eye, 1660 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer, 1661 .tg_init = optc1_tg_init, 1662 .is_tg_enabled = optc1_is_tg_enabled, 1663 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 1664 .clear_optc_underflow = optc1_clear_optc_underflow, 1665 .get_crc = optc1_get_crc, 1666 .configure_crc = optc1_configure_crc, 1667 .set_vtg_params = optc1_set_vtg_params, 1668 .program_manual_trigger = optc1_program_manual_trigger, 1669 .setup_manual_trigger = optc1_setup_manual_trigger, 1670 .get_hw_timing = optc1_get_hw_timing, 1671 .is_two_pixels_per_container = optc1_is_two_pixels_per_container, 1672 .read_otg_state = optc1_read_otg_state, 1673 }; 1674 1675 void dcn10_timing_generator_init(struct optc *optc1) 1676 { 1677 optc1->base.funcs = &dcn10_tg_funcs; 1678 1679 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 1680 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 1681 1682 optc1->min_h_blank = 32; 1683 optc1->min_v_blank = 3; 1684 optc1->min_v_blank_interlace = 5; 1685 optc1->min_h_sync_width = 4; 1686 optc1->min_v_sync_width = 1; 1687 } 1688