1 /*
2 * QEMU OpenRISC CPU
3 *
4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "qemu/qemu-print.h"
23 #include "cpu.h"
24 #include "exec/translation-block.h"
25 #include "fpu/softfloat-helpers.h"
26 #include "accel/tcg/cpu-ops.h"
27 #include "tcg/tcg.h"
28
openrisc_cpu_set_pc(CPUState * cs,vaddr value)29 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
30 {
31 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
32
33 cpu->env.pc = value;
34 cpu->env.dflag = 0;
35 }
36
openrisc_cpu_get_pc(CPUState * cs)37 static vaddr openrisc_cpu_get_pc(CPUState *cs)
38 {
39 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
40
41 return cpu->env.pc;
42 }
43
openrisc_get_tb_cpu_state(CPUState * cs)44 static TCGTBCPUState openrisc_get_tb_cpu_state(CPUState *cs)
45 {
46 CPUOpenRISCState *env = cpu_env(cs);
47
48 return (TCGTBCPUState){
49 .pc = env->pc,
50 .flags = ((env->dflag ? TB_FLAGS_DFLAG : 0)
51 | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0)
52 | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE))),
53 };
54 }
55
openrisc_cpu_synchronize_from_tb(CPUState * cs,const TranslationBlock * tb)56 static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
57 const TranslationBlock *tb)
58 {
59 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
60
61 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
62 cpu->env.pc = tb->pc;
63 }
64
openrisc_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)65 static void openrisc_restore_state_to_opc(CPUState *cs,
66 const TranslationBlock *tb,
67 const uint64_t *data)
68 {
69 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
70
71 cpu->env.pc = data[0];
72 cpu->env.dflag = data[1] & 1;
73 if (data[1] & 2) {
74 cpu->env.ppc = cpu->env.pc - 4;
75 }
76 }
77
78 #ifndef CONFIG_USER_ONLY
openrisc_cpu_has_work(CPUState * cs)79 static bool openrisc_cpu_has_work(CPUState *cs)
80 {
81 return cs->interrupt_request & (CPU_INTERRUPT_HARD |
82 CPU_INTERRUPT_TIMER);
83 }
84 #endif /* !CONFIG_USER_ONLY */
85
openrisc_cpu_mmu_index(CPUState * cs,bool ifetch)86 static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch)
87 {
88 CPUOpenRISCState *env = cpu_env(cs);
89
90 if (env->sr & (ifetch ? SR_IME : SR_DME)) {
91 /* The mmu is enabled; test supervisor state. */
92 return env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX;
93 }
94
95 return MMU_NOMMU_IDX; /* mmu is disabled */
96 }
97
openrisc_disas_set_info(CPUState * cpu,disassemble_info * info)98 static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info)
99 {
100 info->endian = BFD_ENDIAN_BIG;
101 info->print_insn = print_insn_or1k;
102 }
103
openrisc_cpu_reset_hold(Object * obj,ResetType type)104 static void openrisc_cpu_reset_hold(Object *obj, ResetType type)
105 {
106 CPUState *cs = CPU(obj);
107 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
108 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(obj);
109
110 if (occ->parent_phases.hold) {
111 occ->parent_phases.hold(obj, type);
112 }
113
114 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
115
116 cpu->env.pc = 0x100;
117 cpu->env.sr = SR_FO | SR_SM;
118 cpu->env.lock_addr = -1;
119 cs->exception_index = -1;
120 cpu_set_fpcsr(&cpu->env, 0);
121
122 set_float_detect_tininess(float_tininess_before_rounding,
123 &cpu->env.fp_status);
124 /*
125 * TODO: this is probably not the correct NaN propagation rule for
126 * this architecture.
127 */
128 set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status);
129
130 /* Default NaN: sign bit clear, frac msb set */
131 set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status);
132
133 #ifndef CONFIG_USER_ONLY
134 cpu->env.picmr = 0x00000000;
135 cpu->env.picsr = 0x00000000;
136
137 cpu->env.ttmr = 0x00000000;
138 #endif
139 }
140
141 #ifndef CONFIG_USER_ONLY
openrisc_cpu_set_irq(void * opaque,int irq,int level)142 static void openrisc_cpu_set_irq(void *opaque, int irq, int level)
143 {
144 OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
145 CPUState *cs = CPU(cpu);
146 uint32_t irq_bit;
147
148 if (irq > 31 || irq < 0) {
149 return;
150 }
151
152 irq_bit = 1U << irq;
153
154 if (level) {
155 cpu->env.picsr |= irq_bit;
156 } else {
157 cpu->env.picsr &= ~irq_bit;
158 }
159
160 if (cpu->env.picsr & cpu->env.picmr) {
161 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
162 } else {
163 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
164 }
165 }
166 #endif
167
openrisc_cpu_realizefn(DeviceState * dev,Error ** errp)168 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
169 {
170 CPUState *cs = CPU(dev);
171 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
172 Error *local_err = NULL;
173
174 cpu_exec_realizefn(cs, &local_err);
175 if (local_err != NULL) {
176 error_propagate(errp, local_err);
177 return;
178 }
179
180 qemu_init_vcpu(cs);
181 cpu_reset(cs);
182
183 #ifndef CONFIG_USER_ONLY
184 cpu_openrisc_clock_init(OPENRISC_CPU(dev));
185 #endif
186
187 occ->parent_realize(dev, errp);
188 }
189
openrisc_cpu_initfn(Object * obj)190 static void openrisc_cpu_initfn(Object *obj)
191 {
192 #ifndef CONFIG_USER_ONLY
193 qdev_init_gpio_in_named(DEVICE(obj), openrisc_cpu_set_irq, "IRQ", NR_IRQS);
194 #endif
195 }
196
197 /* CPU models */
198
openrisc_cpu_class_by_name(const char * cpu_model)199 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
200 {
201 ObjectClass *oc;
202 char *typename;
203
204 typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model);
205 oc = object_class_by_name(typename);
206 g_free(typename);
207
208 return oc;
209 }
210
or1200_initfn(Object * obj)211 static void or1200_initfn(Object *obj)
212 {
213 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
214
215 cpu->env.vr = 0x13000008;
216 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
217 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
218 CPUCFGR_EVBARP;
219
220 /* 1Way, TLB_SIZE entries. */
221 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
222 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
223 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
224 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
225 }
226
openrisc_any_initfn(Object * obj)227 static void openrisc_any_initfn(Object *obj)
228 {
229 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
230
231 cpu->env.vr = 0x13000040; /* Obsolete VER + UVRP for new SPRs */
232 cpu->env.vr2 = 0; /* No version specific id */
233 cpu->env.avr = 0x01030000; /* Architecture v1.3 */
234
235 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
236 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
237 CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S;
238
239 /* 1Way, TLB_SIZE entries. */
240 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
241 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
242 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
243 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
244 }
245
246 #ifndef CONFIG_USER_ONLY
247 #include "hw/core/sysemu-cpu-ops.h"
248
249 static const struct SysemuCPUOps openrisc_sysemu_ops = {
250 .has_work = openrisc_cpu_has_work,
251 .get_phys_page_debug = openrisc_cpu_get_phys_page_debug,
252 };
253 #endif
254
255 static const TCGCPUOps openrisc_tcg_ops = {
256 .guest_default_memory_order = 0,
257 .mttcg_supported = true,
258
259 .initialize = openrisc_translate_init,
260 .translate_code = openrisc_translate_code,
261 .get_tb_cpu_state = openrisc_get_tb_cpu_state,
262 .synchronize_from_tb = openrisc_cpu_synchronize_from_tb,
263 .restore_state_to_opc = openrisc_restore_state_to_opc,
264 .mmu_index = openrisc_cpu_mmu_index,
265
266 #ifndef CONFIG_USER_ONLY
267 .tlb_fill = openrisc_cpu_tlb_fill,
268 .pointer_wrap = cpu_pointer_wrap_uint32,
269 .cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
270 .cpu_exec_halt = openrisc_cpu_has_work,
271 .cpu_exec_reset = cpu_reset,
272 .do_interrupt = openrisc_cpu_do_interrupt,
273 #endif /* !CONFIG_USER_ONLY */
274 };
275
openrisc_cpu_class_init(ObjectClass * oc,const void * data)276 static void openrisc_cpu_class_init(ObjectClass *oc, const void *data)
277 {
278 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
279 CPUClass *cc = CPU_CLASS(occ);
280 DeviceClass *dc = DEVICE_CLASS(oc);
281 ResettableClass *rc = RESETTABLE_CLASS(oc);
282
283 device_class_set_parent_realize(dc, openrisc_cpu_realizefn,
284 &occ->parent_realize);
285 resettable_class_set_parent_phases(rc, NULL, openrisc_cpu_reset_hold, NULL,
286 &occ->parent_phases);
287
288 cc->class_by_name = openrisc_cpu_class_by_name;
289 cc->dump_state = openrisc_cpu_dump_state;
290 cc->set_pc = openrisc_cpu_set_pc;
291 cc->get_pc = openrisc_cpu_get_pc;
292 cc->gdb_read_register = openrisc_cpu_gdb_read_register;
293 cc->gdb_write_register = openrisc_cpu_gdb_write_register;
294 #ifndef CONFIG_USER_ONLY
295 dc->vmsd = &vmstate_openrisc_cpu;
296 cc->sysemu_ops = &openrisc_sysemu_ops;
297 #endif
298 cc->gdb_num_core_regs = 32 + 3;
299 cc->disas_set_info = openrisc_disas_set_info;
300 cc->tcg_ops = &openrisc_tcg_ops;
301 }
302
303 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \
304 { \
305 .parent = TYPE_OPENRISC_CPU, \
306 .instance_init = initfn, \
307 .name = OPENRISC_CPU_TYPE_NAME(cpu_model), \
308 }
309
310 static const TypeInfo openrisc_cpus_type_infos[] = {
311 { /* base class should be registered first */
312 .name = TYPE_OPENRISC_CPU,
313 .parent = TYPE_CPU,
314 .instance_size = sizeof(OpenRISCCPU),
315 .instance_align = __alignof(OpenRISCCPU),
316 .instance_init = openrisc_cpu_initfn,
317 .abstract = true,
318 .class_size = sizeof(OpenRISCCPUClass),
319 .class_init = openrisc_cpu_class_init,
320 },
321 DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn),
322 DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn),
323 };
324
325 DEFINE_TYPES(openrisc_cpus_type_infos)
326