1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * NVMe admin command implementation.
4 * Copyright (c) 2015-2016 HGST, a Western Digital Company.
5 */
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7 #include <linux/module.h>
8 #include <linux/rculist.h>
9 #include <linux/part_stat.h>
10
11 #include <generated/utsrelease.h>
12 #include <linux/unaligned.h>
13 #include "nvmet.h"
14
nvmet_execute_delete_sq(struct nvmet_req * req)15 static void nvmet_execute_delete_sq(struct nvmet_req *req)
16 {
17 struct nvmet_ctrl *ctrl = req->sq->ctrl;
18 u16 sqid = le16_to_cpu(req->cmd->delete_queue.qid);
19 u16 status;
20
21 if (!nvmet_is_pci_ctrl(ctrl)) {
22 status = nvmet_report_invalid_opcode(req);
23 goto complete;
24 }
25
26 if (!sqid) {
27 status = NVME_SC_QID_INVALID | NVME_STATUS_DNR;
28 goto complete;
29 }
30
31 status = nvmet_check_sqid(ctrl, sqid, false);
32 if (status != NVME_SC_SUCCESS)
33 goto complete;
34
35 status = ctrl->ops->delete_sq(ctrl, sqid);
36
37 complete:
38 nvmet_req_complete(req, status);
39 }
40
nvmet_execute_create_sq(struct nvmet_req * req)41 static void nvmet_execute_create_sq(struct nvmet_req *req)
42 {
43 struct nvmet_ctrl *ctrl = req->sq->ctrl;
44 struct nvme_command *cmd = req->cmd;
45 u16 sqid = le16_to_cpu(cmd->create_sq.sqid);
46 u16 cqid = le16_to_cpu(cmd->create_sq.cqid);
47 u16 sq_flags = le16_to_cpu(cmd->create_sq.sq_flags);
48 u16 qsize = le16_to_cpu(cmd->create_sq.qsize);
49 u64 prp1 = le64_to_cpu(cmd->create_sq.prp1);
50 u16 status;
51
52 if (!nvmet_is_pci_ctrl(ctrl)) {
53 status = nvmet_report_invalid_opcode(req);
54 goto complete;
55 }
56
57 if (!sqid) {
58 status = NVME_SC_QID_INVALID | NVME_STATUS_DNR;
59 goto complete;
60 }
61
62 status = nvmet_check_sqid(ctrl, sqid, true);
63 if (status != NVME_SC_SUCCESS)
64 goto complete;
65
66 status = nvmet_check_io_cqid(ctrl, cqid, false);
67 if (status != NVME_SC_SUCCESS) {
68 pr_err("SQ %u: Invalid CQID %u\n", sqid, cqid);
69 goto complete;
70 }
71
72 if (!qsize || qsize > NVME_CAP_MQES(ctrl->cap)) {
73 status = NVME_SC_QUEUE_SIZE | NVME_STATUS_DNR;
74 goto complete;
75 }
76
77 status = ctrl->ops->create_sq(ctrl, sqid, cqid, sq_flags, qsize, prp1);
78
79 complete:
80 nvmet_req_complete(req, status);
81 }
82
nvmet_execute_delete_cq(struct nvmet_req * req)83 static void nvmet_execute_delete_cq(struct nvmet_req *req)
84 {
85 struct nvmet_ctrl *ctrl = req->sq->ctrl;
86 u16 cqid = le16_to_cpu(req->cmd->delete_queue.qid);
87 u16 status;
88
89 if (!nvmet_is_pci_ctrl(ctrl)) {
90 status = nvmet_report_invalid_opcode(req);
91 goto complete;
92 }
93
94 status = nvmet_check_io_cqid(ctrl, cqid, false);
95 if (status != NVME_SC_SUCCESS)
96 goto complete;
97
98 if (!ctrl->cqs[cqid] || nvmet_cq_in_use(ctrl->cqs[cqid])) {
99 /* Some SQs are still using this CQ */
100 status = NVME_SC_QID_INVALID | NVME_STATUS_DNR;
101 goto complete;
102 }
103
104 status = ctrl->ops->delete_cq(ctrl, cqid);
105
106 complete:
107 nvmet_req_complete(req, status);
108 }
109
nvmet_execute_create_cq(struct nvmet_req * req)110 static void nvmet_execute_create_cq(struct nvmet_req *req)
111 {
112 struct nvmet_ctrl *ctrl = req->sq->ctrl;
113 struct nvme_command *cmd = req->cmd;
114 u16 cqid = le16_to_cpu(cmd->create_cq.cqid);
115 u16 cq_flags = le16_to_cpu(cmd->create_cq.cq_flags);
116 u16 qsize = le16_to_cpu(cmd->create_cq.qsize);
117 u16 irq_vector = le16_to_cpu(cmd->create_cq.irq_vector);
118 u64 prp1 = le64_to_cpu(cmd->create_cq.prp1);
119 u16 status;
120
121 if (!nvmet_is_pci_ctrl(ctrl)) {
122 status = nvmet_report_invalid_opcode(req);
123 goto complete;
124 }
125
126 status = nvmet_check_io_cqid(ctrl, cqid, true);
127 if (status != NVME_SC_SUCCESS)
128 goto complete;
129
130 if (!qsize || qsize > NVME_CAP_MQES(ctrl->cap)) {
131 status = NVME_SC_QUEUE_SIZE | NVME_STATUS_DNR;
132 goto complete;
133 }
134
135 status = ctrl->ops->create_cq(ctrl, cqid, cq_flags, qsize,
136 prp1, irq_vector);
137
138 complete:
139 nvmet_req_complete(req, status);
140 }
141
nvmet_get_log_page_len(struct nvme_command * cmd)142 u32 nvmet_get_log_page_len(struct nvme_command *cmd)
143 {
144 u32 len = le16_to_cpu(cmd->get_log_page.numdu);
145
146 len <<= 16;
147 len += le16_to_cpu(cmd->get_log_page.numdl);
148 /* NUMD is a 0's based value */
149 len += 1;
150 len *= sizeof(u32);
151
152 return len;
153 }
154
nvmet_feat_data_len(struct nvmet_req * req,u32 cdw10)155 static u32 nvmet_feat_data_len(struct nvmet_req *req, u32 cdw10)
156 {
157 switch (cdw10 & 0xff) {
158 case NVME_FEAT_HOST_ID:
159 return sizeof(req->sq->ctrl->hostid);
160 default:
161 return 0;
162 }
163 }
164
nvmet_get_log_page_offset(struct nvme_command * cmd)165 u64 nvmet_get_log_page_offset(struct nvme_command *cmd)
166 {
167 return le64_to_cpu(cmd->get_log_page.lpo);
168 }
169
nvmet_execute_get_log_page_noop(struct nvmet_req * req)170 static void nvmet_execute_get_log_page_noop(struct nvmet_req *req)
171 {
172 nvmet_req_complete(req, nvmet_zero_sgl(req, 0, req->transfer_len));
173 }
174
nvmet_execute_get_log_page_error(struct nvmet_req * req)175 static void nvmet_execute_get_log_page_error(struct nvmet_req *req)
176 {
177 struct nvmet_ctrl *ctrl = req->sq->ctrl;
178 unsigned long flags;
179 off_t offset = 0;
180 u64 slot;
181 u64 i;
182
183 spin_lock_irqsave(&ctrl->error_lock, flags);
184 slot = ctrl->err_counter % NVMET_ERROR_LOG_SLOTS;
185
186 for (i = 0; i < NVMET_ERROR_LOG_SLOTS; i++) {
187 if (nvmet_copy_to_sgl(req, offset, &ctrl->slots[slot],
188 sizeof(struct nvme_error_slot)))
189 break;
190
191 if (slot == 0)
192 slot = NVMET_ERROR_LOG_SLOTS - 1;
193 else
194 slot--;
195 offset += sizeof(struct nvme_error_slot);
196 }
197 spin_unlock_irqrestore(&ctrl->error_lock, flags);
198 nvmet_req_complete(req, 0);
199 }
200
nvmet_execute_get_supported_log_pages(struct nvmet_req * req)201 static void nvmet_execute_get_supported_log_pages(struct nvmet_req *req)
202 {
203 struct nvme_supported_log *logs;
204 u16 status;
205
206 logs = kzalloc_obj(*logs);
207 if (!logs) {
208 status = NVME_SC_INTERNAL;
209 goto out;
210 }
211
212 logs->lids[NVME_LOG_SUPPORTED] = cpu_to_le32(NVME_LIDS_LSUPP);
213 logs->lids[NVME_LOG_ERROR] = cpu_to_le32(NVME_LIDS_LSUPP);
214 logs->lids[NVME_LOG_SMART] = cpu_to_le32(NVME_LIDS_LSUPP);
215 logs->lids[NVME_LOG_FW_SLOT] = cpu_to_le32(NVME_LIDS_LSUPP);
216 logs->lids[NVME_LOG_CHANGED_NS] = cpu_to_le32(NVME_LIDS_LSUPP);
217 logs->lids[NVME_LOG_CMD_EFFECTS] = cpu_to_le32(NVME_LIDS_LSUPP);
218 logs->lids[NVME_LOG_ENDURANCE_GROUP] = cpu_to_le32(NVME_LIDS_LSUPP);
219 logs->lids[NVME_LOG_ANA] = cpu_to_le32(NVME_LIDS_LSUPP);
220 logs->lids[NVME_LOG_FEATURES] = cpu_to_le32(NVME_LIDS_LSUPP);
221 logs->lids[NVME_LOG_RMI] = cpu_to_le32(NVME_LIDS_LSUPP);
222 logs->lids[NVME_LOG_RESERVATION] = cpu_to_le32(NVME_LIDS_LSUPP);
223
224 status = nvmet_copy_to_sgl(req, 0, logs, sizeof(*logs));
225 kfree(logs);
226 out:
227 nvmet_req_complete(req, status);
228 }
229
nvmet_get_smart_log_nsid(struct nvmet_req * req,struct nvme_smart_log * slog)230 static u16 nvmet_get_smart_log_nsid(struct nvmet_req *req,
231 struct nvme_smart_log *slog)
232 {
233 u64 host_reads, host_writes, data_units_read, data_units_written;
234 u16 status;
235
236 status = nvmet_req_find_ns(req);
237 if (status)
238 return status;
239
240 /* we don't have the right data for file backed ns */
241 if (!req->ns->bdev)
242 return NVME_SC_SUCCESS;
243
244 host_reads = part_stat_read(req->ns->bdev, ios[READ]);
245 data_units_read =
246 DIV_ROUND_UP(part_stat_read(req->ns->bdev, sectors[READ]), 1000);
247 host_writes = part_stat_read(req->ns->bdev, ios[WRITE]);
248 data_units_written =
249 DIV_ROUND_UP(part_stat_read(req->ns->bdev, sectors[WRITE]), 1000);
250
251 put_unaligned_le64(host_reads, &slog->host_reads[0]);
252 put_unaligned_le64(data_units_read, &slog->data_units_read[0]);
253 put_unaligned_le64(host_writes, &slog->host_writes[0]);
254 put_unaligned_le64(data_units_written, &slog->data_units_written[0]);
255
256 return NVME_SC_SUCCESS;
257 }
258
nvmet_get_smart_log_all(struct nvmet_req * req,struct nvme_smart_log * slog)259 static u16 nvmet_get_smart_log_all(struct nvmet_req *req,
260 struct nvme_smart_log *slog)
261 {
262 u64 host_reads = 0, host_writes = 0;
263 u64 data_units_read = 0, data_units_written = 0;
264 struct nvmet_ns *ns;
265 struct nvmet_ctrl *ctrl;
266 unsigned long idx;
267
268 ctrl = req->sq->ctrl;
269 nvmet_for_each_enabled_ns(&ctrl->subsys->namespaces, idx, ns) {
270 /* we don't have the right data for file backed ns */
271 if (!ns->bdev)
272 continue;
273 host_reads += part_stat_read(ns->bdev, ios[READ]);
274 data_units_read += DIV_ROUND_UP(
275 part_stat_read(ns->bdev, sectors[READ]), 1000);
276 host_writes += part_stat_read(ns->bdev, ios[WRITE]);
277 data_units_written += DIV_ROUND_UP(
278 part_stat_read(ns->bdev, sectors[WRITE]), 1000);
279 }
280
281 put_unaligned_le64(host_reads, &slog->host_reads[0]);
282 put_unaligned_le64(data_units_read, &slog->data_units_read[0]);
283 put_unaligned_le64(host_writes, &slog->host_writes[0]);
284 put_unaligned_le64(data_units_written, &slog->data_units_written[0]);
285
286 return NVME_SC_SUCCESS;
287 }
288
nvmet_execute_get_log_page_rmi(struct nvmet_req * req)289 static void nvmet_execute_get_log_page_rmi(struct nvmet_req *req)
290 {
291 struct nvme_rotational_media_log *log;
292 struct gendisk *disk;
293 u16 status;
294
295 req->cmd->common.nsid = cpu_to_le32(le16_to_cpu(
296 req->cmd->get_log_page.lsi));
297 status = nvmet_req_find_ns(req);
298 if (status)
299 goto out;
300
301 if (!req->ns->bdev || !bdev_rot(req->ns->bdev)) {
302 status = NVME_SC_INVALID_FIELD | NVME_STATUS_DNR;
303 goto out;
304 }
305
306 if (req->transfer_len != sizeof(*log)) {
307 status = NVME_SC_SGL_INVALID_DATA | NVME_STATUS_DNR;
308 goto out;
309 }
310
311 log = kzalloc_obj(*log);
312 if (!log)
313 goto out;
314
315 log->endgid = req->cmd->get_log_page.lsi;
316 disk = req->ns->bdev->bd_disk;
317 if (disk && disk->ia_ranges)
318 log->numa = cpu_to_le16(disk->ia_ranges->nr_ia_ranges);
319 else
320 log->numa = cpu_to_le16(1);
321
322 status = nvmet_copy_to_sgl(req, 0, log, sizeof(*log));
323 kfree(log);
324 out:
325 nvmet_req_complete(req, status);
326 }
327
nvmet_execute_get_log_page_smart(struct nvmet_req * req)328 static void nvmet_execute_get_log_page_smart(struct nvmet_req *req)
329 {
330 struct nvme_smart_log *log;
331 u16 status = NVME_SC_INTERNAL;
332 unsigned long flags;
333
334 if (req->transfer_len != sizeof(*log))
335 goto out;
336
337 log = kzalloc_obj(*log);
338 if (!log)
339 goto out;
340
341 if (req->cmd->get_log_page.nsid == cpu_to_le32(NVME_NSID_ALL))
342 status = nvmet_get_smart_log_all(req, log);
343 else
344 status = nvmet_get_smart_log_nsid(req, log);
345 if (status)
346 goto out_free_log;
347
348 spin_lock_irqsave(&req->sq->ctrl->error_lock, flags);
349 put_unaligned_le64(req->sq->ctrl->err_counter,
350 &log->num_err_log_entries);
351 spin_unlock_irqrestore(&req->sq->ctrl->error_lock, flags);
352
353 status = nvmet_copy_to_sgl(req, 0, log, sizeof(*log));
354 out_free_log:
355 kfree(log);
356 out:
357 nvmet_req_complete(req, status);
358 }
359
nvmet_get_cmd_effects_admin(struct nvmet_ctrl * ctrl,struct nvme_effects_log * log)360 static void nvmet_get_cmd_effects_admin(struct nvmet_ctrl *ctrl,
361 struct nvme_effects_log *log)
362 {
363 /* For a PCI target controller, advertize support for the . */
364 if (nvmet_is_pci_ctrl(ctrl)) {
365 log->acs[nvme_admin_delete_sq] =
366 log->acs[nvme_admin_create_sq] =
367 log->acs[nvme_admin_delete_cq] =
368 log->acs[nvme_admin_create_cq] =
369 cpu_to_le32(NVME_CMD_EFFECTS_CSUPP);
370 }
371
372 log->acs[nvme_admin_get_log_page] =
373 log->acs[nvme_admin_identify] =
374 log->acs[nvme_admin_abort_cmd] =
375 log->acs[nvme_admin_set_features] =
376 log->acs[nvme_admin_get_features] =
377 log->acs[nvme_admin_async_event] =
378 log->acs[nvme_admin_keep_alive] =
379 cpu_to_le32(NVME_CMD_EFFECTS_CSUPP);
380 }
381
nvmet_get_cmd_effects_nvm(struct nvme_effects_log * log)382 static void nvmet_get_cmd_effects_nvm(struct nvme_effects_log *log)
383 {
384 log->iocs[nvme_cmd_read] =
385 log->iocs[nvme_cmd_flush] =
386 log->iocs[nvme_cmd_dsm] =
387 log->iocs[nvme_cmd_resv_acquire] =
388 log->iocs[nvme_cmd_resv_register] =
389 log->iocs[nvme_cmd_resv_release] =
390 log->iocs[nvme_cmd_resv_report] =
391 cpu_to_le32(NVME_CMD_EFFECTS_CSUPP);
392 log->iocs[nvme_cmd_write] =
393 log->iocs[nvme_cmd_write_zeroes] =
394 cpu_to_le32(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC);
395 }
396
nvmet_get_cmd_effects_zns(struct nvme_effects_log * log)397 static void nvmet_get_cmd_effects_zns(struct nvme_effects_log *log)
398 {
399 log->iocs[nvme_cmd_zone_append] =
400 log->iocs[nvme_cmd_zone_mgmt_send] =
401 cpu_to_le32(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC);
402 log->iocs[nvme_cmd_zone_mgmt_recv] =
403 cpu_to_le32(NVME_CMD_EFFECTS_CSUPP);
404 }
405
nvmet_execute_get_log_cmd_effects_ns(struct nvmet_req * req)406 static void nvmet_execute_get_log_cmd_effects_ns(struct nvmet_req *req)
407 {
408 struct nvmet_ctrl *ctrl = req->sq->ctrl;
409 struct nvme_effects_log *log;
410 u16 status = NVME_SC_SUCCESS;
411
412 log = kzalloc_obj(*log);
413 if (!log) {
414 status = NVME_SC_INTERNAL;
415 goto out;
416 }
417
418 switch (req->cmd->get_log_page.csi) {
419 case NVME_CSI_NVM:
420 nvmet_get_cmd_effects_admin(ctrl, log);
421 nvmet_get_cmd_effects_nvm(log);
422 break;
423 case NVME_CSI_ZNS:
424 if (!IS_ENABLED(CONFIG_BLK_DEV_ZONED)) {
425 status = NVME_SC_INVALID_IO_CMD_SET;
426 goto free;
427 }
428 nvmet_get_cmd_effects_admin(ctrl, log);
429 nvmet_get_cmd_effects_nvm(log);
430 nvmet_get_cmd_effects_zns(log);
431 break;
432 default:
433 status = NVME_SC_INVALID_LOG_PAGE;
434 goto free;
435 }
436
437 status = nvmet_copy_to_sgl(req, 0, log, sizeof(*log));
438 free:
439 kfree(log);
440 out:
441 nvmet_req_complete(req, status);
442 }
443
nvmet_execute_get_log_changed_ns(struct nvmet_req * req)444 static void nvmet_execute_get_log_changed_ns(struct nvmet_req *req)
445 {
446 struct nvmet_ctrl *ctrl = req->sq->ctrl;
447 u16 status = NVME_SC_INTERNAL;
448 size_t len;
449
450 if (req->transfer_len != NVME_MAX_CHANGED_NAMESPACES * sizeof(__le32))
451 goto out;
452
453 mutex_lock(&ctrl->lock);
454 if (ctrl->nr_changed_ns == U32_MAX)
455 len = sizeof(__le32);
456 else
457 len = ctrl->nr_changed_ns * sizeof(__le32);
458 status = nvmet_copy_to_sgl(req, 0, ctrl->changed_ns_list, len);
459 if (!status)
460 status = nvmet_zero_sgl(req, len, req->transfer_len - len);
461 ctrl->nr_changed_ns = 0;
462 nvmet_clear_aen_bit(req, NVME_AEN_BIT_NS_ATTR);
463 mutex_unlock(&ctrl->lock);
464 out:
465 nvmet_req_complete(req, status);
466 }
467
nvmet_format_ana_group(struct nvmet_req * req,u32 grpid,struct nvme_ana_group_desc * desc)468 static u32 nvmet_format_ana_group(struct nvmet_req *req, u32 grpid,
469 struct nvme_ana_group_desc *desc)
470 {
471 struct nvmet_ctrl *ctrl = req->sq->ctrl;
472 struct nvmet_ns *ns;
473 unsigned long idx;
474 u32 count = 0;
475
476 if (!(req->cmd->get_log_page.lsp & NVME_ANA_LOG_RGO)) {
477 nvmet_for_each_enabled_ns(&ctrl->subsys->namespaces, idx, ns) {
478 if (ns->anagrpid == grpid)
479 desc->nsids[count++] = cpu_to_le32(ns->nsid);
480 }
481 }
482
483 desc->grpid = cpu_to_le32(grpid);
484 desc->nnsids = cpu_to_le32(count);
485 desc->chgcnt = cpu_to_le64(nvmet_ana_chgcnt);
486 desc->state = req->port->ana_state[grpid];
487 memset(desc->rsvd17, 0, sizeof(desc->rsvd17));
488 return struct_size(desc, nsids, count);
489 }
490
nvmet_execute_get_log_page_endgrp(struct nvmet_req * req)491 static void nvmet_execute_get_log_page_endgrp(struct nvmet_req *req)
492 {
493 u64 host_reads, host_writes, data_units_read, data_units_written;
494 struct nvme_endurance_group_log *log;
495 u16 status;
496
497 /*
498 * The target driver emulates each endurance group as its own
499 * namespace, reusing the nsid as the endurance group identifier.
500 */
501 req->cmd->common.nsid = cpu_to_le32(le16_to_cpu(
502 req->cmd->get_log_page.lsi));
503 status = nvmet_req_find_ns(req);
504 if (status)
505 goto out;
506
507 log = kzalloc_obj(*log);
508 if (!log) {
509 status = NVME_SC_INTERNAL;
510 goto out;
511 }
512
513 if (!req->ns->bdev)
514 goto copy;
515
516 host_reads = part_stat_read(req->ns->bdev, ios[READ]);
517 data_units_read =
518 DIV_ROUND_UP(part_stat_read(req->ns->bdev, sectors[READ]), 1000);
519 host_writes = part_stat_read(req->ns->bdev, ios[WRITE]);
520 data_units_written =
521 DIV_ROUND_UP(part_stat_read(req->ns->bdev, sectors[WRITE]), 1000);
522
523 put_unaligned_le64(host_reads, &log->hrc[0]);
524 put_unaligned_le64(data_units_read, &log->dur[0]);
525 put_unaligned_le64(host_writes, &log->hwc[0]);
526 put_unaligned_le64(data_units_written, &log->duw[0]);
527 copy:
528 status = nvmet_copy_to_sgl(req, 0, log, sizeof(*log));
529 kfree(log);
530 out:
531 nvmet_req_complete(req, status);
532 }
533
nvmet_execute_get_log_page_ana(struct nvmet_req * req)534 static void nvmet_execute_get_log_page_ana(struct nvmet_req *req)
535 {
536 struct nvme_ana_rsp_hdr hdr = { 0, };
537 struct nvme_ana_group_desc *desc;
538 size_t offset = sizeof(struct nvme_ana_rsp_hdr); /* start beyond hdr */
539 size_t len;
540 u32 grpid;
541 u16 ngrps = 0;
542 u16 status;
543
544 status = NVME_SC_INTERNAL;
545 desc = kmalloc_flex(*desc, nsids, NVMET_MAX_NAMESPACES);
546 if (!desc)
547 goto out;
548
549 down_read(&nvmet_ana_sem);
550 for (grpid = 1; grpid <= NVMET_MAX_ANAGRPS; grpid++) {
551 if (!nvmet_ana_group_enabled[grpid])
552 continue;
553 len = nvmet_format_ana_group(req, grpid, desc);
554 status = nvmet_copy_to_sgl(req, offset, desc, len);
555 if (status)
556 break;
557 offset += len;
558 ngrps++;
559 }
560 for ( ; grpid <= NVMET_MAX_ANAGRPS; grpid++) {
561 if (nvmet_ana_group_enabled[grpid])
562 ngrps++;
563 }
564
565 hdr.chgcnt = cpu_to_le64(nvmet_ana_chgcnt);
566 hdr.ngrps = cpu_to_le16(ngrps);
567 nvmet_clear_aen_bit(req, NVME_AEN_BIT_ANA_CHANGE);
568 up_read(&nvmet_ana_sem);
569
570 kfree(desc);
571
572 /* copy the header last once we know the number of groups */
573 status = nvmet_copy_to_sgl(req, 0, &hdr, sizeof(hdr));
574 out:
575 nvmet_req_complete(req, status);
576 }
577
nvmet_execute_get_log_page_features(struct nvmet_req * req)578 static void nvmet_execute_get_log_page_features(struct nvmet_req *req)
579 {
580 struct nvme_supported_features_log *features;
581 u16 status;
582
583 features = kzalloc_obj(*features);
584 if (!features) {
585 status = NVME_SC_INTERNAL;
586 goto out;
587 }
588
589 features->fis[NVME_FEAT_NUM_QUEUES] =
590 cpu_to_le32(NVME_FIS_FSUPP | NVME_FIS_CSCPE);
591 features->fis[NVME_FEAT_KATO] =
592 cpu_to_le32(NVME_FIS_FSUPP | NVME_FIS_CSCPE);
593 features->fis[NVME_FEAT_ASYNC_EVENT] =
594 cpu_to_le32(NVME_FIS_FSUPP | NVME_FIS_CSCPE);
595 features->fis[NVME_FEAT_HOST_ID] =
596 cpu_to_le32(NVME_FIS_FSUPP | NVME_FIS_CSCPE);
597 features->fis[NVME_FEAT_WRITE_PROTECT] =
598 cpu_to_le32(NVME_FIS_FSUPP | NVME_FIS_NSCPE);
599 features->fis[NVME_FEAT_RESV_MASK] =
600 cpu_to_le32(NVME_FIS_FSUPP | NVME_FIS_NSCPE);
601
602 status = nvmet_copy_to_sgl(req, 0, features, sizeof(*features));
603 kfree(features);
604 out:
605 nvmet_req_complete(req, status);
606 }
607
nvmet_execute_get_log_page(struct nvmet_req * req)608 static void nvmet_execute_get_log_page(struct nvmet_req *req)
609 {
610 if (!nvmet_check_transfer_len(req, nvmet_get_log_page_len(req->cmd)))
611 return;
612
613 switch (req->cmd->get_log_page.lid) {
614 case NVME_LOG_SUPPORTED:
615 return nvmet_execute_get_supported_log_pages(req);
616 case NVME_LOG_ERROR:
617 return nvmet_execute_get_log_page_error(req);
618 case NVME_LOG_SMART:
619 return nvmet_execute_get_log_page_smart(req);
620 case NVME_LOG_FW_SLOT:
621 /*
622 * We only support a single firmware slot which always is
623 * active, so we can zero out the whole firmware slot log and
624 * still claim to fully implement this mandatory log page.
625 */
626 return nvmet_execute_get_log_page_noop(req);
627 case NVME_LOG_CHANGED_NS:
628 return nvmet_execute_get_log_changed_ns(req);
629 case NVME_LOG_CMD_EFFECTS:
630 return nvmet_execute_get_log_cmd_effects_ns(req);
631 case NVME_LOG_ENDURANCE_GROUP:
632 return nvmet_execute_get_log_page_endgrp(req);
633 case NVME_LOG_ANA:
634 return nvmet_execute_get_log_page_ana(req);
635 case NVME_LOG_FEATURES:
636 return nvmet_execute_get_log_page_features(req);
637 case NVME_LOG_RMI:
638 return nvmet_execute_get_log_page_rmi(req);
639 case NVME_LOG_RESERVATION:
640 return nvmet_execute_get_log_page_resv(req);
641 }
642 pr_debug("unhandled lid %d on qid %d\n",
643 req->cmd->get_log_page.lid, req->sq->qid);
644 req->error_loc = offsetof(struct nvme_get_log_page_command, lid);
645 nvmet_req_complete(req, NVME_SC_INVALID_FIELD | NVME_STATUS_DNR);
646 }
647
nvmet_execute_identify_ctrl(struct nvmet_req * req)648 static void nvmet_execute_identify_ctrl(struct nvmet_req *req)
649 {
650 struct nvmet_ctrl *ctrl = req->sq->ctrl;
651 struct nvmet_subsys *subsys = ctrl->subsys;
652 struct nvme_id_ctrl *id;
653 u32 cmd_capsule_size, ctratt;
654 u16 status = 0;
655
656 if (!subsys->subsys_discovered) {
657 mutex_lock(&subsys->lock);
658 subsys->subsys_discovered = true;
659 mutex_unlock(&subsys->lock);
660 }
661
662 id = kzalloc_obj(*id);
663 if (!id) {
664 status = NVME_SC_INTERNAL;
665 goto out;
666 }
667
668 id->vid = cpu_to_le16(subsys->vendor_id);
669 id->ssvid = cpu_to_le16(subsys->subsys_vendor_id);
670
671 memcpy(id->sn, ctrl->subsys->serial, NVMET_SN_MAX_SIZE);
672 memcpy_and_pad(id->mn, sizeof(id->mn), subsys->model_number,
673 strlen(subsys->model_number), ' ');
674 memcpy_and_pad(id->fr, sizeof(id->fr),
675 subsys->firmware_rev, strlen(subsys->firmware_rev), ' ');
676
677 put_unaligned_le24(subsys->ieee_oui, id->ieee);
678
679 id->rab = 6;
680
681 if (nvmet_is_disc_subsys(ctrl->subsys))
682 id->cntrltype = NVME_CTRL_DISC;
683 else
684 id->cntrltype = NVME_CTRL_IO;
685
686 /* we support multiple ports, multiples hosts and ANA: */
687 id->cmic = NVME_CTRL_CMIC_MULTI_PORT | NVME_CTRL_CMIC_MULTI_CTRL |
688 NVME_CTRL_CMIC_ANA;
689
690 /* Limit MDTS according to transport capability */
691 if (ctrl->ops->get_mdts)
692 id->mdts = ctrl->ops->get_mdts(ctrl);
693 else
694 id->mdts = 0;
695
696 id->cntlid = cpu_to_le16(ctrl->cntlid);
697 id->ver = cpu_to_le32(ctrl->subsys->ver);
698
699 /* XXX: figure out what to do about RTD3R/RTD3 */
700 id->oaes = cpu_to_le32(NVMET_AEN_CFG_OPTIONAL);
701 ctratt = NVME_CTRL_ATTR_HID_128_BIT | NVME_CTRL_ATTR_TBKAS;
702 if (nvmet_is_pci_ctrl(ctrl))
703 ctratt |= NVME_CTRL_ATTR_RHII;
704 id->ctratt = cpu_to_le32(ctratt);
705
706 id->oacs = 0;
707
708 /*
709 * We don't really have a practical limit on the number of abort
710 * commands. But we don't do anything useful for abort either, so
711 * no point in allowing more abort commands than the spec requires.
712 */
713 id->acl = 3;
714
715 id->aerl = NVMET_ASYNC_EVENTS - 1;
716
717 /* first slot is read-only, only one slot supported */
718 id->frmw = (1 << 0) | (1 << 1);
719 id->lpa = (1 << 0) | (1 << 1) | (1 << 2);
720 id->elpe = NVMET_ERROR_LOG_SLOTS - 1;
721 id->npss = 0;
722
723 /* We support keep-alive timeout in granularity of seconds */
724 id->kas = cpu_to_le16(NVMET_KAS);
725
726 id->sqes = (0x6 << 4) | 0x6;
727 id->cqes = (0x4 << 4) | 0x4;
728
729 /* no enforcement soft-limit for maxcmd - pick arbitrary high value */
730 id->maxcmd = cpu_to_le16(NVMET_MAX_CMD(ctrl));
731
732 id->nn = cpu_to_le32(NVMET_MAX_NAMESPACES);
733 id->mnan = cpu_to_le32(NVMET_MAX_NAMESPACES);
734 id->oncs = cpu_to_le16(NVME_CTRL_ONCS_DSM |
735 NVME_CTRL_ONCS_WRITE_ZEROES |
736 NVME_CTRL_ONCS_RESERVATIONS);
737
738 /* XXX: don't report vwc if the underlying device is write through */
739 id->vwc = NVME_CTRL_VWC_PRESENT;
740
741 /*
742 * We can't support atomic writes bigger than a LBA without support
743 * from the backend device.
744 */
745 id->awun = 0;
746 id->awupf = 0;
747
748 /* we always support SGLs */
749 id->sgls = cpu_to_le32(NVME_CTRL_SGLS_BYTE_ALIGNED);
750 if (ctrl->ops->flags & NVMF_KEYED_SGLS)
751 id->sgls |= cpu_to_le32(NVME_CTRL_SGLS_KSDBDS);
752 if (req->port->inline_data_size)
753 id->sgls |= cpu_to_le32(NVME_CTRL_SGLS_SAOS);
754
755 strscpy(id->subnqn, ctrl->subsys->subsysnqn, sizeof(id->subnqn));
756
757 /*
758 * Max command capsule size is sqe + in-capsule data size.
759 * Disable in-capsule data for Metadata capable controllers.
760 */
761 cmd_capsule_size = sizeof(struct nvme_command);
762 if (!ctrl->pi_support)
763 cmd_capsule_size += req->port->inline_data_size;
764 id->ioccsz = cpu_to_le32(cmd_capsule_size / 16);
765
766 /* Max response capsule size is cqe */
767 id->iorcsz = cpu_to_le32(sizeof(struct nvme_completion) / 16);
768
769 id->msdbd = ctrl->ops->msdbd;
770
771 /*
772 * Endurance group identifier is 16 bits, so we can't let namespaces
773 * overflow that since we reuse the nsid
774 */
775 BUILD_BUG_ON(NVMET_MAX_NAMESPACES > USHRT_MAX);
776 id->endgidmax = cpu_to_le16(NVMET_MAX_NAMESPACES);
777
778 id->anacap = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4);
779 id->anatt = 10; /* random value */
780 id->anagrpmax = cpu_to_le32(NVMET_MAX_ANAGRPS);
781 id->nanagrpid = cpu_to_le32(NVMET_MAX_ANAGRPS);
782
783 /*
784 * Meh, we don't really support any power state. Fake up the same
785 * values that qemu does.
786 */
787 id->psd[0].max_power = cpu_to_le16(0x9c4);
788 id->psd[0].entry_lat = cpu_to_le32(0x10);
789 id->psd[0].exit_lat = cpu_to_le32(0x4);
790
791 id->nwpc = 1 << 0; /* write protect and no write protect */
792
793 status = nvmet_copy_to_sgl(req, 0, id, sizeof(*id));
794
795 kfree(id);
796 out:
797 nvmet_req_complete(req, status);
798 }
799
nvmet_execute_identify_ns(struct nvmet_req * req)800 static void nvmet_execute_identify_ns(struct nvmet_req *req)
801 {
802 struct nvme_id_ns *id;
803 u16 status;
804
805 if (le32_to_cpu(req->cmd->identify.nsid) == NVME_NSID_ALL) {
806 req->error_loc = offsetof(struct nvme_identify, nsid);
807 status = NVME_SC_INVALID_NS | NVME_STATUS_DNR;
808 goto out;
809 }
810
811 id = kzalloc_obj(*id);
812 if (!id) {
813 status = NVME_SC_INTERNAL;
814 goto out;
815 }
816
817 /* return an all zeroed buffer if we can't find an active namespace */
818 status = nvmet_req_find_ns(req);
819 if (status) {
820 status = 0;
821 goto done;
822 }
823
824 if (nvmet_ns_revalidate(req->ns)) {
825 mutex_lock(&req->ns->subsys->lock);
826 nvmet_ns_changed(req->ns->subsys, req->ns->nsid);
827 mutex_unlock(&req->ns->subsys->lock);
828 }
829
830 /*
831 * nuse = ncap = nsze isn't always true, but we have no way to find
832 * that out from the underlying device.
833 */
834 id->ncap = id->nsze =
835 cpu_to_le64(req->ns->size >> req->ns->blksize_shift);
836 switch (req->port->ana_state[req->ns->anagrpid]) {
837 case NVME_ANA_INACCESSIBLE:
838 case NVME_ANA_PERSISTENT_LOSS:
839 break;
840 default:
841 id->nuse = id->nsze;
842 break;
843 }
844
845 if (req->ns->bdev)
846 nvmet_bdev_set_limits(req->ns->bdev, id);
847
848 /*
849 * We just provide a single LBA format that matches what the
850 * underlying device reports.
851 */
852 id->nlbaf = 0;
853 id->flbas = 0;
854
855 /*
856 * Our namespace might always be shared. Not just with other
857 * controllers, but also with any other user of the block device.
858 */
859 id->nmic = NVME_NS_NMIC_SHARED;
860 id->anagrpid = cpu_to_le32(req->ns->anagrpid);
861
862 if (req->ns->pr.enable)
863 id->rescap = NVME_PR_SUPPORT_WRITE_EXCLUSIVE |
864 NVME_PR_SUPPORT_EXCLUSIVE_ACCESS |
865 NVME_PR_SUPPORT_WRITE_EXCLUSIVE_REG_ONLY |
866 NVME_PR_SUPPORT_EXCLUSIVE_ACCESS_REG_ONLY |
867 NVME_PR_SUPPORT_WRITE_EXCLUSIVE_ALL_REGS |
868 NVME_PR_SUPPORT_EXCLUSIVE_ACCESS_ALL_REGS |
869 NVME_PR_SUPPORT_IEKEY_VER_1_3_DEF;
870
871 /*
872 * Since we don't know any better, every namespace is its own endurance
873 * group.
874 */
875 id->endgid = cpu_to_le16(req->ns->nsid);
876
877 memcpy(&id->nguid, &req->ns->nguid, sizeof(id->nguid));
878
879 id->lbaf[0].ds = req->ns->blksize_shift;
880
881 if (req->sq->ctrl->pi_support && nvmet_ns_has_pi(req->ns)) {
882 id->dpc = NVME_NS_DPC_PI_FIRST | NVME_NS_DPC_PI_LAST |
883 NVME_NS_DPC_PI_TYPE1 | NVME_NS_DPC_PI_TYPE2 |
884 NVME_NS_DPC_PI_TYPE3;
885 id->mc = NVME_MC_EXTENDED_LBA;
886 id->dps = req->ns->pi_type;
887 id->flbas = NVME_NS_FLBAS_META_EXT;
888 id->lbaf[0].ms = cpu_to_le16(req->ns->metadata_size);
889 }
890
891 if (req->ns->readonly)
892 id->nsattr |= NVME_NS_ATTR_RO;
893 done:
894 if (!status)
895 status = nvmet_copy_to_sgl(req, 0, id, sizeof(*id));
896
897 kfree(id);
898 out:
899 nvmet_req_complete(req, status);
900 }
901
nvmet_execute_identify_endgrp_list(struct nvmet_req * req)902 static void nvmet_execute_identify_endgrp_list(struct nvmet_req *req)
903 {
904 u16 min_endgid = le16_to_cpu(req->cmd->identify.cnssid);
905 static const int buf_size = NVME_IDENTIFY_DATA_SIZE;
906 struct nvmet_ctrl *ctrl = req->sq->ctrl;
907 struct nvmet_ns *ns;
908 unsigned long idx;
909 __le16 *list;
910 u16 status;
911 int i = 1;
912
913 list = kzalloc(buf_size, GFP_KERNEL);
914 if (!list) {
915 status = NVME_SC_INTERNAL;
916 goto out;
917 }
918
919 nvmet_for_each_enabled_ns(&ctrl->subsys->namespaces, idx, ns) {
920 if (ns->nsid <= min_endgid)
921 continue;
922
923 list[i++] = cpu_to_le16(ns->nsid);
924 if (i == buf_size / sizeof(__le16))
925 break;
926 }
927
928 list[0] = cpu_to_le16(i - 1);
929 status = nvmet_copy_to_sgl(req, 0, list, buf_size);
930 kfree(list);
931 out:
932 nvmet_req_complete(req, status);
933 }
934
nvmet_execute_identify_nslist(struct nvmet_req * req,bool match_css)935 static void nvmet_execute_identify_nslist(struct nvmet_req *req, bool match_css)
936 {
937 static const int buf_size = NVME_IDENTIFY_DATA_SIZE;
938 struct nvmet_ctrl *ctrl = req->sq->ctrl;
939 struct nvmet_ns *ns;
940 unsigned long idx;
941 u32 min_nsid = le32_to_cpu(req->cmd->identify.nsid);
942 __le32 *list;
943 u16 status = 0;
944 int i = 0;
945
946 /*
947 * NSID values 0xFFFFFFFE and NVME_NSID_ALL are invalid
948 * See NVMe Base Specification, Active Namespace ID list (CNS 02h).
949 */
950 if (min_nsid == 0xFFFFFFFE || min_nsid == NVME_NSID_ALL) {
951 req->error_loc = offsetof(struct nvme_identify, nsid);
952 status = NVME_SC_INVALID_NS | NVME_STATUS_DNR;
953 goto out;
954 }
955
956 list = kzalloc(buf_size, GFP_KERNEL);
957 if (!list) {
958 status = NVME_SC_INTERNAL;
959 goto out;
960 }
961
962 nvmet_for_each_enabled_ns(&ctrl->subsys->namespaces, idx, ns) {
963 if (ns->nsid <= min_nsid)
964 continue;
965 if (match_css && req->ns->csi != req->cmd->identify.csi)
966 continue;
967 list[i++] = cpu_to_le32(ns->nsid);
968 if (i == buf_size / sizeof(__le32))
969 break;
970 }
971
972 status = nvmet_copy_to_sgl(req, 0, list, buf_size);
973
974 kfree(list);
975 out:
976 nvmet_req_complete(req, status);
977 }
978
nvmet_copy_ns_identifier(struct nvmet_req * req,u8 type,u8 len,void * id,off_t * off)979 static u16 nvmet_copy_ns_identifier(struct nvmet_req *req, u8 type, u8 len,
980 void *id, off_t *off)
981 {
982 struct nvme_ns_id_desc desc = {
983 .nidt = type,
984 .nidl = len,
985 };
986 u16 status;
987
988 status = nvmet_copy_to_sgl(req, *off, &desc, sizeof(desc));
989 if (status)
990 return status;
991 *off += sizeof(desc);
992
993 status = nvmet_copy_to_sgl(req, *off, id, len);
994 if (status)
995 return status;
996 *off += len;
997
998 return 0;
999 }
1000
nvmet_execute_identify_desclist(struct nvmet_req * req)1001 static void nvmet_execute_identify_desclist(struct nvmet_req *req)
1002 {
1003 off_t off = 0;
1004 u16 status;
1005
1006 status = nvmet_req_find_ns(req);
1007 if (status)
1008 goto out;
1009
1010 if (memchr_inv(&req->ns->uuid, 0, sizeof(req->ns->uuid))) {
1011 status = nvmet_copy_ns_identifier(req, NVME_NIDT_UUID,
1012 NVME_NIDT_UUID_LEN,
1013 &req->ns->uuid, &off);
1014 if (status)
1015 goto out;
1016 }
1017 if (memchr_inv(req->ns->nguid, 0, sizeof(req->ns->nguid))) {
1018 status = nvmet_copy_ns_identifier(req, NVME_NIDT_NGUID,
1019 NVME_NIDT_NGUID_LEN,
1020 &req->ns->nguid, &off);
1021 if (status)
1022 goto out;
1023 }
1024
1025 status = nvmet_copy_ns_identifier(req, NVME_NIDT_CSI,
1026 NVME_NIDT_CSI_LEN,
1027 &req->ns->csi, &off);
1028 if (status)
1029 goto out;
1030
1031 if (sg_zero_buffer(req->sg, req->sg_cnt, NVME_IDENTIFY_DATA_SIZE - off,
1032 off) != NVME_IDENTIFY_DATA_SIZE - off)
1033 status = NVME_SC_INTERNAL | NVME_STATUS_DNR;
1034
1035 out:
1036 nvmet_req_complete(req, status);
1037 }
1038
nvmet_execute_identify_ctrl_nvm(struct nvmet_req * req)1039 static void nvmet_execute_identify_ctrl_nvm(struct nvmet_req *req)
1040 {
1041 /* Not supported: return zeroes */
1042 nvmet_req_complete(req,
1043 nvmet_zero_sgl(req, 0, sizeof(struct nvme_id_ctrl_nvm)));
1044 }
1045
nvme_execute_identify_ns_nvm(struct nvmet_req * req)1046 static void nvme_execute_identify_ns_nvm(struct nvmet_req *req)
1047 {
1048 u16 status;
1049 struct nvme_id_ns_nvm *id;
1050
1051 status = nvmet_req_find_ns(req);
1052 if (status)
1053 goto out;
1054
1055 id = kzalloc_obj(*id);
1056 if (!id) {
1057 status = NVME_SC_INTERNAL;
1058 goto out;
1059 }
1060 if (req->ns->bdev)
1061 nvmet_bdev_set_nvm_limits(req->ns->bdev, id);
1062 status = nvmet_copy_to_sgl(req, 0, id, sizeof(*id));
1063 kfree(id);
1064 out:
1065 nvmet_req_complete(req, status);
1066 }
1067
nvmet_execute_id_cs_indep(struct nvmet_req * req)1068 static void nvmet_execute_id_cs_indep(struct nvmet_req *req)
1069 {
1070 struct nvme_id_ns_cs_indep *id;
1071 u16 status;
1072
1073 status = nvmet_req_find_ns(req);
1074 if (status)
1075 goto out;
1076
1077 id = kzalloc_obj(*id);
1078 if (!id) {
1079 status = NVME_SC_INTERNAL;
1080 goto out;
1081 }
1082
1083 id->nstat = NVME_NSTAT_NRDY;
1084 id->anagrpid = cpu_to_le32(req->ns->anagrpid);
1085 id->nmic = NVME_NS_NMIC_SHARED;
1086 if (req->ns->readonly)
1087 id->nsattr |= NVME_NS_ATTR_RO;
1088 if (req->ns->bdev && bdev_rot(req->ns->bdev))
1089 id->nsfeat |= NVME_NS_ROTATIONAL;
1090 /*
1091 * We need flush command to flush the file's metadata,
1092 * so report supporting vwc if backend is file, even
1093 * though buffered_io is disable.
1094 */
1095 if (req->ns->bdev && !bdev_write_cache(req->ns->bdev))
1096 id->nsfeat |= NVME_NS_VWC_NOT_PRESENT;
1097
1098 status = nvmet_copy_to_sgl(req, 0, id, sizeof(*id));
1099 kfree(id);
1100 out:
1101 nvmet_req_complete(req, status);
1102 }
1103
nvmet_execute_identify(struct nvmet_req * req)1104 static void nvmet_execute_identify(struct nvmet_req *req)
1105 {
1106 if (!nvmet_check_transfer_len(req, NVME_IDENTIFY_DATA_SIZE))
1107 return;
1108
1109 switch (req->cmd->identify.cns) {
1110 case NVME_ID_CNS_NS:
1111 nvmet_execute_identify_ns(req);
1112 return;
1113 case NVME_ID_CNS_CTRL:
1114 nvmet_execute_identify_ctrl(req);
1115 return;
1116 case NVME_ID_CNS_NS_ACTIVE_LIST:
1117 nvmet_execute_identify_nslist(req, false);
1118 return;
1119 case NVME_ID_CNS_NS_DESC_LIST:
1120 nvmet_execute_identify_desclist(req);
1121 return;
1122 case NVME_ID_CNS_CS_NS:
1123 switch (req->cmd->identify.csi) {
1124 case NVME_CSI_NVM:
1125 nvme_execute_identify_ns_nvm(req);
1126 return;
1127 case NVME_CSI_ZNS:
1128 if (IS_ENABLED(CONFIG_BLK_DEV_ZONED)) {
1129 nvmet_execute_identify_ns_zns(req);
1130 return;
1131 }
1132 break;
1133 }
1134 break;
1135 case NVME_ID_CNS_CS_CTRL:
1136 switch (req->cmd->identify.csi) {
1137 case NVME_CSI_NVM:
1138 nvmet_execute_identify_ctrl_nvm(req);
1139 return;
1140 case NVME_CSI_ZNS:
1141 if (IS_ENABLED(CONFIG_BLK_DEV_ZONED)) {
1142 nvmet_execute_identify_ctrl_zns(req);
1143 return;
1144 }
1145 break;
1146 }
1147 break;
1148 case NVME_ID_CNS_NS_ACTIVE_LIST_CS:
1149 nvmet_execute_identify_nslist(req, true);
1150 return;
1151 case NVME_ID_CNS_NS_CS_INDEP:
1152 nvmet_execute_id_cs_indep(req);
1153 return;
1154 case NVME_ID_CNS_ENDGRP_LIST:
1155 nvmet_execute_identify_endgrp_list(req);
1156 return;
1157 }
1158
1159 pr_debug("unhandled identify cns %d on qid %d\n",
1160 req->cmd->identify.cns, req->sq->qid);
1161 req->error_loc = offsetof(struct nvme_identify, cns);
1162 nvmet_req_complete(req, NVME_SC_INVALID_FIELD | NVME_STATUS_DNR);
1163 }
1164
1165 /*
1166 * A "minimum viable" abort implementation: the command is mandatory in the
1167 * spec, but we are not required to do any useful work. We couldn't really
1168 * do a useful abort, so don't bother even with waiting for the command
1169 * to be executed and return immediately telling the command to abort
1170 * wasn't found.
1171 */
nvmet_execute_abort(struct nvmet_req * req)1172 static void nvmet_execute_abort(struct nvmet_req *req)
1173 {
1174 if (!nvmet_check_transfer_len(req, 0))
1175 return;
1176 nvmet_set_result(req, 1);
1177 nvmet_req_complete(req, 0);
1178 }
1179
nvmet_write_protect_flush_sync(struct nvmet_req * req)1180 static u16 nvmet_write_protect_flush_sync(struct nvmet_req *req)
1181 {
1182 u16 status;
1183
1184 if (req->ns->file)
1185 status = nvmet_file_flush(req);
1186 else
1187 status = nvmet_bdev_flush(req);
1188
1189 if (status)
1190 pr_err("write protect flush failed nsid: %u\n", req->ns->nsid);
1191 return status;
1192 }
1193
nvmet_set_feat_write_protect(struct nvmet_req * req)1194 static u16 nvmet_set_feat_write_protect(struct nvmet_req *req)
1195 {
1196 u32 write_protect = le32_to_cpu(req->cmd->common.cdw11);
1197 struct nvmet_subsys *subsys = nvmet_req_subsys(req);
1198 u16 status;
1199
1200 status = nvmet_req_find_ns(req);
1201 if (status)
1202 return status;
1203
1204 mutex_lock(&subsys->lock);
1205 switch (write_protect) {
1206 case NVME_NS_WRITE_PROTECT:
1207 req->ns->readonly = true;
1208 status = nvmet_write_protect_flush_sync(req);
1209 if (status)
1210 req->ns->readonly = false;
1211 break;
1212 case NVME_NS_NO_WRITE_PROTECT:
1213 req->ns->readonly = false;
1214 status = 0;
1215 break;
1216 default:
1217 break;
1218 }
1219
1220 if (!status)
1221 nvmet_ns_changed(subsys, req->ns->nsid);
1222 mutex_unlock(&subsys->lock);
1223 return status;
1224 }
1225
nvmet_set_feat_kato(struct nvmet_req * req)1226 u16 nvmet_set_feat_kato(struct nvmet_req *req)
1227 {
1228 u32 val32 = le32_to_cpu(req->cmd->common.cdw11);
1229
1230 nvmet_stop_keep_alive_timer(req->sq->ctrl);
1231 req->sq->ctrl->kato = DIV_ROUND_UP(val32, 1000);
1232 nvmet_start_keep_alive_timer(req->sq->ctrl);
1233
1234 nvmet_set_result(req, req->sq->ctrl->kato);
1235
1236 return 0;
1237 }
1238
nvmet_set_feat_async_event(struct nvmet_req * req,u32 mask)1239 u16 nvmet_set_feat_async_event(struct nvmet_req *req, u32 mask)
1240 {
1241 u32 val32 = le32_to_cpu(req->cmd->common.cdw11);
1242
1243 if (val32 & ~mask) {
1244 req->error_loc = offsetof(struct nvme_common_command, cdw11);
1245 return NVME_SC_INVALID_FIELD | NVME_STATUS_DNR;
1246 }
1247
1248 WRITE_ONCE(req->sq->ctrl->aen_enabled, val32);
1249 nvmet_set_result(req, val32);
1250
1251 return 0;
1252 }
1253
nvmet_set_feat_host_id(struct nvmet_req * req)1254 static u16 nvmet_set_feat_host_id(struct nvmet_req *req)
1255 {
1256 struct nvmet_ctrl *ctrl = req->sq->ctrl;
1257
1258 if (!nvmet_is_pci_ctrl(ctrl))
1259 return NVME_SC_CMD_SEQ_ERROR | NVME_STATUS_DNR;
1260
1261 /*
1262 * The NVMe base specifications v2.1 recommends supporting 128-bits host
1263 * IDs (section 5.1.25.1.28.1). However, that same section also says
1264 * that "The controller may support a 64-bit Host Identifier and/or an
1265 * extended 128-bit Host Identifier". So simplify this support and do
1266 * not support 64-bits host IDs to avoid needing to check that all
1267 * controllers associated with the same subsystem all use the same host
1268 * ID size.
1269 */
1270 if (!(req->cmd->common.cdw11 & cpu_to_le32(1 << 0))) {
1271 req->error_loc = offsetof(struct nvme_common_command, cdw11);
1272 return NVME_SC_INVALID_FIELD | NVME_STATUS_DNR;
1273 }
1274
1275 return nvmet_copy_from_sgl(req, 0, &req->sq->ctrl->hostid,
1276 sizeof(req->sq->ctrl->hostid));
1277 }
1278
nvmet_set_feat_irq_coalesce(struct nvmet_req * req)1279 static u16 nvmet_set_feat_irq_coalesce(struct nvmet_req *req)
1280 {
1281 struct nvmet_ctrl *ctrl = req->sq->ctrl;
1282 u32 cdw11 = le32_to_cpu(req->cmd->common.cdw11);
1283 struct nvmet_feat_irq_coalesce irqc = {
1284 .time = (cdw11 >> 8) & 0xff,
1285 .thr = cdw11 & 0xff,
1286 };
1287
1288 /*
1289 * This feature is not supported for fabrics controllers and mandatory
1290 * for PCI controllers.
1291 */
1292 if (!nvmet_is_pci_ctrl(ctrl)) {
1293 req->error_loc = offsetof(struct nvme_common_command, cdw10);
1294 return NVME_SC_INVALID_FIELD | NVME_STATUS_DNR;
1295 }
1296
1297 return ctrl->ops->set_feature(ctrl, NVME_FEAT_IRQ_COALESCE, &irqc);
1298 }
1299
nvmet_set_feat_irq_config(struct nvmet_req * req)1300 static u16 nvmet_set_feat_irq_config(struct nvmet_req *req)
1301 {
1302 struct nvmet_ctrl *ctrl = req->sq->ctrl;
1303 u32 cdw11 = le32_to_cpu(req->cmd->common.cdw11);
1304 struct nvmet_feat_irq_config irqcfg = {
1305 .iv = cdw11 & 0xffff,
1306 .cd = (cdw11 >> 16) & 0x1,
1307 };
1308
1309 /*
1310 * This feature is not supported for fabrics controllers and mandatory
1311 * for PCI controllers.
1312 */
1313 if (!nvmet_is_pci_ctrl(ctrl)) {
1314 req->error_loc = offsetof(struct nvme_common_command, cdw10);
1315 return NVME_SC_INVALID_FIELD | NVME_STATUS_DNR;
1316 }
1317
1318 return ctrl->ops->set_feature(ctrl, NVME_FEAT_IRQ_CONFIG, &irqcfg);
1319 }
1320
nvmet_set_feat_arbitration(struct nvmet_req * req)1321 static u16 nvmet_set_feat_arbitration(struct nvmet_req *req)
1322 {
1323 struct nvmet_ctrl *ctrl = req->sq->ctrl;
1324 u32 cdw11 = le32_to_cpu(req->cmd->common.cdw11);
1325 struct nvmet_feat_arbitration arb = {
1326 .hpw = (cdw11 >> 24) & 0xff,
1327 .mpw = (cdw11 >> 16) & 0xff,
1328 .lpw = (cdw11 >> 8) & 0xff,
1329 .ab = cdw11 & 0x3,
1330 };
1331
1332 if (!ctrl->ops->set_feature) {
1333 req->error_loc = offsetof(struct nvme_common_command, cdw10);
1334 return NVME_SC_INVALID_FIELD | NVME_STATUS_DNR;
1335 }
1336
1337 return ctrl->ops->set_feature(ctrl, NVME_FEAT_ARBITRATION, &arb);
1338 }
1339
nvmet_execute_set_features(struct nvmet_req * req)1340 void nvmet_execute_set_features(struct nvmet_req *req)
1341 {
1342 struct nvmet_subsys *subsys = nvmet_req_subsys(req);
1343 u32 cdw10 = le32_to_cpu(req->cmd->common.cdw10);
1344 u32 cdw11 = le32_to_cpu(req->cmd->common.cdw11);
1345 u16 status = 0;
1346 u16 nsqr;
1347 u16 ncqr;
1348
1349 if (!nvmet_check_data_len_lte(req, 0))
1350 return;
1351
1352 switch (cdw10 & 0xff) {
1353 case NVME_FEAT_ARBITRATION:
1354 status = nvmet_set_feat_arbitration(req);
1355 break;
1356 case NVME_FEAT_NUM_QUEUES:
1357 ncqr = (cdw11 >> 16) & 0xffff;
1358 nsqr = cdw11 & 0xffff;
1359 if (ncqr == 0xffff || nsqr == 0xffff) {
1360 status = NVME_SC_INVALID_FIELD | NVME_STATUS_DNR;
1361 break;
1362 }
1363 nvmet_set_result(req,
1364 (subsys->max_qid - 1) | ((subsys->max_qid - 1) << 16));
1365 break;
1366 case NVME_FEAT_IRQ_COALESCE:
1367 status = nvmet_set_feat_irq_coalesce(req);
1368 break;
1369 case NVME_FEAT_IRQ_CONFIG:
1370 status = nvmet_set_feat_irq_config(req);
1371 break;
1372 case NVME_FEAT_KATO:
1373 status = nvmet_set_feat_kato(req);
1374 break;
1375 case NVME_FEAT_ASYNC_EVENT:
1376 status = nvmet_set_feat_async_event(req, NVMET_AEN_CFG_ALL);
1377 break;
1378 case NVME_FEAT_HOST_ID:
1379 status = nvmet_set_feat_host_id(req);
1380 break;
1381 case NVME_FEAT_WRITE_PROTECT:
1382 status = nvmet_set_feat_write_protect(req);
1383 break;
1384 case NVME_FEAT_RESV_MASK:
1385 status = nvmet_set_feat_resv_notif_mask(req, cdw11);
1386 break;
1387 default:
1388 req->error_loc = offsetof(struct nvme_common_command, cdw10);
1389 status = NVME_SC_INVALID_FIELD | NVME_STATUS_DNR;
1390 break;
1391 }
1392
1393 nvmet_req_complete(req, status);
1394 }
1395
nvmet_get_feat_write_protect(struct nvmet_req * req)1396 static u16 nvmet_get_feat_write_protect(struct nvmet_req *req)
1397 {
1398 struct nvmet_subsys *subsys = nvmet_req_subsys(req);
1399 u32 result;
1400
1401 result = nvmet_req_find_ns(req);
1402 if (result)
1403 return result;
1404
1405 mutex_lock(&subsys->lock);
1406 if (req->ns->readonly == true)
1407 result = NVME_NS_WRITE_PROTECT;
1408 else
1409 result = NVME_NS_NO_WRITE_PROTECT;
1410 nvmet_set_result(req, result);
1411 mutex_unlock(&subsys->lock);
1412
1413 return 0;
1414 }
1415
nvmet_get_feat_irq_coalesce(struct nvmet_req * req)1416 static u16 nvmet_get_feat_irq_coalesce(struct nvmet_req *req)
1417 {
1418 struct nvmet_ctrl *ctrl = req->sq->ctrl;
1419 struct nvmet_feat_irq_coalesce irqc = { };
1420 u16 status;
1421
1422 /*
1423 * This feature is not supported for fabrics controllers and mandatory
1424 * for PCI controllers.
1425 */
1426 if (!nvmet_is_pci_ctrl(ctrl)) {
1427 req->error_loc = offsetof(struct nvme_common_command, cdw10);
1428 return NVME_SC_INVALID_FIELD | NVME_STATUS_DNR;
1429 }
1430
1431 status = ctrl->ops->get_feature(ctrl, NVME_FEAT_IRQ_COALESCE, &irqc);
1432 if (status != NVME_SC_SUCCESS)
1433 return status;
1434
1435 nvmet_set_result(req, ((u32)irqc.time << 8) | (u32)irqc.thr);
1436
1437 return NVME_SC_SUCCESS;
1438 }
1439
nvmet_get_feat_irq_config(struct nvmet_req * req)1440 static u16 nvmet_get_feat_irq_config(struct nvmet_req *req)
1441 {
1442 struct nvmet_ctrl *ctrl = req->sq->ctrl;
1443 u32 iv = le32_to_cpu(req->cmd->common.cdw11) & 0xffff;
1444 struct nvmet_feat_irq_config irqcfg = { .iv = iv };
1445 u16 status;
1446
1447 /*
1448 * This feature is not supported for fabrics controllers and mandatory
1449 * for PCI controllers.
1450 */
1451 if (!nvmet_is_pci_ctrl(ctrl)) {
1452 req->error_loc = offsetof(struct nvme_common_command, cdw10);
1453 return NVME_SC_INVALID_FIELD | NVME_STATUS_DNR;
1454 }
1455
1456 status = ctrl->ops->get_feature(ctrl, NVME_FEAT_IRQ_CONFIG, &irqcfg);
1457 if (status != NVME_SC_SUCCESS)
1458 return status;
1459
1460 nvmet_set_result(req, ((u32)irqcfg.cd << 16) | iv);
1461
1462 return NVME_SC_SUCCESS;
1463 }
1464
nvmet_get_feat_arbitration(struct nvmet_req * req)1465 static u16 nvmet_get_feat_arbitration(struct nvmet_req *req)
1466 {
1467 struct nvmet_ctrl *ctrl = req->sq->ctrl;
1468 struct nvmet_feat_arbitration arb = { };
1469 u16 status;
1470
1471 if (!ctrl->ops->get_feature) {
1472 req->error_loc = offsetof(struct nvme_common_command, cdw10);
1473 return NVME_SC_INVALID_FIELD | NVME_STATUS_DNR;
1474 }
1475
1476 status = ctrl->ops->get_feature(ctrl, NVME_FEAT_ARBITRATION, &arb);
1477 if (status != NVME_SC_SUCCESS)
1478 return status;
1479
1480 nvmet_set_result(req,
1481 ((u32)arb.hpw << 24) |
1482 ((u32)arb.mpw << 16) |
1483 ((u32)arb.lpw << 8) |
1484 (arb.ab & 0x3));
1485
1486 return NVME_SC_SUCCESS;
1487 }
1488
nvmet_get_feat_kato(struct nvmet_req * req)1489 void nvmet_get_feat_kato(struct nvmet_req *req)
1490 {
1491 nvmet_set_result(req, req->sq->ctrl->kato * 1000);
1492 }
1493
nvmet_get_feat_async_event(struct nvmet_req * req)1494 void nvmet_get_feat_async_event(struct nvmet_req *req)
1495 {
1496 nvmet_set_result(req, READ_ONCE(req->sq->ctrl->aen_enabled));
1497 }
1498
nvmet_execute_get_features(struct nvmet_req * req)1499 void nvmet_execute_get_features(struct nvmet_req *req)
1500 {
1501 struct nvmet_subsys *subsys = nvmet_req_subsys(req);
1502 u32 cdw10 = le32_to_cpu(req->cmd->common.cdw10);
1503 u16 status = 0;
1504
1505 if (!nvmet_check_transfer_len(req, nvmet_feat_data_len(req, cdw10)))
1506 return;
1507
1508 switch (cdw10 & 0xff) {
1509 /*
1510 * These features are mandatory in the spec, but we don't
1511 * have a useful way to implement them. We'll eventually
1512 * need to come up with some fake values for these.
1513 */
1514 #if 0
1515 case NVME_FEAT_POWER_MGMT:
1516 break;
1517 case NVME_FEAT_TEMP_THRESH:
1518 break;
1519 case NVME_FEAT_ERR_RECOVERY:
1520 break;
1521 case NVME_FEAT_WRITE_ATOMIC:
1522 break;
1523 #endif
1524 case NVME_FEAT_ARBITRATION:
1525 status = nvmet_get_feat_arbitration(req);
1526 break;
1527 case NVME_FEAT_IRQ_COALESCE:
1528 status = nvmet_get_feat_irq_coalesce(req);
1529 break;
1530 case NVME_FEAT_IRQ_CONFIG:
1531 status = nvmet_get_feat_irq_config(req);
1532 break;
1533 case NVME_FEAT_ASYNC_EVENT:
1534 nvmet_get_feat_async_event(req);
1535 break;
1536 case NVME_FEAT_VOLATILE_WC:
1537 nvmet_set_result(req, 1);
1538 break;
1539 case NVME_FEAT_NUM_QUEUES:
1540 nvmet_set_result(req,
1541 (subsys->max_qid-1) | ((subsys->max_qid-1) << 16));
1542 break;
1543 case NVME_FEAT_KATO:
1544 nvmet_get_feat_kato(req);
1545 break;
1546 case NVME_FEAT_HOST_ID:
1547 /* need 128-bit host identifier flag */
1548 if (!(req->cmd->common.cdw11 & cpu_to_le32(1 << 0))) {
1549 req->error_loc =
1550 offsetof(struct nvme_common_command, cdw11);
1551 status = NVME_SC_INVALID_FIELD | NVME_STATUS_DNR;
1552 break;
1553 }
1554
1555 status = nvmet_copy_to_sgl(req, 0, &req->sq->ctrl->hostid,
1556 sizeof(req->sq->ctrl->hostid));
1557 break;
1558 case NVME_FEAT_WRITE_PROTECT:
1559 status = nvmet_get_feat_write_protect(req);
1560 break;
1561 case NVME_FEAT_RESV_MASK:
1562 status = nvmet_get_feat_resv_notif_mask(req);
1563 break;
1564 default:
1565 req->error_loc =
1566 offsetof(struct nvme_common_command, cdw10);
1567 status = NVME_SC_INVALID_FIELD | NVME_STATUS_DNR;
1568 break;
1569 }
1570
1571 nvmet_req_complete(req, status);
1572 }
1573
nvmet_execute_async_event(struct nvmet_req * req)1574 void nvmet_execute_async_event(struct nvmet_req *req)
1575 {
1576 struct nvmet_ctrl *ctrl = req->sq->ctrl;
1577
1578 if (!nvmet_check_transfer_len(req, 0))
1579 return;
1580
1581 mutex_lock(&ctrl->lock);
1582 if (ctrl->nr_async_event_cmds >= NVMET_ASYNC_EVENTS) {
1583 mutex_unlock(&ctrl->lock);
1584 nvmet_req_complete(req, NVME_SC_ASYNC_LIMIT | NVME_STATUS_DNR);
1585 return;
1586 }
1587 ctrl->async_event_cmds[ctrl->nr_async_event_cmds++] = req;
1588 mutex_unlock(&ctrl->lock);
1589
1590 queue_work(nvmet_aen_wq, &ctrl->async_event_work);
1591 }
1592
nvmet_execute_keep_alive(struct nvmet_req * req)1593 void nvmet_execute_keep_alive(struct nvmet_req *req)
1594 {
1595 struct nvmet_ctrl *ctrl = req->sq->ctrl;
1596 u16 status = 0;
1597
1598 if (!nvmet_check_transfer_len(req, 0))
1599 return;
1600
1601 if (!ctrl->kato) {
1602 status = NVME_SC_KA_TIMEOUT_INVALID;
1603 goto out;
1604 }
1605
1606 pr_debug("ctrl %d update keep-alive timer for %d secs\n",
1607 ctrl->cntlid, ctrl->kato);
1608 mod_delayed_work(system_percpu_wq, &ctrl->ka_work, ctrl->kato * HZ);
1609 out:
1610 nvmet_req_complete(req, status);
1611 }
1612
nvmet_admin_cmd_data_len(struct nvmet_req * req)1613 u32 nvmet_admin_cmd_data_len(struct nvmet_req *req)
1614 {
1615 struct nvme_command *cmd = req->cmd;
1616
1617 if (nvme_is_fabrics(cmd))
1618 return nvmet_fabrics_admin_cmd_data_len(req);
1619 if (nvmet_is_disc_subsys(nvmet_req_subsys(req)))
1620 return nvmet_discovery_cmd_data_len(req);
1621
1622 switch (cmd->common.opcode) {
1623 case nvme_admin_get_log_page:
1624 return nvmet_get_log_page_len(cmd);
1625 case nvme_admin_identify:
1626 return NVME_IDENTIFY_DATA_SIZE;
1627 case nvme_admin_get_features:
1628 return nvmet_feat_data_len(req, le32_to_cpu(cmd->common.cdw10));
1629 default:
1630 return 0;
1631 }
1632 }
1633
nvmet_parse_admin_cmd(struct nvmet_req * req)1634 u16 nvmet_parse_admin_cmd(struct nvmet_req *req)
1635 {
1636 struct nvme_command *cmd = req->cmd;
1637 u16 ret;
1638
1639 if (nvme_is_fabrics(cmd))
1640 return nvmet_parse_fabrics_admin_cmd(req);
1641 if (nvmet_is_disc_subsys(nvmet_req_subsys(req)))
1642 return nvmet_parse_discovery_cmd(req);
1643
1644 ret = nvmet_check_ctrl_status(req);
1645 if (unlikely(ret))
1646 return ret;
1647
1648 /* For PCI controllers, admin commands shall not use SGL. */
1649 if (nvmet_is_pci_ctrl(req->sq->ctrl) && !req->sq->qid &&
1650 cmd->common.flags & NVME_CMD_SGL_ALL)
1651 return NVME_SC_INVALID_FIELD | NVME_STATUS_DNR;
1652
1653 if (nvmet_is_passthru_req(req))
1654 return nvmet_parse_passthru_admin_cmd(req);
1655
1656 switch (cmd->common.opcode) {
1657 case nvme_admin_delete_sq:
1658 req->execute = nvmet_execute_delete_sq;
1659 return 0;
1660 case nvme_admin_create_sq:
1661 req->execute = nvmet_execute_create_sq;
1662 return 0;
1663 case nvme_admin_get_log_page:
1664 req->execute = nvmet_execute_get_log_page;
1665 return 0;
1666 case nvme_admin_delete_cq:
1667 req->execute = nvmet_execute_delete_cq;
1668 return 0;
1669 case nvme_admin_create_cq:
1670 req->execute = nvmet_execute_create_cq;
1671 return 0;
1672 case nvme_admin_identify:
1673 req->execute = nvmet_execute_identify;
1674 return 0;
1675 case nvme_admin_abort_cmd:
1676 req->execute = nvmet_execute_abort;
1677 return 0;
1678 case nvme_admin_set_features:
1679 req->execute = nvmet_execute_set_features;
1680 return 0;
1681 case nvme_admin_get_features:
1682 req->execute = nvmet_execute_get_features;
1683 return 0;
1684 case nvme_admin_async_event:
1685 req->execute = nvmet_execute_async_event;
1686 return 0;
1687 case nvme_admin_keep_alive:
1688 req->execute = nvmet_execute_keep_alive;
1689 return 0;
1690 default:
1691 return nvmet_report_invalid_opcode(req);
1692 }
1693 }
1694