xref: /linux/drivers/gpu/drm/nouveau/include/nvkm/core/device.h (revision ab93e0dd72c37d378dd936f031ffb83ff2bd87ce)
1 /* SPDX-License-Identifier: MIT */
2 #ifndef __NVKM_DEVICE_H__
3 #define __NVKM_DEVICE_H__
4 #include <core/oclass.h>
5 #include <core/intr.h>
6 enum nvkm_subdev_type;
7 
8 enum nvkm_device_type {
9 	NVKM_DEVICE_PCI,
10 	NVKM_DEVICE_AGP,
11 	NVKM_DEVICE_PCIE,
12 	NVKM_DEVICE_TEGRA,
13 };
14 
15 struct nvkm_device {
16 	const struct nvkm_device_func *func;
17 	const struct nvkm_device_quirk *quirk;
18 	struct device *dev;
19 	enum nvkm_device_type type;
20 	u64 handle;
21 	const char *name;
22 	const char *cfgopt;
23 	const char *dbgopt;
24 
25 	struct list_head head;
26 	struct mutex mutex;
27 	int refcount;
28 
29 	void __iomem *pri;
30 
31 	u32 debug;
32 
33 	const struct nvkm_device_chip *chip;
34 	enum {
35 		NV_04    = 0x04,
36 		NV_10    = 0x10,
37 		NV_11    = 0x11,
38 		NV_20    = 0x20,
39 		NV_30    = 0x30,
40 		NV_40    = 0x40,
41 		NV_50    = 0x50,
42 		NV_C0    = 0xc0,
43 		NV_E0    = 0xe0,
44 		GM100    = 0x110,
45 		GP100    = 0x130,
46 		GV100    = 0x140,
47 		TU100    = 0x160,
48 		GA100    = 0x170,
49 		GH100    = 0x180,
50 		AD100    = 0x190,
51 		GB10x    = 0x1a0,
52 		GB20x    = 0x1b0,
53 	} card_type;
54 	u32 chipset;
55 	u8  chiprev;
56 	u32 crystal;
57 
58 	struct {
59 		struct notifier_block nb;
60 	} acpi;
61 
62 #define NVKM_LAYOUT_ONCE(type,data,ptr) data *ptr;
63 #define NVKM_LAYOUT_INST(type,data,ptr,cnt) data *ptr[cnt];
64 #include <core/layout.h>
65 #undef NVKM_LAYOUT_INST
66 #undef NVKM_LAYOUT_ONCE
67 	struct list_head subdev;
68 
69 	struct {
70 		struct list_head intr;
71 		struct list_head prio[NVKM_INTR_PRIO_NR];
72 		spinlock_t lock;
73 		int irq;
74 		bool alloc;
75 		bool armed;
76 		bool legacy_done;
77 	} intr;
78 };
79 
80 struct nvkm_subdev *nvkm_device_subdev(struct nvkm_device *, int type, int inst);
81 struct nvkm_engine *nvkm_device_engine(struct nvkm_device *, int type, int inst);
82 
83 enum nvkm_bar_id {
84 	NVKM_BAR_INVALID = 0,
85 	NVKM_BAR0_PRI,
86 	NVKM_BAR1_FB,
87 	NVKM_BAR2_INST,
88 };
89 
90 struct nvkm_device_func {
91 	struct nvkm_device_pci *(*pci)(struct nvkm_device *);
92 	struct nvkm_device_tegra *(*tegra)(struct nvkm_device *);
93 	void *(*dtor)(struct nvkm_device *);
94 	int (*preinit)(struct nvkm_device *);
95 	int (*init)(struct nvkm_device *);
96 	void (*fini)(struct nvkm_device *, bool suspend);
97 	int (*irq)(struct nvkm_device *);
98 	resource_size_t (*resource_addr)(struct nvkm_device *, enum nvkm_bar_id);
99 	resource_size_t (*resource_size)(struct nvkm_device *, enum nvkm_bar_id);
100 	bool cpu_coherent;
101 };
102 
103 struct nvkm_device_quirk {
104 	u8 tv_pin_mask;
105 	u8 tv_gpio;
106 };
107 
108 struct nvkm_device_chip {
109 	const char *name;
110 #define NVKM_LAYOUT_ONCE(type,data,ptr,...)                                                  \
111 	struct {                                                                             \
112 		u32 inst;                                                                    \
113 		int (*ctor)(struct nvkm_device *, enum nvkm_subdev_type, int inst, data **); \
114 	} ptr;
115 #define NVKM_LAYOUT_INST(A...) NVKM_LAYOUT_ONCE(A)
116 #include <core/layout.h>
117 #undef NVKM_LAYOUT_INST
118 #undef NVKM_LAYOUT_ONCE
119 };
120 
121 struct nvkm_device *nvkm_device_find(u64 name);
122 
123 /* privileged register interface accessor macros */
124 #define nvkm_rd08(d,a) ioread8((d)->pri + (a))
125 #define nvkm_rd16(d,a) ioread16_native((d)->pri + (a))
126 #define nvkm_rd32(d,a) ioread32_native((d)->pri + (a))
127 #define nvkm_wr08(d,a,v) iowrite8((v), (d)->pri + (a))
128 #define nvkm_wr16(d,a,v) iowrite16_native((v), (d)->pri + (a))
129 #define nvkm_wr32(d,a,v) iowrite32_native((v), (d)->pri + (a))
130 #define nvkm_mask(d,a,m,v) ({                                                  \
131 	struct nvkm_device *_device = (d);                                     \
132 	u32 _addr = (a), _temp = nvkm_rd32(_device, _addr);                    \
133 	nvkm_wr32(_device, _addr, (_temp & ~(m)) | (v));                       \
134 	_temp;                                                                 \
135 })
136 
137 #define NVKM_RD32_(p,o,dr) nvkm_rd32((p), (o) + (dr))
138 #define NVKM_RD32(p,A...) DRF_RV(NVKM_RD32_, (p), 0, ##A)
139 
140 void nvkm_device_del(struct nvkm_device **);
141 
142 struct nvkm_device_oclass {
143 	int (*ctor)(struct nvkm_device *, const struct nvkm_oclass *,
144 		    void *data, u32 size, struct nvkm_object **);
145 	struct nvkm_sclass base;
146 };
147 
148 extern const struct nvkm_sclass nvkm_udevice_sclass;
149 
150 /* device logging */
151 #define nvdev_printk_(d,l,p,f,a...) do {                                       \
152 	const struct nvkm_device *_device = (d);                               \
153 	if (_device->debug >= (l))                                             \
154 		dev_##p(_device->dev, f, ##a);                                 \
155 } while(0)
156 #define nvdev_printk(d,l,p,f,a...) nvdev_printk_((d), NV_DBG_##l, p, f, ##a)
157 #define nvdev_fatal(d,f,a...) nvdev_printk((d), FATAL,   crit, f, ##a)
158 #define nvdev_error(d,f,a...) nvdev_printk((d), ERROR,    err, f, ##a)
159 #define nvdev_warn(d,f,a...)  nvdev_printk((d),  WARN, notice, f, ##a)
160 #define nvdev_info(d,f,a...)  nvdev_printk((d),  INFO,   info, f, ##a)
161 #define nvdev_debug(d,f,a...) nvdev_printk((d), DEBUG,   info, f, ##a)
162 #define nvdev_trace(d,f,a...) nvdev_printk((d), TRACE,   info, f, ##a)
163 #define nvdev_spam(d,f,a...)  nvdev_printk((d),  SPAM,    dbg, f, ##a)
164 #endif
165