1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #ifndef __INTEL_DISPLAY_CORE_H__
7 #define __INTEL_DISPLAY_CORE_H__
8 
9 #include <linux/list.h>
10 #include <linux/llist.h>
11 #include <linux/mutex.h>
12 #include <linux/types.h>
13 #include <linux/wait.h>
14 #include <linux/workqueue.h>
15 
16 #include <drm/drm_connector.h>
17 #include <drm/drm_modeset_lock.h>
18 
19 #include "intel_cdclk.h"
20 #include "intel_display_device.h"
21 #include "intel_display_limits.h"
22 #include "intel_display_params.h"
23 #include "intel_display_power.h"
24 #include "intel_dpll_mgr.h"
25 #include "intel_fbc.h"
26 #include "intel_global_state.h"
27 #include "intel_gmbus.h"
28 #include "intel_opregion.h"
29 #include "intel_dmc_wl.h"
30 #include "intel_wm_types.h"
31 
32 struct task_struct;
33 
34 struct drm_i915_private;
35 struct drm_property;
36 struct drm_property_blob;
37 struct i915_audio_component;
38 struct i915_hdcp_arbiter;
39 struct intel_atomic_state;
40 struct intel_audio_funcs;
41 struct intel_cdclk_funcs;
42 struct intel_cdclk_vals;
43 struct intel_color_funcs;
44 struct intel_crtc;
45 struct intel_crtc_state;
46 struct intel_dmc;
47 struct intel_dpll_funcs;
48 struct intel_dpll_mgr;
49 struct intel_fbdev;
50 struct intel_fdi_funcs;
51 struct intel_hotplug_funcs;
52 struct intel_initial_plane_config;
53 struct intel_opregion;
54 struct intel_overlay;
55 
56 /* Amount of SAGV/QGV points, BSpec precisely defines this */
57 #define I915_NUM_QGV_POINTS 8
58 
59 /* Amount of PSF GV points, BSpec precisely defines this */
60 #define I915_NUM_PSF_GV_POINTS 3
61 
62 struct intel_display_funcs {
63 	/*
64 	 * Returns the active state of the crtc, and if the crtc is active,
65 	 * fills out the pipe-config with the hw state.
66 	 */
67 	bool (*get_pipe_config)(struct intel_crtc *,
68 				struct intel_crtc_state *);
69 	void (*get_initial_plane_config)(struct intel_crtc *,
70 					 struct intel_initial_plane_config *);
71 	bool (*fixup_initial_plane_config)(struct intel_crtc *crtc,
72 					   const struct intel_initial_plane_config *plane_config);
73 	void (*crtc_enable)(struct intel_atomic_state *state,
74 			    struct intel_crtc *crtc);
75 	void (*crtc_disable)(struct intel_atomic_state *state,
76 			     struct intel_crtc *crtc);
77 	void (*commit_modeset_enables)(struct intel_atomic_state *state);
78 };
79 
80 /* functions used for watermark calcs for display. */
81 struct intel_wm_funcs {
82 	/* update_wm is for legacy wm management */
83 	void (*update_wm)(struct drm_i915_private *dev_priv);
84 	int (*compute_watermarks)(struct intel_atomic_state *state,
85 				  struct intel_crtc *crtc);
86 	void (*initial_watermarks)(struct intel_atomic_state *state,
87 				   struct intel_crtc *crtc);
88 	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
89 					 struct intel_crtc *crtc);
90 	void (*optimize_watermarks)(struct intel_atomic_state *state,
91 				    struct intel_crtc *crtc);
92 	int (*compute_global_watermarks)(struct intel_atomic_state *state);
93 	void (*get_hw_state)(struct drm_i915_private *i915);
94 	void (*sanitize)(struct drm_i915_private *i915);
95 };
96 
97 struct intel_audio_state {
98 	struct intel_encoder *encoder;
99 	u8 eld[MAX_ELD_BYTES];
100 };
101 
102 struct intel_audio {
103 	/* hda/i915 audio component */
104 	struct i915_audio_component *component;
105 	bool component_registered;
106 	/* mutex for audio/video sync */
107 	struct mutex mutex;
108 	int power_refcount;
109 	u32 freq_cntrl;
110 
111 	/* current audio state for the audio component hooks */
112 	struct intel_audio_state state[I915_MAX_TRANSCODERS];
113 
114 	/* necessary resource sharing with HDMI LPE audio driver. */
115 	struct {
116 		struct platform_device *platdev;
117 		int irq;
118 	} lpe;
119 };
120 
121 /*
122  * dpll and cdclk state is protected by connection_mutex dpll.lock serializes
123  * intel_{prepare,enable,disable}_shared_dpll.  Must be global rather than per
124  * dpll, because on some platforms plls share registers.
125  */
126 struct intel_dpll {
127 	struct mutex lock;
128 
129 	int num_shared_dpll;
130 	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
131 	const struct intel_dpll_mgr *mgr;
132 
133 	struct {
134 		int nssc;
135 		int ssc;
136 	} ref_clks;
137 
138 	/*
139 	 * Bitmask of PLLs using the PCH SSC, indexed using enum intel_dpll_id.
140 	 */
141 	u8 pch_ssc_use;
142 };
143 
144 struct intel_frontbuffer_tracking {
145 	spinlock_t lock;
146 
147 	/*
148 	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
149 	 * scheduled flips.
150 	 */
151 	unsigned busy_bits;
152 	unsigned flip_bits;
153 };
154 
155 struct intel_hotplug {
156 	struct delayed_work hotplug_work;
157 
158 	const u32 *hpd, *pch_hpd;
159 
160 	struct {
161 		unsigned long last_jiffies;
162 		int count;
163 		enum {
164 			HPD_ENABLED = 0,
165 			HPD_DISABLED = 1,
166 			HPD_MARK_DISABLED = 2
167 		} state;
168 	} stats[HPD_NUM_PINS];
169 	u32 event_bits;
170 	u32 retry_bits;
171 	struct delayed_work reenable_work;
172 
173 	u32 long_port_mask;
174 	u32 short_port_mask;
175 	struct work_struct dig_port_work;
176 
177 	struct work_struct poll_init_work;
178 	bool poll_enabled;
179 
180 	/*
181 	 * Queuing of hotplug_work, reenable_work and poll_init_work is
182 	 * enabled. Protected by drm_i915_private::irq_lock.
183 	 */
184 	bool detection_work_enabled;
185 
186 	unsigned int hpd_storm_threshold;
187 	/* Whether or not to count short HPD IRQs in HPD storms */
188 	u8 hpd_short_storm_enabled;
189 
190 	/* Last state reported by oob_hotplug_event for each encoder */
191 	unsigned long oob_hotplug_last_state;
192 
193 	/*
194 	 * if we get a HPD irq from DP and a HPD irq from non-DP
195 	 * the non-DP HPD could block the workqueue on a mode config
196 	 * mutex getting, that userspace may have taken. However
197 	 * userspace is waiting on the DP workqueue to run which is
198 	 * blocked behind the non-DP one.
199 	 */
200 	struct workqueue_struct *dp_wq;
201 
202 	/*
203 	 * Flag to track if long HPDs need not to be processed
204 	 *
205 	 * Some panels generate long HPDs while keep connected to the port.
206 	 * This can cause issues with CI tests results. In CI systems we
207 	 * don't expect to disconnect the panels and could ignore the long
208 	 * HPDs generated from the faulty panels. This flag can be used as
209 	 * cue to ignore the long HPDs and can be set / unset using debugfs.
210 	 */
211 	bool ignore_long_hpd;
212 };
213 
214 struct intel_vbt_data {
215 	/* bdb version */
216 	u16 version;
217 
218 	/* Feature bits */
219 	unsigned int int_tv_support:1;
220 	unsigned int int_crt_support:1;
221 	unsigned int lvds_use_ssc:1;
222 	unsigned int int_lvds_support:1;
223 	unsigned int display_clock_mode:1;
224 	unsigned int fdi_rx_polarity_inverted:1;
225 	int lvds_ssc_freq;
226 	enum drm_panel_orientation orientation;
227 
228 	bool override_afc_startup;
229 	u8 override_afc_startup_val;
230 
231 	int crt_ddc_pin;
232 
233 	struct list_head display_devices;
234 	struct list_head bdb_blocks;
235 
236 	struct sdvo_device_mapping {
237 		u8 initialized;
238 		u8 dvo_port;
239 		u8 target_addr;
240 		u8 dvo_wiring;
241 		u8 i2c_pin;
242 		u8 ddc_pin;
243 	} sdvo_mappings[2];
244 };
245 
246 struct intel_wm {
247 	/*
248 	 * Raw watermark latency values:
249 	 * in 0.1us units for WM0,
250 	 * in 0.5us units for WM1+.
251 	 */
252 	/* primary */
253 	u16 pri_latency[5];
254 	/* sprite */
255 	u16 spr_latency[5];
256 	/* cursor */
257 	u16 cur_latency[5];
258 	/*
259 	 * Raw watermark memory latency values
260 	 * for SKL for all 8 levels
261 	 * in 1us units.
262 	 */
263 	u16 skl_latency[8];
264 
265 	/* current hardware state */
266 	union {
267 		struct ilk_wm_values hw;
268 		struct vlv_wm_values vlv;
269 		struct g4x_wm_values g4x;
270 	};
271 
272 	u8 num_levels;
273 
274 	/*
275 	 * Should be held around atomic WM register writing; also
276 	 * protects * intel_crtc->wm.active and
277 	 * crtc_state->wm.need_postvbl_update.
278 	 */
279 	struct mutex wm_mutex;
280 
281 	bool ipc_enabled;
282 };
283 
284 struct intel_display {
285 	/* drm device backpointer */
286 	struct drm_device *drm;
287 
288 	/* Platform (and subplatform, if any) identification */
289 	struct intel_display_platforms platform;
290 
291 	/* Display functions */
292 	struct {
293 		/* Top level crtc-ish functions */
294 		const struct intel_display_funcs *display;
295 
296 		/* Display CDCLK functions */
297 		const struct intel_cdclk_funcs *cdclk;
298 
299 		/* Display pll funcs */
300 		const struct intel_dpll_funcs *dpll;
301 
302 		/* irq display functions */
303 		const struct intel_hotplug_funcs *hotplug;
304 
305 		/* pm display functions */
306 		const struct intel_wm_funcs *wm;
307 
308 		/* fdi display functions */
309 		const struct intel_fdi_funcs *fdi;
310 
311 		/* Display internal color functions */
312 		const struct intel_color_funcs *color;
313 
314 		/* Display internal audio functions */
315 		const struct intel_audio_funcs *audio;
316 	} funcs;
317 
318 	struct {
319 		bool any_task_allowed;
320 		struct task_struct *allowed_task;
321 	} access;
322 
323 	struct {
324 		/* backlight registers and fields in struct intel_panel */
325 		struct mutex lock;
326 	} backlight;
327 
328 	struct {
329 		struct intel_global_obj obj;
330 
331 		struct intel_bw_info {
332 			/* for each QGV point */
333 			unsigned int deratedbw[I915_NUM_QGV_POINTS];
334 			/* for each PSF GV point */
335 			unsigned int psf_bw[I915_NUM_PSF_GV_POINTS];
336 			/* Peak BW for each QGV point */
337 			unsigned int peakbw[I915_NUM_QGV_POINTS];
338 			u8 num_qgv_points;
339 			u8 num_psf_gv_points;
340 			u8 num_planes;
341 		} max[6];
342 	} bw;
343 
344 	struct {
345 		/* The current hardware cdclk configuration */
346 		struct intel_cdclk_config hw;
347 
348 		/* cdclk, divider, and ratio table from bspec */
349 		const struct intel_cdclk_vals *table;
350 
351 		struct intel_global_obj obj;
352 
353 		unsigned int max_cdclk_freq;
354 		unsigned int max_dotclk_freq;
355 		unsigned int skl_preferred_vco_freq;
356 	} cdclk;
357 
358 	struct {
359 		struct drm_property_blob *glk_linear_degamma_lut;
360 	} color;
361 
362 	struct {
363 		/* The current hardware dbuf configuration */
364 		u8 enabled_slices;
365 
366 		struct intel_global_obj obj;
367 	} dbuf;
368 
369 	struct {
370 		/*
371 		 * dkl.phy_lock protects against concurrent access of the
372 		 * Dekel TypeC PHYs.
373 		 */
374 		spinlock_t phy_lock;
375 	} dkl;
376 
377 	struct {
378 		struct intel_dmc *dmc;
379 		intel_wakeref_t wakeref;
380 	} dmc;
381 
382 	struct {
383 		/* VLV/CHV/BXT/GLK DSI MMIO register base address */
384 		u32 mmio_base;
385 	} dsi;
386 
387 	struct {
388 		/* list of fbdev register on this device */
389 		struct intel_fbdev *fbdev;
390 	} fbdev;
391 
392 	struct {
393 		unsigned int pll_freq;
394 		u32 rx_config;
395 	} fdi;
396 
397 	struct {
398 		struct list_head obj_list;
399 	} global;
400 
401 	struct {
402 		/*
403 		 * Base address of where the gmbus and gpio blocks are located
404 		 * (either on PCH or on SoC for platforms without PCH).
405 		 */
406 		u32 mmio_base;
407 
408 		/*
409 		 * gmbus.mutex protects against concurrent usage of the single
410 		 * hw gmbus controller on different i2c buses.
411 		 */
412 		struct mutex mutex;
413 
414 		struct intel_gmbus *bus[GMBUS_NUM_PINS];
415 
416 		wait_queue_head_t wait_queue;
417 	} gmbus;
418 
419 	struct {
420 		struct i915_hdcp_arbiter *arbiter;
421 		bool comp_added;
422 
423 		/*
424 		 * HDCP message struct for allocation of memory which can be
425 		 * reused when sending message to gsc cs.
426 		 * this is only populated post Meteorlake
427 		 */
428 		struct intel_hdcp_gsc_message *hdcp_message;
429 		/* Mutex to protect the above hdcp related values. */
430 		struct mutex hdcp_mutex;
431 	} hdcp;
432 
433 	struct {
434 		/*
435 		 * HTI (aka HDPORT) state read during initial hw readout. Most
436 		 * platforms don't have HTI, so this will just stay 0. Those
437 		 * that do will use this later to figure out which PLLs and PHYs
438 		 * are unavailable for driver usage.
439 		 */
440 		u32 state;
441 	} hti;
442 
443 	struct {
444 		/* Access with DISPLAY_INFO() */
445 		const struct intel_display_device_info *__device_info;
446 
447 		/* Access with DISPLAY_RUNTIME_INFO() */
448 		struct intel_display_runtime_info __runtime_info;
449 	} info;
450 
451 	struct {
452 		bool false_color;
453 	} ips;
454 
455 	struct {
456 		/*
457 		 * Most platforms treat the display irq block as an always-on
458 		 * power domain. vlv/chv can disable it at runtime and need
459 		 * special care to avoid writing any of the display block
460 		 * registers outside of the power domain. We defer setting up
461 		 * the display irqs in this case to the runtime pm.
462 		 */
463 		bool vlv_display_irqs_enabled;
464 
465 		/* For i915gm/i945gm vblank irq workaround */
466 		u8 vblank_enabled;
467 
468 		int vblank_wa_num_pipes;
469 
470 		struct work_struct vblank_dc_work;
471 
472 		u32 de_irq_mask[I915_MAX_PIPES];
473 		u32 pipestat_irq_mask[I915_MAX_PIPES];
474 	} irq;
475 
476 	struct {
477 		wait_queue_head_t waitqueue;
478 
479 		/* mutex to protect pmdemand programming sequence */
480 		struct mutex lock;
481 
482 		struct intel_global_obj obj;
483 	} pmdemand;
484 
485 	struct {
486 		struct i915_power_domains domains;
487 
488 		/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
489 		u32 chv_phy_control;
490 
491 		/* perform PHY state sanity checks? */
492 		bool chv_phy_assert[2];
493 	} power;
494 
495 	struct {
496 		u32 mmio_base;
497 
498 		/* protects panel power sequencer state */
499 		struct mutex mutex;
500 	} pps;
501 
502 	struct {
503 		struct drm_property *broadcast_rgb;
504 		struct drm_property *force_audio;
505 	} properties;
506 
507 	struct {
508 		unsigned long mask;
509 	} quirks;
510 
511 	struct {
512 		/* restore state for suspend/resume and display reset */
513 		struct drm_atomic_state *modeset_state;
514 		struct drm_modeset_acquire_ctx reset_ctx;
515 		/* modeset stuck tracking for reset */
516 		atomic_t pending_fb_pin;
517 		u32 saveDSPARB;
518 		u32 saveSWF0[16];
519 		u32 saveSWF1[16];
520 		u32 saveSWF3[3];
521 		u16 saveGCDGMBUS;
522 	} restore;
523 
524 	struct {
525 		enum {
526 			I915_SAGV_UNKNOWN = 0,
527 			I915_SAGV_DISABLED,
528 			I915_SAGV_ENABLED,
529 			I915_SAGV_NOT_CONTROLLED
530 		} status;
531 
532 		u32 block_time_us;
533 	} sagv;
534 
535 	struct {
536 		/*
537 		 * DG2: Mask of PHYs that were not calibrated by the firmware
538 		 * and should not be used.
539 		 */
540 		u8 phy_failed_calibration;
541 	} snps;
542 
543 	struct {
544 		/*
545 		 * Shadows for CHV DPLL_MD regs to keep the state
546 		 * checker somewhat working in the presence hardware
547 		 * crappiness (can't read out DPLL_MD for pipes B & C).
548 		 */
549 		u32 chv_dpll_md[I915_MAX_PIPES];
550 		u32 bxt_phy_grc;
551 	} state;
552 
553 	struct {
554 		/* ordered wq for modesets */
555 		struct workqueue_struct *modeset;
556 
557 		/* unbound hipri wq for page flips/plane updates */
558 		struct workqueue_struct *flip;
559 
560 		/* hipri wq for commit cleanups */
561 		struct workqueue_struct *cleanup;
562 	} wq;
563 
564 	/* Grouping using named structs. Keep sorted. */
565 	struct drm_dp_tunnel_mgr *dp_tunnel_mgr;
566 	struct intel_audio audio;
567 	struct intel_dpll dpll;
568 	struct intel_fbc *fbc[I915_MAX_FBCS];
569 	struct intel_frontbuffer_tracking fb_tracking;
570 	struct intel_hotplug hotplug;
571 	struct intel_opregion *opregion;
572 	struct intel_overlay *overlay;
573 	struct intel_display_params params;
574 	struct intel_vbt_data vbt;
575 	struct intel_dmc_wl wl;
576 	struct intel_wm wm;
577 };
578 
579 #endif /* __INTEL_DISPLAY_CORE_H__ */
580