1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4 */
5
6 #ifndef __MT76_H
7 #define __MT76_H
8
9 #include <linux/kernel.h>
10 #include <linux/io.h>
11 #include <linux/spinlock.h>
12 #include <linux/skbuff.h>
13 #include <linux/leds.h>
14 #include <linux/usb.h>
15 #include <linux/average.h>
16 #include <linux/soc/airoha/airoha_offload.h>
17 #include <linux/soc/mediatek/mtk_wed.h>
18 #include <net/mac80211.h>
19 #include <net/page_pool/helpers.h>
20 #include "util.h"
21 #include "testmode.h"
22
23 #define MT_MCU_RING_SIZE 32
24 #define MT_RX_BUF_SIZE 2048
25 #define MT_SKB_HEAD_LEN 256
26
27 #define MT_MAX_NON_AQL_PKT 16
28 #define MT_TXQ_FREE_THR 32
29
30 #define MT76_TOKEN_FREE_THR 64
31
32 #define MT_QFLAG_WED_RING GENMASK(1, 0)
33 #define MT_QFLAG_WED_TYPE GENMASK(4, 2)
34 #define MT_QFLAG_WED BIT(5)
35 #define MT_QFLAG_WED_RRO BIT(6)
36 #define MT_QFLAG_WED_RRO_EN BIT(7)
37 #define MT_QFLAG_EMI_EN BIT(8)
38 #define MT_QFLAG_NPU BIT(9)
39
40 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \
41 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \
42 FIELD_PREP(MT_QFLAG_WED_RING, _n))
43 #define __MT_WED_RRO_Q(_type, _n) (MT_QFLAG_WED_RRO | __MT_WED_Q(_type, _n))
44
45 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n)
46 #define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n)
47 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0)
48 #define MT_WED_RRO_Q_DATA(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_DATA, _n)
49 #define MT_WED_RRO_Q_MSDU_PG(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_MSDU_PG, _n)
50 #define MT_WED_RRO_Q_IND __MT_WED_RRO_Q(MT76_WED_RRO_Q_IND, 0)
51 #define MT_WED_RRO_Q_RXDMAD_C __MT_WED_RRO_Q(MT76_WED_RRO_Q_RXDMAD_C, 0)
52
53 #define __MT_NPU_Q(_type, _n) (MT_QFLAG_NPU | \
54 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \
55 FIELD_PREP(MT_QFLAG_WED_RING, _n))
56 #define MT_NPU_Q_TX(_n) __MT_NPU_Q(MT76_WED_Q_TX, _n)
57 #define MT_NPU_Q_RX(_n) __MT_NPU_Q(MT76_WED_Q_RX, _n)
58
59 struct mt76_dev;
60 struct mt76_phy;
61 struct mt76_wcid;
62 struct mt76s_intr;
63 struct mt76_chanctx;
64 struct mt76_vif_link;
65
66 struct mt76_reg_pair {
67 u32 reg;
68 u32 value;
69 };
70
71 enum mt76_bus_type {
72 MT76_BUS_MMIO,
73 MT76_BUS_USB,
74 MT76_BUS_SDIO,
75 };
76
77 enum mt76_wed_type {
78 MT76_WED_Q_TX,
79 MT76_WED_Q_TXFREE,
80 MT76_WED_Q_RX,
81 MT76_WED_RRO_Q_DATA,
82 MT76_WED_RRO_Q_MSDU_PG,
83 MT76_WED_RRO_Q_IND,
84 MT76_WED_RRO_Q_RXDMAD_C,
85 };
86
87 enum mt76_hwrro_mode {
88 MT76_HWRRO_OFF,
89 MT76_HWRRO_V3,
90 MT76_HWRRO_V3_1,
91 };
92
93 struct mt76_bus_ops {
94 u32 (*rr)(struct mt76_dev *dev, u32 offset);
95 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val);
96 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val);
97 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data,
98 int len);
99 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data,
100 int len);
101 int (*wr_rp)(struct mt76_dev *dev, u32 base,
102 const struct mt76_reg_pair *rp, int len);
103 int (*rd_rp)(struct mt76_dev *dev, u32 base,
104 struct mt76_reg_pair *rp, int len);
105 enum mt76_bus_type type;
106 };
107
108 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB)
109 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO)
110 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO)
111
112 enum mt76_txq_id {
113 MT_TXQ_VO = IEEE80211_AC_VO,
114 MT_TXQ_VI = IEEE80211_AC_VI,
115 MT_TXQ_BE = IEEE80211_AC_BE,
116 MT_TXQ_BK = IEEE80211_AC_BK,
117 MT_TXQ_PSD,
118 MT_TXQ_BEACON,
119 MT_TXQ_CAB,
120 __MT_TXQ_MAX
121 };
122
123 enum mt76_mcuq_id {
124 MT_MCUQ_WM,
125 MT_MCUQ_WA,
126 MT_MCUQ_FWDL,
127 __MT_MCUQ_MAX
128 };
129
130 enum mt76_rxq_id {
131 MT_RXQ_MAIN,
132 MT_RXQ_MCU,
133 MT_RXQ_MCU_WA,
134 MT_RXQ_BAND1,
135 MT_RXQ_BAND1_WA,
136 MT_RXQ_MAIN_WA,
137 MT_RXQ_BAND2,
138 MT_RXQ_BAND2_WA,
139 MT_RXQ_RRO_BAND0,
140 MT_RXQ_RRO_BAND1,
141 MT_RXQ_RRO_BAND2,
142 MT_RXQ_MSDU_PAGE_BAND0,
143 MT_RXQ_MSDU_PAGE_BAND1,
144 MT_RXQ_MSDU_PAGE_BAND2,
145 MT_RXQ_TXFREE_BAND0,
146 MT_RXQ_TXFREE_BAND1,
147 MT_RXQ_TXFREE_BAND2,
148 MT_RXQ_RRO_IND,
149 MT_RXQ_RRO_RXDMAD_C,
150 MT_RXQ_NPU0,
151 MT_RXQ_NPU1,
152 __MT_RXQ_MAX
153 };
154
155 enum mt76_band_id {
156 MT_BAND0,
157 MT_BAND1,
158 MT_BAND2,
159 __MT_MAX_BAND
160 };
161
162 enum mt76_cipher_type {
163 MT_CIPHER_NONE,
164 MT_CIPHER_WEP40,
165 MT_CIPHER_TKIP,
166 MT_CIPHER_TKIP_NO_MIC,
167 MT_CIPHER_AES_CCMP,
168 MT_CIPHER_WEP104,
169 MT_CIPHER_BIP_CMAC_128,
170 MT_CIPHER_WEP128,
171 MT_CIPHER_WAPI,
172 MT_CIPHER_CCMP_CCX,
173 MT_CIPHER_CCMP_256,
174 MT_CIPHER_GCMP,
175 MT_CIPHER_GCMP_256,
176 };
177
178 enum mt76_dfs_state {
179 MT_DFS_STATE_UNKNOWN,
180 MT_DFS_STATE_DISABLED,
181 MT_DFS_STATE_CAC,
182 MT_DFS_STATE_ACTIVE,
183 };
184
185 #define MT76_RNR_SCAN_MAX_BSSIDS 16
186 struct mt76_scan_rnr_param {
187 u8 bssid[MT76_RNR_SCAN_MAX_BSSIDS][ETH_ALEN];
188 u8 channel[MT76_RNR_SCAN_MAX_BSSIDS];
189 u8 random_mac[ETH_ALEN];
190 u8 seq_num;
191 u8 bssid_num;
192 u32 sreq_flag;
193 };
194
195 struct mt76_queue_buf {
196 dma_addr_t addr;
197 u16 len:15,
198 skip_unmap:1;
199 };
200
201 struct mt76_tx_info {
202 struct mt76_queue_buf buf[32];
203 struct sk_buff *skb;
204 int nbuf;
205 u32 info;
206 };
207
208 struct mt76_queue_entry {
209 union {
210 void *buf;
211 struct sk_buff *skb;
212 };
213 union {
214 struct mt76_txwi_cache *txwi;
215 struct urb *urb;
216 int buf_sz;
217 };
218 dma_addr_t dma_addr[2];
219 u16 dma_len[2];
220 u16 wcid;
221 bool skip_buf0:1;
222 bool skip_buf1:1;
223 bool done:1;
224 };
225
226 struct mt76_queue_regs {
227 u32 desc_base;
228 u32 ring_size;
229 u32 cpu_idx;
230 u32 dma_idx;
231 } __packed __aligned(4);
232
233 struct mt76_queue {
234 struct mt76_queue_regs __iomem *regs;
235
236 spinlock_t lock;
237 spinlock_t cleanup_lock;
238 struct mt76_queue_entry *entry;
239 struct mt76_rro_desc *rro_desc;
240 struct mt76_desc *desc;
241
242 u16 first;
243 u16 head;
244 u16 tail;
245 u8 hw_idx;
246 u8 ep;
247 int ndesc;
248 int queued;
249 int buf_size;
250 bool stopped;
251 bool blocked;
252
253 u8 buf_offset;
254 u16 flags;
255 u8 magic_cnt;
256
257 __le16 *emi_cpu_idx;
258
259 struct mtk_wed_device *wed;
260 struct mt76_dev *dev;
261 u32 wed_regs;
262
263 dma_addr_t desc_dma;
264 struct sk_buff *rx_head;
265 struct page_pool *page_pool;
266 };
267
268 struct mt76_mcu_ops {
269 unsigned int max_retry;
270 u32 headroom;
271 u32 tailroom;
272
273 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data,
274 int len, bool wait_resp);
275 int (*mcu_skb_prepare_msg)(struct mt76_dev *dev, struct sk_buff *skb,
276 int cmd, int *seq);
277 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb,
278 int cmd, int *seq);
279 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd,
280 struct sk_buff *skb, int seq);
281 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset);
282 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val);
283 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base,
284 const struct mt76_reg_pair *rp, int len);
285 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base,
286 struct mt76_reg_pair *rp, int len);
287 int (*mcu_restart)(struct mt76_dev *dev);
288 };
289
290 struct mt76_queue_ops {
291 int (*init)(struct mt76_dev *dev,
292 int (*poll)(struct napi_struct *napi, int budget));
293
294 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q,
295 int idx, int n_desc, int bufsize,
296 u32 ring_base);
297
298 int (*tx_queue_skb)(struct mt76_phy *phy, struct mt76_queue *q,
299 enum mt76_txq_id qid, struct sk_buff *skb,
300 struct mt76_wcid *wcid, struct ieee80211_sta *sta);
301
302 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q,
303 struct sk_buff *skb, u32 tx_info);
304
305 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
306 int *len, u32 *info, bool *more);
307
308 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid);
309
310 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q,
311 bool flush);
312
313 void (*rx_queue_init)(struct mt76_dev *dev, enum mt76_rxq_id qid,
314 int (*poll)(struct napi_struct *napi, int budget));
315
316 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q);
317
318 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q);
319
320 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q,
321 bool reset_idx);
322 };
323
324 enum mt76_phy_type {
325 MT_PHY_TYPE_CCK,
326 MT_PHY_TYPE_OFDM,
327 MT_PHY_TYPE_HT,
328 MT_PHY_TYPE_HT_GF,
329 MT_PHY_TYPE_VHT,
330 MT_PHY_TYPE_HE_SU = 8,
331 MT_PHY_TYPE_HE_EXT_SU,
332 MT_PHY_TYPE_HE_TB,
333 MT_PHY_TYPE_HE_MU,
334 MT_PHY_TYPE_EHT_SU = 13,
335 MT_PHY_TYPE_EHT_TRIG,
336 MT_PHY_TYPE_EHT_MU,
337 __MT_PHY_TYPE_MAX,
338 };
339
340 struct mt76_sta_stats {
341 u64 tx_mode[__MT_PHY_TYPE_MAX];
342 u64 tx_bw[5]; /* 20, 40, 80, 160, 320 */
343 u64 tx_nss[4]; /* 1, 2, 3, 4 */
344 u64 tx_mcs[16]; /* mcs idx */
345 u64 tx_bytes;
346 /* WED TX */
347 u32 tx_packets; /* unit: MSDU */
348 u32 tx_retries;
349 u32 tx_failed;
350 /* WED RX */
351 u64 rx_bytes;
352 u32 rx_packets;
353 u32 rx_errors;
354 u32 rx_drops;
355 };
356
357 enum mt76_wcid_flags {
358 MT_WCID_FLAG_CHECK_PS,
359 MT_WCID_FLAG_PS,
360 MT_WCID_FLAG_4ADDR,
361 MT_WCID_FLAG_HDR_TRANS,
362 };
363
364 #define MT76_N_WCIDS 1088
365
366 /* stored in ieee80211_tx_info::hw_queue */
367 #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2)
368
369 DECLARE_EWMA(signal, 10, 8);
370
371 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0)
372 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16)
373 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18)
374 #define MT_WCID_TX_INFO_SET BIT(31)
375
376 struct mt76_wcid {
377 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS];
378
379 atomic_t non_aql_packets;
380 unsigned long flags;
381
382 struct ewma_signal rssi;
383 int inactive_count;
384
385 struct rate_info rate;
386 unsigned long ampdu_state;
387
388 u16 idx;
389 u8 hw_key_idx;
390 u8 hw_key_idx2;
391
392 u8 offchannel:1;
393 u8 sta:1;
394 u8 sta_disabled:1;
395 u8 amsdu:1;
396 u8 phy_idx:2;
397 u8 link_id:4;
398 bool link_valid;
399
400 u8 rx_check_pn;
401 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6];
402 u16 cipher;
403
404 u32 tx_info;
405 bool sw_iv;
406
407 struct list_head tx_list;
408 struct sk_buff_head tx_pending;
409 struct sk_buff_head tx_offchannel;
410
411 struct list_head list;
412 struct idr pktid;
413
414 struct mt76_sta_stats stats;
415
416 struct list_head poll_list;
417
418 struct mt76_wcid *def_wcid;
419 };
420
421 struct mt76_txq {
422 u16 wcid;
423
424 u16 agg_ssn;
425 bool send_bar;
426 bool aggr;
427 };
428
429 /* data0 */
430 #define RRO_IND_DATA0_IND_REASON_MASK GENMASK(31, 28)
431 #define RRO_IND_DATA0_START_SEQ_MASK GENMASK(27, 16)
432 #define RRO_IND_DATA0_SEQ_ID_MASK GENMASK(11, 0)
433 /* data1 */
434 #define RRO_IND_DATA1_MAGIC_CNT_MASK GENMASK(31, 29)
435 #define RRO_IND_DATA1_IND_COUNT_MASK GENMASK(12, 0)
436 struct mt76_wed_rro_ind {
437 __le32 data0;
438 __le32 data1;
439 };
440
441 struct mt76_txwi_cache {
442 struct list_head list;
443 dma_addr_t dma_addr;
444
445 union {
446 struct sk_buff *skb;
447 void *ptr;
448 };
449
450 u8 qid;
451 };
452
453 struct mt76_rx_tid {
454 struct rcu_head rcu_head;
455
456 struct mt76_dev *dev;
457
458 spinlock_t lock;
459 struct delayed_work reorder_work;
460
461 u16 id;
462 u16 head;
463 u16 size;
464 u16 nframes;
465
466 u8 num;
467
468 u8 started:1, stopped:1, timer_pending:1;
469
470 struct sk_buff *reorder_buf[] __counted_by(size);
471 };
472
473 #define MT_TX_CB_DMA_DONE BIT(0)
474 #define MT_TX_CB_TXS_DONE BIT(1)
475 #define MT_TX_CB_TXS_FAILED BIT(2)
476
477 #define MT_PACKET_ID_MASK GENMASK(6, 0)
478 #define MT_PACKET_ID_NO_ACK 0
479 #define MT_PACKET_ID_NO_SKB 1
480 #define MT_PACKET_ID_WED 2
481 #define MT_PACKET_ID_FIRST 3
482 #define MT_PACKET_ID_HAS_RATE BIT(7)
483 /* This is timer for when to give up when waiting for TXS callback,
484 * with starting time being the time at which the DMA_DONE callback
485 * was seen (so, we know packet was processed then, it should not take
486 * long after that for firmware to send the TXS callback if it is going
487 * to do so.)
488 */
489 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4)
490
491 struct mt76_tx_cb {
492 unsigned long jiffies;
493 u16 wcid;
494 u8 pktid;
495 u8 flags;
496 };
497
498 enum {
499 MT76_STATE_INITIALIZED,
500 MT76_STATE_REGISTERED,
501 MT76_STATE_RUNNING,
502 MT76_STATE_MCU_RUNNING,
503 MT76_SCANNING,
504 MT76_HW_SCANNING,
505 MT76_HW_SCHED_SCANNING,
506 MT76_RESTART,
507 MT76_RESET,
508 MT76_MCU_RESET,
509 MT76_REMOVED,
510 MT76_READING_STATS,
511 MT76_STATE_POWER_OFF,
512 MT76_STATE_SUSPEND,
513 MT76_STATE_ROC,
514 MT76_STATE_PM,
515 MT76_STATE_WED_RESET,
516 };
517
518 enum mt76_sta_event {
519 MT76_STA_EVENT_ASSOC,
520 MT76_STA_EVENT_AUTHORIZE,
521 MT76_STA_EVENT_DISASSOC,
522 };
523
524 struct mt76_hw_cap {
525 bool has_2ghz;
526 bool has_5ghz;
527 bool has_6ghz;
528 };
529
530 #define MT_DRV_TXWI_NO_FREE BIT(0)
531 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1)
532 #define MT_DRV_SW_RX_AIRTIME BIT(2)
533 #define MT_DRV_RX_DMA_HDR BIT(3)
534 #define MT_DRV_HW_MGMT_TXQ BIT(4)
535 #define MT_DRV_AMSDU_OFFLOAD BIT(5)
536 #define MT_DRV_IGNORE_TXS_FAILED BIT(6)
537
538 struct mt76_driver_ops {
539 u32 drv_flags;
540 u32 survey_flags;
541 u16 txwi_size;
542 u16 token_size;
543 u8 mcs_rates;
544
545 unsigned int link_data_size;
546
547 void (*update_survey)(struct mt76_phy *phy);
548 int (*set_channel)(struct mt76_phy *phy);
549
550 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr,
551 enum mt76_txq_id qid, struct mt76_wcid *wcid,
552 struct ieee80211_sta *sta,
553 struct mt76_tx_info *tx_info);
554
555 void (*tx_complete_skb)(struct mt76_dev *dev,
556 struct mt76_queue_entry *e);
557
558 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update);
559
560 bool (*rx_check)(struct mt76_dev *dev, void *data, int len);
561
562 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q,
563 struct sk_buff *skb, u32 *info);
564
565 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q);
566
567 void (*rx_rro_ind_process)(struct mt76_dev *dev, void *data);
568 int (*rx_rro_add_msdu_page)(struct mt76_dev *dev, struct mt76_queue *q,
569 dma_addr_t p, void *data);
570
571 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta,
572 bool ps);
573
574 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif,
575 struct ieee80211_sta *sta);
576
577 int (*sta_event)(struct mt76_dev *dev, struct ieee80211_vif *vif,
578 struct ieee80211_sta *sta, enum mt76_sta_event ev);
579
580 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif,
581 struct ieee80211_sta *sta);
582
583 int (*vif_link_add)(struct mt76_phy *phy, struct ieee80211_vif *vif,
584 struct ieee80211_bss_conf *link_conf,
585 struct mt76_vif_link *mlink);
586
587 void (*vif_link_remove)(struct mt76_phy *phy,
588 struct ieee80211_vif *vif,
589 struct ieee80211_bss_conf *link_conf,
590 struct mt76_vif_link *mlink);
591 };
592
593 struct mt76_channel_state {
594 u64 cc_active;
595 u64 cc_busy;
596 u64 cc_rx;
597 u64 cc_bss_rx;
598 u64 cc_tx;
599
600 s8 noise;
601 };
602
603 struct mt76_sband {
604 struct ieee80211_supported_band sband;
605 struct mt76_channel_state *chan;
606 };
607
608 /* addr req mask */
609 #define MT_VEND_TYPE_EEPROM BIT(31)
610 #define MT_VEND_TYPE_CFG BIT(30)
611 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG)
612
613 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n))
614 enum mt_vendor_req {
615 MT_VEND_DEV_MODE = 0x1,
616 MT_VEND_WRITE = 0x2,
617 MT_VEND_POWER_ON = 0x4,
618 MT_VEND_MULTI_WRITE = 0x6,
619 MT_VEND_MULTI_READ = 0x7,
620 MT_VEND_READ_EEPROM = 0x9,
621 MT_VEND_WRITE_FCE = 0x42,
622 MT_VEND_WRITE_CFG = 0x46,
623 MT_VEND_READ_CFG = 0x47,
624 MT_VEND_READ_EXT = 0x63,
625 MT_VEND_WRITE_EXT = 0x66,
626 MT_VEND_FEATURE_SET = 0x91,
627 };
628
629 enum mt76u_in_ep {
630 MT_EP_IN_PKT_RX,
631 MT_EP_IN_CMD_RESP,
632 __MT_EP_IN_MAX,
633 };
634
635 enum mt76u_out_ep {
636 MT_EP_OUT_INBAND_CMD,
637 MT_EP_OUT_AC_BE,
638 MT_EP_OUT_AC_BK,
639 MT_EP_OUT_AC_VI,
640 MT_EP_OUT_AC_VO,
641 MT_EP_OUT_HCCA,
642 __MT_EP_OUT_MAX,
643 };
644
645 struct mt76_mcu {
646 struct mutex mutex;
647 u32 msg_seq;
648 int timeout;
649
650 struct sk_buff_head res_q;
651 wait_queue_head_t wait;
652 };
653
654 #define MT_TX_SG_MAX_SIZE 8
655 #define MT_RX_SG_MAX_SIZE 4
656 #define MT_NUM_TX_ENTRIES 256
657 #define MT_NUM_RX_ENTRIES 128
658 #define MCU_RESP_URB_SIZE 1024
659 struct mt76_usb {
660 struct mutex usb_ctrl_mtx;
661 u8 *data;
662 u16 data_len;
663
664 struct mt76_worker status_worker;
665 struct mt76_worker rx_worker;
666
667 struct work_struct stat_work;
668
669 u8 out_ep[__MT_EP_OUT_MAX];
670 u8 in_ep[__MT_EP_IN_MAX];
671 bool sg_en;
672
673 struct mt76u_mcu {
674 u8 *data;
675 /* multiple reads */
676 struct mt76_reg_pair *rp;
677 int rp_len;
678 u32 base;
679 } mcu;
680 };
681
682 #define MT76S_XMIT_BUF_SZ 0x3fe00
683 #define MT76S_NUM_TX_ENTRIES 256
684 #define MT76S_NUM_RX_ENTRIES 512
685 struct mt76_sdio {
686 struct mt76_worker txrx_worker;
687 struct mt76_worker status_worker;
688 struct mt76_worker net_worker;
689 struct mt76_worker stat_worker;
690
691 u8 *xmit_buf;
692 u32 xmit_buf_sz;
693
694 struct sdio_func *func;
695 void *intr_data;
696 u8 hw_ver;
697 wait_queue_head_t wait;
698
699 int pse_mcu_quota_max;
700 struct {
701 int pse_data_quota;
702 int ple_data_quota;
703 int pse_mcu_quota;
704 int pse_page_size;
705 int deficit;
706 } sched;
707
708 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr);
709 };
710
711 struct mt76_mmio {
712 void __iomem *regs;
713 spinlock_t irq_lock;
714 u32 irqmask;
715
716 struct mtk_wed_device wed;
717 struct mtk_wed_device wed_hif2;
718 struct completion wed_reset;
719 struct completion wed_reset_complete;
720
721 struct airoha_ppe_dev __rcu *ppe_dev;
722 struct airoha_npu __rcu *npu;
723 phys_addr_t phy_addr;
724 int npu_type;
725 };
726
727 struct mt76_rx_status {
728 union {
729 struct mt76_wcid *wcid;
730 u16 wcid_idx;
731 };
732
733 u32 reorder_time;
734
735 u32 ampdu_ref;
736 u32 timestamp;
737
738 u8 iv[6];
739
740 u8 phy_idx:2;
741 u8 aggr:1;
742 u8 qos_ctl;
743 u16 seqno;
744
745 u16 freq;
746 u32 flag;
747 u8 enc_flags;
748 u8 encoding:3, bw:4;
749 union {
750 struct {
751 u8 he_ru:3;
752 u8 he_gi:2;
753 u8 he_dcm:1;
754 };
755 struct {
756 u8 ru:4;
757 u8 gi:2;
758 } eht;
759 };
760
761 u8 amsdu:1, first_amsdu:1, last_amsdu:1;
762 u8 rate_idx;
763 u8 nss:5, band:3;
764 s8 signal;
765 u8 chains;
766 s8 chain_signal[IEEE80211_MAX_CHAINS];
767 };
768
769 struct mt76_freq_range_power {
770 const struct cfg80211_sar_freq_ranges *range;
771 s8 power;
772 };
773
774 struct mt76_testmode_ops {
775 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state);
776 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb,
777 enum mt76_testmode_state new_state);
778 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg);
779 };
780
781 struct mt76_testmode_data {
782 enum mt76_testmode_state state;
783
784 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)];
785 struct sk_buff *tx_skb;
786
787 u32 tx_count;
788 u16 tx_mpdu_len;
789
790 u8 tx_rate_mode;
791 u8 tx_rate_idx;
792 u8 tx_rate_nss;
793 u8 tx_rate_sgi;
794 u8 tx_rate_ldpc;
795 u8 tx_rate_stbc;
796 u8 tx_ltf;
797
798 u8 tx_antenna_mask;
799 u8 tx_spe_idx;
800
801 u8 tx_duty_cycle;
802 u32 tx_time;
803 u32 tx_ipg;
804
805 u32 freq_offset;
806
807 u8 tx_power[4];
808 u8 tx_power_control;
809
810 u8 addr[3][ETH_ALEN];
811
812 u32 tx_pending;
813 u32 tx_queued;
814 u16 tx_queued_limit;
815 u32 tx_done;
816 struct {
817 u64 packets[__MT_RXQ_MAX];
818 u64 fcs_error[__MT_RXQ_MAX];
819 } rx_stats;
820 };
821
822 struct mt76_vif_link {
823 u8 idx;
824 u8 link_idx;
825 u8 omac_idx;
826 u8 band_idx;
827 u8 wmm_idx;
828 u8 scan_seq_num;
829 u8 cipher;
830 u8 basic_rates_idx;
831 u8 mcast_rates_idx;
832 u8 beacon_rates_idx;
833 bool offchannel;
834 struct ieee80211_chanctx_conf *ctx;
835 struct mt76_wcid *wcid;
836 struct mt76_vif_data *mvif;
837 struct rcu_head rcu_head;
838 };
839
840 struct mt76_vif_data {
841 struct mt76_vif_link __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS];
842 struct mt76_vif_link __rcu *offchannel_link;
843
844 struct mt76_phy *roc_phy;
845 u16 valid_links;
846 u8 deflink_id;
847 };
848
849 struct mt76_phy {
850 struct ieee80211_hw *hw;
851 struct mt76_dev *dev;
852 void *priv;
853
854 unsigned long state;
855 unsigned int num_sta;
856 u8 band_idx;
857
858 spinlock_t tx_lock;
859 struct list_head tx_list;
860 struct mt76_queue *q_tx[__MT_TXQ_MAX];
861
862 struct cfg80211_chan_def chandef;
863 struct cfg80211_chan_def main_chandef;
864 bool offchannel;
865 bool radar_enabled;
866
867 struct delayed_work roc_work;
868 struct ieee80211_vif *roc_vif;
869 struct mt76_vif_link *roc_link;
870
871 struct mt76_chanctx *chanctx;
872
873 struct mt76_channel_state *chan_state;
874 enum mt76_dfs_state dfs_state;
875 ktime_t survey_time;
876
877 u32 aggr_stats[32];
878
879 struct mt76_hw_cap cap;
880 struct mt76_sband sband_2g;
881 struct mt76_sband sband_5g;
882 struct mt76_sband sband_6g;
883
884 u8 macaddr[ETH_ALEN];
885
886 int txpower_cur;
887 u8 antenna_mask;
888 u16 chainmask;
889
890 #ifdef CONFIG_NL80211_TESTMODE
891 struct mt76_testmode_data test;
892 #endif
893
894 struct delayed_work mac_work;
895 u8 mac_work_count;
896
897 struct {
898 struct sk_buff *head;
899 struct sk_buff **tail;
900 u16 seqno;
901 } rx_amsdu[__MT_RXQ_MAX];
902
903 struct mt76_freq_range_power *frp;
904
905 struct {
906 struct led_classdev cdev;
907 char name[32];
908 bool al;
909 u8 pin;
910 } leds;
911 };
912
913 struct mt76_dev {
914 struct mt76_phy phy; /* must be first */
915 struct mt76_phy *phys[__MT_MAX_BAND];
916 struct mt76_phy *band_phys[NUM_NL80211_BANDS];
917
918 struct ieee80211_hw *hw;
919
920 spinlock_t wed_lock;
921 spinlock_t lock;
922 spinlock_t cc_lock;
923
924 u32 cur_cc_bss_rx;
925
926 struct mt76_rx_status rx_ampdu_status;
927 u32 rx_ampdu_len;
928 u32 rx_ampdu_ref;
929
930 struct mutex mutex;
931
932 const struct mt76_bus_ops *bus;
933 const struct mt76_driver_ops *drv;
934 const struct mt76_mcu_ops *mcu_ops;
935 struct device *dev;
936 struct device *dma_dev;
937
938 struct mt76_mcu mcu;
939
940 struct net_device *napi_dev;
941 struct net_device *tx_napi_dev;
942 spinlock_t rx_lock;
943 struct napi_struct napi[__MT_RXQ_MAX];
944 struct sk_buff_head rx_skb[__MT_RXQ_MAX];
945 struct tasklet_struct irq_tasklet;
946
947 struct list_head txwi_cache;
948 struct list_head rxwi_cache;
949 struct mt76_queue *q_mcu[__MT_MCUQ_MAX];
950 struct mt76_queue q_rx[__MT_RXQ_MAX];
951 const struct mt76_queue_ops *queue_ops;
952 int tx_dma_idx[4];
953 enum mt76_hwrro_mode hwrro_mode;
954
955 struct mt76_worker tx_worker;
956 struct napi_struct tx_napi;
957
958 spinlock_t token_lock;
959 struct idr token;
960 u16 wed_token_count;
961 u16 token_count;
962 u16 token_start;
963 u16 token_size;
964
965 spinlock_t rx_token_lock;
966 struct idr rx_token;
967 u16 rx_token_size;
968
969 wait_queue_head_t tx_wait;
970 /* spinclock used to protect wcid pktid linked list */
971 spinlock_t status_lock;
972
973 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)];
974
975 u64 vif_mask;
976
977 struct mt76_wcid global_wcid;
978 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS];
979 struct list_head wcid_list;
980
981 struct list_head sta_poll_list;
982 spinlock_t sta_poll_lock;
983
984 u32 rev;
985
986 struct tasklet_struct pre_tbtt_tasklet;
987 int beacon_int;
988 u8 beacon_mask;
989
990 struct debugfs_blob_wrapper eeprom;
991 struct debugfs_blob_wrapper otp;
992
993 char alpha2[3];
994 enum nl80211_dfs_regions region;
995
996 struct mt76_scan_rnr_param rnr;
997
998 u32 debugfs_reg;
999
1000 u8 csa_complete;
1001
1002 u32 rxfilter;
1003
1004 struct delayed_work scan_work;
1005 struct {
1006 struct cfg80211_scan_request *req;
1007 struct ieee80211_channel *chan;
1008 struct ieee80211_vif *vif;
1009 struct mt76_vif_link *mlink;
1010 struct mt76_phy *phy;
1011 int chan_idx;
1012 } scan;
1013
1014 #ifdef CONFIG_NL80211_TESTMODE
1015 const struct mt76_testmode_ops *test_ops;
1016 struct {
1017 const char *name;
1018 u32 offset;
1019 } test_mtd;
1020 #endif
1021 struct workqueue_struct *wq;
1022
1023 union {
1024 struct mt76_mmio mmio;
1025 struct mt76_usb usb;
1026 struct mt76_sdio sdio;
1027 };
1028
1029 atomic_t bus_hung;
1030 };
1031
1032 /* per-phy stats. */
1033 struct mt76_mib_stats {
1034 u32 ack_fail_cnt;
1035 u32 fcs_err_cnt;
1036 u32 rts_cnt;
1037 u32 rts_retries_cnt;
1038 u32 ba_miss_cnt;
1039 u32 tx_bf_cnt;
1040 u32 tx_mu_bf_cnt;
1041 u32 tx_mu_mpdu_cnt;
1042 u32 tx_mu_acked_mpdu_cnt;
1043 u32 tx_su_acked_mpdu_cnt;
1044 u32 tx_bf_ibf_ppdu_cnt;
1045 u32 tx_bf_ebf_ppdu_cnt;
1046
1047 u32 tx_bf_rx_fb_all_cnt;
1048 u32 tx_bf_rx_fb_eht_cnt;
1049 u32 tx_bf_rx_fb_he_cnt;
1050 u32 tx_bf_rx_fb_vht_cnt;
1051 u32 tx_bf_rx_fb_ht_cnt;
1052
1053 u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */
1054 u32 tx_bf_rx_fb_nc_cnt;
1055 u32 tx_bf_rx_fb_nr_cnt;
1056 u32 tx_bf_fb_cpl_cnt;
1057 u32 tx_bf_fb_trig_cnt;
1058
1059 u32 tx_ampdu_cnt;
1060 u32 tx_stop_q_empty_cnt;
1061 u32 tx_mpdu_attempts_cnt;
1062 u32 tx_mpdu_success_cnt;
1063 u32 tx_pkt_ebf_cnt;
1064 u32 tx_pkt_ibf_cnt;
1065
1066 u32 tx_rwp_fail_cnt;
1067 u32 tx_rwp_need_cnt;
1068
1069 /* rx stats */
1070 u32 rx_fifo_full_cnt;
1071 u32 channel_idle_cnt;
1072 u32 primary_cca_busy_time;
1073 u32 secondary_cca_busy_time;
1074 u32 primary_energy_detect_time;
1075 u32 cck_mdrdy_time;
1076 u32 ofdm_mdrdy_time;
1077 u32 green_mdrdy_time;
1078 u32 rx_vector_mismatch_cnt;
1079 u32 rx_delimiter_fail_cnt;
1080 u32 rx_mrdy_cnt;
1081 u32 rx_len_mismatch_cnt;
1082 u32 rx_mpdu_cnt;
1083 u32 rx_ampdu_cnt;
1084 u32 rx_ampdu_bytes_cnt;
1085 u32 rx_ampdu_valid_subframe_cnt;
1086 u32 rx_ampdu_valid_subframe_bytes_cnt;
1087 u32 rx_pfdrop_cnt;
1088 u32 rx_vec_queue_overflow_drop_cnt;
1089 u32 rx_ba_cnt;
1090
1091 u32 tx_amsdu[8];
1092 u32 tx_amsdu_cnt;
1093
1094 /* mcu_muru_stats */
1095 u32 dl_cck_cnt;
1096 u32 dl_ofdm_cnt;
1097 u32 dl_htmix_cnt;
1098 u32 dl_htgf_cnt;
1099 u32 dl_vht_su_cnt;
1100 u32 dl_vht_2mu_cnt;
1101 u32 dl_vht_3mu_cnt;
1102 u32 dl_vht_4mu_cnt;
1103 u32 dl_he_su_cnt;
1104 u32 dl_he_ext_su_cnt;
1105 u32 dl_he_2ru_cnt;
1106 u32 dl_he_2mu_cnt;
1107 u32 dl_he_3ru_cnt;
1108 u32 dl_he_3mu_cnt;
1109 u32 dl_he_4ru_cnt;
1110 u32 dl_he_4mu_cnt;
1111 u32 dl_he_5to8ru_cnt;
1112 u32 dl_he_9to16ru_cnt;
1113 u32 dl_he_gtr16ru_cnt;
1114
1115 u32 ul_hetrig_su_cnt;
1116 u32 ul_hetrig_2ru_cnt;
1117 u32 ul_hetrig_3ru_cnt;
1118 u32 ul_hetrig_4ru_cnt;
1119 u32 ul_hetrig_5to8ru_cnt;
1120 u32 ul_hetrig_9to16ru_cnt;
1121 u32 ul_hetrig_gtr16ru_cnt;
1122 u32 ul_hetrig_2mu_cnt;
1123 u32 ul_hetrig_3mu_cnt;
1124 u32 ul_hetrig_4mu_cnt;
1125 };
1126
1127 struct mt76_power_limits {
1128 s8 cck[4];
1129 s8 ofdm[8];
1130 s8 mcs[4][10];
1131 s8 ru[7][12];
1132 s8 eht[16][16];
1133
1134 struct {
1135 s8 cck[4];
1136 s8 ofdm[4];
1137 s8 ofdm_bf[4];
1138 s8 ru[7][10];
1139 s8 ru_bf[7][10];
1140 } path;
1141 };
1142
1143 struct mt76_ethtool_worker_info {
1144 u64 *data;
1145 int idx;
1146 int initial_stat_idx;
1147 int worker_stat_count;
1148 int sta_count;
1149 };
1150
1151 struct mt76_chanctx {
1152 struct mt76_phy *phy;
1153 };
1154
1155 #define CCK_RATE(_idx, _rate) { \
1156 .bitrate = _rate, \
1157 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \
1158 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \
1159 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \
1160 }
1161
1162 #define OFDM_RATE(_idx, _rate) { \
1163 .bitrate = _rate, \
1164 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
1165 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
1166 }
1167
1168 extern struct ieee80211_rate mt76_rates[12];
1169
1170 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__)
1171 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__)
1172 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__)
1173 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__)
1174 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__)
1175
1176 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val)
1177 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0)
1178
1179 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__)
1180 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__)
1181 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__)
1182 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__)
1183 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__)
1184 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__)
1185 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__)
1186
1187
1188 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76))
1189
1190 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val)
1191 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0)
1192
1193 #define mt76_get_field(_dev, _reg, _field) \
1194 FIELD_GET(_field, mt76_rr(dev, _reg))
1195
1196 #define mt76_rmw_field(_dev, _reg, _field, _val) \
1197 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
1198
1199 #define __mt76_rmw_field(_dev, _reg, _field, _val) \
1200 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
1201
1202 #define mt76_hw(dev) (dev)->mphy.hw
1203
1204 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
1205 int timeout);
1206
1207 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__)
1208
1209 bool ____mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
1210 int timeout, int kick);
1211 #define __mt76_poll_msec(...) ____mt76_poll_msec(__VA_ARGS__, 10)
1212 #define mt76_poll_msec(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__, 10)
1213 #define mt76_poll_msec_tick(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__)
1214
1215 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs);
1216 void mt76_pci_disable_aspm(struct pci_dev *pdev);
1217 bool mt76_pci_aspm_supported(struct pci_dev *pdev);
1218
mt76_chip(struct mt76_dev * dev)1219 static inline u16 mt76_chip(struct mt76_dev *dev)
1220 {
1221 return dev->rev >> 16;
1222 }
1223
mt76_rev(struct mt76_dev * dev)1224 static inline u16 mt76_rev(struct mt76_dev *dev)
1225 {
1226 return dev->rev & 0xffff;
1227 }
1228
1229 void mt76_wed_release_rx_buf(struct mtk_wed_device *wed);
1230 void mt76_wed_offload_disable(struct mtk_wed_device *wed);
1231 void mt76_wed_reset_complete(struct mtk_wed_device *wed);
1232 void mt76_wed_dma_reset(struct mt76_dev *dev);
1233 int mt76_wed_net_setup_tc(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1234 struct net_device *netdev, enum tc_setup_type type,
1235 void *type_data);
1236 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
1237 u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size);
1238 int mt76_wed_offload_enable(struct mtk_wed_device *wed);
1239 int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset);
1240 #else
mt76_wed_init_rx_buf(struct mtk_wed_device * wed,int size)1241 static inline u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size)
1242 {
1243 return 0;
1244 }
1245
mt76_wed_offload_enable(struct mtk_wed_device * wed)1246 static inline int mt76_wed_offload_enable(struct mtk_wed_device *wed)
1247 {
1248 return 0;
1249 }
1250
mt76_wed_dma_setup(struct mt76_dev * dev,struct mt76_queue * q,bool reset)1251 static inline int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q,
1252 bool reset)
1253 {
1254 return 0;
1255 }
1256 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */
1257
1258 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76))
1259 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76))
1260
1261 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__)
1262 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__)
1263 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__)
1264 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mphy), __VA_ARGS__)
1265 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__)
1266 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__)
1267 #define mt76_queue_rx_init(dev, ...) (dev)->mt76.queue_ops->rx_queue_init(&((dev)->mt76), __VA_ARGS__)
1268 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__)
1269 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__)
1270 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__)
1271
1272 #define mt76_for_each_q_rx(dev, i) \
1273 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \
1274 if ((dev)->q_rx[i].ndesc)
1275
1276
1277 #define mt76_dereference(p, dev) \
1278 rcu_dereference_protected(p, lockdep_is_held(&(dev)->mutex))
1279
mt76_wed_to_dev(struct mtk_wed_device * wed)1280 static inline struct mt76_dev *mt76_wed_to_dev(struct mtk_wed_device *wed)
1281 {
1282 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
1283 if (wed->wlan.hif2)
1284 return container_of(wed, struct mt76_dev, mmio.wed_hif2);
1285 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */
1286 return container_of(wed, struct mt76_dev, mmio.wed);
1287 }
1288
1289 static inline struct mt76_wcid *
__mt76_wcid_ptr(struct mt76_dev * dev,u16 idx)1290 __mt76_wcid_ptr(struct mt76_dev *dev, u16 idx)
1291 {
1292 if (idx >= ARRAY_SIZE(dev->wcid))
1293 return NULL;
1294 return rcu_dereference(dev->wcid[idx]);
1295 }
1296
1297 #define mt76_wcid_ptr(dev, idx) __mt76_wcid_ptr(&(dev)->mt76, idx)
1298
1299 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size,
1300 const struct ieee80211_ops *ops,
1301 const struct mt76_driver_ops *drv_ops);
1302 int mt76_register_device(struct mt76_dev *dev, bool vht,
1303 struct ieee80211_rate *rates, int n_rates);
1304 void mt76_unregister_device(struct mt76_dev *dev);
1305 void mt76_free_device(struct mt76_dev *dev);
1306 void mt76_reset_device(struct mt76_dev *dev);
1307 void mt76_unregister_phy(struct mt76_phy *phy);
1308
1309 struct mt76_phy *mt76_alloc_radio_phy(struct mt76_dev *dev, unsigned int size,
1310 u8 band_idx);
1311 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size,
1312 const struct ieee80211_ops *ops,
1313 u8 band_idx);
1314 int mt76_register_phy(struct mt76_phy *phy, bool vht,
1315 struct ieee80211_rate *rates, int n_rates);
1316 struct mt76_phy *mt76_vif_phy(struct ieee80211_hw *hw,
1317 struct ieee80211_vif *vif);
1318
1319 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy,
1320 const struct file_operations *ops);
mt76_register_debugfs(struct mt76_dev * dev)1321 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev)
1322 {
1323 return mt76_register_debugfs_fops(&dev->phy, NULL);
1324 }
1325
1326 int mt76_queues_read(struct seq_file *s, void *data);
1327 void mt76_seq_puts_array(struct seq_file *file, const char *str,
1328 s8 *val, int len);
1329
1330 int mt76_eeprom_init(struct mt76_dev *dev, int len);
1331 int mt76_eeprom_override(struct mt76_phy *phy);
1332 int mt76_get_of_data_from_mtd(struct mt76_dev *dev, void *eep, int offset, int len);
1333 int mt76_get_of_data_from_nvmem(struct mt76_dev *dev, void *eep,
1334 const char *cell_name, int len);
1335
1336 struct mt76_queue *
1337 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc,
1338 int ring_base, void *wed, u32 flags);
mt76_init_tx_queue(struct mt76_phy * phy,int qid,int idx,int n_desc,int ring_base,void * wed,u32 flags)1339 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx,
1340 int n_desc, int ring_base, void *wed,
1341 u32 flags)
1342 {
1343 struct mt76_queue *q;
1344
1345 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, wed, flags);
1346 if (IS_ERR(q))
1347 return PTR_ERR(q);
1348
1349 phy->q_tx[qid] = q;
1350
1351 return 0;
1352 }
1353
mt76_init_mcu_queue(struct mt76_dev * dev,int qid,int idx,int n_desc,int ring_base)1354 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx,
1355 int n_desc, int ring_base)
1356 {
1357 struct mt76_queue *q;
1358
1359 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, NULL, 0);
1360 if (IS_ERR(q))
1361 return PTR_ERR(q);
1362
1363 dev->q_mcu[qid] = q;
1364
1365 return 0;
1366 }
1367
1368 static inline struct mt76_phy *
mt76_dev_phy(struct mt76_dev * dev,u8 phy_idx)1369 mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx)
1370 {
1371 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) ||
1372 (phy_idx == MT_BAND2 && dev->phys[phy_idx]))
1373 return dev->phys[phy_idx];
1374
1375 return &dev->phy;
1376 }
1377
1378 static inline struct ieee80211_hw *
mt76_phy_hw(struct mt76_dev * dev,u8 phy_idx)1379 mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx)
1380 {
1381 return mt76_dev_phy(dev, phy_idx)->hw;
1382 }
1383
1384 static inline u8 *
mt76_get_txwi_ptr(struct mt76_dev * dev,struct mt76_txwi_cache * t)1385 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t)
1386 {
1387 return (u8 *)t - dev->drv->txwi_size;
1388 }
1389
1390 /* increment with wrap-around */
mt76_incr(int val,int size)1391 static inline int mt76_incr(int val, int size)
1392 {
1393 return (val + 1) & (size - 1);
1394 }
1395
1396 /* decrement with wrap-around */
mt76_decr(int val,int size)1397 static inline int mt76_decr(int val, int size)
1398 {
1399 return (val - 1) & (size - 1);
1400 }
1401
1402 u8 mt76_ac_to_hwq(u8 ac);
1403
1404 static inline struct ieee80211_txq *
mtxq_to_txq(struct mt76_txq * mtxq)1405 mtxq_to_txq(struct mt76_txq *mtxq)
1406 {
1407 void *ptr = mtxq;
1408
1409 return container_of(ptr, struct ieee80211_txq, drv_priv);
1410 }
1411
1412 static inline struct ieee80211_sta *
wcid_to_sta(struct mt76_wcid * wcid)1413 wcid_to_sta(struct mt76_wcid *wcid)
1414 {
1415 void *ptr = wcid;
1416
1417 if (!wcid || !wcid->sta)
1418 return NULL;
1419
1420 if (wcid->def_wcid)
1421 ptr = wcid->def_wcid;
1422
1423 return container_of(ptr, struct ieee80211_sta, drv_priv);
1424 }
1425
mt76_tx_skb_cb(struct sk_buff * skb)1426 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb)
1427 {
1428 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) >
1429 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data));
1430 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data);
1431 }
1432
mt76_skb_get_hdr(struct sk_buff * skb)1433 static inline void *mt76_skb_get_hdr(struct sk_buff *skb)
1434 {
1435 struct mt76_rx_status mstat;
1436 u8 *data = skb->data;
1437
1438 /* Alignment concerns */
1439 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4);
1440 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4);
1441
1442 mstat = *((struct mt76_rx_status *)skb->cb);
1443
1444 if (mstat.flag & RX_FLAG_RADIOTAP_HE)
1445 data += sizeof(struct ieee80211_radiotap_he);
1446 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU)
1447 data += sizeof(struct ieee80211_radiotap_he_mu);
1448
1449 return data;
1450 }
1451
mt76_insert_hdr_pad(struct sk_buff * skb)1452 static inline void mt76_insert_hdr_pad(struct sk_buff *skb)
1453 {
1454 int len = ieee80211_get_hdrlen_from_skb(skb);
1455
1456 if (len % 4 == 0)
1457 return;
1458
1459 skb_push(skb, 2);
1460 memmove(skb->data, skb->data + 2, len);
1461
1462 skb->data[len] = 0;
1463 skb->data[len + 1] = 0;
1464 }
1465
mt76_is_skb_pktid(u8 pktid)1466 static inline bool mt76_is_skb_pktid(u8 pktid)
1467 {
1468 if (pktid & MT_PACKET_ID_HAS_RATE)
1469 return false;
1470
1471 return pktid >= MT_PACKET_ID_FIRST;
1472 }
1473
mt76_tx_power_path_delta(u8 path)1474 static inline u8 mt76_tx_power_path_delta(u8 path)
1475 {
1476 static const u8 path_delta[5] = { 0, 6, 9, 12, 14 };
1477 u8 idx = path - 1;
1478
1479 return (idx < ARRAY_SIZE(path_delta)) ? path_delta[idx] : 0;
1480 }
1481
mt76_testmode_enabled(struct mt76_phy * phy)1482 static inline bool mt76_testmode_enabled(struct mt76_phy *phy)
1483 {
1484 #ifdef CONFIG_NL80211_TESTMODE
1485 return phy->test.state != MT76_TM_STATE_OFF;
1486 #else
1487 return false;
1488 #endif
1489 }
1490
mt76_is_testmode_skb(struct mt76_dev * dev,struct sk_buff * skb,struct ieee80211_hw ** hw)1491 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev,
1492 struct sk_buff *skb,
1493 struct ieee80211_hw **hw)
1494 {
1495 #ifdef CONFIG_NL80211_TESTMODE
1496 int i;
1497
1498 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) {
1499 struct mt76_phy *phy = dev->phys[i];
1500
1501 if (phy && skb == phy->test.tx_skb) {
1502 *hw = dev->phys[i]->hw;
1503 return true;
1504 }
1505 }
1506 return false;
1507 #else
1508 return false;
1509 #endif
1510 }
1511
1512 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb);
1513 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta,
1514 struct mt76_wcid *wcid, struct sk_buff *skb);
1515 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq);
1516 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta,
1517 bool send_bar);
1518 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb);
1519 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid);
1520 void mt76_txq_schedule_all(struct mt76_phy *phy);
1521 void mt76_tx_worker_run(struct mt76_dev *dev);
1522 void mt76_tx_worker(struct mt76_worker *w);
1523 void mt76_release_buffered_frames(struct ieee80211_hw *hw,
1524 struct ieee80211_sta *sta,
1525 u16 tids, int nframes,
1526 enum ieee80211_frame_release_type reason,
1527 bool more_data);
1528 bool mt76_has_tx_pending(struct mt76_phy *phy);
1529 int mt76_update_channel(struct mt76_phy *phy);
1530 void mt76_update_survey(struct mt76_phy *phy);
1531 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time);
1532 int mt76_get_survey(struct ieee80211_hw *hw, int idx,
1533 struct survey_info *survey);
1534 int mt76_rx_signal(u8 chain_mask, s8 *chain_signal);
1535 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht);
1536
1537 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid,
1538 u16 ssn, u16 size);
1539 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid);
1540
1541 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid,
1542 struct ieee80211_key_conf *key);
1543
1544 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list)
1545 __acquires(&dev->status_lock);
1546 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list)
1547 __releases(&dev->status_lock);
1548
1549 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid,
1550 struct sk_buff *skb);
1551 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev,
1552 struct mt76_wcid *wcid, int pktid,
1553 struct sk_buff_head *list);
1554 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb,
1555 struct sk_buff_head *list);
1556 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb,
1557 struct list_head *free_list);
1558 static inline void
mt76_tx_complete_skb(struct mt76_dev * dev,u16 wcid,struct sk_buff * skb)1559 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb)
1560 {
1561 __mt76_tx_complete_skb(dev, wcid, skb, NULL);
1562 }
1563
1564 void mt76_tx_status_check(struct mt76_dev *dev, bool flush);
1565 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1566 struct ieee80211_sta *sta,
1567 enum ieee80211_sta_state old_state,
1568 enum ieee80211_sta_state new_state);
1569 void __mt76_sta_remove(struct mt76_phy *phy, struct ieee80211_vif *vif,
1570 struct ieee80211_sta *sta);
1571 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1572 struct ieee80211_sta *sta);
1573
1574 int mt76_get_min_avg_rssi(struct mt76_dev *dev, u8 phy_idx);
1575
1576 s8 mt76_get_power_bound(struct mt76_phy *phy, s8 txpower);
1577
1578 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1579 unsigned int link_id, int *dbm);
1580 int mt76_init_sar_power(struct ieee80211_hw *hw,
1581 const struct cfg80211_sar_specs *sar);
1582 int mt76_get_sar_power(struct mt76_phy *phy,
1583 struct ieee80211_channel *chan,
1584 int power);
1585
1586 void mt76_csa_check(struct mt76_dev *dev);
1587 void mt76_csa_finish(struct mt76_dev *dev);
1588
1589 int mt76_get_antenna(struct ieee80211_hw *hw, int radio_idx, u32 *tx_ant,
1590 u32 *rx_ant);
1591 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set);
1592 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id);
1593 int mt76_get_rate(struct mt76_dev *dev,
1594 struct ieee80211_supported_band *sband,
1595 int idx, bool cck);
1596 int mt76_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1597 struct ieee80211_scan_request *hw_req);
1598 void mt76_cancel_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1599 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1600 const u8 *mac);
1601 void mt76_sw_scan_complete(struct ieee80211_hw *hw,
1602 struct ieee80211_vif *vif);
1603 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy);
1604 int mt76_add_chanctx(struct ieee80211_hw *hw,
1605 struct ieee80211_chanctx_conf *conf);
1606 void mt76_remove_chanctx(struct ieee80211_hw *hw,
1607 struct ieee80211_chanctx_conf *conf);
1608 void mt76_change_chanctx(struct ieee80211_hw *hw,
1609 struct ieee80211_chanctx_conf *conf,
1610 u32 changed);
1611 int mt76_assign_vif_chanctx(struct ieee80211_hw *hw,
1612 struct ieee80211_vif *vif,
1613 struct ieee80211_bss_conf *link_conf,
1614 struct ieee80211_chanctx_conf *conf);
1615 void mt76_unassign_vif_chanctx(struct ieee80211_hw *hw,
1616 struct ieee80211_vif *vif,
1617 struct ieee80211_bss_conf *link_conf,
1618 struct ieee80211_chanctx_conf *conf);
1619 int mt76_switch_vif_chanctx(struct ieee80211_hw *hw,
1620 struct ieee80211_vif_chanctx_switch *vifs,
1621 int n_vifs,
1622 enum ieee80211_chanctx_switch_mode mode);
1623 int mt76_remain_on_channel(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1624 struct ieee80211_channel *chan, int duration,
1625 enum ieee80211_roc_type type);
1626 int mt76_cancel_remain_on_channel(struct ieee80211_hw *hw,
1627 struct ieee80211_vif *vif);
1628 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1629 void *data, int len);
1630 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb,
1631 struct netlink_callback *cb, void *data, int len);
1632 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state);
1633 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len);
1634
1635 #ifdef CONFIG_MT76_NPU
1636 void mt76_npu_check_ppe(struct mt76_dev *dev, struct sk_buff *skb,
1637 u32 info);
1638 int mt76_npu_dma_add_buf(struct mt76_phy *phy, struct mt76_queue *q,
1639 struct sk_buff *skb, struct mt76_queue_buf *buf,
1640 void *txwi_ptr);
1641 int mt76_npu_rx_queue_init(struct mt76_dev *dev, struct mt76_queue *q);
1642 int mt76_npu_fill_rx_queue(struct mt76_dev *dev, struct mt76_queue *q);
1643 void mt76_npu_queue_cleanup(struct mt76_dev *dev, struct mt76_queue *q);
1644 void mt76_npu_disable_irqs(struct mt76_dev *dev);
1645 int mt76_npu_init(struct mt76_dev *dev, phys_addr_t phy_addr, int type);
1646 void mt76_npu_deinit(struct mt76_dev *dev);
1647 void mt76_npu_queue_setup(struct mt76_dev *dev, struct mt76_queue *q);
1648 void mt76_npu_txdesc_cleanup(struct mt76_queue *q, int index);
1649 int mt76_npu_net_setup_tc(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1650 struct net_device *dev, enum tc_setup_type type,
1651 void *type_data);
1652 #else
mt76_npu_check_ppe(struct mt76_dev * dev,struct sk_buff * skb,u32 info)1653 static inline void mt76_npu_check_ppe(struct mt76_dev *dev,
1654 struct sk_buff *skb, u32 info)
1655 {
1656 }
1657
mt76_npu_dma_add_buf(struct mt76_phy * phy,struct mt76_queue * q,struct sk_buff * skb,struct mt76_queue_buf * buf,void * txwi_ptr)1658 static inline int mt76_npu_dma_add_buf(struct mt76_phy *phy,
1659 struct mt76_queue *q,
1660 struct sk_buff *skb,
1661 struct mt76_queue_buf *buf,
1662 void *txwi_ptr)
1663 {
1664 return -EOPNOTSUPP;
1665 }
1666
mt76_npu_fill_rx_queue(struct mt76_dev * dev,struct mt76_queue * q)1667 static inline int mt76_npu_fill_rx_queue(struct mt76_dev *dev,
1668 struct mt76_queue *q)
1669 {
1670 return 0;
1671 }
1672
mt76_npu_queue_cleanup(struct mt76_dev * dev,struct mt76_queue * q)1673 static inline void mt76_npu_queue_cleanup(struct mt76_dev *dev,
1674 struct mt76_queue *q)
1675 {
1676 }
1677
mt76_npu_disable_irqs(struct mt76_dev * dev)1678 static inline void mt76_npu_disable_irqs(struct mt76_dev *dev)
1679 {
1680 }
1681
mt76_npu_init(struct mt76_dev * dev,phys_addr_t phy_addr,int type)1682 static inline int mt76_npu_init(struct mt76_dev *dev, phys_addr_t phy_addr,
1683 int type)
1684 {
1685 return 0;
1686 }
1687
mt76_npu_deinit(struct mt76_dev * dev)1688 static inline void mt76_npu_deinit(struct mt76_dev *dev)
1689 {
1690 }
1691
mt76_npu_queue_setup(struct mt76_dev * dev,struct mt76_queue * q)1692 static inline void mt76_npu_queue_setup(struct mt76_dev *dev,
1693 struct mt76_queue *q)
1694 {
1695 }
1696
mt76_npu_txdesc_cleanup(struct mt76_queue * q,int index)1697 static inline void mt76_npu_txdesc_cleanup(struct mt76_queue *q,
1698 int index)
1699 {
1700 }
1701
mt76_npu_net_setup_tc(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct net_device * dev,enum tc_setup_type type,void * type_data)1702 static inline int mt76_npu_net_setup_tc(struct ieee80211_hw *hw,
1703 struct ieee80211_vif *vif,
1704 struct net_device *dev,
1705 enum tc_setup_type type,
1706 void *type_data)
1707 {
1708 return -EOPNOTSUPP;
1709 }
1710 #endif /* CONFIG_MT76_NPU */
1711
mt76_npu_device_active(struct mt76_dev * dev)1712 static inline bool mt76_npu_device_active(struct mt76_dev *dev)
1713 {
1714 return !!rcu_access_pointer(dev->mmio.npu);
1715 }
1716
mt76_ppe_device_active(struct mt76_dev * dev)1717 static inline bool mt76_ppe_device_active(struct mt76_dev *dev)
1718 {
1719 return !!rcu_access_pointer(dev->mmio.ppe_dev);
1720 }
1721
mt76_npu_send_msg(struct airoha_npu * npu,int ifindex,enum airoha_npu_wlan_set_cmd cmd,u32 val,gfp_t gfp)1722 static inline int mt76_npu_send_msg(struct airoha_npu *npu, int ifindex,
1723 enum airoha_npu_wlan_set_cmd cmd,
1724 u32 val, gfp_t gfp)
1725 {
1726 return airoha_npu_wlan_send_msg(npu, ifindex, cmd, &val, sizeof(val),
1727 gfp);
1728 }
1729
mt76_npu_get_msg(struct airoha_npu * npu,int ifindex,enum airoha_npu_wlan_get_cmd cmd,u32 * val,gfp_t gfp)1730 static inline int mt76_npu_get_msg(struct airoha_npu *npu, int ifindex,
1731 enum airoha_npu_wlan_get_cmd cmd,
1732 u32 *val, gfp_t gfp)
1733 {
1734 return airoha_npu_wlan_get_msg(npu, ifindex, cmd, val, sizeof(*val),
1735 gfp);
1736 }
1737
mt76_testmode_reset(struct mt76_phy * phy,bool disable)1738 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable)
1739 {
1740 #ifdef CONFIG_NL80211_TESTMODE
1741 enum mt76_testmode_state state = MT76_TM_STATE_IDLE;
1742
1743 if (disable || phy->test.state == MT76_TM_STATE_OFF)
1744 state = MT76_TM_STATE_OFF;
1745
1746 mt76_testmode_set_state(phy, state);
1747 #endif
1748 }
1749
1750
1751 /* internal */
1752 static inline struct ieee80211_hw *
mt76_tx_status_get_hw(struct mt76_dev * dev,struct sk_buff * skb)1753 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb)
1754 {
1755 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1756 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2;
1757 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx);
1758
1759 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY;
1760
1761 return hw;
1762 }
1763
1764 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
1765 void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
1766 struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev);
1767 void mt76_free_pending_rxwi(struct mt76_dev *dev);
1768 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames,
1769 struct napi_struct *napi);
1770 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
1771 struct napi_struct *napi);
1772 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames);
1773 void mt76_testmode_tx_pending(struct mt76_phy *phy);
1774 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q,
1775 struct mt76_queue_entry *e);
1776 int __mt76_set_channel(struct mt76_phy *phy, struct cfg80211_chan_def *chandef,
1777 bool offchannel);
1778 int mt76_set_channel(struct mt76_phy *phy, struct cfg80211_chan_def *chandef,
1779 bool offchannel);
1780 void mt76_scan_work(struct work_struct *work);
1781 void mt76_abort_scan(struct mt76_dev *dev);
1782 void mt76_roc_complete_work(struct work_struct *work);
1783 void mt76_roc_complete(struct mt76_phy *phy);
1784 void mt76_abort_roc(struct mt76_phy *phy);
1785 struct mt76_vif_link *mt76_get_vif_phy_link(struct mt76_phy *phy,
1786 struct ieee80211_vif *vif);
1787 void mt76_put_vif_phy_link(struct mt76_phy *phy, struct ieee80211_vif *vif,
1788 struct mt76_vif_link *mlink);
1789
1790 /* usb */
mt76u_urb_error(struct urb * urb)1791 static inline bool mt76u_urb_error(struct urb *urb)
1792 {
1793 return urb->status &&
1794 urb->status != -ECONNRESET &&
1795 urb->status != -ESHUTDOWN &&
1796 urb->status != -ENOENT;
1797 }
1798
1799 static inline int
mt76u_bulk_msg(struct mt76_dev * dev,void * data,int len,int * actual_len,int timeout,int ep)1800 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len,
1801 int timeout, int ep)
1802 {
1803 struct usb_interface *uintf = to_usb_interface(dev->dev);
1804 struct usb_device *udev = interface_to_usbdev(uintf);
1805 struct mt76_usb *usb = &dev->usb;
1806 unsigned int pipe;
1807
1808 if (actual_len)
1809 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]);
1810 else
1811 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]);
1812
1813 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout);
1814 }
1815
1816 void mt76_ethtool_page_pool_stats(struct mt76_dev *dev, u64 *data, int *index);
1817 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi,
1818 struct mt76_sta_stats *stats, bool eht);
1819 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad);
1820 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type,
1821 u16 val, u16 offset, void *buf, size_t len);
1822 int mt76u_vendor_request(struct mt76_dev *dev, u8 req,
1823 u8 req_type, u16 val, u16 offset,
1824 void *buf, size_t len);
1825 void mt76u_single_wr(struct mt76_dev *dev, const u8 req,
1826 const u16 offset, const u32 val);
1827 void mt76u_read_copy(struct mt76_dev *dev, u32 offset,
1828 void *data, int len);
1829 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr);
1830 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type,
1831 u32 addr, u32 val);
1832 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf,
1833 struct mt76_bus_ops *ops);
1834 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf);
1835 int mt76u_alloc_mcu_queue(struct mt76_dev *dev);
1836 int mt76u_alloc_queues(struct mt76_dev *dev);
1837 void mt76u_stop_tx(struct mt76_dev *dev);
1838 void mt76u_stop_rx(struct mt76_dev *dev);
1839 int mt76u_resume_rx(struct mt76_dev *dev);
1840 void mt76u_queues_deinit(struct mt76_dev *dev);
1841
1842 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func,
1843 const struct mt76_bus_ops *bus_ops);
1844 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid);
1845 int mt76s_alloc_tx(struct mt76_dev *dev);
1846 void mt76s_deinit(struct mt76_dev *dev);
1847 void mt76s_sdio_irq(struct sdio_func *func);
1848 void mt76s_txrx_worker(struct mt76_sdio *sdio);
1849 bool mt76s_txqs_empty(struct mt76_dev *dev);
1850 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func,
1851 int hw_ver);
1852 u32 mt76s_rr(struct mt76_dev *dev, u32 offset);
1853 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val);
1854 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val);
1855 u32 mt76s_read_pcr(struct mt76_dev *dev);
1856 void mt76s_write_copy(struct mt76_dev *dev, u32 offset,
1857 const void *data, int len);
1858 void mt76s_read_copy(struct mt76_dev *dev, u32 offset,
1859 void *data, int len);
1860 int mt76s_wr_rp(struct mt76_dev *dev, u32 base,
1861 const struct mt76_reg_pair *data,
1862 int len);
1863 int mt76s_rd_rp(struct mt76_dev *dev, u32 base,
1864 struct mt76_reg_pair *data, int len);
1865
1866 struct sk_buff *
1867 __mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data,
1868 int len, int data_len, gfp_t gfp);
1869 static inline struct sk_buff *
mt76_mcu_msg_alloc(struct mt76_dev * dev,const void * data,int data_len)1870 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data,
1871 int data_len)
1872 {
1873 return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL);
1874 }
1875
1876 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb);
1877 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev,
1878 unsigned long expires);
1879 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data,
1880 int len, bool wait_resp, struct sk_buff **ret);
1881 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb,
1882 int cmd, bool wait_resp, struct sk_buff **ret);
1883 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data,
1884 int len, int max_len);
1885 static inline int
mt76_mcu_send_firmware(struct mt76_dev * dev,int cmd,const void * data,int len)1886 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data,
1887 int len)
1888 {
1889 int max_len = 4096 - dev->mcu_ops->headroom;
1890
1891 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len);
1892 }
1893
1894 static inline int
mt76_mcu_send_msg(struct mt76_dev * dev,int cmd,const void * data,int len,bool wait_resp)1895 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len,
1896 bool wait_resp)
1897 {
1898 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL);
1899 }
1900
1901 static inline int
mt76_mcu_skb_send_msg(struct mt76_dev * dev,struct sk_buff * skb,int cmd,bool wait_resp)1902 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd,
1903 bool wait_resp)
1904 {
1905 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL);
1906 }
1907
1908 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set);
1909
1910 struct device_node *
1911 mt76_find_power_limits_node(struct mt76_dev *dev);
1912 struct device_node *
1913 mt76_find_channel_node(struct device_node *np, struct ieee80211_channel *chan);
1914
1915 s8 mt76_get_rate_power_limits(struct mt76_phy *phy,
1916 struct ieee80211_channel *chan,
1917 struct mt76_power_limits *dest,
1918 s8 target_power);
1919
mt76_queue_is_rx(struct mt76_dev * dev,struct mt76_queue * q)1920 static inline bool mt76_queue_is_rx(struct mt76_dev *dev, struct mt76_queue *q)
1921 {
1922 int i;
1923
1924 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++) {
1925 if (q == &dev->q_rx[i])
1926 return true;
1927 }
1928
1929 return false;
1930 }
1931
mt76_queue_is_wed_tx_free(struct mt76_queue * q)1932 static inline bool mt76_queue_is_wed_tx_free(struct mt76_queue *q)
1933 {
1934 return (q->flags & MT_QFLAG_WED) &&
1935 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_TXFREE;
1936 }
1937
mt76_queue_is_wed_rro(struct mt76_queue * q)1938 static inline bool mt76_queue_is_wed_rro(struct mt76_queue *q)
1939 {
1940 return q->flags & MT_QFLAG_WED_RRO;
1941 }
1942
mt76_queue_is_wed_rro_ind(struct mt76_queue * q)1943 static inline bool mt76_queue_is_wed_rro_ind(struct mt76_queue *q)
1944 {
1945 return mt76_queue_is_wed_rro(q) &&
1946 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_IND;
1947 }
1948
mt76_queue_is_wed_rro_rxdmad_c(struct mt76_queue * q)1949 static inline bool mt76_queue_is_wed_rro_rxdmad_c(struct mt76_queue *q)
1950 {
1951 return mt76_queue_is_wed_rro(q) &&
1952 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_RXDMAD_C;
1953 }
1954
mt76_queue_is_wed_rro_data(struct mt76_queue * q)1955 static inline bool mt76_queue_is_wed_rro_data(struct mt76_queue *q)
1956 {
1957 return mt76_queue_is_wed_rro(q) &&
1958 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_DATA;
1959 }
1960
mt76_queue_is_wed_rro_msdu_pg(struct mt76_queue * q)1961 static inline bool mt76_queue_is_wed_rro_msdu_pg(struct mt76_queue *q)
1962 {
1963 return mt76_queue_is_wed_rro(q) &&
1964 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) ==
1965 MT76_WED_RRO_Q_MSDU_PG;
1966 }
1967
mt76_queue_is_wed_rx(struct mt76_queue * q)1968 static inline bool mt76_queue_is_wed_rx(struct mt76_queue *q)
1969 {
1970 return (q->flags & MT_QFLAG_WED) &&
1971 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX;
1972 }
1973
mt76_queue_is_emi(struct mt76_queue * q)1974 static inline bool mt76_queue_is_emi(struct mt76_queue *q)
1975 {
1976 return q->flags & MT_QFLAG_EMI_EN;
1977 }
1978
mt76_queue_is_npu(struct mt76_queue * q)1979 static inline bool mt76_queue_is_npu(struct mt76_queue *q)
1980 {
1981 return q->flags & MT_QFLAG_NPU;
1982 }
1983
mt76_queue_is_npu_tx(struct mt76_queue * q)1984 static inline bool mt76_queue_is_npu_tx(struct mt76_queue *q)
1985 {
1986 return mt76_queue_is_npu(q) &&
1987 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_TX;
1988 }
1989
mt76_queue_is_npu_rx(struct mt76_queue * q)1990 static inline bool mt76_queue_is_npu_rx(struct mt76_queue *q)
1991 {
1992 return mt76_queue_is_npu(q) &&
1993 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX;
1994 }
1995
1996 struct mt76_txwi_cache *
1997 mt76_token_release(struct mt76_dev *dev, int token, bool *wake);
1998 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi);
1999 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked);
2000 struct mt76_txwi_cache *mt76_rx_token_release(struct mt76_dev *dev, int token);
2001 int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr,
2002 struct mt76_txwi_cache *r, dma_addr_t phys);
2003 int mt76_create_page_pool(struct mt76_dev *dev, struct mt76_queue *q);
mt76_put_page_pool_buf(void * buf,bool allow_direct)2004 static inline void mt76_put_page_pool_buf(void *buf, bool allow_direct)
2005 {
2006 struct page *page = virt_to_head_page(buf);
2007
2008 page_pool_put_full_page(pp_page_to_nmdesc(page)->pp, page,
2009 allow_direct);
2010 }
2011
2012 static inline void *
mt76_get_page_pool_buf(struct mt76_queue * q,u32 * offset,u32 size)2013 mt76_get_page_pool_buf(struct mt76_queue *q, u32 *offset, u32 size)
2014 {
2015 struct page *page;
2016
2017 page = page_pool_alloc_frag(q->page_pool, offset, size,
2018 GFP_ATOMIC | __GFP_NOWARN | GFP_DMA32);
2019 if (!page)
2020 return NULL;
2021
2022 return page_address(page) + *offset;
2023 }
2024
mt76_set_tx_blocked(struct mt76_dev * dev,bool blocked)2025 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked)
2026 {
2027 spin_lock_bh(&dev->token_lock);
2028 __mt76_set_tx_blocked(dev, blocked);
2029 spin_unlock_bh(&dev->token_lock);
2030 }
2031
2032 static inline int
mt76_token_get(struct mt76_dev * dev,struct mt76_txwi_cache ** ptxwi)2033 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi)
2034 {
2035 int token;
2036
2037 spin_lock_bh(&dev->token_lock);
2038 token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC);
2039 spin_unlock_bh(&dev->token_lock);
2040
2041 return token;
2042 }
2043
2044 static inline struct mt76_txwi_cache *
mt76_token_put(struct mt76_dev * dev,int token)2045 mt76_token_put(struct mt76_dev *dev, int token)
2046 {
2047 struct mt76_txwi_cache *txwi;
2048
2049 spin_lock_bh(&dev->token_lock);
2050 txwi = idr_remove(&dev->token, token);
2051 spin_unlock_bh(&dev->token_lock);
2052
2053 return txwi;
2054 }
2055
2056 void mt76_wcid_init(struct mt76_wcid *wcid, u8 band_idx);
2057 void mt76_wcid_cleanup(struct mt76_dev *dev, struct mt76_wcid *wcid);
2058 void mt76_wcid_add_poll(struct mt76_dev *dev, struct mt76_wcid *wcid);
2059
2060 static inline void
mt76_vif_init(struct ieee80211_vif * vif,struct mt76_vif_data * mvif)2061 mt76_vif_init(struct ieee80211_vif *vif, struct mt76_vif_data *mvif)
2062 {
2063 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv;
2064
2065 mlink->mvif = mvif;
2066 rcu_assign_pointer(mvif->link[0], mlink);
2067 }
2068
2069 void mt76_vif_cleanup(struct mt76_dev *dev, struct ieee80211_vif *vif);
2070 u16 mt76_select_links(struct ieee80211_vif *vif, int max_active_links);
2071
2072 static inline struct mt76_vif_link *
mt76_vif_link(struct mt76_dev * dev,struct ieee80211_vif * vif,int link_id)2073 mt76_vif_link(struct mt76_dev *dev, struct ieee80211_vif *vif, int link_id)
2074 {
2075 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv;
2076 struct mt76_vif_data *mvif = mlink->mvif;
2077
2078 if (!link_id)
2079 return mlink;
2080
2081 return mt76_dereference(mvif->link[link_id], dev);
2082 }
2083
2084 static inline struct mt76_vif_link *
mt76_vif_conf_link(struct mt76_dev * dev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * link_conf)2085 mt76_vif_conf_link(struct mt76_dev *dev, struct ieee80211_vif *vif,
2086 struct ieee80211_bss_conf *link_conf)
2087 {
2088 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv;
2089 struct mt76_vif_data *mvif = mlink->mvif;
2090
2091 if (link_conf == &vif->bss_conf || !link_conf->link_id)
2092 return mlink;
2093
2094 return mt76_dereference(mvif->link[link_conf->link_id], dev);
2095 }
2096
2097 static inline struct mt76_phy *
mt76_vif_link_phy(struct mt76_vif_link * mlink)2098 mt76_vif_link_phy(struct mt76_vif_link *mlink)
2099 {
2100 struct mt76_chanctx *ctx;
2101
2102 if (!mlink->ctx)
2103 return NULL;
2104
2105 ctx = (struct mt76_chanctx *)mlink->ctx->drv_priv;
2106
2107 return ctx->phy;
2108 }
2109
2110 #endif
2111