1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include <nvif/push006c.h>
25
26 #include <nvif/class.h>
27 #include <nvif/cl0002.h>
28 #include <nvif/if0020.h>
29
30 #include "nouveau_drv.h"
31 #include "nouveau_dma.h"
32 #include "nouveau_bo.h"
33 #include "nouveau_chan.h"
34 #include "nouveau_fence.h"
35 #include "nouveau_abi16.h"
36 #include "nouveau_vmm.h"
37 #include "nouveau_svm.h"
38
39 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM");
40 int nouveau_vram_pushbuf;
41 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
42
43 void
nouveau_channel_kill(struct nouveau_channel * chan)44 nouveau_channel_kill(struct nouveau_channel *chan)
45 {
46 atomic_set(&chan->killed, 1);
47 if (chan->fence)
48 nouveau_fence_context_kill(chan->fence, -ENODEV);
49 }
50
51 static int
nouveau_channel_killed(struct nvif_event * event,void * repv,u32 repc)52 nouveau_channel_killed(struct nvif_event *event, void *repv, u32 repc)
53 {
54 struct nouveau_channel *chan = container_of(event, typeof(*chan), kill);
55 struct nouveau_cli *cli = chan->cli;
56
57 NV_PRINTK(warn, cli, "channel %d killed!\n", chan->chid);
58
59 if (unlikely(!atomic_read(&chan->killed)))
60 nouveau_channel_kill(chan);
61
62 return NVIF_EVENT_DROP;
63 }
64
65 int
nouveau_channel_idle(struct nouveau_channel * chan)66 nouveau_channel_idle(struct nouveau_channel *chan)
67 {
68 if (likely(chan && chan->fence && !atomic_read(&chan->killed))) {
69 struct nouveau_cli *cli = chan->cli;
70 struct nouveau_fence *fence = NULL;
71 int ret;
72
73 ret = nouveau_fence_new(&fence, chan);
74 if (!ret) {
75 ret = nouveau_fence_wait(fence, false, false);
76 nouveau_fence_unref(&fence);
77 }
78
79 if (ret) {
80 NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n",
81 chan->chid, cli->name);
82 return ret;
83 }
84 }
85 return 0;
86 }
87
88 void
nouveau_channel_del(struct nouveau_channel ** pchan)89 nouveau_channel_del(struct nouveau_channel **pchan)
90 {
91 struct nouveau_channel *chan = *pchan;
92 if (chan) {
93 if (chan->fence)
94 nouveau_fence(chan->cli->drm)->context_del(chan);
95
96 if (nvif_object_constructed(&chan->user))
97 nouveau_svmm_part(chan->vmm->svmm, chan->inst);
98
99 nvif_object_dtor(&chan->blit);
100 nvif_object_dtor(&chan->nvsw);
101 nvif_object_dtor(&chan->gart);
102 nvif_object_dtor(&chan->vram);
103 nvif_event_dtor(&chan->kill);
104 nvif_object_dtor(&chan->user);
105 nvif_mem_dtor(&chan->mem_userd);
106 nouveau_vma_del(&chan->sema.vma);
107 nouveau_bo_unpin_del(&chan->sema.bo);
108 nvif_object_dtor(&chan->push.ctxdma);
109 nouveau_vma_del(&chan->push.vma);
110 nouveau_bo_unpin_del(&chan->push.buffer);
111 kfree(chan);
112 }
113 *pchan = NULL;
114 }
115
116 static void
nouveau_channel_kick(struct nvif_push * push)117 nouveau_channel_kick(struct nvif_push *push)
118 {
119 struct nouveau_channel *chan = container_of(push, typeof(*chan), chan.push);
120 chan->dma.cur = chan->dma.cur + (chan->chan.push.cur - chan->chan.push.bgn);
121 FIRE_RING(chan);
122 chan->chan.push.bgn = chan->chan.push.cur;
123 }
124
125 static int
nouveau_channel_wait(struct nvif_push * push,u32 size)126 nouveau_channel_wait(struct nvif_push *push, u32 size)
127 {
128 struct nouveau_channel *chan = container_of(push, typeof(*chan), chan.push);
129 int ret;
130 chan->dma.cur = chan->dma.cur + (chan->chan.push.cur - chan->chan.push.bgn);
131 ret = RING_SPACE(chan, size);
132 if (ret == 0) {
133 chan->chan.push.bgn = chan->chan.push.mem.object.map.ptr;
134 chan->chan.push.bgn = chan->chan.push.bgn + chan->dma.cur;
135 chan->chan.push.cur = chan->chan.push.bgn;
136 chan->chan.push.end = chan->chan.push.bgn + size;
137 }
138 return ret;
139 }
140
141 static int
nouveau_channel_prep(struct nouveau_cli * cli,u32 size,struct nouveau_channel ** pchan)142 nouveau_channel_prep(struct nouveau_cli *cli,
143 u32 size, struct nouveau_channel **pchan)
144 {
145 struct nouveau_drm *drm = cli->drm;
146 struct nvif_device *device = &cli->device;
147 struct nv_dma_v0 args = {};
148 struct nouveau_channel *chan;
149 u32 target;
150 int ret;
151
152 chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL);
153 if (!chan)
154 return -ENOMEM;
155
156 chan->cli = cli;
157 chan->vmm = nouveau_cli_vmm(cli);
158 atomic_set(&chan->killed, 0);
159
160 /* allocate memory for dma push buffer */
161 target = NOUVEAU_GEM_DOMAIN_GART | NOUVEAU_GEM_DOMAIN_COHERENT;
162 if (nouveau_vram_pushbuf)
163 target = NOUVEAU_GEM_DOMAIN_VRAM;
164
165 ret = nouveau_bo_new_map(cli, target, size, &chan->push.buffer);
166 if (ret) {
167 nouveau_channel_del(pchan);
168 return ret;
169 }
170
171 chan->chan.push.mem.object.parent = cli->base.object.parent;
172 chan->chan.push.mem.object.client = &cli->base;
173 chan->chan.push.mem.object.name = "chanPush";
174 chan->chan.push.mem.object.map.ptr = chan->push.buffer->kmap.virtual;
175 chan->chan.push.wait = nouveau_channel_wait;
176 chan->chan.push.kick = nouveau_channel_kick;
177
178 /* create dma object covering the *entire* memory space that the
179 * pushbuf lives in, this is because the GEM code requires that
180 * we be able to call out to other (indirect) push buffers
181 */
182 chan->push.addr = chan->push.buffer->offset;
183
184 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
185 ret = nouveau_vma_new(chan->push.buffer, chan->vmm,
186 &chan->push.vma);
187 if (ret) {
188 nouveau_channel_del(pchan);
189 return ret;
190 }
191
192 chan->push.addr = chan->push.vma->addr;
193
194 if (device->info.family >= NV_DEVICE_INFO_V0_FERMI) {
195 return nouveau_bo_new_map_gpu(cli, NOUVEAU_GEM_DOMAIN_GART, PAGE_SIZE,
196 &chan->sema.bo, &chan->sema.vma);
197 }
198
199 args.target = NV_DMA_V0_TARGET_VM;
200 args.access = NV_DMA_V0_ACCESS_VM;
201 args.start = 0;
202 args.limit = chan->vmm->vmm.limit - 1;
203 } else
204 if (chan->push.buffer->bo.resource->mem_type == TTM_PL_VRAM) {
205 if (device->info.family == NV_DEVICE_INFO_V0_TNT) {
206 struct nvkm_device *nvkm_device = nvxx_device(drm);
207
208 /* nv04 vram pushbuf hack, retarget to its location in
209 * the framebuffer bar rather than direct vram access..
210 * nfi why this exists, it came from the -nv ddx.
211 */
212 args.target = NV_DMA_V0_TARGET_PCI;
213 args.access = NV_DMA_V0_ACCESS_RDWR;
214 args.start = nvkm_device->func->resource_addr(nvkm_device, NVKM_BAR1_FB);
215 args.limit = args.start + device->info.ram_user - 1;
216 } else {
217 args.target = NV_DMA_V0_TARGET_VRAM;
218 args.access = NV_DMA_V0_ACCESS_RDWR;
219 args.start = 0;
220 args.limit = device->info.ram_user - 1;
221 }
222 } else {
223 if (drm->agp.bridge) {
224 args.target = NV_DMA_V0_TARGET_AGP;
225 args.access = NV_DMA_V0_ACCESS_RDWR;
226 args.start = drm->agp.base;
227 args.limit = drm->agp.base + drm->agp.size - 1;
228 } else {
229 args.target = NV_DMA_V0_TARGET_VM;
230 args.access = NV_DMA_V0_ACCESS_RDWR;
231 args.start = 0;
232 args.limit = chan->vmm->vmm.limit - 1;
233 }
234 }
235
236 ret = nvif_object_ctor(&device->object, "abi16PushCtxDma", 0,
237 NV_DMA_FROM_MEMORY, &args, sizeof(args),
238 &chan->push.ctxdma);
239 if (ret) {
240 nouveau_channel_del(pchan);
241 return ret;
242 }
243
244 return 0;
245 }
246
247 static int
nouveau_channel_ctor(struct nouveau_cli * cli,bool priv,u64 runm,struct nouveau_channel ** pchan)248 nouveau_channel_ctor(struct nouveau_cli *cli, bool priv, u64 runm,
249 struct nouveau_channel **pchan)
250 {
251 const struct nvif_mclass hosts[] = {
252 { BLACKWELL_CHANNEL_GPFIFO_B, 0 },
253 { BLACKWELL_CHANNEL_GPFIFO_A, 0 },
254 { HOPPER_CHANNEL_GPFIFO_A, 0 },
255 { AMPERE_CHANNEL_GPFIFO_B, 0 },
256 { AMPERE_CHANNEL_GPFIFO_A, 0 },
257 { TURING_CHANNEL_GPFIFO_A, 0 },
258 { VOLTA_CHANNEL_GPFIFO_A, 0 },
259 { PASCAL_CHANNEL_GPFIFO_A, 0 },
260 { MAXWELL_CHANNEL_GPFIFO_A, 0 },
261 { KEPLER_CHANNEL_GPFIFO_B, 0 },
262 { KEPLER_CHANNEL_GPFIFO_A, 0 },
263 { FERMI_CHANNEL_GPFIFO , 0 },
264 { G82_CHANNEL_GPFIFO , 0 },
265 { NV50_CHANNEL_GPFIFO , 0 },
266 { NV40_CHANNEL_DMA , 0 },
267 { NV17_CHANNEL_DMA , 0 },
268 { NV10_CHANNEL_DMA , 0 },
269 { NV03_CHANNEL_DMA , 0 },
270 {}
271 };
272 DEFINE_RAW_FLEX(struct nvif_chan_v0, args, name, TASK_COMM_LEN + 16);
273 struct nvif_device *device = &cli->device;
274 struct nouveau_channel *chan;
275 const u64 plength = 0x10000;
276 const u64 ioffset = plength;
277 const u64 ilength = 0x02000;
278 int cid, ret;
279 u64 size;
280
281 cid = nvif_mclass(&device->object, hosts);
282 if (cid < 0)
283 return cid;
284
285 if (hosts[cid].oclass < NV50_CHANNEL_GPFIFO)
286 size = plength;
287 else
288 size = ioffset + ilength;
289
290 /* allocate dma push buffer */
291 ret = nouveau_channel_prep(cli, size, &chan);
292 *pchan = chan;
293 if (ret)
294 return ret;
295
296 /* create channel object */
297 args->version = 0;
298 args->namelen = __member_size(args->name);
299 args->runlist = __ffs64(runm);
300 args->runq = 0;
301 args->priv = priv;
302 args->devm = BIT(0);
303 if (hosts[cid].oclass < NV50_CHANNEL_GPFIFO) {
304 args->vmm = 0;
305 args->ctxdma = nvif_handle(&chan->push.ctxdma);
306 args->offset = chan->push.addr;
307 args->length = 0;
308 } else {
309 args->vmm = nvif_handle(&chan->vmm->vmm.object);
310 if (hosts[cid].oclass < FERMI_CHANNEL_GPFIFO)
311 args->ctxdma = nvif_handle(&chan->push.ctxdma);
312 else
313 args->ctxdma = 0;
314 args->offset = ioffset + chan->push.addr;
315 args->length = ilength;
316 }
317 args->huserd = 0;
318 args->ouserd = 0;
319
320 /* allocate userd */
321 if (hosts[cid].oclass >= VOLTA_CHANNEL_GPFIFO_A) {
322 ret = nvif_mem_ctor(&cli->mmu, "abi16ChanUSERD", NVIF_CLASS_MEM_GF100,
323 NVIF_MEM_VRAM | NVIF_MEM_COHERENT | NVIF_MEM_MAPPABLE,
324 0, PAGE_SIZE, NULL, 0, &chan->mem_userd);
325 if (ret)
326 return ret;
327
328 args->huserd = nvif_handle(&chan->mem_userd.object);
329 args->ouserd = 0;
330
331 chan->userd = &chan->mem_userd.object;
332 } else {
333 chan->userd = &chan->user;
334 }
335
336 snprintf(args->name, __member_size(args->name), "%s[%d]",
337 current->comm, task_pid_nr(current));
338
339 ret = nvif_object_ctor(&device->object, "abi16ChanUser", 0, hosts[cid].oclass,
340 args, __struct_size(args), &chan->user);
341 if (ret) {
342 nouveau_channel_del(pchan);
343 return ret;
344 }
345
346 chan->runlist = args->runlist;
347 chan->chid = args->chid;
348 chan->inst = args->inst;
349 chan->token = args->token;
350 return 0;
351 }
352
353 static int
nouveau_channel_init(struct nouveau_channel * chan,u32 vram,u32 gart)354 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
355 {
356 struct nouveau_cli *cli = chan->cli;
357 struct nouveau_drm *drm = cli->drm;
358 struct nvif_device *device = &cli->device;
359 struct nv_dma_v0 args = {};
360 int ret, i;
361
362 ret = nvif_object_map(chan->userd, NULL, 0);
363 if (ret)
364 return ret;
365
366 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) {
367 DEFINE_RAW_FLEX(struct nvif_event_v0, args, data,
368 sizeof(struct nvif_chan_event_v0));
369 struct nvif_chan_event_v0 *host =
370 (struct nvif_chan_event_v0 *)args->data;
371
372 host->version = 0;
373 host->type = NVIF_CHAN_EVENT_V0_KILLED;
374
375 ret = nvif_event_ctor(&chan->user, "abi16ChanKilled", chan->chid,
376 nouveau_channel_killed, false,
377 args, __struct_size(args), &chan->kill);
378 if (ret == 0)
379 ret = nvif_event_allow(&chan->kill);
380 if (ret) {
381 NV_ERROR(drm, "Failed to request channel kill "
382 "notification: %d\n", ret);
383 return ret;
384 }
385 }
386
387 /* allocate dma objects to cover all allowed vram, and gart */
388 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
389 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
390 args.target = NV_DMA_V0_TARGET_VM;
391 args.access = NV_DMA_V0_ACCESS_VM;
392 args.start = 0;
393 args.limit = chan->vmm->vmm.limit - 1;
394 } else {
395 args.target = NV_DMA_V0_TARGET_VRAM;
396 args.access = NV_DMA_V0_ACCESS_RDWR;
397 args.start = 0;
398 args.limit = device->info.ram_user - 1;
399 }
400
401 ret = nvif_object_ctor(&chan->user, "abi16ChanVramCtxDma", vram,
402 NV_DMA_IN_MEMORY, &args, sizeof(args),
403 &chan->vram);
404 if (ret)
405 return ret;
406
407 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
408 args.target = NV_DMA_V0_TARGET_VM;
409 args.access = NV_DMA_V0_ACCESS_VM;
410 args.start = 0;
411 args.limit = chan->vmm->vmm.limit - 1;
412 } else
413 if (drm->agp.bridge) {
414 args.target = NV_DMA_V0_TARGET_AGP;
415 args.access = NV_DMA_V0_ACCESS_RDWR;
416 args.start = drm->agp.base;
417 args.limit = drm->agp.base + drm->agp.size - 1;
418 } else {
419 args.target = NV_DMA_V0_TARGET_VM;
420 args.access = NV_DMA_V0_ACCESS_RDWR;
421 args.start = 0;
422 args.limit = chan->vmm->vmm.limit - 1;
423 }
424
425 ret = nvif_object_ctor(&chan->user, "abi16ChanGartCtxDma", gart,
426 NV_DMA_IN_MEMORY, &args, sizeof(args),
427 &chan->gart);
428 if (ret)
429 return ret;
430 }
431
432 /* initialise dma tracking parameters */
433 if (chan->user.oclass < NV50_CHANNEL_GPFIFO) {
434 chan->user_put = 0x40;
435 chan->user_get = 0x44;
436 chan->dma.max = (0x10000 / 4) - 2;
437 } else
438 if (chan->user.oclass < FERMI_CHANNEL_GPFIFO) {
439 ret = nvif_chan506f_ctor(&chan->chan, chan->userd->map.ptr,
440 (u8*)chan->push.buffer->kmap.virtual + 0x10000, 0x2000,
441 chan->push.buffer->kmap.virtual, chan->push.addr, 0x10000);
442 if (ret)
443 return ret;
444 } else
445 if (chan->user.oclass < VOLTA_CHANNEL_GPFIFO_A) {
446 ret = nvif_chan906f_ctor(&chan->chan, chan->userd->map.ptr,
447 (u8*)chan->push.buffer->kmap.virtual + 0x10000, 0x2000,
448 chan->push.buffer->kmap.virtual, chan->push.addr, 0x10000,
449 chan->sema.bo->kmap.virtual, chan->sema.vma->addr);
450 if (ret)
451 return ret;
452 } else {
453 ret = nvif_chanc36f_ctor(&chan->chan, chan->userd->map.ptr,
454 (u8*)chan->push.buffer->kmap.virtual + 0x10000, 0x2000,
455 chan->push.buffer->kmap.virtual, chan->push.addr, 0x10000,
456 chan->sema.bo->kmap.virtual, chan->sema.vma->addr,
457 &drm->client.device.user, chan->token);
458 if (ret)
459 return ret;
460 }
461
462 chan->dma.put = 0;
463 chan->dma.cur = chan->dma.put;
464 chan->dma.free = chan->dma.max - chan->dma.cur;
465
466 ret = PUSH_WAIT(&chan->chan.push, NOUVEAU_DMA_SKIPS);
467 if (ret)
468 return ret;
469
470 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
471 PUSH_DATA(&chan->chan.push, 0x00000000);
472
473 /* allocate software object class (used for fences on <= nv05) */
474 if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) {
475 ret = nvif_object_ctor(&chan->user, "abi16NvswFence", 0x006e,
476 NVIF_CLASS_SW_NV04,
477 NULL, 0, &chan->nvsw);
478 if (ret)
479 return ret;
480
481 ret = PUSH_WAIT(&chan->chan.push, 2);
482 if (ret)
483 return ret;
484
485 PUSH_NVSQ(&chan->chan.push, NV_SW, 0x0000, chan->nvsw.handle);
486 PUSH_KICK(&chan->chan.push);
487 }
488
489 /* initialise synchronisation */
490 return nouveau_fence(drm)->context_new(chan);
491 }
492
493 int
nouveau_channel_new(struct nouveau_cli * cli,bool priv,u64 runm,u32 vram,u32 gart,struct nouveau_channel ** pchan)494 nouveau_channel_new(struct nouveau_cli *cli,
495 bool priv, u64 runm, u32 vram, u32 gart, struct nouveau_channel **pchan)
496 {
497 int ret;
498
499 ret = nouveau_channel_ctor(cli, priv, runm, pchan);
500 if (ret) {
501 NV_PRINTK(dbg, cli, "channel create, %d\n", ret);
502 return ret;
503 }
504
505 ret = nouveau_channel_init(*pchan, vram, gart);
506 if (ret) {
507 NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret);
508 nouveau_channel_del(pchan);
509 return ret;
510 }
511
512 ret = nouveau_svmm_join((*pchan)->vmm->svmm, (*pchan)->inst);
513 if (ret)
514 nouveau_channel_del(pchan);
515
516 return ret;
517 }
518
519 void
nouveau_channels_fini(struct nouveau_drm * drm)520 nouveau_channels_fini(struct nouveau_drm *drm)
521 {
522 kfree(drm->runl);
523 }
524
525 int
nouveau_channels_init(struct nouveau_drm * drm)526 nouveau_channels_init(struct nouveau_drm *drm)
527 {
528 DEFINE_RAW_FLEX(struct nv_device_info_v1, args, data, 2);
529 struct nv_device_info_v1_data *channels = &args->data[0];
530 struct nv_device_info_v1_data *runlists = &args->data[1];
531 struct nvif_object *device = &drm->client.device.object;
532 int ret, i;
533
534 args->version = 1;
535 args->count = __member_size(args->data) / sizeof(*args->data);
536 channels->mthd = NV_DEVICE_HOST_CHANNELS;
537 runlists->mthd = NV_DEVICE_HOST_RUNLISTS;
538
539 ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, args,
540 __struct_size(args));
541 if (ret ||
542 runlists->mthd == NV_DEVICE_INFO_INVALID || !runlists->data ||
543 channels->mthd == NV_DEVICE_INFO_INVALID)
544 return -ENODEV;
545
546 drm->chan_nr = drm->chan_total = channels->data;
547 drm->runl_nr = fls64(runlists->data);
548 drm->runl = kcalloc(drm->runl_nr, sizeof(*drm->runl), GFP_KERNEL);
549 if (!drm->runl)
550 return -ENOMEM;
551
552 if (drm->chan_nr == 0) {
553 for (i = 0; i < drm->runl_nr; i++) {
554 if (!(runlists->data & BIT(i)))
555 continue;
556
557 channels->mthd = NV_DEVICE_HOST_RUNLIST_CHANNELS;
558 channels->data = i;
559
560 ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, args,
561 __struct_size(args));
562 if (ret || channels->mthd == NV_DEVICE_INFO_INVALID)
563 return -ENODEV;
564
565 drm->runl[i].chan_nr = channels->data;
566 drm->runl[i].chan_id_base = drm->chan_total;
567 drm->runl[i].context_base = dma_fence_context_alloc(drm->runl[i].chan_nr);
568
569 drm->chan_total += drm->runl[i].chan_nr;
570 }
571 } else {
572 drm->runl[0].context_base = dma_fence_context_alloc(drm->chan_nr);
573 for (i = 1; i < drm->runl_nr; i++)
574 drm->runl[i].context_base = drm->runl[0].context_base;
575
576 }
577
578 return 0;
579 }
580