1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qobject/qnum.h"
26 #include "acpi-build.h"
27 #include "acpi-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci_bridge.h"
31 #include "hw/cxl/cxl.h"
32 #include "hw/core/cpu.h"
33 #include "target/i386/cpu.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/cpu.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/acpi/acpi_aml_interface.h"
41 #include "hw/input/i8042.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "system/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/vmgenid.h"
46 #include "hw/acpi/vmclock.h"
47 #include "hw/acpi/erst.h"
48 #include "hw/acpi/piix4.h"
49 #include "system/tpm_backend.h"
50 #include "hw/rtc/mc146818rtc_regs.h"
51 #include "migration/vmstate.h"
52 #include "hw/mem/memory-device.h"
53 #include "hw/mem/nvdimm.h"
54 #include "system/numa.h"
55 #include "system/reset.h"
56 #include "hw/hyperv/vmbus-bridge.h"
57
58 /* Supported chipsets: */
59 #include "hw/southbridge/ich9.h"
60 #include "hw/acpi/pcihp.h"
61 #include "hw/i386/fw_cfg.h"
62 #include "hw/i386/pc.h"
63 #include "hw/pci/pci_bus.h"
64 #include "hw/pci-host/i440fx.h"
65 #include "hw/pci-host/q35.h"
66 #include "hw/i386/x86-iommu.h"
67
68 #include "hw/acpi/aml-build.h"
69 #include "hw/acpi/utils.h"
70 #include "hw/acpi/pci.h"
71 #include "hw/acpi/cxl.h"
72
73 #include "qom/qom-qobject.h"
74 #include "hw/i386/amd_iommu.h"
75 #include "hw/i386/intel_iommu.h"
76 #include "hw/virtio/virtio-iommu.h"
77
78 #include "hw/acpi/hmat.h"
79 #include "hw/acpi/viot.h"
80
81 #include CONFIG_DEVICES
82
83 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
84 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
85 * a little bit, there should be plenty of free space since the DSDT
86 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
87 */
88 #define ACPI_BUILD_ALIGN_SIZE 0x1000
89
90 #define ACPI_BUILD_TABLE_SIZE 0x20000
91
92 /* #define DEBUG_ACPI_BUILD */
93 #ifdef DEBUG_ACPI_BUILD
94 #define ACPI_BUILD_DPRINTF(fmt, ...) \
95 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
96 #else
97 #define ACPI_BUILD_DPRINTF(fmt, ...)
98 #endif
99
100 typedef struct AcpiPmInfo {
101 bool s3_disabled;
102 bool s4_disabled;
103 bool pcihp_bridge_en;
104 bool smi_on_cpuhp;
105 bool smi_on_cpu_unplug;
106 bool pcihp_root_en;
107 uint8_t s4_val;
108 AcpiFadtData fadt;
109 uint16_t cpu_hp_io_base;
110 uint16_t pcihp_io_base;
111 uint16_t pcihp_io_len;
112 } AcpiPmInfo;
113
114 typedef struct AcpiMiscInfo {
115 bool has_hpet;
116 #ifdef CONFIG_TPM
117 TPMVersion tpm_version;
118 #endif
119 } AcpiMiscInfo;
120
121 typedef struct FwCfgTPMConfig {
122 uint32_t tpmppi_address;
123 uint8_t tpm_version;
124 uint8_t tpmppi_version;
125 } QEMU_PACKED FwCfgTPMConfig;
126
127 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
128
129 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = {
130 .space_id = AML_AS_SYSTEM_IO,
131 .address = NVDIMM_ACPI_IO_BASE,
132 .bit_width = NVDIMM_ACPI_IO_LEN << 3
133 };
134
init_common_fadt_data(MachineState * ms,Object * o,AcpiFadtData * data)135 static void init_common_fadt_data(MachineState *ms, Object *o,
136 AcpiFadtData *data)
137 {
138 X86MachineState *x86ms = X86_MACHINE(ms);
139 /*
140 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old
141 * behavior for compatibility irrelevant to smm_enabled, which doesn't
142 * conform to the ACPI spec.
143 */
144 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ?
145 true : x86_machine_is_smm_enabled(x86ms);
146 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
147 AmlAddressSpace as = AML_AS_SYSTEM_IO;
148 AcpiFadtData fadt = {
149 .rev = 3,
150 .flags =
151 (1 << ACPI_FADT_F_WBINVD) |
152 (1 << ACPI_FADT_F_PROC_C1) |
153 (1 << ACPI_FADT_F_SLP_BUTTON) |
154 (1 << ACPI_FADT_F_RTC_S4) |
155 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
156 /* APIC destination mode ("Flat Logical") has an upper limit of 8
157 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
158 * used
159 */
160 ((ms->smp.max_cpus > 8) ?
161 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
162 .int_model = 1 /* Multiple APIC */,
163 .rtc_century = RTC_CENTURY,
164 .plvl2_lat = 0xfff /* C2 state not supported */,
165 .plvl3_lat = 0xfff /* C3 state not supported */,
166 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0,
167 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
168 .acpi_enable_cmd =
169 smm_enabled ?
170 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) :
171 0,
172 .acpi_disable_cmd =
173 smm_enabled ?
174 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) :
175 0,
176 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
177 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
178 .address = io + 0x04 },
179 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
180 .gpe0_blk = { .space_id = as, .bit_width =
181 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
182 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
183 },
184 };
185
186 /*
187 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture
188 * Flags, bit offset 1 - 8042.
189 */
190 fadt.iapc_boot_arch = iapc_boot_arch_8042();
191
192 *data = fadt;
193 }
194
acpi_get_pm_info(MachineState * machine,AcpiPmInfo * pm)195 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
196 {
197 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM, NULL);
198 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE, NULL);
199 Object *obj = piix ? piix : lpc;
200 QObject *o;
201 pm->cpu_hp_io_base = 0;
202 pm->pcihp_io_base = 0;
203 pm->pcihp_io_len = 0;
204 pm->smi_on_cpuhp = false;
205 pm->smi_on_cpu_unplug = false;
206
207 assert(obj);
208 init_common_fadt_data(machine, obj, &pm->fadt);
209 if (piix) {
210 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
211 pm->fadt.rev = 1;
212 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
213 }
214 if (lpc) {
215 uint64_t smi_features = object_property_get_uint(lpc,
216 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL);
217 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
218 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
219 pm->fadt.reset_reg = r;
220 pm->fadt.reset_val = 0xf;
221 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
222 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
223 pm->smi_on_cpuhp =
224 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT));
225 pm->smi_on_cpu_unplug =
226 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT));
227 }
228 pm->pcihp_io_base =
229 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
230 pm->pcihp_io_len =
231 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
232
233 /* Fill in optional s3/s4 related properties */
234 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
235 if (o) {
236 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
237 } else {
238 pm->s3_disabled = false;
239 }
240 qobject_unref(o);
241 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
242 if (o) {
243 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
244 } else {
245 pm->s4_disabled = false;
246 }
247 qobject_unref(o);
248 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
249 if (o) {
250 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
251 } else {
252 pm->s4_val = false;
253 }
254 qobject_unref(o);
255
256 pm->pcihp_bridge_en =
257 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
258 NULL);
259 pm->pcihp_root_en =
260 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP,
261 NULL);
262 }
263
acpi_get_misc_info(AcpiMiscInfo * info)264 static void acpi_get_misc_info(AcpiMiscInfo *info)
265 {
266 info->has_hpet = hpet_find();
267 #ifdef CONFIG_TPM
268 info->tpm_version = tpm_get_version(tpm_find());
269 #endif
270 }
271
272 /*
273 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
274 * On i386 arch we only have two pci hosts, so we can look only for them.
275 */
acpi_get_i386_pci_host(void)276 Object *acpi_get_i386_pci_host(void)
277 {
278 PCIHostState *host;
279
280 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL));
281 if (!host) {
282 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL));
283 }
284
285 return OBJECT(host);
286 }
287
acpi_get_pci_holes(Range * hole,Range * hole64)288 static void acpi_get_pci_holes(Range *hole, Range *hole64)
289 {
290 Object *pci_host;
291
292 pci_host = acpi_get_i386_pci_host();
293
294 if (!pci_host) {
295 return;
296 }
297
298 range_set_bounds1(hole,
299 object_property_get_uint(pci_host,
300 PCI_HOST_PROP_PCI_HOLE_START,
301 NULL),
302 object_property_get_uint(pci_host,
303 PCI_HOST_PROP_PCI_HOLE_END,
304 NULL));
305 range_set_bounds1(hole64,
306 object_property_get_uint(pci_host,
307 PCI_HOST_PROP_PCI_HOLE64_START,
308 NULL),
309 object_property_get_uint(pci_host,
310 PCI_HOST_PROP_PCI_HOLE64_END,
311 NULL));
312 }
313
acpi_align_size(GArray * blob,unsigned align)314 static void acpi_align_size(GArray *blob, unsigned align)
315 {
316 /* Align size to multiple of given size. This reduces the chance
317 * we need to change size in the future (breaking cross version migration).
318 */
319 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
320 }
321
322 /*
323 * ACPI spec 1.0b,
324 * 5.2.6 Firmware ACPI Control Structure
325 */
326 static void
build_facs(GArray * table_data)327 build_facs(GArray *table_data)
328 {
329 const char *sig = "FACS";
330 const uint8_t reserved[40] = {};
331
332 g_array_append_vals(table_data, sig, 4); /* Signature */
333 build_append_int_noprefix(table_data, 64, 4); /* Length */
334 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */
335 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */
336 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */
337 build_append_int_noprefix(table_data, 0, 4); /* Flags */
338 g_array_append_vals(table_data, reserved, 40); /* Reserved */
339 }
340
aml_pci_device_dsm(void)341 Aml *aml_pci_device_dsm(void)
342 {
343 Aml *method;
344
345 method = aml_method("_DSM", 4, AML_SERIALIZED);
346 {
347 Aml *params = aml_local(0);
348 Aml *pkg = aml_package(2);
349 aml_append(pkg, aml_int(0));
350 aml_append(pkg, aml_int(0));
351 aml_append(method, aml_store(pkg, params));
352 aml_append(method,
353 aml_store(aml_name("BSEL"), aml_index(params, aml_int(0))));
354 aml_append(method,
355 aml_store(aml_name("ASUN"), aml_index(params, aml_int(1))));
356 aml_append(method,
357 aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1),
358 aml_arg(2), aml_arg(3), params))
359 );
360 }
361 return method;
362 }
363
build_append_pci_dsm_func0_common(Aml * ctx,Aml * retvar)364 static void build_append_pci_dsm_func0_common(Aml *ctx, Aml *retvar)
365 {
366 Aml *UUID, *ifctx1;
367 uint8_t byte_list[1] = { 0 }; /* nothing supported yet */
368
369 aml_append(ctx, aml_store(aml_buffer(1, byte_list), retvar));
370 /*
371 * PCI Firmware Specification 3.1
372 * 4.6. _DSM Definitions for PCI
373 */
374 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
375 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID)));
376 {
377 /* call is for unsupported UUID, bail out */
378 aml_append(ifctx1, aml_return(retvar));
379 }
380 aml_append(ctx, ifctx1);
381
382 ifctx1 = aml_if(aml_lless(aml_arg(1), aml_int(2)));
383 {
384 /* call is for unsupported REV, bail out */
385 aml_append(ifctx1, aml_return(retvar));
386 }
387 aml_append(ctx, ifctx1);
388 }
389
aml_pci_edsm(void)390 static Aml *aml_pci_edsm(void)
391 {
392 Aml *method, *ifctx;
393 Aml *zero = aml_int(0);
394 Aml *func = aml_arg(2);
395 Aml *ret = aml_local(0);
396 Aml *aidx = aml_local(1);
397 Aml *params = aml_arg(4);
398
399 method = aml_method("EDSM", 5, AML_SERIALIZED);
400
401 /* get supported functions */
402 ifctx = aml_if(aml_equal(func, zero));
403 {
404 /* 1: have supported functions */
405 /* 7: support for function 7 */
406 const uint8_t caps = 1 | BIT(7);
407 build_append_pci_dsm_func0_common(ifctx, ret);
408 aml_append(ifctx, aml_store(aml_int(caps), aml_index(ret, zero)));
409 aml_append(ifctx, aml_return(ret));
410 }
411 aml_append(method, ifctx);
412
413 /* handle specific functions requests */
414 /*
415 * PCI Firmware Specification 3.1
416 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
417 * Operating Systems
418 */
419 ifctx = aml_if(aml_equal(func, aml_int(7)));
420 {
421 Aml *pkg = aml_package(2);
422 aml_append(pkg, zero);
423 /* optional, if not impl. should return null string */
424 aml_append(pkg, aml_string("%s", ""));
425 aml_append(ifctx, aml_store(pkg, ret));
426
427 /*
428 * IASL is fine when initializing Package with computational data,
429 * however it makes guest unhappy /it fails to process such AML/.
430 * So use runtime assignment to set acpi-index after initializer
431 * to make OSPM happy.
432 */
433 aml_append(ifctx,
434 aml_store(aml_derefof(aml_index(params, aml_int(0))), aidx));
435 aml_append(ifctx, aml_store(aidx, aml_index(ret, zero)));
436 aml_append(ifctx, aml_return(ret));
437 }
438 aml_append(method, ifctx);
439
440 return method;
441 }
442
aml_pci_static_endpoint_dsm(PCIDevice * pdev)443 static Aml *aml_pci_static_endpoint_dsm(PCIDevice *pdev)
444 {
445 Aml *method;
446
447 g_assert(pdev->acpi_index != 0);
448 method = aml_method("_DSM", 4, AML_SERIALIZED);
449 {
450 Aml *params = aml_local(0);
451 Aml *pkg = aml_package(1);
452 aml_append(pkg, aml_int(pdev->acpi_index));
453 aml_append(method, aml_store(pkg, params));
454 aml_append(method,
455 aml_return(aml_call5("EDSM", aml_arg(0), aml_arg(1),
456 aml_arg(2), aml_arg(3), params))
457 );
458 }
459 return method;
460 }
461
build_append_pcihp_notify_entry(Aml * method,int slot)462 static void build_append_pcihp_notify_entry(Aml *method, int slot)
463 {
464 Aml *if_ctx;
465 int32_t devfn = PCI_DEVFN(slot, 0);
466
467 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
468 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
469 aml_append(method, if_ctx);
470 }
471
is_devfn_ignored_generic(const int devfn,const PCIBus * bus)472 static bool is_devfn_ignored_generic(const int devfn, const PCIBus *bus)
473 {
474 const PCIDevice *pdev = bus->devices[devfn];
475
476 if (PCI_FUNC(devfn)) {
477 if (IS_PCI_BRIDGE(pdev)) {
478 /*
479 * Ignore only hotplugged PCI bridges on !0 functions, but
480 * allow describing cold plugged bridges on all functions
481 */
482 if (DEVICE(pdev)->hotplugged) {
483 return true;
484 }
485 }
486 }
487 return false;
488 }
489
is_devfn_ignored_hotplug(const int devfn,const PCIBus * bus)490 static bool is_devfn_ignored_hotplug(const int devfn, const PCIBus *bus)
491 {
492 PCIDevice *pdev = bus->devices[devfn];
493 if (pdev) {
494 return is_devfn_ignored_generic(devfn, bus) ||
495 !DEVICE_GET_CLASS(pdev)->hotpluggable ||
496 /* Cold plugged bridges aren't themselves hot-pluggable */
497 (IS_PCI_BRIDGE(pdev) && !DEVICE(pdev)->hotplugged);
498 } else { /* non populated slots */
499 /*
500 * hotplug is supported only for non-multifunction device
501 * so generate device description only for function 0
502 */
503 if (PCI_FUNC(devfn) ||
504 (pci_bus_is_express(bus) && PCI_SLOT(devfn) > 0)) {
505 return true;
506 }
507 }
508 return false;
509 }
510
build_append_pcihp_slots(Aml * parent_scope,PCIBus * bus)511 void build_append_pcihp_slots(Aml *parent_scope, PCIBus *bus)
512 {
513 int devfn;
514 Aml *dev, *notify_method = NULL, *method;
515 QObject *bsel = object_property_get_qobject(OBJECT(bus),
516 ACPI_PCIHP_PROP_BSEL, NULL);
517 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
518 qobject_unref(bsel);
519
520 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
521 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
522
523 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
524 int slot = PCI_SLOT(devfn);
525 int adr = slot << 16 | PCI_FUNC(devfn);
526
527 if (is_devfn_ignored_hotplug(devfn, bus)) {
528 continue;
529 }
530
531 if (bus->devices[devfn]) {
532 dev = aml_scope("S%.02X", devfn);
533 } else {
534 dev = aml_device("S%.02X", devfn);
535 aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
536 }
537
538 /*
539 * Can't declare _SUN here for every device as it changes 'slot'
540 * enumeration order in linux kernel, so use another variable for it
541 */
542 aml_append(dev, aml_name_decl("ASUN", aml_int(slot)));
543 aml_append(dev, aml_pci_device_dsm());
544
545 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
546 /* add _EJ0 to make slot hotpluggable */
547 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
548 aml_append(method,
549 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
550 );
551 aml_append(dev, method);
552
553 build_append_pcihp_notify_entry(notify_method, slot);
554
555 /* device descriptor has been composed, add it into parent context */
556 aml_append(parent_scope, dev);
557 }
558 aml_append(parent_scope, notify_method);
559 }
560
build_append_pci_bus_devices(Aml * parent_scope,PCIBus * bus)561 void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus)
562 {
563 int devfn;
564 Aml *dev;
565
566 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
567 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */
568 int adr = PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn);
569 PCIDevice *pdev = bus->devices[devfn];
570
571 if (!pdev || is_devfn_ignored_generic(devfn, bus)) {
572 continue;
573 }
574
575 /* start to compose PCI device descriptor */
576 dev = aml_device("S%.02X", devfn);
577 aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
578
579 call_dev_aml_func(DEVICE(bus->devices[devfn]), dev);
580 /* add _DSM if device has acpi-index set */
581 if (pdev->acpi_index &&
582 !object_property_get_bool(OBJECT(pdev), "hotpluggable",
583 &error_abort)) {
584 aml_append(dev, aml_pci_static_endpoint_dsm(pdev));
585 }
586
587 /* device descriptor has been composed, add it into parent context */
588 aml_append(parent_scope, dev);
589 }
590 }
591
build_append_notification_callback(Aml * parent_scope,const PCIBus * bus)592 static bool build_append_notification_callback(Aml *parent_scope,
593 const PCIBus *bus)
594 {
595 Aml *method;
596 PCIBus *sec;
597 QObject *bsel;
598 int nr_notifiers = 0;
599 GQueue *pcnt_bus_list = g_queue_new();
600
601 QLIST_FOREACH(sec, &bus->child, sibling) {
602 Aml *br_scope = aml_scope("S%.02X", sec->parent_dev->devfn);
603 if (pci_bus_is_root(sec)) {
604 continue;
605 }
606 nr_notifiers = nr_notifiers +
607 build_append_notification_callback(br_scope, sec);
608 /*
609 * add new child scope to parent
610 * and keep track of bus that have PCNT,
611 * bus list is used later to call children PCNTs from this level PCNT
612 */
613 if (nr_notifiers) {
614 g_queue_push_tail(pcnt_bus_list, sec);
615 aml_append(parent_scope, br_scope);
616 }
617 }
618
619 /*
620 * Append PCNT method to notify about events on local and child buses.
621 * ps: hostbridge might not have hotplug (bsel) enabled but might have
622 * child bridges that do have bsel.
623 */
624 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
625
626 /* If bus supports hotplug select it and notify about local events */
627 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
628 if (bsel) {
629 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
630
631 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
632 aml_append(method, aml_call2("DVNT", aml_name("PCIU"),
633 aml_int(1))); /* Device Check */
634 aml_append(method, aml_call2("DVNT", aml_name("PCID"),
635 aml_int(3))); /* Eject Request */
636 nr_notifiers++;
637 }
638
639 /* Notify about child bus events in any case */
640 while ((sec = g_queue_pop_head(pcnt_bus_list))) {
641 aml_append(method, aml_name("^S%.02X.PCNT", sec->parent_dev->devfn));
642 }
643
644 aml_append(parent_scope, method);
645 qobject_unref(bsel);
646 g_queue_free(pcnt_bus_list);
647 return !!nr_notifiers;
648 }
649
aml_pci_pdsm(void)650 static Aml *aml_pci_pdsm(void)
651 {
652 Aml *method, *ifctx, *ifctx1;
653 Aml *ret = aml_local(0);
654 Aml *caps = aml_local(1);
655 Aml *acpi_index = aml_local(2);
656 Aml *zero = aml_int(0);
657 Aml *one = aml_int(1);
658 Aml *not_supp = aml_int(0xFFFFFFFF);
659 Aml *func = aml_arg(2);
660 Aml *params = aml_arg(4);
661 Aml *bnum = aml_derefof(aml_index(params, aml_int(0)));
662 Aml *sunum = aml_derefof(aml_index(params, aml_int(1)));
663
664 method = aml_method("PDSM", 5, AML_SERIALIZED);
665
666 /* get supported functions */
667 ifctx = aml_if(aml_equal(func, zero));
668 {
669 build_append_pci_dsm_func0_common(ifctx, ret);
670
671 aml_append(ifctx, aml_store(zero, caps));
672 aml_append(ifctx,
673 aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
674 /*
675 * advertise function 7 if device has acpi-index
676 * acpi_index values:
677 * 0: not present (default value)
678 * FFFFFFFF: not supported (old QEMU without PIDX reg)
679 * other: device's acpi-index
680 */
681 ifctx1 = aml_if(aml_lnot(
682 aml_or(aml_equal(acpi_index, zero),
683 aml_equal(acpi_index, not_supp), NULL)
684 ));
685 {
686 /* have supported functions */
687 aml_append(ifctx1, aml_or(caps, one, caps));
688 /* support for function 7 */
689 aml_append(ifctx1,
690 aml_or(caps, aml_shiftleft(one, aml_int(7)), caps));
691 }
692 aml_append(ifctx, ifctx1);
693
694 aml_append(ifctx, aml_store(caps, aml_index(ret, zero)));
695 aml_append(ifctx, aml_return(ret));
696 }
697 aml_append(method, ifctx);
698
699 /* handle specific functions requests */
700 /*
701 * PCI Firmware Specification 3.1
702 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
703 * Operating Systems
704 */
705 ifctx = aml_if(aml_equal(func, aml_int(7)));
706 {
707 Aml *pkg = aml_package(2);
708
709 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
710 aml_append(ifctx, aml_store(pkg, ret));
711 /*
712 * Windows calls func=7 without checking if it's available,
713 * as workaround Microsoft has suggested to return invalid for func7
714 * Package, so return 2 elements package but only initialize elements
715 * when acpi_index is supported and leave them uninitialized, which
716 * leads elements to being Uninitialized ObjectType and should trip
717 * Windows into discarding result as an unexpected and prevent setting
718 * bogus 'PCI Label' on the device.
719 */
720 ifctx1 = aml_if(aml_lnot(aml_lor(
721 aml_equal(acpi_index, zero), aml_equal(acpi_index, not_supp)
722 )));
723 {
724 aml_append(ifctx1, aml_store(acpi_index, aml_index(ret, zero)));
725 /*
726 * optional, if not impl. should return null string
727 */
728 aml_append(ifctx1, aml_store(aml_string("%s", ""),
729 aml_index(ret, one)));
730 }
731 aml_append(ifctx, ifctx1);
732
733 aml_append(ifctx, aml_return(ret));
734 }
735
736 aml_append(method, ifctx);
737 return method;
738 }
739
740 /*
741 * build_prt - Define interrupt routing rules
742 *
743 * Returns an array of 128 routes, one for each device,
744 * based on device location.
745 * The main goal is to equally distribute the interrupts
746 * over the 4 existing ACPI links (works only for i440fx).
747 * The hash function is: (slot + pin) & 3 -> "LNK[D|A|B|C]".
748 *
749 */
build_prt(bool is_pci0_prt)750 static Aml *build_prt(bool is_pci0_prt)
751 {
752 const int nroutes = 128;
753 Aml *rt_pkg, *method;
754 int pin;
755
756 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
757 assert(nroutes < 256);
758 rt_pkg = aml_package(nroutes);
759
760 for (pin = 0; pin < nroutes; pin++) {
761 Aml *pkg = aml_package(4);
762 int slot = pin >> 2;
763
764 aml_append(pkg, aml_int((slot << 16) | 0xFFFF));
765 aml_append(pkg, aml_int(pin & 3));
766 /* device 1 is the power-management device, needs SCI */
767 if (is_pci0_prt && pin == 4) {
768 aml_append(pkg, aml_name("%s", "LNKS"));
769 } else {
770 static const char link_name[][5] = {"LNKD", "LNKA", "LNKB", "LNKC"};
771 int hash = (slot + pin) & 3;
772 aml_append(pkg, aml_name("%s", link_name[hash]));
773 }
774 aml_append(pkg, aml_int(0));
775 aml_append(rt_pkg, pkg);
776 }
777
778 aml_append(method, aml_return(rt_pkg));
779
780 return method;
781 }
782
build_hpet_aml(Aml * table)783 static void build_hpet_aml(Aml *table)
784 {
785 Aml *crs;
786 Aml *field;
787 Aml *method;
788 Aml *if_ctx;
789 Aml *scope = aml_scope("_SB");
790 Aml *dev = aml_device("HPET");
791 Aml *zero = aml_int(0);
792 Aml *id = aml_local(0);
793 Aml *period = aml_local(1);
794
795 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
796 aml_append(dev, aml_name_decl("_UID", zero));
797
798 aml_append(dev,
799 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
800 HPET_LEN));
801 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
802 aml_append(field, aml_named_field("VEND", 32));
803 aml_append(field, aml_named_field("PRD", 32));
804 aml_append(dev, field);
805
806 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
807 aml_append(method, aml_store(aml_name("VEND"), id));
808 aml_append(method, aml_store(aml_name("PRD"), period));
809 aml_append(method, aml_shiftright(id, aml_int(16), id));
810 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
811 aml_equal(id, aml_int(0xffff))));
812 {
813 aml_append(if_ctx, aml_return(zero));
814 }
815 aml_append(method, if_ctx);
816
817 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
818 aml_lgreater(period, aml_int(100000000))));
819 {
820 aml_append(if_ctx, aml_return(zero));
821 }
822 aml_append(method, if_ctx);
823
824 aml_append(method, aml_return(aml_int(0x0F)));
825 aml_append(dev, method);
826
827 crs = aml_resource_template();
828 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
829 aml_append(dev, aml_name_decl("_CRS", crs));
830
831 aml_append(scope, dev);
832 aml_append(table, scope);
833 }
834
build_vmbus_device_aml(VMBusBridge * vmbus_bridge)835 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge)
836 {
837 Aml *dev;
838 Aml *method;
839 Aml *crs;
840
841 dev = aml_device("VMBS");
842 aml_append(dev, aml_name_decl("STA", aml_int(0xF)));
843 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus")));
844 aml_append(dev, aml_name_decl("_UID", aml_int(0x0)));
845 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS")));
846
847 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
848 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL),
849 aml_name("STA")));
850 aml_append(dev, method);
851
852 method = aml_method("_PS0", 0, AML_NOTSERIALIZED);
853 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL),
854 aml_name("STA")));
855 aml_append(dev, method);
856
857 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
858 aml_append(method, aml_return(aml_name("STA")));
859 aml_append(dev, method);
860
861 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0)));
862
863 crs = aml_resource_template();
864 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq));
865 aml_append(dev, aml_name_decl("_CRS", crs));
866
867 return dev;
868 }
869
build_dbg_aml(Aml * table)870 static void build_dbg_aml(Aml *table)
871 {
872 Aml *field;
873 Aml *method;
874 Aml *while_ctx;
875 Aml *scope = aml_scope("\\");
876 Aml *buf = aml_local(0);
877 Aml *len = aml_local(1);
878 Aml *idx = aml_local(2);
879
880 aml_append(scope,
881 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
882 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
883 aml_append(field, aml_named_field("DBGB", 8));
884 aml_append(scope, field);
885
886 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
887
888 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
889 aml_append(method, aml_to_buffer(buf, buf));
890 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
891 aml_append(method, aml_store(aml_int(0), idx));
892
893 while_ctx = aml_while(aml_lless(idx, len));
894 aml_append(while_ctx,
895 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
896 aml_append(while_ctx, aml_increment(idx));
897 aml_append(method, while_ctx);
898
899 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
900 aml_append(scope, method);
901
902 aml_append(table, scope);
903 }
904
build_link_dev(const char * name,uint8_t uid,Aml * reg)905 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
906 {
907 Aml *dev;
908 Aml *crs;
909 Aml *method;
910 uint32_t irqs[] = {5, 10, 11};
911
912 dev = aml_device("%s", name);
913 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
914 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
915
916 crs = aml_resource_template();
917 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
918 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
919 aml_append(dev, aml_name_decl("_PRS", crs));
920
921 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
922 aml_append(method, aml_return(aml_call1("IQST", reg)));
923 aml_append(dev, method);
924
925 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
926 aml_append(method, aml_or(reg, aml_int(0x80), reg));
927 aml_append(dev, method);
928
929 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
930 aml_append(method, aml_return(aml_call1("IQCR", reg)));
931 aml_append(dev, method);
932
933 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
934 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
935 aml_append(method, aml_store(aml_name("PRRI"), reg));
936 aml_append(dev, method);
937
938 return dev;
939 }
940
build_gsi_link_dev(const char * name,uint8_t uid,uint8_t gsi)941 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
942 {
943 Aml *dev;
944 Aml *crs;
945 Aml *method;
946 uint32_t irqs;
947
948 dev = aml_device("%s", name);
949 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
950 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
951
952 crs = aml_resource_template();
953 irqs = gsi;
954 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
955 AML_SHARED, &irqs, 1));
956 aml_append(dev, aml_name_decl("_PRS", crs));
957
958 aml_append(dev, aml_name_decl("_CRS", crs));
959
960 /*
961 * _DIS can be no-op because the interrupt cannot be disabled.
962 */
963 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
964 aml_append(dev, method);
965
966 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
967 aml_append(dev, method);
968
969 return dev;
970 }
971
972 /* _CRS method - get current settings */
build_iqcr_method(bool is_piix4)973 static Aml *build_iqcr_method(bool is_piix4)
974 {
975 Aml *if_ctx;
976 uint32_t irqs;
977 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
978 Aml *crs = aml_resource_template();
979
980 irqs = 0;
981 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
982 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
983 aml_append(method, aml_name_decl("PRR0", crs));
984
985 aml_append(method,
986 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
987
988 if (is_piix4) {
989 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
990 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
991 aml_append(method, if_ctx);
992 } else {
993 aml_append(method,
994 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
995 aml_name("PRRI")));
996 }
997
998 aml_append(method, aml_return(aml_name("PRR0")));
999 return method;
1000 }
1001
1002 /* _STA method - get status */
build_irq_status_method(void)1003 static Aml *build_irq_status_method(void)
1004 {
1005 Aml *if_ctx;
1006 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1007
1008 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1009 aml_append(if_ctx, aml_return(aml_int(0x09)));
1010 aml_append(method, if_ctx);
1011 aml_append(method, aml_return(aml_int(0x0B)));
1012 return method;
1013 }
1014
build_piix4_pci0_int(Aml * table)1015 static void build_piix4_pci0_int(Aml *table)
1016 {
1017 Aml *dev;
1018 Aml *crs;
1019 Aml *method;
1020 uint32_t irqs;
1021 Aml *sb_scope = aml_scope("_SB");
1022 Aml *pci0_scope = aml_scope("PCI0");
1023
1024 aml_append(pci0_scope, build_prt(true));
1025 aml_append(sb_scope, pci0_scope);
1026
1027 aml_append(sb_scope, build_irq_status_method());
1028 aml_append(sb_scope, build_iqcr_method(true));
1029
1030 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1031 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1032 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1033 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1034
1035 dev = aml_device("LNKS");
1036 {
1037 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1038 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1039
1040 crs = aml_resource_template();
1041 irqs = 9;
1042 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1043 AML_ACTIVE_HIGH, AML_SHARED,
1044 &irqs, 1));
1045 aml_append(dev, aml_name_decl("_PRS", crs));
1046
1047 /* The SCI cannot be disabled and is always attached to GSI 9,
1048 * so these are no-ops. We only need this link to override the
1049 * polarity to active high and match the content of the MADT.
1050 */
1051 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1052 aml_append(method, aml_return(aml_int(0x0b)));
1053 aml_append(dev, method);
1054
1055 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1056 aml_append(dev, method);
1057
1058 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1059 aml_append(method, aml_return(aml_name("_PRS")));
1060 aml_append(dev, method);
1061
1062 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1063 aml_append(dev, method);
1064 }
1065 aml_append(sb_scope, dev);
1066
1067 aml_append(table, sb_scope);
1068 }
1069
append_q35_prt_entry(Aml * ctx,uint32_t nr,const char * name)1070 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1071 {
1072 int i;
1073 int head;
1074 Aml *pkg;
1075 char base = name[3] < 'E' ? 'A' : 'E';
1076 char *s = g_strdup(name);
1077 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1078
1079 assert(strlen(s) == 4);
1080
1081 head = name[3] - base;
1082 for (i = 0; i < 4; i++) {
1083 if (head + i > 3) {
1084 head = i * -1;
1085 }
1086 s[3] = base + head + i;
1087 pkg = aml_package(4);
1088 aml_append(pkg, a_nr);
1089 aml_append(pkg, aml_int(i));
1090 aml_append(pkg, aml_name("%s", s));
1091 aml_append(pkg, aml_int(0));
1092 aml_append(ctx, pkg);
1093 }
1094 g_free(s);
1095 }
1096
build_q35_routing_table(const char * str)1097 static Aml *build_q35_routing_table(const char *str)
1098 {
1099 int i;
1100 Aml *pkg;
1101 char *name = g_strdup_printf("%s ", str);
1102
1103 pkg = aml_package(128);
1104 for (i = 0; i < 0x18; i++) {
1105 name[3] = 'E' + (i & 0x3);
1106 append_q35_prt_entry(pkg, i, name);
1107 }
1108
1109 name[3] = 'E';
1110 append_q35_prt_entry(pkg, 0x18, name);
1111
1112 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1113 for (i = 0x0019; i < 0x1e; i++) {
1114 name[3] = 'A';
1115 append_q35_prt_entry(pkg, i, name);
1116 }
1117
1118 /* PCIe->PCI bridge. use PIRQ[E-H] */
1119 name[3] = 'E';
1120 append_q35_prt_entry(pkg, 0x1e, name);
1121 name[3] = 'A';
1122 append_q35_prt_entry(pkg, 0x1f, name);
1123
1124 g_free(name);
1125 return pkg;
1126 }
1127
build_q35_pci0_int(Aml * table)1128 static void build_q35_pci0_int(Aml *table)
1129 {
1130 Aml *method;
1131 Aml *sb_scope = aml_scope("_SB");
1132 Aml *pci0_scope = aml_scope("PCI0");
1133
1134 /* Zero => PIC mode, One => APIC Mode */
1135 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1136 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1137 {
1138 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1139 }
1140 aml_append(table, method);
1141
1142 aml_append(pci0_scope,
1143 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1144 aml_append(pci0_scope,
1145 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1146
1147 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1148 {
1149 Aml *if_ctx;
1150 Aml *else_ctx;
1151
1152 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1153 section 6.2.8.1 */
1154 /* Note: we provide the same info as the PCI routing
1155 table of the Bochs BIOS */
1156 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1157 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1158 aml_append(method, if_ctx);
1159 else_ctx = aml_else();
1160 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1161 aml_append(method, else_ctx);
1162 }
1163 aml_append(pci0_scope, method);
1164 aml_append(sb_scope, pci0_scope);
1165
1166 aml_append(sb_scope, build_irq_status_method());
1167 aml_append(sb_scope, build_iqcr_method(false));
1168
1169 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1170 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1171 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1172 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1173 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1174 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1175 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1176 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1177
1178 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1179 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1180 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1181 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1182 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1183 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1184 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1185 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1186
1187 aml_append(table, sb_scope);
1188 }
1189
build_q35_dram_controller(const AcpiMcfgInfo * mcfg)1190 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg)
1191 {
1192 Aml *dev;
1193 Aml *resource_template;
1194
1195 /* DRAM controller */
1196 dev = aml_device("DRAC");
1197 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01")));
1198
1199 resource_template = aml_resource_template();
1200 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) {
1201 aml_append(resource_template,
1202 aml_qword_memory(AML_POS_DECODE,
1203 AML_MIN_FIXED,
1204 AML_MAX_FIXED,
1205 AML_NON_CACHEABLE,
1206 AML_READ_WRITE,
1207 0x0000000000000000,
1208 mcfg->base,
1209 mcfg->base + mcfg->size - 1,
1210 0x0000000000000000,
1211 mcfg->size));
1212 } else {
1213 aml_append(resource_template,
1214 aml_dword_memory(AML_POS_DECODE,
1215 AML_MIN_FIXED,
1216 AML_MAX_FIXED,
1217 AML_NON_CACHEABLE,
1218 AML_READ_WRITE,
1219 0x0000000000000000,
1220 mcfg->base,
1221 mcfg->base + mcfg->size - 1,
1222 0x0000000000000000,
1223 mcfg->size));
1224 }
1225 aml_append(dev, aml_name_decl("_CRS", resource_template));
1226
1227 return dev;
1228 }
1229
build_x86_acpi_pci_hotplug(Aml * table,uint64_t pcihp_addr)1230 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr)
1231 {
1232 Aml *scope;
1233 Aml *field;
1234 Aml *method;
1235
1236 scope = aml_scope("_SB.PCI0");
1237
1238 aml_append(scope,
1239 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08));
1240 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1241 aml_append(field, aml_named_field("PCIU", 32));
1242 aml_append(field, aml_named_field("PCID", 32));
1243 aml_append(scope, field);
1244
1245 aml_append(scope,
1246 aml_operation_region("SEJ", AML_SYSTEM_IO,
1247 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04));
1248 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1249 aml_append(field, aml_named_field("B0EJ", 32));
1250 aml_append(scope, field);
1251
1252 aml_append(scope,
1253 aml_operation_region("BNMR", AML_SYSTEM_IO,
1254 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08));
1255 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1256 aml_append(field, aml_named_field("BNUM", 32));
1257 aml_append(field, aml_named_field("PIDX", 32));
1258 aml_append(scope, field);
1259
1260 aml_append(scope, aml_mutex("BLCK", 0));
1261
1262 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1263 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1264 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1265 aml_append(method,
1266 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1267 aml_append(method, aml_release(aml_name("BLCK")));
1268 aml_append(method, aml_return(aml_int(0)));
1269 aml_append(scope, method);
1270
1271 method = aml_method("AIDX", 2, AML_NOTSERIALIZED);
1272 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1273 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1274 aml_append(method,
1275 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX")));
1276 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0)));
1277 aml_append(method, aml_release(aml_name("BLCK")));
1278 aml_append(method, aml_return(aml_local(0)));
1279 aml_append(scope, method);
1280
1281 aml_append(scope, aml_pci_pdsm());
1282
1283 aml_append(table, scope);
1284 }
1285
build_q35_osc_method(bool enable_native_pcie_hotplug)1286 static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug)
1287 {
1288 Aml *if_ctx;
1289 Aml *if_ctx2;
1290 Aml *else_ctx;
1291 Aml *method;
1292 Aml *a_cwd1 = aml_name("CDW1");
1293 Aml *a_ctrl = aml_local(0);
1294
1295 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1296 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1297
1298 if_ctx = aml_if(aml_equal(
1299 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1300 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1301 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1302
1303 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1304
1305 /*
1306 * Always allow native PME, AER (no dependencies)
1307 * Allow SHPC (PCI bridges can have SHPC controller)
1308 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled.
1309 */
1310 aml_append(if_ctx, aml_and(a_ctrl,
1311 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl));
1312
1313 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1314 /* Unknown revision */
1315 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1316 aml_append(if_ctx, if_ctx2);
1317
1318 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1319 /* Capabilities bits were masked */
1320 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1321 aml_append(if_ctx, if_ctx2);
1322
1323 /* Update DWORD3 in the buffer */
1324 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1325 aml_append(method, if_ctx);
1326
1327 else_ctx = aml_else();
1328 /* Unrecognized UUID */
1329 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1330 aml_append(method, else_ctx);
1331
1332 aml_append(method, aml_return(aml_arg(3)));
1333 return method;
1334 }
1335
build_acpi0017(Aml * table)1336 static void build_acpi0017(Aml *table)
1337 {
1338 Aml *dev, *scope, *method;
1339
1340 scope = aml_scope("_SB");
1341 dev = aml_device("CXLM");
1342 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017")));
1343
1344 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1345 aml_append(method, aml_return(aml_int(0x0B)));
1346 aml_append(dev, method);
1347 build_cxl_dsm_method(dev);
1348
1349 aml_append(scope, dev);
1350 aml_append(table, scope);
1351 }
1352
1353 static void
build_dsdt(GArray * table_data,BIOSLinker * linker,AcpiPmInfo * pm,AcpiMiscInfo * misc,Range * pci_hole,Range * pci_hole64,MachineState * machine)1354 build_dsdt(GArray *table_data, BIOSLinker *linker,
1355 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1356 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1357 {
1358 Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE,
1359 NULL);
1360 Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE, NULL);
1361 CrsRangeEntry *entry;
1362 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1363 CrsRangeSet crs_range_set;
1364 PCMachineState *pcms = PC_MACHINE(machine);
1365 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1366 X86MachineState *x86ms = X86_MACHINE(machine);
1367 AcpiMcfgInfo mcfg;
1368 bool mcfg_valid = !!acpi_get_mcfg(&mcfg);
1369 uint32_t nr_mem = machine->ram_slots;
1370 int root_bus_limit = 0xFF;
1371 PCIBus *bus = NULL;
1372 #ifdef CONFIG_TPM
1373 TPMIf *tpm = tpm_find();
1374 #endif
1375 bool cxl_present = false;
1376 int i;
1377 VMBusBridge *vmbus_bridge = vmbus_bridge_find();
1378 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id,
1379 .oem_table_id = x86ms->oem_table_id };
1380
1381 assert(!!i440fx != !!q35);
1382
1383 acpi_table_begin(&table, table_data);
1384 dsdt = init_aml_allocator();
1385
1386 build_dbg_aml(dsdt);
1387 if (i440fx) {
1388 sb_scope = aml_scope("_SB");
1389 dev = aml_device("PCI0");
1390 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1391 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
1392 aml_append(dev, aml_pci_edsm());
1393 aml_append(sb_scope, dev);
1394 aml_append(dsdt, sb_scope);
1395
1396 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1397 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
1398 }
1399 build_piix4_pci0_int(dsdt);
1400 } else if (q35) {
1401 sb_scope = aml_scope("_SB");
1402 dev = aml_device("PCI0");
1403 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1404 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1405 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
1406 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en));
1407 aml_append(dev, aml_pci_edsm());
1408 aml_append(sb_scope, dev);
1409 if (mcfg_valid) {
1410 aml_append(sb_scope, build_q35_dram_controller(&mcfg));
1411 }
1412
1413 if (pm->smi_on_cpuhp) {
1414 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */
1415 dev = aml_device("PCI0.SMI0");
1416 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1417 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources")));
1418 crs = aml_resource_template();
1419 aml_append(crs,
1420 aml_io(
1421 AML_DECODE16,
1422 pm->fadt.smi_cmd,
1423 pm->fadt.smi_cmd,
1424 1,
1425 2)
1426 );
1427 aml_append(dev, aml_name_decl("_CRS", crs));
1428 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO,
1429 aml_int(pm->fadt.smi_cmd), 2));
1430 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK,
1431 AML_WRITE_AS_ZEROS);
1432 aml_append(field, aml_named_field("SMIC", 8));
1433 aml_append(field, aml_reserved_field(8));
1434 aml_append(dev, field);
1435 aml_append(sb_scope, dev);
1436 }
1437
1438 aml_append(dsdt, sb_scope);
1439
1440 if (pm->pcihp_bridge_en) {
1441 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
1442 }
1443 build_q35_pci0_int(dsdt);
1444 }
1445
1446 if (misc->has_hpet) {
1447 build_hpet_aml(dsdt);
1448 }
1449
1450 if (vmbus_bridge) {
1451 sb_scope = aml_scope("_SB");
1452 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge));
1453 aml_append(dsdt, sb_scope);
1454 }
1455
1456 scope = aml_scope("_GPE");
1457 {
1458 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1459 if (machine->nvdimms_state->is_enabled) {
1460 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1461 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1462 aml_int(0x80)));
1463 aml_append(scope, method);
1464 }
1465 }
1466 aml_append(dsdt, scope);
1467
1468 if (pcmc->legacy_cpu_hotplug) {
1469 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1470 } else {
1471 CPUHotplugFeatures opts = {
1472 .acpi_1_compatible = true, .has_legacy_cphp = true,
1473 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL,
1474 .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
1475 };
1476 build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry,
1477 pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02",
1478 AML_SYSTEM_IO);
1479 }
1480
1481 if (pcms->memhp_io_base && nr_mem) {
1482 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
1483 "\\_GPE._E03", AML_SYSTEM_IO,
1484 pcms->memhp_io_base);
1485 }
1486
1487 crs_range_set_init(&crs_range_set);
1488 bus = PC_MACHINE(machine)->pcibus;
1489 if (bus) {
1490 QLIST_FOREACH(bus, &bus->child, sibling) {
1491 uint8_t bus_num = pci_bus_num(bus);
1492 uint8_t numa_node = pci_bus_numa_node(bus);
1493 uint32_t uid;
1494
1495 /* look only for expander root buses */
1496 if (!pci_bus_is_root(bus)) {
1497 continue;
1498 }
1499
1500 if (bus_num < root_bus_limit) {
1501 root_bus_limit = bus_num - 1;
1502 }
1503
1504 uid = object_property_get_uint(OBJECT(bus), "acpi_uid",
1505 &error_fatal);
1506 scope = aml_scope("\\_SB");
1507
1508 if (pci_bus_is_cxl(bus)) {
1509 dev = aml_device("CL%.02X", bus_num);
1510 } else {
1511 dev = aml_device("PC%.02X", bus_num);
1512 }
1513 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1514 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1515 if (pci_bus_is_cxl(bus)) {
1516 struct Aml *aml_pkg = aml_package(2);
1517
1518 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016")));
1519 aml_append(aml_pkg, aml_eisaid("PNP0A08"));
1520 aml_append(aml_pkg, aml_eisaid("PNP0A03"));
1521 aml_append(dev, aml_name_decl("_CID", aml_pkg));
1522 build_cxl_osc_method(dev);
1523 } else if (pci_bus_is_express(bus)) {
1524 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1525 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1526
1527 /* Expander bridges do not have ACPI PCI Hot-plug enabled */
1528 aml_append(dev, build_q35_osc_method(true));
1529 } else {
1530 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1531 }
1532
1533 if (numa_node != NUMA_NODE_UNASSIGNED) {
1534 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1535 }
1536
1537 aml_append(dev, build_prt(false));
1538 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
1539 0, 0, 0, 0);
1540 aml_append(dev, aml_name_decl("_CRS", crs));
1541 aml_append(scope, dev);
1542 aml_append(dsdt, scope);
1543
1544 /* Handle the ranges for the PXB expanders */
1545 if (pci_bus_is_cxl(bus)) {
1546 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
1547 uint64_t base = mr->addr;
1548
1549 cxl_present = true;
1550 crs_range_insert(crs_range_set.mem_ranges, base,
1551 base + memory_region_size(mr) - 1);
1552 }
1553 }
1554 }
1555
1556 if (cxl_present) {
1557 build_acpi0017(dsdt);
1558 }
1559
1560 /*
1561 * At this point crs_range_set has all the ranges used by pci
1562 * busses *other* than PCI0. These ranges will be excluded from
1563 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1564 * too.
1565 */
1566 if (mcfg_valid) {
1567 crs_range_insert(crs_range_set.mem_ranges,
1568 mcfg.base, mcfg.base + mcfg.size - 1);
1569 }
1570
1571 scope = aml_scope("\\_SB.PCI0");
1572 /* build PCI0._CRS */
1573 crs = aml_resource_template();
1574 aml_append(crs,
1575 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1576 0x0000, 0x0, root_bus_limit,
1577 0x0000, root_bus_limit + 1));
1578 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1579
1580 aml_append(crs,
1581 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1582 AML_POS_DECODE, AML_ENTIRE_RANGE,
1583 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1584
1585 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1586 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1587 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1588 aml_append(crs,
1589 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1590 AML_POS_DECODE, AML_ENTIRE_RANGE,
1591 0x0000, entry->base, entry->limit,
1592 0x0000, entry->limit - entry->base + 1));
1593 }
1594
1595 aml_append(crs,
1596 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1597 AML_CACHEABLE, AML_READ_WRITE,
1598 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1599
1600 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
1601 range_lob(pci_hole),
1602 range_upb(pci_hole));
1603 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1604 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
1605 aml_append(crs,
1606 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1607 AML_NON_CACHEABLE, AML_READ_WRITE,
1608 0, entry->base, entry->limit,
1609 0, entry->limit - entry->base + 1));
1610 }
1611
1612 if (!range_is_empty(pci_hole64)) {
1613 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1614 range_lob(pci_hole64),
1615 range_upb(pci_hole64));
1616 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1617 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1618 aml_append(crs,
1619 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1620 AML_MAX_FIXED,
1621 AML_CACHEABLE, AML_READ_WRITE,
1622 0, entry->base, entry->limit,
1623 0, entry->limit - entry->base + 1));
1624 }
1625 }
1626
1627 #ifdef CONFIG_TPM
1628 if (TPM_IS_TIS_ISA(tpm_find())) {
1629 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1630 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1631 }
1632 #endif
1633 aml_append(scope, aml_name_decl("_CRS", crs));
1634
1635 /* reserve GPE0 block resources */
1636 dev = aml_device("GPE0");
1637 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1638 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1639 /* device present, functioning, decoding, not shown in UI */
1640 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1641 crs = aml_resource_template();
1642 aml_append(crs,
1643 aml_io(
1644 AML_DECODE16,
1645 pm->fadt.gpe0_blk.address,
1646 pm->fadt.gpe0_blk.address,
1647 1,
1648 pm->fadt.gpe0_blk.bit_width / 8)
1649 );
1650 aml_append(dev, aml_name_decl("_CRS", crs));
1651 aml_append(scope, dev);
1652
1653 crs_range_set_free(&crs_range_set);
1654
1655 /* reserve PCIHP resources */
1656 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
1657 dev = aml_device("PHPR");
1658 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1659 aml_append(dev,
1660 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1661 /* device present, functioning, decoding, not shown in UI */
1662 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1663 crs = aml_resource_template();
1664 aml_append(crs,
1665 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
1666 pm->pcihp_io_len)
1667 );
1668 aml_append(dev, aml_name_decl("_CRS", crs));
1669 aml_append(scope, dev);
1670 }
1671 aml_append(dsdt, scope);
1672
1673 /* create S3_ / S4_ / S5_ packages if necessary */
1674 scope = aml_scope("\\");
1675 if (!pm->s3_disabled) {
1676 pkg = aml_package(4);
1677 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1678 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1679 aml_append(pkg, aml_int(0)); /* reserved */
1680 aml_append(pkg, aml_int(0)); /* reserved */
1681 aml_append(scope, aml_name_decl("_S3", pkg));
1682 }
1683
1684 if (!pm->s4_disabled) {
1685 pkg = aml_package(4);
1686 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1687 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1688 aml_append(pkg, aml_int(pm->s4_val));
1689 aml_append(pkg, aml_int(0)); /* reserved */
1690 aml_append(pkg, aml_int(0)); /* reserved */
1691 aml_append(scope, aml_name_decl("_S4", pkg));
1692 }
1693
1694 pkg = aml_package(4);
1695 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1696 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1697 aml_append(pkg, aml_int(0)); /* reserved */
1698 aml_append(pkg, aml_int(0)); /* reserved */
1699 aml_append(scope, aml_name_decl("_S5", pkg));
1700 aml_append(dsdt, scope);
1701
1702 /* create fw_cfg node, unconditionally */
1703 {
1704 scope = aml_scope("\\_SB.PCI0");
1705 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg);
1706 aml_append(dsdt, scope);
1707 }
1708
1709 sb_scope = aml_scope("\\_SB");
1710 {
1711 Object *pci_host = acpi_get_i386_pci_host();
1712
1713 if (pci_host) {
1714 PCIBus *pbus = PCI_HOST_BRIDGE(pci_host)->bus;
1715 Aml *ascope = aml_scope("PCI0");
1716 /* Scan all PCI buses. Generate tables to support hotplug. */
1717 build_append_pci_bus_devices(ascope, pbus);
1718 if (object_property_find(OBJECT(pbus), ACPI_PCIHP_PROP_BSEL)) {
1719 build_append_pcihp_slots(ascope, pbus);
1720 }
1721 aml_append(sb_scope, ascope);
1722 }
1723 }
1724
1725 #ifdef CONFIG_TPM
1726 if (TPM_IS_CRB(tpm)) {
1727 dev = aml_device("TPM");
1728 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
1729 aml_append(dev, aml_name_decl("_STR",
1730 aml_string("TPM 2.0 Device")));
1731 crs = aml_resource_template();
1732 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
1733 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
1734 aml_append(dev, aml_name_decl("_CRS", crs));
1735
1736 aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
1737 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1738
1739 tpm_build_ppi_acpi(tpm, dev);
1740
1741 aml_append(sb_scope, dev);
1742 }
1743 #endif
1744
1745 if (pcms->sgx_epc.size != 0) {
1746 uint64_t epc_base = pcms->sgx_epc.base;
1747 uint64_t epc_size = pcms->sgx_epc.size;
1748
1749 dev = aml_device("EPC");
1750 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C")));
1751 aml_append(dev, aml_name_decl("_STR",
1752 aml_unicode("Enclave Page Cache 1.0")));
1753 crs = aml_resource_template();
1754 aml_append(crs,
1755 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1756 AML_MAX_FIXED, AML_NON_CACHEABLE,
1757 AML_READ_WRITE, 0, epc_base,
1758 epc_base + epc_size - 1, 0, epc_size));
1759 aml_append(dev, aml_name_decl("_CRS", crs));
1760
1761 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1762 aml_append(method, aml_return(aml_int(0x0f)));
1763 aml_append(dev, method);
1764
1765 aml_append(sb_scope, dev);
1766 }
1767 aml_append(dsdt, sb_scope);
1768
1769 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1770 bool has_pcnt;
1771
1772 Object *pci_host = acpi_get_i386_pci_host();
1773 PCIBus *b = PCI_HOST_BRIDGE(pci_host)->bus;
1774
1775 scope = aml_scope("\\_SB.PCI0");
1776 has_pcnt = build_append_notification_callback(scope, b);
1777 if (has_pcnt) {
1778 aml_append(dsdt, scope);
1779 }
1780
1781 scope = aml_scope("_GPE");
1782 {
1783 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1784 if (has_pcnt) {
1785 aml_append(method,
1786 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1787 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1788 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1789 }
1790 aml_append(scope, method);
1791 }
1792 aml_append(dsdt, scope);
1793 }
1794
1795 /* copy AML table into ACPI tables blob and patch header there */
1796 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
1797 acpi_table_end(linker, &table);
1798 free_aml_allocator();
1799 }
1800
1801 /*
1802 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a)
1803 * 3.2.4The ACPI 2.0 HPET Description Table (HPET)
1804 */
1805 static void
build_hpet(GArray * table_data,BIOSLinker * linker,const char * oem_id,const char * oem_table_id)1806 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
1807 const char *oem_table_id)
1808 {
1809 AcpiTable table = { .sig = "HPET", .rev = 1,
1810 .oem_id = oem_id, .oem_table_id = oem_table_id };
1811
1812 acpi_table_begin(&table, table_data);
1813 /* Note timer_block_id value must be kept in sync with value advertised by
1814 * emulated hpet
1815 */
1816 /* Event Timer Block ID */
1817 build_append_int_noprefix(table_data, 0x8086a201, 4);
1818 /* BASE_ADDRESS */
1819 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE);
1820 /* HPET Number */
1821 build_append_int_noprefix(table_data, 0, 1);
1822 /* Main Counter Minimum Clock_tick in Periodic Mode */
1823 build_append_int_noprefix(table_data, 0, 2);
1824 /* Page Protection And OEM Attribute */
1825 build_append_int_noprefix(table_data, 0, 1);
1826 acpi_table_end(linker, &table);
1827 }
1828
1829 #ifdef CONFIG_TPM
1830 /*
1831 * TCPA Description Table
1832 *
1833 * Following Level 00, Rev 00.37 of specs:
1834 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification
1835 * 7.1.2 ACPI Table Layout
1836 */
1837 static void
build_tpm_tcpa(GArray * table_data,BIOSLinker * linker,GArray * tcpalog,const char * oem_id,const char * oem_table_id)1838 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
1839 const char *oem_id, const char *oem_table_id)
1840 {
1841 unsigned log_addr_offset;
1842 AcpiTable table = { .sig = "TCPA", .rev = 2,
1843 .oem_id = oem_id, .oem_table_id = oem_table_id };
1844
1845 acpi_table_begin(&table, table_data);
1846 /* Platform Class */
1847 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2);
1848 /* Log Area Minimum Length (LAML) */
1849 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4);
1850 /* Log Area Start Address (LASA) */
1851 log_addr_offset = table_data->len;
1852 build_append_int_noprefix(table_data, 0, 8);
1853
1854 /* allocate/reserve space for TPM log area */
1855 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
1856 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
1857 false /* high memory */);
1858 /* log area start address to be filled by Guest linker */
1859 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
1860 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0);
1861
1862 acpi_table_end(linker, &table);
1863 }
1864 #endif
1865
1866 #define HOLE_640K_START (640 * KiB)
1867 #define HOLE_640K_END (1 * MiB)
1868
1869 /*
1870 * ACPI spec, Revision 3.0
1871 * 5.2.15 System Resource Affinity Table (SRAT)
1872 */
1873 static void
build_srat(GArray * table_data,BIOSLinker * linker,MachineState * machine)1874 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
1875 {
1876 int i;
1877 int numa_mem_start, slots;
1878 uint64_t mem_len, mem_base, next_base;
1879 MachineClass *mc = MACHINE_GET_CLASS(machine);
1880 X86MachineState *x86ms = X86_MACHINE(machine);
1881 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
1882 int nb_numa_nodes = machine->numa_state->num_nodes;
1883 NodeInfo *numa_info = machine->numa_state->nodes;
1884 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id,
1885 .oem_table_id = x86ms->oem_table_id };
1886
1887 acpi_table_begin(&table, table_data);
1888 build_append_int_noprefix(table_data, 1, 4); /* Reserved */
1889 build_append_int_noprefix(table_data, 0, 8); /* Reserved */
1890
1891 for (i = 0; i < apic_ids->len; i++) {
1892 int node_id = apic_ids->cpus[i].props.node_id;
1893 uint32_t apic_id = apic_ids->cpus[i].arch_id;
1894
1895 if (apic_id < 255) {
1896 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */
1897 build_append_int_noprefix(table_data, 0, 1); /* Type */
1898 build_append_int_noprefix(table_data, 16, 1); /* Length */
1899 /* Proximity Domain [7:0] */
1900 build_append_int_noprefix(table_data, node_id, 1);
1901 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */
1902 /* Flags, Table 5-36 */
1903 build_append_int_noprefix(table_data, 1, 4);
1904 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */
1905 /* Proximity Domain [31:8] */
1906 build_append_int_noprefix(table_data, 0, 3);
1907 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
1908 } else {
1909 /*
1910 * ACPI spec, Revision 4.0
1911 * 5.2.16.3 Processor Local x2APIC Affinity Structure
1912 */
1913 build_append_int_noprefix(table_data, 2, 1); /* Type */
1914 build_append_int_noprefix(table_data, 24, 1); /* Length */
1915 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
1916 /* Proximity Domain */
1917 build_append_int_noprefix(table_data, node_id, 4);
1918 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */
1919 /* Flags, Table 5-39 */
1920 build_append_int_noprefix(table_data, 1 /* Enabled */, 4);
1921 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
1922 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
1923 }
1924 }
1925
1926 /* the memory map is a bit tricky, it contains at least one hole
1927 * from 640k-1M and possibly another one from 3.5G-4G.
1928 */
1929 next_base = 0;
1930 numa_mem_start = table_data->len;
1931
1932 for (i = 1; i < nb_numa_nodes + 1; ++i) {
1933 mem_base = next_base;
1934 mem_len = numa_info[i - 1].node_mem;
1935 next_base = mem_base + mem_len;
1936
1937 /* Cut out the 640K hole */
1938 if (mem_base <= HOLE_640K_START &&
1939 next_base > HOLE_640K_START) {
1940 mem_len -= next_base - HOLE_640K_START;
1941 if (mem_len > 0) {
1942 build_srat_memory(table_data, mem_base, mem_len, i - 1,
1943 MEM_AFFINITY_ENABLED);
1944 }
1945
1946 /* Check for the rare case: 640K < RAM < 1M */
1947 if (next_base <= HOLE_640K_END) {
1948 next_base = HOLE_640K_END;
1949 continue;
1950 }
1951 mem_base = HOLE_640K_END;
1952 mem_len = next_base - HOLE_640K_END;
1953 }
1954
1955 /* Cut out the ACPI_PCI hole */
1956 if (mem_base <= x86ms->below_4g_mem_size &&
1957 next_base > x86ms->below_4g_mem_size) {
1958 mem_len -= next_base - x86ms->below_4g_mem_size;
1959 if (mem_len > 0) {
1960 build_srat_memory(table_data, mem_base, mem_len, i - 1,
1961 MEM_AFFINITY_ENABLED);
1962 }
1963 mem_base = x86ms->above_4g_mem_start;
1964 mem_len = next_base - x86ms->below_4g_mem_size;
1965 next_base = mem_base + mem_len;
1966 }
1967
1968 if (mem_len > 0) {
1969 build_srat_memory(table_data, mem_base, mem_len, i - 1,
1970 MEM_AFFINITY_ENABLED);
1971 }
1972 }
1973
1974 if (machine->nvdimms_state->is_enabled) {
1975 nvdimm_build_srat(table_data);
1976 }
1977
1978 sgx_epc_build_srat(table_data);
1979
1980 /*
1981 * TODO: this part is not in ACPI spec and current linux kernel boots fine
1982 * without these entries. But I recall there were issues the last time I
1983 * tried to remove it with some ancient guest OS, however I can't remember
1984 * what that was so keep this around for now
1985 */
1986 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */;
1987 for (; slots < nb_numa_nodes + 2; slots++) {
1988 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
1989 }
1990
1991 build_srat_generic_affinity_structures(table_data);
1992
1993 /*
1994 * Entry is required for Windows to enable memory hotplug in OS
1995 * and for Linux to enable SWIOTLB when booted with less than
1996 * 4G of RAM. Windows works better if the entry sets proximity
1997 * to the highest NUMA node in the machine.
1998 * Memory devices may override proximity set by this entry,
1999 * providing _PXM method if necessary.
2000 */
2001 if (machine->device_memory) {
2002 build_srat_memory(table_data, machine->device_memory->base,
2003 memory_region_size(&machine->device_memory->mr),
2004 nb_numa_nodes - 1,
2005 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2006 }
2007
2008 acpi_table_end(linker, &table);
2009 }
2010
2011 /*
2012 * Insert DMAR scope for PCI bridges and endpoint devices
2013 */
2014 static void
insert_scope(PCIBus * bus,PCIDevice * dev,void * opaque)2015 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque)
2016 {
2017 const size_t device_scope_size = 6 /* device scope structure */ +
2018 2 /* 1 path entry */;
2019 GArray *scope_blob = opaque;
2020
2021 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2022 /* Dmar Scope Type: 0x02 for PCI Bridge */
2023 build_append_int_noprefix(scope_blob, 0x02, 1);
2024 } else {
2025 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */
2026 build_append_int_noprefix(scope_blob, 0x01, 1);
2027 }
2028
2029 /* length */
2030 build_append_int_noprefix(scope_blob, device_scope_size, 1);
2031 /* reserved */
2032 build_append_int_noprefix(scope_blob, 0, 2);
2033 /* enumeration_id */
2034 build_append_int_noprefix(scope_blob, 0, 1);
2035 /* bus */
2036 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1);
2037 /* device */
2038 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1);
2039 /* function */
2040 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1);
2041 }
2042
2043 /* For a given PCI host bridge, walk and insert DMAR scope */
2044 static int
dmar_host_bridges(Object * obj,void * opaque)2045 dmar_host_bridges(Object *obj, void *opaque)
2046 {
2047 GArray *scope_blob = opaque;
2048
2049 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2050 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2051
2052 if (bus && !pci_bus_bypass_iommu(bus)) {
2053 pci_for_each_device_under_bus(bus, insert_scope, scope_blob);
2054 }
2055 }
2056
2057 return 0;
2058 }
2059
2060 /*
2061 * Intel ® Virtualization Technology for Directed I/O
2062 * Architecture Specification. Revision 3.3
2063 * 8.1 DMA Remapping Reporting Structure
2064 */
2065 static void
build_dmar_q35(GArray * table_data,BIOSLinker * linker,const char * oem_id,const char * oem_table_id)2066 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2067 const char *oem_table_id)
2068 {
2069 uint8_t dmar_flags = 0;
2070 uint8_t rsvd10[10] = {};
2071 /* Root complex IOAPIC uses one path only */
2072 const size_t ioapic_scope_size = 6 /* device scope structure */ +
2073 2 /* 1 path entry */;
2074 X86IOMMUState *iommu = x86_iommu_get_default();
2075 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2076 GArray *scope_blob = g_array_new(false, true, 1);
2077
2078 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id,
2079 .oem_table_id = oem_table_id };
2080
2081 /*
2082 * A PCI bus walk, for each PCI host bridge.
2083 * Insert scope for each PCI bridge and endpoint device which
2084 * is attached to a bus with iommu enabled.
2085 */
2086 object_child_foreach_recursive(object_get_root(),
2087 dmar_host_bridges, scope_blob);
2088
2089 assert(iommu);
2090 if (x86_iommu_ir_supported(iommu)) {
2091 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2092 }
2093
2094 acpi_table_begin(&table, table_data);
2095 /* Host Address Width */
2096 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1);
2097 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */
2098 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */
2099
2100 /* 8.3 DMAR Remapping Hardware Unit Definition structure */
2101 build_append_int_noprefix(table_data, 0, 2); /* Type */
2102 /* Length */
2103 build_append_int_noprefix(table_data,
2104 16 + ioapic_scope_size + scope_blob->len, 2);
2105 /* Flags */
2106 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ ,
2107 1);
2108 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */
2109 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */
2110 /* Register Base Address */
2111 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8);
2112
2113 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2114 * 8.3.1 (version Oct. 2014 or later). */
2115 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */
2116 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */
2117 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
2118 /* Enumeration ID */
2119 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1);
2120 /* Start Bus Number */
2121 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1);
2122 /* Path, {Device, Function} pair */
2123 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1);
2124 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1);
2125
2126 /* Add scope found above */
2127 g_array_append_vals(table_data, scope_blob->data, scope_blob->len);
2128 g_array_free(scope_blob, true);
2129
2130 if (iommu->dt_supported) {
2131 /* 8.5 Root Port ATS Capability Reporting Structure */
2132 build_append_int_noprefix(table_data, 2, 2); /* Type */
2133 build_append_int_noprefix(table_data, 8, 2); /* Length */
2134 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */
2135 build_append_int_noprefix(table_data, 0, 1); /* Reserved */
2136 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */
2137 }
2138
2139 acpi_table_end(linker, &table);
2140 }
2141
2142 /*
2143 * Windows ACPI Emulated Devices Table
2144 * (Version 1.0 - April 6, 2009)
2145 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
2146 *
2147 * Helpful to speedup Windows guests and ignored by others.
2148 */
2149 static void
build_waet(GArray * table_data,BIOSLinker * linker,const char * oem_id,const char * oem_table_id)2150 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2151 const char *oem_table_id)
2152 {
2153 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id,
2154 .oem_table_id = oem_table_id };
2155
2156 acpi_table_begin(&table, table_data);
2157 /*
2158 * Set "ACPI PM timer good" flag.
2159 *
2160 * Tells Windows guests that our ACPI PM timer is reliable in the
2161 * sense that guest can read it only once to obtain a reliable value.
2162 * Which avoids costly VMExits caused by guest re-reading it unnecessarily.
2163 */
2164 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4);
2165 acpi_table_end(linker, &table);
2166 }
2167
2168 /*
2169 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2170 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2171 */
2172 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2173
2174 /*
2175 * Insert IVHD entry for device and recurse, insert alias, or insert range as
2176 * necessary for the PCI topology.
2177 */
2178 static void
insert_ivhd(PCIBus * bus,PCIDevice * dev,void * opaque)2179 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque)
2180 {
2181 GArray *table_data = opaque;
2182 uint32_t entry;
2183
2184 /* "Select" IVHD entry, type 0x2 */
2185 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2;
2186 build_append_int_noprefix(table_data, entry, 4);
2187
2188 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2189 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
2190 uint8_t sec = pci_bus_num(sec_bus);
2191 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS];
2192
2193 if (pci_bus_is_express(sec_bus)) {
2194 /*
2195 * Walk the bus if there are subordinates, otherwise use a range
2196 * to cover an entire leaf bus. We could potentially also use a
2197 * range for traversed buses, but we'd need to take care not to
2198 * create both Select and Range entries covering the same device.
2199 * This is easier and potentially more compact.
2200 *
2201 * An example bare metal system seems to use Select entries for
2202 * root ports without a slot (ie. built-ins) and Range entries
2203 * when there is a slot. The same system also only hard-codes
2204 * the alias range for an onboard PCIe-to-PCI bridge, apparently
2205 * making no effort to support nested bridges. We attempt to
2206 * be more thorough here.
2207 */
2208 if (sec == sub) { /* leaf bus */
2209 /* "Start of Range" IVHD entry, type 0x3 */
2210 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3;
2211 build_append_int_noprefix(table_data, entry, 4);
2212 /* "End of Range" IVHD entry, type 0x4 */
2213 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2214 build_append_int_noprefix(table_data, entry, 4);
2215 } else {
2216 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data);
2217 }
2218 } else {
2219 /*
2220 * If the secondary bus is conventional, then we need to create an
2221 * Alias range for everything downstream. The range covers the
2222 * first devfn on the secondary bus to the last devfn on the
2223 * subordinate bus. The alias target depends on legacy versus
2224 * express bridges, just as in pci_device_iommu_address_space().
2225 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
2226 */
2227 uint16_t dev_id_a, dev_id_b;
2228
2229 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0));
2230
2231 if (pci_is_express(dev) &&
2232 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
2233 dev_id_b = dev_id_a;
2234 } else {
2235 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn);
2236 }
2237
2238 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
2239 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4);
2240 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4);
2241
2242 /* "End of Range" IVHD entry, type 0x4 */
2243 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2244 build_append_int_noprefix(table_data, entry, 4);
2245 }
2246 }
2247 }
2248
2249 /* For all PCI host bridges, walk and insert IVHD entries */
2250 static int
ivrs_host_bridges(Object * obj,void * opaque)2251 ivrs_host_bridges(Object *obj, void *opaque)
2252 {
2253 GArray *ivhd_blob = opaque;
2254
2255 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2256 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2257
2258 if (bus && !pci_bus_bypass_iommu(bus)) {
2259 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob);
2260 }
2261 }
2262
2263 return 0;
2264 }
2265
2266 static void
build_amd_iommu(GArray * table_data,BIOSLinker * linker,const char * oem_id,const char * oem_table_id)2267 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2268 const char *oem_table_id)
2269 {
2270 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2271 GArray *ivhd_blob = g_array_new(false, true, 1);
2272 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id,
2273 .oem_table_id = oem_table_id };
2274 uint64_t feature_report;
2275
2276 acpi_table_begin(&table, table_data);
2277 /* IVinfo - IO virtualization information common to all
2278 * IOMMU units in a system
2279 */
2280 build_append_int_noprefix(table_data,
2281 (1UL << 0) | /* EFRSup */
2282 (40UL << 8), /* PASize */
2283 4);
2284 /* reserved */
2285 build_append_int_noprefix(table_data, 0, 8);
2286
2287 /*
2288 * A PCI bus walk, for each PCI host bridge, is necessary to create a
2289 * complete set of IVHD entries. Do this into a separate blob so that we
2290 * can calculate the total IVRS table length here and then append the new
2291 * blob further below. Fall back to an entry covering all devices, which
2292 * is sufficient when no aliases are present.
2293 */
2294 object_child_foreach_recursive(object_get_root(),
2295 ivrs_host_bridges, ivhd_blob);
2296
2297 if (!ivhd_blob->len) {
2298 /*
2299 * Type 1 device entry reporting all devices
2300 * These are 4-byte device entries currently reporting the range of
2301 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2302 */
2303 build_append_int_noprefix(ivhd_blob, 0x0000001, 4);
2304 }
2305
2306 /*
2307 * When interrupt remapping is supported, we add a special IVHD device
2308 * for type IO-APIC
2309 * Refer to spec - Table 95: IVHD device entry type codes
2310 *
2311 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2312 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2313 */
2314 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2315 build_append_int_noprefix(ivhd_blob,
2316 (0x1ull << 56) | /* type IOAPIC */
2317 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
2318 0x48, /* special device */
2319 8);
2320 }
2321
2322 /* IVHD definition - type 10h */
2323 build_append_int_noprefix(table_data, 0x10, 1);
2324 /* virtualization flags */
2325 build_append_int_noprefix(table_data,
2326 (1UL << 0) | /* HtTunEn */
2327 (1UL << 4) | /* iotblSup */
2328 (1UL << 6) | /* PrefSup */
2329 (1UL << 7), /* PPRSup */
2330 1);
2331
2332 /* IVHD length */
2333 build_append_int_noprefix(table_data, ivhd_blob->len + 24, 2);
2334 /* DeviceID */
2335 build_append_int_noprefix(table_data,
2336 object_property_get_int(OBJECT(s->pci), "addr",
2337 &error_abort), 2);
2338 /* Capability offset */
2339 build_append_int_noprefix(table_data, s->pci->capab_offset, 2);
2340 /* IOMMU base address */
2341 build_append_int_noprefix(table_data, s->mr_mmio.addr, 8);
2342 /* PCI Segment Group */
2343 build_append_int_noprefix(table_data, 0, 2);
2344 /* IOMMU info */
2345 build_append_int_noprefix(table_data, 0, 2);
2346 /* IOMMU Feature Reporting */
2347 feature_report = (48UL << 30) | /* HATS */
2348 (48UL << 28) | /* GATS */
2349 (1UL << 2) | /* GTSup */
2350 (1UL << 6); /* GASup */
2351 if (s->xtsup) {
2352 feature_report |= (1UL << 0); /* XTSup */
2353 }
2354 build_append_int_noprefix(table_data, feature_report, 4);
2355
2356 /* IVHD entries as found above */
2357 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
2358
2359 /* IVHD definition - type 11h */
2360 build_append_int_noprefix(table_data, 0x11, 1);
2361 /* virtualization flags */
2362 build_append_int_noprefix(table_data,
2363 (1UL << 0) | /* HtTunEn */
2364 (1UL << 4), /* iotblSup */
2365 1);
2366
2367 /* IVHD length */
2368 build_append_int_noprefix(table_data, ivhd_blob->len + 40, 2);
2369 /* DeviceID */
2370 build_append_int_noprefix(table_data,
2371 object_property_get_int(OBJECT(s->pci), "addr",
2372 &error_abort), 2);
2373 /* Capability offset */
2374 build_append_int_noprefix(table_data, s->pci->capab_offset, 2);
2375 /* IOMMU base address */
2376 build_append_int_noprefix(table_data, s->mr_mmio.addr, 8);
2377 /* PCI Segment Group */
2378 build_append_int_noprefix(table_data, 0, 2);
2379 /* IOMMU info */
2380 build_append_int_noprefix(table_data, 0, 2);
2381 /* IOMMU Attributes */
2382 build_append_int_noprefix(table_data, 0, 4);
2383 /* EFR Register Image */
2384 build_append_int_noprefix(table_data,
2385 amdvi_extended_feature_register(s),
2386 8);
2387 /* EFR Register Image 2 */
2388 build_append_int_noprefix(table_data, 0, 8);
2389
2390 /* IVHD entries as found above */
2391 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
2392
2393 g_array_free(ivhd_blob, TRUE);
2394 acpi_table_end(linker, &table);
2395 }
2396
2397 typedef
2398 struct AcpiBuildState {
2399 /* Copy of table in RAM (for patching). */
2400 MemoryRegion *table_mr;
2401 /* Is table patched? */
2402 uint8_t patched;
2403 MemoryRegion *rsdp_mr;
2404 MemoryRegion *linker_mr;
2405 } AcpiBuildState;
2406
acpi_get_mcfg(AcpiMcfgInfo * mcfg)2407 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2408 {
2409 Object *pci_host;
2410 QObject *o;
2411
2412 pci_host = acpi_get_i386_pci_host();
2413 if (!pci_host) {
2414 return false;
2415 }
2416
2417 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2418 if (!o) {
2419 return false;
2420 }
2421 mcfg->base = qnum_get_uint(qobject_to(QNum, o));
2422 qobject_unref(o);
2423 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) {
2424 return false;
2425 }
2426
2427 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2428 assert(o);
2429 mcfg->size = qnum_get_uint(qobject_to(QNum, o));
2430 qobject_unref(o);
2431 return true;
2432 }
2433
2434 static
acpi_build(AcpiBuildTables * tables,MachineState * machine)2435 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2436 {
2437 PCMachineState *pcms = PC_MACHINE(machine);
2438 X86MachineState *x86ms = X86_MACHINE(machine);
2439 DeviceState *iommu = pcms->iommu;
2440 GArray *table_offsets;
2441 unsigned facs, dsdt, rsdt;
2442 AcpiPmInfo pm;
2443 AcpiMiscInfo misc;
2444 AcpiMcfgInfo mcfg;
2445 Range pci_hole = {}, pci_hole64 = {};
2446 uint8_t *u;
2447 GArray *tables_blob = tables->table_data;
2448 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2449 Object *vmgenid_dev, *vmclock_dev;
2450 char *oem_id;
2451 char *oem_table_id;
2452
2453 acpi_get_pm_info(machine, &pm);
2454 acpi_get_misc_info(&misc);
2455 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2456 acpi_get_slic_oem(&slic_oem);
2457
2458 if (slic_oem.id) {
2459 oem_id = slic_oem.id;
2460 } else {
2461 oem_id = x86ms->oem_id;
2462 }
2463
2464 if (slic_oem.table_id) {
2465 oem_table_id = slic_oem.table_id;
2466 } else {
2467 oem_table_id = x86ms->oem_table_id;
2468 }
2469
2470 table_offsets = g_array_new(false, true /* clear */,
2471 sizeof(uint32_t));
2472 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2473
2474 bios_linker_loader_alloc(tables->linker,
2475 ACPI_BUILD_TABLE_FILE, tables_blob,
2476 64 /* Ensure FACS is aligned */,
2477 false /* high memory */);
2478
2479 /*
2480 * FACS is pointed to by FADT.
2481 * We place it first since it's the only table that has alignment
2482 * requirements.
2483 */
2484 facs = tables_blob->len;
2485 build_facs(tables_blob);
2486
2487 /* DSDT is pointed to by FADT */
2488 dsdt = tables_blob->len;
2489 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2490 &pci_hole, &pci_hole64, machine);
2491
2492 /* ACPI tables pointed to by RSDT */
2493 acpi_add_table(table_offsets, tables_blob);
2494 pm.fadt.facs_tbl_offset = &facs;
2495 pm.fadt.dsdt_tbl_offset = &dsdt;
2496 pm.fadt.xdsdt_tbl_offset = &dsdt;
2497 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id);
2498
2499 acpi_add_table(table_offsets, tables_blob);
2500 acpi_build_madt(tables_blob, tables->linker, x86ms,
2501 x86ms->oem_id, x86ms->oem_table_id);
2502
2503 #ifdef CONFIG_ACPI_ERST
2504 {
2505 Object *erst_dev;
2506 erst_dev = find_erst_dev();
2507 if (erst_dev) {
2508 acpi_add_table(table_offsets, tables_blob);
2509 build_erst(tables_blob, tables->linker, erst_dev,
2510 x86ms->oem_id, x86ms->oem_table_id);
2511 }
2512 }
2513 #endif
2514
2515 vmgenid_dev = find_vmgenid_dev();
2516 if (vmgenid_dev) {
2517 acpi_add_table(table_offsets, tables_blob);
2518 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2519 tables->vmgenid, tables->linker, x86ms->oem_id);
2520 }
2521
2522 vmclock_dev = find_vmclock_dev();
2523 if (vmclock_dev) {
2524 acpi_add_table(table_offsets, tables_blob);
2525 vmclock_build_acpi(VMCLOCK(vmclock_dev), tables_blob, tables->linker,
2526 x86ms->oem_id);
2527 }
2528
2529 if (misc.has_hpet) {
2530 acpi_add_table(table_offsets, tables_blob);
2531 build_hpet(tables_blob, tables->linker, x86ms->oem_id,
2532 x86ms->oem_table_id);
2533 }
2534 #ifdef CONFIG_TPM
2535 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2536 if (misc.tpm_version == TPM_VERSION_1_2) {
2537 acpi_add_table(table_offsets, tables_blob);
2538 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog,
2539 x86ms->oem_id, x86ms->oem_table_id);
2540 } else { /* TPM_VERSION_2_0 */
2541 acpi_add_table(table_offsets, tables_blob);
2542 build_tpm2(tables_blob, tables->linker, tables->tcpalog,
2543 x86ms->oem_id, x86ms->oem_table_id);
2544 }
2545 }
2546 #endif
2547 if (machine->numa_state->num_nodes) {
2548 acpi_add_table(table_offsets, tables_blob);
2549 build_srat(tables_blob, tables->linker, machine);
2550 if (machine->numa_state->have_numa_distance) {
2551 acpi_add_table(table_offsets, tables_blob);
2552 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id,
2553 x86ms->oem_table_id);
2554 }
2555 if (machine->numa_state->hmat_enabled) {
2556 acpi_add_table(table_offsets, tables_blob);
2557 build_hmat(tables_blob, tables->linker, machine->numa_state,
2558 x86ms->oem_id, x86ms->oem_table_id);
2559 }
2560 }
2561 if (acpi_get_mcfg(&mcfg)) {
2562 acpi_add_table(table_offsets, tables_blob);
2563 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id,
2564 x86ms->oem_table_id);
2565 }
2566 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) {
2567 acpi_add_table(table_offsets, tables_blob);
2568 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id,
2569 x86ms->oem_table_id);
2570 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) {
2571 acpi_add_table(table_offsets, tables_blob);
2572 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id,
2573 x86ms->oem_table_id);
2574 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) {
2575 PCIDevice *pdev = PCI_DEVICE(iommu);
2576
2577 acpi_add_table(table_offsets, tables_blob);
2578 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev),
2579 x86ms->oem_id, x86ms->oem_table_id);
2580 }
2581 if (machine->nvdimms_state->is_enabled) {
2582 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2583 machine->nvdimms_state, machine->ram_slots,
2584 x86ms->oem_id, x86ms->oem_table_id);
2585 }
2586 if (pcms->cxl_devices_state.is_enabled) {
2587 cxl_build_cedt(table_offsets, tables_blob, tables->linker,
2588 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state);
2589 }
2590
2591 acpi_add_table(table_offsets, tables_blob);
2592 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id);
2593
2594 /* Add tables supplied by user (if any) */
2595 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2596 unsigned len = acpi_table_len(u);
2597
2598 acpi_add_table(table_offsets, tables_blob);
2599 g_array_append_vals(tables_blob, u, len);
2600 }
2601
2602 /* RSDT is pointed to by RSDP */
2603 rsdt = tables_blob->len;
2604 build_rsdt(tables_blob, tables->linker, table_offsets,
2605 oem_id, oem_table_id);
2606
2607 /* RSDP is in FSEG memory, so allocate it separately */
2608 {
2609 AcpiRsdpData rsdp_data = {
2610 .revision = 0,
2611 .oem_id = x86ms->oem_id,
2612 .xsdt_tbl_offset = NULL,
2613 .rsdt_tbl_offset = &rsdt,
2614 };
2615 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2616 }
2617
2618 /* We'll expose it all to Guest so we want to reduce
2619 * chance of size changes.
2620 *
2621 * We used to align the tables to 4k, but of course this would
2622 * too simple to be enough. 4k turned out to be too small an
2623 * alignment very soon, and in fact it is almost impossible to
2624 * keep the table size stable for all (max_cpus, max_memory_slots)
2625 * combinations.
2626 */
2627 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2628
2629 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2630
2631 /* Cleanup memory that's no longer used. */
2632 g_array_free(table_offsets, true);
2633 g_free(slic_oem.id);
2634 g_free(slic_oem.table_id);
2635 }
2636
acpi_ram_update(MemoryRegion * mr,GArray * data)2637 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2638 {
2639 uint32_t size = acpi_data_len(data);
2640
2641 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2642 memory_region_ram_resize(mr, size, &error_abort);
2643
2644 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2645 memory_region_set_dirty(mr, 0, size);
2646 }
2647
acpi_build_update(void * build_opaque)2648 static void acpi_build_update(void *build_opaque)
2649 {
2650 AcpiBuildState *build_state = build_opaque;
2651 AcpiBuildTables tables;
2652
2653 /* No state to update or already patched? Nothing to do. */
2654 if (!build_state || build_state->patched) {
2655 return;
2656 }
2657 build_state->patched = 1;
2658
2659 acpi_build_tables_init(&tables);
2660
2661 acpi_build(&tables, MACHINE(qdev_get_machine()));
2662
2663 acpi_ram_update(build_state->table_mr, tables.table_data);
2664
2665 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2666
2667 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2668 acpi_build_tables_cleanup(&tables, true);
2669 }
2670
acpi_build_reset(void * build_opaque)2671 static void acpi_build_reset(void *build_opaque)
2672 {
2673 AcpiBuildState *build_state = build_opaque;
2674 build_state->patched = 0;
2675 }
2676
2677 static const VMStateDescription vmstate_acpi_build = {
2678 .name = "acpi_build",
2679 .version_id = 1,
2680 .minimum_version_id = 1,
2681 .fields = (const VMStateField[]) {
2682 VMSTATE_UINT8(patched, AcpiBuildState),
2683 VMSTATE_END_OF_LIST()
2684 },
2685 };
2686
acpi_setup(void)2687 void acpi_setup(void)
2688 {
2689 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2690 X86MachineState *x86ms = X86_MACHINE(pcms);
2691 AcpiBuildTables tables;
2692 AcpiBuildState *build_state;
2693 Object *vmgenid_dev;
2694 #ifdef CONFIG_TPM
2695 TPMIf *tpm;
2696 static FwCfgTPMConfig tpm_config;
2697 #endif
2698
2699 if (!x86ms->fw_cfg) {
2700 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2701 return;
2702 }
2703
2704 if (!pcms->acpi_build_enabled) {
2705 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2706 return;
2707 }
2708
2709 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
2710 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2711 return;
2712 }
2713
2714 build_state = g_malloc0(sizeof *build_state);
2715
2716 acpi_build_tables_init(&tables);
2717 acpi_build(&tables, MACHINE(pcms));
2718
2719 /* Now expose it all to Guest */
2720 build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
2721 build_state, tables.table_data,
2722 ACPI_BUILD_TABLE_FILE);
2723 assert(build_state->table_mr != NULL);
2724
2725 build_state->linker_mr =
2726 acpi_add_rom_blob(acpi_build_update, build_state,
2727 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE);
2728
2729 #ifdef CONFIG_TPM
2730 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2731 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2732
2733 tpm = tpm_find();
2734 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
2735 tpm_config = (FwCfgTPMConfig) {
2736 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
2737 .tpm_version = tpm_get_version(tpm),
2738 .tpmppi_version = TPM_PPI_VERSION_1_30
2739 };
2740 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config",
2741 &tpm_config, sizeof tpm_config);
2742 }
2743 #endif
2744
2745 vmgenid_dev = find_vmgenid_dev();
2746 if (vmgenid_dev) {
2747 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg,
2748 tables.vmgenid);
2749 }
2750
2751 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
2752 build_state, tables.rsdp,
2753 ACPI_BUILD_RSDP_FILE);
2754
2755 qemu_register_reset(acpi_build_reset, build_state);
2756 acpi_build_reset(build_state);
2757 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2758
2759 /* Cleanup tables but don't free the memory: we track it
2760 * in build_state.
2761 */
2762 acpi_build_tables_cleanup(&tables, false);
2763 }
2764