1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #ifndef RVU_H
9 #define RVU_H
10
11 #include <linux/pci.h>
12 #include <net/devlink.h>
13
14 #include "rvu_struct.h"
15 #include "rvu_devlink.h"
16 #include "common.h"
17 #include "mbox.h"
18 #include "npc.h"
19 #include "rvu_reg.h"
20 #include "ptp.h"
21
22 /* PCI device IDs */
23 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
24 #define PCI_DEVID_OCTEONTX2_LBK 0xA061
25
26 /* Subsystem Device ID */
27 #define PCI_SUBSYS_DEVID_98XX 0xB100
28 #define PCI_SUBSYS_DEVID_96XX 0xB200
29 #define PCI_SUBSYS_DEVID_CN10K_A 0xB900
30 #define PCI_SUBSYS_DEVID_CNF10K_A 0xBA00
31 #define PCI_SUBSYS_DEVID_CNF10K_B 0xBC00
32 #define PCI_SUBSYS_DEVID_CN10K_B 0xBD00
33
34 /* PCI BAR nos */
35 #define PCI_AF_REG_BAR_NUM 0
36 #define PCI_PF_REG_BAR_NUM 2
37 #define PCI_MBOX_BAR_NUM 4
38
39 #define NAME_SIZE 32
40 #define MAX_NIX_BLKS 2
41 #define MAX_CPT_BLKS 2
42
43 /* PF_FUNC */
44 #define RVU_PFVF_PF_SHIFT 10
45 #define RVU_PFVF_PF_MASK 0x3F
46 #define RVU_PFVF_FUNC_SHIFT 0
47 #define RVU_PFVF_FUNC_MASK 0x3FF
48
49 #ifdef CONFIG_DEBUG_FS
50 struct dump_ctx {
51 int lf;
52 int id;
53 bool all;
54 };
55
56 struct cpt_ctx {
57 int blkaddr;
58 struct rvu *rvu;
59 };
60
61 struct rvu_debugfs {
62 struct dentry *root;
63 struct dentry *cgx_root;
64 struct dentry *cgx;
65 struct dentry *lmac;
66 struct dentry *npa;
67 struct dentry *nix;
68 struct dentry *npc;
69 struct dentry *cpt;
70 struct dentry *mcs_root;
71 struct dentry *mcs;
72 struct dentry *mcs_rx;
73 struct dentry *mcs_tx;
74 struct dump_ctx npa_aura_ctx;
75 struct dump_ctx npa_pool_ctx;
76 struct dump_ctx nix_cq_ctx;
77 struct dump_ctx nix_rq_ctx;
78 struct dump_ctx nix_sq_ctx;
79 struct cpt_ctx cpt_ctx[MAX_CPT_BLKS];
80 int npa_qsize_id;
81 int nix_qsize_id;
82 };
83 #endif
84
85 struct rvu_work {
86 struct work_struct work;
87 struct rvu *rvu;
88 int num_msgs;
89 int up_num_msgs;
90 };
91
92 struct rsrc_bmap {
93 unsigned long *bmap; /* Pointer to resource bitmap */
94 u16 max; /* Max resource id or count */
95 };
96
97 struct rvu_block {
98 struct rsrc_bmap lf;
99 struct admin_queue *aq; /* NIX/NPA AQ */
100 u16 *fn_map; /* LF to pcifunc mapping */
101 bool multislot;
102 bool implemented;
103 u8 addr; /* RVU_BLOCK_ADDR_E */
104 u8 type; /* RVU_BLOCK_TYPE_E */
105 u8 lfshift;
106 u64 lookup_reg;
107 u64 pf_lfcnt_reg;
108 u64 vf_lfcnt_reg;
109 u64 lfcfg_reg;
110 u64 msixcfg_reg;
111 u64 lfreset_reg;
112 unsigned char name[NAME_SIZE];
113 struct rvu *rvu;
114 u64 cpt_flt_eng_map[3];
115 u64 cpt_rcvrd_eng_map[3];
116 };
117
118 struct nix_mcast {
119 struct qmem *mce_ctx;
120 struct qmem *mcast_buf;
121 int replay_pkind;
122 struct rsrc_bmap mce_counter[2];
123 /* Counters for both ingress and egress mcast lists */
124 struct mutex mce_lock; /* Serialize MCE updates */
125 };
126
127 struct nix_mce_list {
128 struct hlist_head head;
129 int count;
130 int max;
131 };
132
133 struct nix_mcast_grp_elem {
134 struct nix_mce_list mcast_mce_list;
135 u32 mcast_grp_idx;
136 u32 pcifunc;
137 int mcam_index;
138 int mce_start_index;
139 struct list_head list;
140 u8 dir;
141 };
142
143 struct nix_mcast_grp {
144 struct list_head mcast_grp_head;
145 int count;
146 int next_grp_index;
147 struct mutex mcast_grp_lock; /* Serialize MCE updates */
148 };
149
150 /* layer metadata to uniquely identify a packet header field */
151 struct npc_layer_mdata {
152 u8 lid;
153 u8 ltype;
154 u8 hdr;
155 u8 key;
156 u8 len;
157 };
158
159 /* Structure to represent a field present in the
160 * generated key. A key field may present anywhere and can
161 * be of any size in the generated key. Once this structure
162 * is populated for fields of interest then field's presence
163 * and location (if present) can be known.
164 */
165 struct npc_key_field {
166 /* Masks where all set bits indicate position
167 * of a field in the key
168 */
169 u64 kw_mask[NPC_MAX_KWS_IN_KEY];
170 /* Number of words in the key a field spans. If a field is
171 * of 16 bytes and key offset is 4 then the field will use
172 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and
173 * nr_kws will be 3(KW0, KW1 and KW2).
174 */
175 int nr_kws;
176 /* used by packet header fields */
177 struct npc_layer_mdata layer_mdata;
178 };
179
180 struct npc_mcam {
181 struct rsrc_bmap counters;
182 struct mutex lock; /* MCAM entries and counters update lock */
183 unsigned long *bmap; /* bitmap, 0 => bmap_entries */
184 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */
185 u16 bmap_entries; /* Number of unreserved MCAM entries */
186 u16 bmap_fcnt; /* MCAM entries free count */
187 u16 *entry2pfvf_map;
188 u16 *entry2cntr_map;
189 u16 *cntr2pfvf_map;
190 u16 *cntr_refcnt;
191 u16 *entry2target_pffunc;
192 u8 keysize; /* MCAM keysize 112/224/448 bits */
193 u8 banks; /* Number of MCAM banks */
194 u8 banks_per_entry;/* Number of keywords in key */
195 u16 banksize; /* Number of MCAM entries in each bank */
196 u16 total_entries; /* Total number of MCAM entries */
197 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */
198 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */
199 u16 lprio_count;
200 u16 lprio_start;
201 u16 hprio_count;
202 u16 hprio_end;
203 u16 rx_miss_act_cntr; /* Counter for RX MISS action */
204 /* fields present in the generated key */
205 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX];
206 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX];
207 u64 tx_features;
208 u64 rx_features;
209 struct list_head mcam_rules;
210 };
211
212 /* Structure for per RVU func info ie PF/VF */
213 struct rvu_pfvf {
214 bool npalf; /* Only one NPALF per RVU_FUNC */
215 bool nixlf; /* Only one NIXLF per RVU_FUNC */
216 u16 sso;
217 u16 ssow;
218 u16 cptlfs;
219 u16 timlfs;
220 u16 cpt1_lfs;
221 u8 cgx_lmac;
222
223 /* Block LF's MSIX vector info */
224 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */
225 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF))
226 u16 *msix_lfmap; /* Vector to block LF mapping */
227
228 /* NPA contexts */
229 struct qmem *aura_ctx;
230 struct qmem *pool_ctx;
231 struct qmem *npa_qints_ctx;
232 unsigned long *aura_bmap;
233 unsigned long *pool_bmap;
234
235 /* NIX contexts */
236 struct qmem *rq_ctx;
237 struct qmem *sq_ctx;
238 struct qmem *cq_ctx;
239 struct qmem *rss_ctx;
240 struct qmem *cq_ints_ctx;
241 struct qmem *nix_qints_ctx;
242 unsigned long *sq_bmap;
243 unsigned long *rq_bmap;
244 unsigned long *cq_bmap;
245
246 u16 rx_chan_base;
247 u16 tx_chan_base;
248 u8 rx_chan_cnt; /* total number of RX channels */
249 u8 tx_chan_cnt; /* total number of TX channels */
250 u16 maxlen;
251 u16 minlen;
252
253 bool hw_rx_tstamp_en; /* Is rx_tstamp enabled */
254 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */
255 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */
256
257 /* Broadcast/Multicast/Promisc pkt replication info */
258 u16 bcast_mce_idx;
259 u16 mcast_mce_idx;
260 u16 promisc_mce_idx;
261 struct nix_mce_list bcast_mce_list;
262 struct nix_mce_list mcast_mce_list;
263 struct nix_mce_list promisc_mce_list;
264 bool use_mce_list;
265
266 struct rvu_npc_mcam_rule *def_ucast_rule;
267
268 bool cgx_in_use; /* this PF/VF using CGX? */
269 int cgx_users; /* number of cgx users - used only by PFs */
270
271 int intf_mode;
272 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */
273 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */
274 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */
275 u8 lbkid; /* NIX0/1 lbk link ID */
276 u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/
277 u64 lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/
278 unsigned long flags;
279 struct sdp_node_info *sdp_info;
280 };
281
282 enum rvu_pfvf_flags {
283 NIXLF_INITIALIZED = 0,
284 PF_SET_VF_MAC,
285 PF_SET_VF_CFG,
286 PF_SET_VF_TRUSTED,
287 };
288
289 #define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC)
290
291 struct nix_txsch {
292 struct rsrc_bmap schq;
293 u8 lvl;
294 #define NIX_TXSCHQ_FREE BIT_ULL(1)
295 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0)
296 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF)
297 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16)
298 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16))
299 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16))
300 u32 *pfvf_map;
301 };
302
303 struct nix_mark_format {
304 u8 total;
305 u8 in_use;
306 u32 *cfg;
307 };
308
309 /* smq(flush) to tl1 cir/pir info */
310 struct nix_smq_tree_ctx {
311 u64 cir_off;
312 u64 cir_val;
313 u64 pir_off;
314 u64 pir_val;
315 };
316
317 /* smq flush context */
318 struct nix_smq_flush_ctx {
319 int smq;
320 u16 tl1_schq;
321 u16 tl2_schq;
322 struct nix_smq_tree_ctx smq_tree_ctx[NIX_TXSCH_LVL_CNT];
323 };
324
325 struct npc_pkind {
326 struct rsrc_bmap rsrc;
327 u32 *pfchan_map;
328 };
329
330 struct nix_flowkey {
331 #define NIX_FLOW_KEY_ALG_MAX 32
332 u32 flowkey[NIX_FLOW_KEY_ALG_MAX];
333 int in_use;
334 };
335
336 struct nix_lso {
337 u8 total;
338 u8 in_use;
339 };
340
341 struct nix_txvlan {
342 #define NIX_TX_VTAG_DEF_MAX 0x400
343 struct rsrc_bmap rsrc;
344 u16 *entry2pfvf_map;
345 struct mutex rsrc_lock; /* Serialize resource alloc/free */
346 };
347
348 struct nix_ipolicer {
349 struct rsrc_bmap band_prof;
350 u16 *pfvf_map;
351 u16 *match_id;
352 u16 *ref_count;
353 };
354
355 struct nix_hw {
356 int blkaddr;
357 struct rvu *rvu;
358 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */
359 struct nix_mcast mcast;
360 struct nix_mcast_grp mcast_grp;
361 struct nix_flowkey flowkey;
362 struct nix_mark_format mark_format;
363 struct nix_lso lso;
364 struct nix_txvlan txvlan;
365 struct nix_ipolicer *ipolicer;
366 u64 *tx_credits;
367 u8 cc_mcs_cnt;
368 };
369
370 /* RVU block's capabilities or functionality,
371 * which vary by silicon version/skew.
372 */
373 struct hw_cap {
374 /* Transmit side supported functionality */
375 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */
376 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */
377 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */
378 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */
379 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
380 bool nix_shaping; /* Is shaping and coloring supported */
381 bool nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */
382 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */
383 bool nix_rx_multicast; /* Rx packet replication support */
384 bool nix_common_dwrr_mtu; /* Common DWRR MTU for quantum config */
385 bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */
386 bool programmable_chans; /* Channels programmable ? */
387 bool ipolicer;
388 bool nix_multiple_dwrr_mtu; /* Multiple DWRR_MTU to choose from */
389 bool npc_hash_extract; /* Hash extract enabled ? */
390 bool npc_exact_match_enabled; /* Exact match supported ? */
391 };
392
393 struct rvu_hwinfo {
394 u8 total_pfs; /* MAX RVU PFs HW supports */
395 u16 total_vfs; /* Max RVU VFs HW supports */
396 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */
397 u8 cgx;
398 u8 lmac_per_cgx;
399 u16 cgx_chan_base; /* CGX base channel number */
400 u16 lbk_chan_base; /* LBK base channel number */
401 u16 sdp_chan_base; /* SDP base channel number */
402 u16 cpt_chan_base; /* CPT base channel number */
403 u8 cgx_links;
404 u8 lbk_links;
405 u8 sdp_links;
406 u8 cpt_links; /* Number of CPT links */
407 u8 npc_kpus; /* No of parser units */
408 u8 npc_pkinds; /* No of port kinds */
409 u8 npc_intfs; /* No of interfaces */
410 u8 npc_kpu_entries; /* No of KPU entries */
411 u16 npc_counters; /* No of match stats counters */
412 u32 lbk_bufsize; /* FIFO size supported by LBK */
413 bool npc_ext_set; /* Extended register set */
414 u64 npc_stat_ena; /* Match stats enable bit */
415
416 struct hw_cap cap;
417 struct rvu_block block[BLK_COUNT]; /* Block info */
418 struct nix_hw *nix;
419 struct rvu *rvu;
420 struct npc_pkind pkind;
421 struct npc_mcam mcam;
422 struct npc_exact_table *table;
423 };
424
425 struct mbox_wq_info {
426 struct otx2_mbox mbox;
427 struct rvu_work *mbox_wrk;
428
429 struct otx2_mbox mbox_up;
430 struct rvu_work *mbox_wrk_up;
431
432 struct workqueue_struct *mbox_wq;
433 };
434
435 struct rvu_fwdata {
436 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/
437 #define RVU_FWDATA_VERSION 0x0001
438 u32 header_magic;
439 u32 version; /* version id */
440
441 /* MAC address */
442 #define PF_MACNUM_MAX 32
443 #define VF_MACNUM_MAX 256
444 u64 pf_macs[PF_MACNUM_MAX];
445 u64 vf_macs[VF_MACNUM_MAX];
446 u64 sclk;
447 u64 rclk;
448 u64 mcam_addr;
449 u64 mcam_sz;
450 u64 msixtr_base;
451 u32 ptp_ext_clk_rate;
452 u32 ptp_ext_tstamp;
453 #define FWDATA_RESERVED_MEM 1022
454 u64 reserved[FWDATA_RESERVED_MEM];
455 #define CGX_MAX 9
456 #define CGX_LMACS_MAX 4
457 #define CGX_LMACS_USX 8
458 union {
459 struct cgx_lmac_fwdata_s
460 cgx_fw_data[CGX_MAX][CGX_LMACS_MAX];
461 struct cgx_lmac_fwdata_s
462 cgx_fw_data_usx[CGX_MAX][CGX_LMACS_USX];
463 };
464 /* Do not add new fields below this line */
465 };
466
467 struct ptp;
468
469 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the
470 * source where it came from.
471 */
472 struct npc_kpu_profile_adapter {
473 const char *name;
474 u64 version;
475 const struct npc_lt_def_cfg *lt_def;
476 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */
477 const struct npc_kpu_profile *kpu; /* array[kpus] */
478 struct npc_mcam_kex *mkex;
479 struct npc_mcam_kex_hash *mkex_hash;
480 bool custom;
481 size_t pkinds;
482 size_t kpus;
483 };
484
485 #define RVU_SWITCH_LBK_CHAN 63
486
487 struct rvu_switch {
488 struct mutex switch_lock; /* Serialize flow installation */
489 u32 used_entries;
490 u16 *entry2pcifunc;
491 u16 mode;
492 u16 start_entry;
493 };
494
495 struct rvu {
496 void __iomem *afreg_base;
497 void __iomem *pfreg_base;
498 struct pci_dev *pdev;
499 struct device *dev;
500 struct rvu_hwinfo *hw;
501 struct rvu_pfvf *pf;
502 struct rvu_pfvf *hwvf;
503 struct mutex rsrc_lock; /* Serialize resource alloc/free */
504 struct mutex alias_lock; /* Serialize bar2 alias access */
505 int vfs; /* Number of VFs attached to RVU */
506 int nix_blkaddr[MAX_NIX_BLKS];
507
508 /* Mbox */
509 struct mbox_wq_info afpf_wq_info;
510 struct mbox_wq_info afvf_wq_info;
511
512 /* PF FLR */
513 struct rvu_work *flr_wrk;
514 struct workqueue_struct *flr_wq;
515 struct mutex flr_lock; /* Serialize FLRs */
516
517 /* MSI-X */
518 u16 num_vec;
519 char *irq_name;
520 bool *irq_allocated;
521 dma_addr_t msix_base_iova;
522 u64 msixtr_base_phy; /* Register reset value */
523
524 /* CGX */
525 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */
526 u16 cgx_mapped_vfs; /* maximum CGX mapped VFs */
527 u8 cgx_mapped_pfs;
528 u8 cgx_cnt_max; /* CGX port count max */
529 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */
530 u64 *cgxlmac2pf_map; /* bitmap of mapped pfs for
531 * every cgx lmac port
532 */
533 unsigned long pf_notify_bmap; /* Flags for PF notification */
534 void **cgx_idmap; /* cgx id to cgx data map table */
535 struct work_struct cgx_evh_work;
536 struct workqueue_struct *cgx_evh_wq;
537 spinlock_t cgx_evq_lock; /* cgx event queue lock */
538 struct list_head cgx_evq_head; /* cgx event queue head */
539 struct mutex cgx_cfg_lock; /* serialize cgx configuration */
540
541 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */
542 char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */
543
544 /* Firmware data */
545 struct rvu_fwdata *fwdata;
546 void *kpu_fwdata;
547 size_t kpu_fwdata_sz;
548 void __iomem *kpu_prfl_addr;
549
550 /* NPC KPU data */
551 struct npc_kpu_profile_adapter kpu;
552
553 struct ptp *ptp;
554
555 int mcs_blk_cnt;
556 int cpt_pf_num;
557
558 #ifdef CONFIG_DEBUG_FS
559 struct rvu_debugfs rvu_dbg;
560 #endif
561 struct rvu_devlink *rvu_dl;
562
563 /* RVU switch implementation over NPC with DMAC rules */
564 struct rvu_switch rswitch;
565
566 struct work_struct mcs_intr_work;
567 struct workqueue_struct *mcs_intr_wq;
568 struct list_head mcs_intrq_head;
569 /* mcs interrupt queue lock */
570 spinlock_t mcs_intrq_lock;
571 /* CPT interrupt lock */
572 spinlock_t cpt_intr_lock;
573 };
574
rvu_write64(struct rvu * rvu,u64 block,u64 offset,u64 val)575 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
576 {
577 writeq(val, rvu->afreg_base + ((block << 28) | offset));
578 }
579
rvu_read64(struct rvu * rvu,u64 block,u64 offset)580 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset)
581 {
582 return readq(rvu->afreg_base + ((block << 28) | offset));
583 }
584
rvupf_write64(struct rvu * rvu,u64 offset,u64 val)585 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val)
586 {
587 writeq(val, rvu->pfreg_base + offset);
588 }
589
rvupf_read64(struct rvu * rvu,u64 offset)590 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
591 {
592 return readq(rvu->pfreg_base + offset);
593 }
594
rvu_bar2_sel_write64(struct rvu * rvu,u64 block,u64 offset,u64 val)595 static inline void rvu_bar2_sel_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
596 {
597 /* HW requires read back of RVU_AF_BAR2_SEL register to make sure completion of
598 * write operation.
599 */
600 rvu_write64(rvu, block, offset, val);
601 rvu_read64(rvu, block, offset);
602 /* Barrier to ensure read completes before accessing LF registers */
603 mb();
604 }
605
606 /* Silicon revisions */
is_rvu_pre_96xx_C0(struct rvu * rvu)607 static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu)
608 {
609 struct pci_dev *pdev = rvu->pdev;
610 /* 96XX A0/B0, 95XX A0/A1/B0 chips */
611 return ((pdev->revision == 0x00) || (pdev->revision == 0x01) ||
612 (pdev->revision == 0x10) || (pdev->revision == 0x11) ||
613 (pdev->revision == 0x14));
614 }
615
is_rvu_96xx_A0(struct rvu * rvu)616 static inline bool is_rvu_96xx_A0(struct rvu *rvu)
617 {
618 struct pci_dev *pdev = rvu->pdev;
619
620 return (pdev->revision == 0x00);
621 }
622
is_rvu_96xx_B0(struct rvu * rvu)623 static inline bool is_rvu_96xx_B0(struct rvu *rvu)
624 {
625 struct pci_dev *pdev = rvu->pdev;
626
627 return (pdev->revision == 0x00) || (pdev->revision == 0x01);
628 }
629
is_rvu_95xx_A0(struct rvu * rvu)630 static inline bool is_rvu_95xx_A0(struct rvu *rvu)
631 {
632 struct pci_dev *pdev = rvu->pdev;
633
634 return (pdev->revision == 0x10) || (pdev->revision == 0x11);
635 }
636
637 /* REVID for PCIe devices.
638 * Bits 0..1: minor pass, bit 3..2: major pass
639 * bits 7..4: midr id
640 */
641 #define PCI_REVISION_ID_96XX 0x00
642 #define PCI_REVISION_ID_95XX 0x10
643 #define PCI_REVISION_ID_95XXN 0x20
644 #define PCI_REVISION_ID_98XX 0x30
645 #define PCI_REVISION_ID_95XXMM 0x40
646 #define PCI_REVISION_ID_95XXO 0xE0
647
is_rvu_otx2(struct rvu * rvu)648 static inline bool is_rvu_otx2(struct rvu *rvu)
649 {
650 struct pci_dev *pdev = rvu->pdev;
651
652 u8 midr = pdev->revision & 0xF0;
653
654 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX ||
655 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX ||
656 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO);
657 }
658
is_cnf10ka_a0(struct rvu * rvu)659 static inline bool is_cnf10ka_a0(struct rvu *rvu)
660 {
661 struct pci_dev *pdev = rvu->pdev;
662
663 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10K_A &&
664 (pdev->revision & 0x0F) == 0x0)
665 return true;
666 return false;
667 }
668
is_rvu_npc_hash_extract_en(struct rvu * rvu)669 static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu)
670 {
671 u64 npc_const3;
672
673 npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3);
674 if (!(npc_const3 & BIT_ULL(62)))
675 return false;
676
677 return true;
678 }
679
rvu_nix_chan_cgx(struct rvu * rvu,u8 cgxid,u8 lmacid,u8 chan)680 static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid,
681 u8 lmacid, u8 chan)
682 {
683 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
684 u16 cgx_chans = nix_const & 0xFFULL;
685 struct rvu_hwinfo *hw = rvu->hw;
686
687 if (!hw->cap.programmable_chans)
688 return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan);
689
690 return rvu->hw->cgx_chan_base +
691 (cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan;
692 }
693
rvu_nix_chan_lbk(struct rvu * rvu,u8 lbkid,u8 chan)694 static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid,
695 u8 chan)
696 {
697 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
698 u16 lbk_chans = (nix_const >> 16) & 0xFFULL;
699 struct rvu_hwinfo *hw = rvu->hw;
700
701 if (!hw->cap.programmable_chans)
702 return NIX_CHAN_LBK_CHX(lbkid, chan);
703
704 return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan;
705 }
706
rvu_nix_chan_sdp(struct rvu * rvu,u8 chan)707 static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan)
708 {
709 struct rvu_hwinfo *hw = rvu->hw;
710
711 if (!hw->cap.programmable_chans)
712 return NIX_CHAN_SDP_CHX(chan);
713
714 return hw->sdp_chan_base + chan;
715 }
716
rvu_nix_chan_cpt(struct rvu * rvu,u8 chan)717 static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan)
718 {
719 return rvu->hw->cpt_chan_base + chan;
720 }
721
is_rvu_supports_nix1(struct rvu * rvu)722 static inline bool is_rvu_supports_nix1(struct rvu *rvu)
723 {
724 struct pci_dev *pdev = rvu->pdev;
725
726 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_98XX)
727 return true;
728
729 return false;
730 }
731
732 /* Function Prototypes
733 * RVU
734 */
is_afvf(u16 pcifunc)735 static inline bool is_afvf(u16 pcifunc)
736 {
737 return !(pcifunc & ~RVU_PFVF_FUNC_MASK);
738 }
739
is_vf(u16 pcifunc)740 static inline bool is_vf(u16 pcifunc)
741 {
742 return !!(pcifunc & RVU_PFVF_FUNC_MASK);
743 }
744
745 /* check if PF_FUNC is AF */
is_pffunc_af(u16 pcifunc)746 static inline bool is_pffunc_af(u16 pcifunc)
747 {
748 return !pcifunc;
749 }
750
is_rvu_fwdata_valid(struct rvu * rvu)751 static inline bool is_rvu_fwdata_valid(struct rvu *rvu)
752 {
753 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) &&
754 (rvu->fwdata->version == RVU_FWDATA_VERSION);
755 }
756
757 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc);
758 void rvu_free_bitmap(struct rsrc_bmap *rsrc);
759 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc);
760 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id);
761 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id);
762 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);
763 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc);
764 void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start);
765 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc);
766 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr);
767 int rvu_get_pf(u16 pcifunc);
768 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc);
769 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf);
770 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr);
771 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype);
772 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot);
773 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf);
774 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc);
775 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
776 int rvu_get_num_lbk_chans(void);
777 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc,
778 u16 global_slot, u16 *slot_in_block);
779
780 /* RVU HW reg validation */
781 enum regmap_block {
782 TXSCHQ_HWREGMAP = 0,
783 MAX_HWREGMAP,
784 };
785
786 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg);
787
788 /* NPA/NIX AQ APIs */
789 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
790 int qsize, int inst_size, int res_size);
791 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq);
792
793 /* SDP APIs */
794 int rvu_sdp_init(struct rvu *rvu);
795 bool is_sdp_pfvf(u16 pcifunc);
796 bool is_sdp_pf(u16 pcifunc);
797 bool is_sdp_vf(u16 pcifunc);
798
799 /* CGX APIs */
is_pf_cgxmapped(struct rvu * rvu,u8 pf)800 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf)
801 {
802 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) &&
803 !is_sdp_pf(pf << RVU_PFVF_PF_SHIFT);
804 }
805
rvu_get_cgx_lmac_id(u8 map,u8 * cgx_id,u8 * lmac_id)806 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id)
807 {
808 *cgx_id = (map >> 4) & 0xF;
809 *lmac_id = (map & 0xF);
810 }
811
is_cgx_vf(struct rvu * rvu,u16 pcifunc)812 static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc)
813 {
814 return ((pcifunc & RVU_PFVF_FUNC_MASK) &&
815 is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)));
816 }
817
818 #define M(_name, _id, fn_name, req, rsp) \
819 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *);
820 MBOX_MESSAGES
821 #undef M
822
823 int rvu_cgx_init(struct rvu *rvu);
824 int rvu_cgx_exit(struct rvu *rvu);
825 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu);
826 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start);
827 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable);
828 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start);
829 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index,
830 int rxtxflag, u64 *stat);
831 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc);
832
833 /* NPA APIs */
834 int rvu_npa_init(struct rvu *rvu);
835 void rvu_npa_freemem(struct rvu *rvu);
836 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf);
837 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req,
838 struct npa_aq_enq_rsp *rsp);
839
840 /* NIX APIs */
841 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc);
842 int rvu_nix_init(struct rvu *rvu);
843 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw,
844 int blkaddr, u32 cfg);
845 void rvu_nix_freemem(struct rvu *rvu);
846 int rvu_get_nixlf_count(struct rvu *rvu);
847 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf);
848 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr);
849 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc,
850 struct nix_mce_list *mce_list,
851 int mce_idx, int mcam_index, bool add);
852 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type,
853 struct nix_mce_list **mce_list, int *mce_idx);
854 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr);
855 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr);
856 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc);
857 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc,
858 struct nix_hw **nix_hw, int *blkaddr);
859 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc,
860 u16 rq_idx, u16 match_id);
861 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw,
862 struct nix_cn10k_aq_enq_req *aq_req,
863 struct nix_cn10k_aq_enq_rsp *aq_rsp,
864 u16 pcifunc, u8 ctype, u32 qidx);
865 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc);
866 int nix_get_dwrr_mtu_reg(struct rvu_hwinfo *hw, int smq_link_type);
867 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu);
868 u32 convert_bytes_to_dwrr_mtu(u32 bytes);
869 void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, u16 pcifunc,
870 struct nix_txsch *txsch, bool enable);
871 void rvu_nix_mcast_flr_free_entries(struct rvu *rvu, u16 pcifunc);
872 int rvu_nix_mcast_get_mce_index(struct rvu *rvu, u16 pcifunc,
873 u32 mcast_grp_idx);
874 int rvu_nix_mcast_update_mcam_entry(struct rvu *rvu, u16 pcifunc,
875 u32 mcast_grp_idx, u16 mcam_index);
876
877 /* NPC APIs */
878 void rvu_npc_freemem(struct rvu *rvu);
879 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
880 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
881 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en);
882 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
883 int nixlf, u64 chan, u8 *mac_addr);
884 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
885 int nixlf, u64 chan, u8 chan_cnt);
886 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
887 bool enable);
888 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
889 int nixlf, u64 chan);
890 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
891 bool enable);
892 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
893 u64 chan);
894 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
895 bool enable);
896
897 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc,
898 int nixlf, int type, bool enable);
899 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
900 bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable);
901 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
902 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
903 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
904 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
905 int group, int alg_idx, int mcam_index);
906
907 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
908 int blkaddr, int *alloc_cnt,
909 int *enable_cnt);
910 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
911 int blkaddr, int *alloc_cnt,
912 int *enable_cnt);
913 bool is_npc_intf_tx(u8 intf);
914 bool is_npc_intf_rx(u8 intf);
915 bool is_npc_interface_valid(struct rvu *rvu, u8 intf);
916 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena);
917 int npc_flow_steering_init(struct rvu *rvu, int blkaddr);
918 const char *npc_get_field_name(u8 hdr);
919 int npc_get_bank(struct npc_mcam *mcam, int index);
920 void npc_mcam_enable_flows(struct rvu *rvu, u16 target);
921 void npc_mcam_disable_flows(struct rvu *rvu, u16 target);
922 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
923 int blkaddr, int index, bool enable);
924 u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,
925 int blkaddr, int index);
926 void npc_set_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,
927 int blkaddr, int index, u64 cfg);
928 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
929 int blkaddr, u16 src, struct mcam_entry *entry,
930 u8 *intf, u8 *ena);
931 bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc);
932 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature);
933 u32 rvu_cgx_get_fifolen(struct rvu *rvu);
934 void *rvu_first_cgx_pdata(struct rvu *rvu);
935 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id);
936 int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable);
937 int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable);
938 int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause,
939 u16 pfc_en);
940 int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause);
941 void rvu_mac_reset(struct rvu *rvu, u16 pcifunc);
942 u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac);
943 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf,
944 int type);
945 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr,
946 int index);
947 int rvu_npc_init(struct rvu *rvu);
948 int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx,
949 u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask,
950 u64 bcast_mcast_val, u64 bcast_mcast_mask);
951 void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx);
952 bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf);
953 int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr);
954 void npc_mcam_rsrcs_deinit(struct rvu *rvu);
955
956 /* CPT APIs */
957 int rvu_cpt_register_interrupts(struct rvu *rvu);
958 void rvu_cpt_unregister_interrupts(struct rvu *rvu);
959 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf,
960 int slot);
961 int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc);
962 int rvu_cpt_init(struct rvu *rvu);
963
964 #define NDC_AF_BANK_MASK GENMASK_ULL(7, 0)
965 #define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16)
966
967 /* CN10K RVU */
968 int rvu_set_channels_base(struct rvu *rvu);
969 void rvu_program_channels(struct rvu *rvu);
970
971 /* CN10K NIX */
972 void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw);
973
974 /* CN10K RVU - LMT*/
975 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc);
976 void rvu_apr_block_cn10k_init(struct rvu *rvu);
977
978 #ifdef CONFIG_DEBUG_FS
979 void rvu_dbg_init(struct rvu *rvu);
980 void rvu_dbg_exit(struct rvu *rvu);
981 #else
rvu_dbg_init(struct rvu * rvu)982 static inline void rvu_dbg_init(struct rvu *rvu) {}
rvu_dbg_exit(struct rvu * rvu)983 static inline void rvu_dbg_exit(struct rvu *rvu) {}
984 #endif
985
986 int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr);
987
988 /* RVU Switch */
989 void rvu_switch_enable(struct rvu *rvu);
990 void rvu_switch_disable(struct rvu *rvu);
991 void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc);
992
993 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir,
994 u64 pkind, u8 var_len_off, u8 var_len_off_mask,
995 u8 shift_dir);
996 int rvu_get_hwvf(struct rvu *rvu, int pcifunc);
997
998 /* CN10K MCS */
999 int rvu_mcs_init(struct rvu *rvu);
1000 int rvu_mcs_flr_handler(struct rvu *rvu, u16 pcifunc);
1001 void rvu_mcs_ptp_cfg(struct rvu *rvu, u8 rpm_id, u8 lmac_id, bool ena);
1002 void rvu_mcs_exit(struct rvu *rvu);
1003
1004 #endif /* RVU_H */
1005