1 // SPDX-License-Identifier: GPL-2.0+ 2 /* vim: set ts=8 sw=8 noet tw=80 nowrap: */ 3 /* 4 * comedi/drivers/ni_routing/ni_route_values/ni_eseries.c 5 * Route information for NI_ESERIES boards. 6 * 7 * COMEDI - Linux Control and Measurement Device Interface 8 * Copyright (C) 2016 Spencer E. Olson <olsonse@umich.edu> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 */ 20 21 /* 22 * This file includes a list of all the values of various signals routes 23 * available on NI 660x hardware. In many cases, one does not explicitly make 24 * these routes, rather one might indicate that something is used as the source 25 * of one particular trigger or another (using *_src=TRIG_EXT). 26 * 27 * The contents of this file can be generated using the tools in 28 * comedi/drivers/ni_routing/tools. This file also contains specific notes to 29 * this family of devices. 30 * 31 * Please use those tools to help maintain the contents of this file, but be 32 * mindful to not lose the notes already made in this file, since these notes 33 * are critical to a complete undertsanding of the register values of this 34 * family. 35 */ 36 37 #include "../ni_route_values.h" 38 #include "all.h" 39 40 /* 41 * Note that for e-series devices, the backplane TRIGGER_LINE(6) is generally 42 * not connected to RTSI(6). 43 */ 44 45 const struct family_route_values ni_eseries_route_values = { 46 .family = "ni_eseries", 47 .register_values = { 48 /* 49 * destination = { 50 * source = register value, 51 * ... 52 * } 53 */ 54 [B(NI_PFI(0))] = { 55 [B(NI_AI_StartTrigger)] = I(NI_PFI_OUTPUT_AI_START1), 56 }, 57 [B(NI_PFI(1))] = { 58 [B(NI_AI_ReferenceTrigger)] = I(NI_PFI_OUTPUT_AI_START2), 59 }, 60 [B(NI_PFI(2))] = { 61 [B(NI_AI_ConvertClock)] = I(NI_PFI_OUTPUT_AI_CONVERT), 62 }, 63 [B(NI_PFI(3))] = { 64 [B(NI_CtrSource(1))] = I(NI_PFI_OUTPUT_G_SRC1), 65 }, 66 [B(NI_PFI(4))] = { 67 [B(NI_CtrGate(1))] = I(NI_PFI_OUTPUT_G_GATE1), 68 }, 69 [B(NI_PFI(5))] = { 70 [B(NI_AO_SampleClock)] = I(NI_PFI_OUTPUT_AO_UPDATE_N), 71 }, 72 [B(NI_PFI(6))] = { 73 [B(NI_AO_StartTrigger)] = I(NI_PFI_OUTPUT_AO_START1), 74 }, 75 [B(NI_PFI(7))] = { 76 [B(NI_AI_SampleClock)] = I(NI_PFI_OUTPUT_AI_START_PULSE), 77 }, 78 [B(NI_PFI(8))] = { 79 [B(NI_CtrSource(0))] = I(NI_PFI_OUTPUT_G_SRC0), 80 }, 81 [B(NI_PFI(9))] = { 82 [B(NI_CtrGate(0))] = I(NI_PFI_OUTPUT_G_GATE0), 83 }, 84 [B(TRIGGER_LINE(0))] = { 85 [B(NI_RTSI_BRD(0))] = I(8), 86 [B(NI_RTSI_BRD(1))] = I(9), 87 [B(NI_RTSI_BRD(2))] = I(10), 88 [B(NI_RTSI_BRD(3))] = I(11), 89 [B(NI_CtrSource(0))] = I(5), 90 [B(NI_CtrGate(0))] = I(6), 91 [B(NI_AI_StartTrigger)] = I(0), 92 [B(NI_AI_ReferenceTrigger)] = I(1), 93 [B(NI_AI_ConvertClock)] = I(2), 94 [B(NI_AO_SampleClock)] = I(3), 95 [B(NI_AO_StartTrigger)] = I(4), 96 [B(NI_RGOUT0)] = I(7), 97 }, 98 [B(TRIGGER_LINE(1))] = { 99 [B(NI_RTSI_BRD(0))] = I(8), 100 [B(NI_RTSI_BRD(1))] = I(9), 101 [B(NI_RTSI_BRD(2))] = I(10), 102 [B(NI_RTSI_BRD(3))] = I(11), 103 [B(NI_CtrSource(0))] = I(5), 104 [B(NI_CtrGate(0))] = I(6), 105 [B(NI_AI_StartTrigger)] = I(0), 106 [B(NI_AI_ReferenceTrigger)] = I(1), 107 [B(NI_AI_ConvertClock)] = I(2), 108 [B(NI_AO_SampleClock)] = I(3), 109 [B(NI_AO_StartTrigger)] = I(4), 110 [B(NI_RGOUT0)] = I(7), 111 }, 112 [B(TRIGGER_LINE(2))] = { 113 [B(NI_RTSI_BRD(0))] = I(8), 114 [B(NI_RTSI_BRD(1))] = I(9), 115 [B(NI_RTSI_BRD(2))] = I(10), 116 [B(NI_RTSI_BRD(3))] = I(11), 117 [B(NI_CtrSource(0))] = I(5), 118 [B(NI_CtrGate(0))] = I(6), 119 [B(NI_AI_StartTrigger)] = I(0), 120 [B(NI_AI_ReferenceTrigger)] = I(1), 121 [B(NI_AI_ConvertClock)] = I(2), 122 [B(NI_AO_SampleClock)] = I(3), 123 [B(NI_AO_StartTrigger)] = I(4), 124 [B(NI_RGOUT0)] = I(7), 125 }, 126 [B(TRIGGER_LINE(3))] = { 127 [B(NI_RTSI_BRD(0))] = I(8), 128 [B(NI_RTSI_BRD(1))] = I(9), 129 [B(NI_RTSI_BRD(2))] = I(10), 130 [B(NI_RTSI_BRD(3))] = I(11), 131 [B(NI_CtrSource(0))] = I(5), 132 [B(NI_CtrGate(0))] = I(6), 133 [B(NI_AI_StartTrigger)] = I(0), 134 [B(NI_AI_ReferenceTrigger)] = I(1), 135 [B(NI_AI_ConvertClock)] = I(2), 136 [B(NI_AO_SampleClock)] = I(3), 137 [B(NI_AO_StartTrigger)] = I(4), 138 [B(NI_RGOUT0)] = I(7), 139 }, 140 [B(TRIGGER_LINE(4))] = { 141 [B(NI_RTSI_BRD(0))] = I(8), 142 [B(NI_RTSI_BRD(1))] = I(9), 143 [B(NI_RTSI_BRD(2))] = I(10), 144 [B(NI_RTSI_BRD(3))] = I(11), 145 [B(NI_CtrSource(0))] = I(5), 146 [B(NI_CtrGate(0))] = I(6), 147 [B(NI_AI_StartTrigger)] = I(0), 148 [B(NI_AI_ReferenceTrigger)] = I(1), 149 [B(NI_AI_ConvertClock)] = I(2), 150 [B(NI_AO_SampleClock)] = I(3), 151 [B(NI_AO_StartTrigger)] = I(4), 152 [B(NI_RGOUT0)] = I(7), 153 }, 154 [B(TRIGGER_LINE(5))] = { 155 [B(NI_RTSI_BRD(0))] = I(8), 156 [B(NI_RTSI_BRD(1))] = I(9), 157 [B(NI_RTSI_BRD(2))] = I(10), 158 [B(NI_RTSI_BRD(3))] = I(11), 159 [B(NI_CtrSource(0))] = I(5), 160 [B(NI_CtrGate(0))] = I(6), 161 [B(NI_AI_StartTrigger)] = I(0), 162 [B(NI_AI_ReferenceTrigger)] = I(1), 163 [B(NI_AI_ConvertClock)] = I(2), 164 [B(NI_AO_SampleClock)] = I(3), 165 [B(NI_AO_StartTrigger)] = I(4), 166 [B(NI_RGOUT0)] = I(7), 167 }, 168 [B(TRIGGER_LINE(6))] = { 169 [B(NI_RTSI_BRD(0))] = I(8), 170 [B(NI_RTSI_BRD(1))] = I(9), 171 [B(NI_RTSI_BRD(2))] = I(10), 172 [B(NI_RTSI_BRD(3))] = I(11), 173 [B(NI_CtrSource(0))] = I(5), 174 [B(NI_CtrGate(0))] = I(6), 175 [B(NI_AI_StartTrigger)] = I(0), 176 [B(NI_AI_ReferenceTrigger)] = I(1), 177 [B(NI_AI_ConvertClock)] = I(2), 178 [B(NI_AO_SampleClock)] = I(3), 179 [B(NI_AO_StartTrigger)] = I(4), 180 [B(NI_RGOUT0)] = I(7), 181 }, 182 [B(TRIGGER_LINE(7))] = { 183 [B(NI_20MHzTimebase)] = I(NI_RTSI_OUTPUT_RTSI_OSC), 184 }, 185 [B(NI_RTSI_BRD(0))] = { 186 [B(TRIGGER_LINE(0))] = I(0), 187 [B(TRIGGER_LINE(1))] = I(1), 188 [B(TRIGGER_LINE(2))] = I(2), 189 [B(TRIGGER_LINE(3))] = I(3), 190 [B(TRIGGER_LINE(4))] = I(4), 191 [B(TRIGGER_LINE(5))] = I(5), 192 [B(TRIGGER_LINE(6))] = I(6), 193 [B(PXI_Star)] = I(6), 194 [B(NI_AI_STOP)] = I(7), 195 }, 196 [B(NI_RTSI_BRD(1))] = { 197 [B(TRIGGER_LINE(0))] = I(0), 198 [B(TRIGGER_LINE(1))] = I(1), 199 [B(TRIGGER_LINE(2))] = I(2), 200 [B(TRIGGER_LINE(3))] = I(3), 201 [B(TRIGGER_LINE(4))] = I(4), 202 [B(TRIGGER_LINE(5))] = I(5), 203 [B(TRIGGER_LINE(6))] = I(6), 204 [B(PXI_Star)] = I(6), 205 [B(NI_AI_STOP)] = I(7), 206 }, 207 [B(NI_RTSI_BRD(2))] = { 208 [B(TRIGGER_LINE(0))] = I(0), 209 [B(TRIGGER_LINE(1))] = I(1), 210 [B(TRIGGER_LINE(2))] = I(2), 211 [B(TRIGGER_LINE(3))] = I(3), 212 [B(TRIGGER_LINE(4))] = I(4), 213 [B(TRIGGER_LINE(5))] = I(5), 214 [B(TRIGGER_LINE(6))] = I(6), 215 [B(PXI_Star)] = I(6), 216 [B(NI_AI_SampleClock)] = I(7), 217 }, 218 [B(NI_RTSI_BRD(3))] = { 219 [B(TRIGGER_LINE(0))] = I(0), 220 [B(TRIGGER_LINE(1))] = I(1), 221 [B(TRIGGER_LINE(2))] = I(2), 222 [B(TRIGGER_LINE(3))] = I(3), 223 [B(TRIGGER_LINE(4))] = I(4), 224 [B(TRIGGER_LINE(5))] = I(5), 225 [B(TRIGGER_LINE(6))] = I(6), 226 [B(PXI_Star)] = I(6), 227 [B(NI_AI_SampleClock)] = I(7), 228 }, 229 [B(NI_CtrSource(0))] = { 230 /* These are not currently implemented in ni modules */ 231 [B(NI_PFI(0))] = U(1), 232 [B(NI_PFI(1))] = U(2), 233 [B(NI_PFI(2))] = U(3), 234 [B(NI_PFI(3))] = U(4), 235 [B(NI_PFI(4))] = U(5), 236 [B(NI_PFI(5))] = U(6), 237 [B(NI_PFI(6))] = U(7), 238 [B(NI_PFI(7))] = U(8), 239 [B(NI_PFI(8))] = U(9), 240 [B(NI_PFI(9))] = U(10), 241 [B(TRIGGER_LINE(0))] = U(11), 242 [B(TRIGGER_LINE(1))] = U(12), 243 [B(TRIGGER_LINE(2))] = U(13), 244 [B(TRIGGER_LINE(3))] = U(14), 245 [B(TRIGGER_LINE(4))] = U(15), 246 [B(TRIGGER_LINE(5))] = U(16), 247 [B(TRIGGER_LINE(6))] = U(17), 248 [B(NI_CtrInternalOutput(1))] = U(19), 249 [B(PXI_Star)] = U(17), 250 [B(NI_20MHzTimebase)] = U(0), 251 [B(NI_100kHzTimebase)] = U(18), 252 [B(NI_LogicLow)] = U(31), 253 }, 254 [B(NI_CtrSource(1))] = { 255 /* These are not currently implemented in ni modules */ 256 [B(NI_PFI(0))] = U(1), 257 [B(NI_PFI(1))] = U(2), 258 [B(NI_PFI(2))] = U(3), 259 [B(NI_PFI(3))] = U(4), 260 [B(NI_PFI(4))] = U(5), 261 [B(NI_PFI(5))] = U(6), 262 [B(NI_PFI(6))] = U(7), 263 [B(NI_PFI(7))] = U(8), 264 [B(NI_PFI(8))] = U(9), 265 [B(NI_PFI(9))] = U(10), 266 [B(TRIGGER_LINE(0))] = U(11), 267 [B(TRIGGER_LINE(1))] = U(12), 268 [B(TRIGGER_LINE(2))] = U(13), 269 [B(TRIGGER_LINE(3))] = U(14), 270 [B(TRIGGER_LINE(4))] = U(15), 271 [B(TRIGGER_LINE(5))] = U(16), 272 [B(TRIGGER_LINE(6))] = U(17), 273 [B(NI_CtrInternalOutput(0))] = U(19), 274 [B(PXI_Star)] = U(17), 275 [B(NI_20MHzTimebase)] = U(0), 276 [B(NI_100kHzTimebase)] = U(18), 277 [B(NI_LogicLow)] = U(31), 278 }, 279 [B(NI_CtrGate(0))] = { 280 [B(NI_PFI(0))] = I(1), 281 [B(NI_PFI(1))] = I(2), 282 [B(NI_PFI(2))] = I(3), 283 [B(NI_PFI(3))] = I(4), 284 [B(NI_PFI(4))] = I(5), 285 [B(NI_PFI(5))] = I(6), 286 [B(NI_PFI(6))] = I(7), 287 [B(NI_PFI(7))] = I(8), 288 [B(NI_PFI(8))] = I(9), 289 [B(NI_PFI(9))] = I(10), 290 [B(TRIGGER_LINE(0))] = I(11), 291 [B(TRIGGER_LINE(1))] = I(12), 292 [B(TRIGGER_LINE(2))] = I(13), 293 [B(TRIGGER_LINE(3))] = I(14), 294 [B(TRIGGER_LINE(4))] = I(15), 295 [B(TRIGGER_LINE(5))] = I(16), 296 [B(TRIGGER_LINE(6))] = I(17), 297 [B(NI_CtrInternalOutput(1))] = I(20), 298 [B(PXI_Star)] = I(17), 299 [B(NI_AI_StartTrigger)] = I(21), 300 [B(NI_AI_ReferenceTrigger)] = I(18), 301 [B(NI_LogicLow)] = I(31), 302 }, 303 [B(NI_CtrGate(1))] = { 304 [B(NI_PFI(0))] = I(1), 305 [B(NI_PFI(1))] = I(2), 306 [B(NI_PFI(2))] = I(3), 307 [B(NI_PFI(3))] = I(4), 308 [B(NI_PFI(4))] = I(5), 309 [B(NI_PFI(5))] = I(6), 310 [B(NI_PFI(6))] = I(7), 311 [B(NI_PFI(7))] = I(8), 312 [B(NI_PFI(8))] = I(9), 313 [B(NI_PFI(9))] = I(10), 314 [B(TRIGGER_LINE(0))] = I(11), 315 [B(TRIGGER_LINE(1))] = I(12), 316 [B(TRIGGER_LINE(2))] = I(13), 317 [B(TRIGGER_LINE(3))] = I(14), 318 [B(TRIGGER_LINE(4))] = I(15), 319 [B(TRIGGER_LINE(5))] = I(16), 320 [B(TRIGGER_LINE(6))] = I(17), 321 [B(NI_CtrInternalOutput(0))] = I(20), 322 [B(PXI_Star)] = I(17), 323 [B(NI_AI_StartTrigger)] = I(21), 324 [B(NI_AI_ReferenceTrigger)] = I(18), 325 [B(NI_LogicLow)] = I(31), 326 }, 327 [B(NI_CtrOut(0))] = { 328 [B(TRIGGER_LINE(0))] = I(1), 329 [B(TRIGGER_LINE(1))] = I(2), 330 [B(TRIGGER_LINE(2))] = I(3), 331 [B(TRIGGER_LINE(3))] = I(4), 332 [B(TRIGGER_LINE(4))] = I(5), 333 [B(TRIGGER_LINE(5))] = I(6), 334 [B(TRIGGER_LINE(6))] = I(7), 335 [B(NI_CtrInternalOutput(0))] = I(0), 336 [B(PXI_Star)] = I(7), 337 }, 338 [B(NI_CtrOut(1))] = { 339 [B(NI_CtrInternalOutput(1))] = I(0), 340 }, 341 [B(NI_AI_SampleClock)] = { 342 [B(NI_PFI(0))] = I(1), 343 [B(NI_PFI(1))] = I(2), 344 [B(NI_PFI(2))] = I(3), 345 [B(NI_PFI(3))] = I(4), 346 [B(NI_PFI(4))] = I(5), 347 [B(NI_PFI(5))] = I(6), 348 [B(NI_PFI(6))] = I(7), 349 [B(NI_PFI(7))] = I(8), 350 [B(NI_PFI(8))] = I(9), 351 [B(NI_PFI(9))] = I(10), 352 [B(TRIGGER_LINE(0))] = I(11), 353 [B(TRIGGER_LINE(1))] = I(12), 354 [B(TRIGGER_LINE(2))] = I(13), 355 [B(TRIGGER_LINE(3))] = I(14), 356 [B(TRIGGER_LINE(4))] = I(15), 357 [B(TRIGGER_LINE(5))] = I(16), 358 [B(TRIGGER_LINE(6))] = I(17), 359 [B(NI_CtrInternalOutput(0))] = I(19), 360 [B(PXI_Star)] = I(17), 361 [B(NI_AI_SampleClockTimebase)] = I(0), 362 [B(NI_LogicLow)] = I(31), 363 }, 364 [B(NI_AI_SampleClockTimebase)] = { 365 /* These are not currently implemented in ni modules */ 366 [B(NI_PFI(0))] = U(1), 367 [B(NI_PFI(1))] = U(2), 368 [B(NI_PFI(2))] = U(3), 369 [B(NI_PFI(3))] = U(4), 370 [B(NI_PFI(4))] = U(5), 371 [B(NI_PFI(5))] = U(6), 372 [B(NI_PFI(6))] = U(7), 373 [B(NI_PFI(7))] = U(8), 374 [B(NI_PFI(8))] = U(9), 375 [B(NI_PFI(9))] = U(10), 376 [B(TRIGGER_LINE(0))] = U(11), 377 [B(TRIGGER_LINE(1))] = U(12), 378 [B(TRIGGER_LINE(2))] = U(13), 379 [B(TRIGGER_LINE(3))] = U(14), 380 [B(TRIGGER_LINE(4))] = U(15), 381 [B(TRIGGER_LINE(5))] = U(16), 382 [B(TRIGGER_LINE(6))] = U(17), 383 [B(PXI_Star)] = U(17), 384 [B(NI_20MHzTimebase)] = U(0), 385 [B(NI_100kHzTimebase)] = U(19), 386 [B(NI_LogicLow)] = U(31), 387 }, 388 [B(NI_AI_StartTrigger)] = { 389 [B(NI_PFI(0))] = I(1), 390 [B(NI_PFI(1))] = I(2), 391 [B(NI_PFI(2))] = I(3), 392 [B(NI_PFI(3))] = I(4), 393 [B(NI_PFI(4))] = I(5), 394 [B(NI_PFI(5))] = I(6), 395 [B(NI_PFI(6))] = I(7), 396 [B(NI_PFI(7))] = I(8), 397 [B(NI_PFI(8))] = I(9), 398 [B(NI_PFI(9))] = I(10), 399 [B(TRIGGER_LINE(0))] = I(11), 400 [B(TRIGGER_LINE(1))] = I(12), 401 [B(TRIGGER_LINE(2))] = I(13), 402 [B(TRIGGER_LINE(3))] = I(14), 403 [B(TRIGGER_LINE(4))] = I(15), 404 [B(TRIGGER_LINE(5))] = I(16), 405 [B(TRIGGER_LINE(6))] = I(17), 406 [B(NI_CtrInternalOutput(0))] = I(18), 407 [B(PXI_Star)] = I(17), 408 [B(NI_LogicLow)] = I(31), 409 }, 410 [B(NI_AI_ReferenceTrigger)] = { 411 /* These are not currently implemented in ni modules */ 412 [B(NI_PFI(0))] = U(1), 413 [B(NI_PFI(1))] = U(2), 414 [B(NI_PFI(2))] = U(3), 415 [B(NI_PFI(3))] = U(4), 416 [B(NI_PFI(4))] = U(5), 417 [B(NI_PFI(5))] = U(6), 418 [B(NI_PFI(6))] = U(7), 419 [B(NI_PFI(7))] = U(8), 420 [B(NI_PFI(8))] = U(9), 421 [B(NI_PFI(9))] = U(10), 422 [B(TRIGGER_LINE(0))] = U(11), 423 [B(TRIGGER_LINE(1))] = U(12), 424 [B(TRIGGER_LINE(2))] = U(13), 425 [B(TRIGGER_LINE(3))] = U(14), 426 [B(TRIGGER_LINE(4))] = U(15), 427 [B(TRIGGER_LINE(5))] = U(16), 428 [B(TRIGGER_LINE(6))] = U(17), 429 [B(PXI_Star)] = U(17), 430 [B(NI_LogicLow)] = U(31), 431 }, 432 [B(NI_AI_ConvertClock)] = { 433 [B(NI_PFI(0))] = I(1), 434 [B(NI_PFI(1))] = I(2), 435 [B(NI_PFI(2))] = I(3), 436 [B(NI_PFI(3))] = I(4), 437 [B(NI_PFI(4))] = I(5), 438 [B(NI_PFI(5))] = I(6), 439 [B(NI_PFI(6))] = I(7), 440 [B(NI_PFI(7))] = I(8), 441 [B(NI_PFI(8))] = I(9), 442 [B(NI_PFI(9))] = I(10), 443 [B(TRIGGER_LINE(0))] = I(11), 444 [B(TRIGGER_LINE(1))] = I(12), 445 [B(TRIGGER_LINE(2))] = I(13), 446 [B(TRIGGER_LINE(3))] = I(14), 447 [B(TRIGGER_LINE(4))] = I(15), 448 [B(TRIGGER_LINE(5))] = I(16), 449 [B(TRIGGER_LINE(6))] = I(17), 450 [B(NI_CtrInternalOutput(0))] = I(19), 451 [B(PXI_Star)] = I(17), 452 [B(NI_AI_ConvertClockTimebase)] = I(0), 453 [B(NI_LogicLow)] = I(31), 454 }, 455 [B(NI_AI_ConvertClockTimebase)] = { 456 /* These are not currently implemented in ni modules */ 457 [B(NI_AI_SampleClockTimebase)] = U(0), 458 [B(NI_20MHzTimebase)] = U(1), 459 }, 460 [B(NI_AI_PauseTrigger)] = { 461 /* These are not currently implemented in ni modules */ 462 [B(NI_PFI(0))] = U(1), 463 [B(NI_PFI(1))] = U(2), 464 [B(NI_PFI(2))] = U(3), 465 [B(NI_PFI(3))] = U(4), 466 [B(NI_PFI(4))] = U(5), 467 [B(NI_PFI(5))] = U(6), 468 [B(NI_PFI(6))] = U(7), 469 [B(NI_PFI(7))] = U(8), 470 [B(NI_PFI(8))] = U(9), 471 [B(NI_PFI(9))] = U(10), 472 [B(TRIGGER_LINE(0))] = U(11), 473 [B(TRIGGER_LINE(1))] = U(12), 474 [B(TRIGGER_LINE(2))] = U(13), 475 [B(TRIGGER_LINE(3))] = U(14), 476 [B(TRIGGER_LINE(4))] = U(15), 477 [B(TRIGGER_LINE(5))] = U(16), 478 [B(TRIGGER_LINE(6))] = U(17), 479 [B(PXI_Star)] = U(17), 480 [B(NI_LogicLow)] = U(31), 481 }, 482 [B(NI_AO_SampleClock)] = { 483 [B(NI_PFI(0))] = I(1), 484 [B(NI_PFI(1))] = I(2), 485 [B(NI_PFI(2))] = I(3), 486 [B(NI_PFI(3))] = I(4), 487 [B(NI_PFI(4))] = I(5), 488 [B(NI_PFI(5))] = I(6), 489 [B(NI_PFI(6))] = I(7), 490 [B(NI_PFI(7))] = I(8), 491 [B(NI_PFI(8))] = I(9), 492 [B(NI_PFI(9))] = I(10), 493 [B(TRIGGER_LINE(0))] = I(11), 494 [B(TRIGGER_LINE(1))] = I(12), 495 [B(TRIGGER_LINE(2))] = I(13), 496 [B(TRIGGER_LINE(3))] = I(14), 497 [B(TRIGGER_LINE(4))] = I(15), 498 [B(TRIGGER_LINE(5))] = I(16), 499 [B(TRIGGER_LINE(6))] = I(17), 500 [B(NI_CtrInternalOutput(1))] = I(19), 501 [B(PXI_Star)] = I(17), 502 [B(NI_AO_SampleClockTimebase)] = I(0), 503 [B(NI_LogicLow)] = I(31), 504 }, 505 [B(NI_AO_SampleClockTimebase)] = { 506 /* These are not currently implemented in ni modules */ 507 [B(NI_PFI(0))] = U(1), 508 [B(NI_PFI(1))] = U(2), 509 [B(NI_PFI(2))] = U(3), 510 [B(NI_PFI(3))] = U(4), 511 [B(NI_PFI(4))] = U(5), 512 [B(NI_PFI(5))] = U(6), 513 [B(NI_PFI(6))] = U(7), 514 [B(NI_PFI(7))] = U(8), 515 [B(NI_PFI(8))] = U(9), 516 [B(NI_PFI(9))] = U(10), 517 [B(TRIGGER_LINE(0))] = U(11), 518 [B(TRIGGER_LINE(1))] = U(12), 519 [B(TRIGGER_LINE(2))] = U(13), 520 [B(TRIGGER_LINE(3))] = U(14), 521 [B(TRIGGER_LINE(4))] = U(15), 522 [B(TRIGGER_LINE(5))] = U(16), 523 [B(TRIGGER_LINE(6))] = U(17), 524 [B(PXI_Star)] = U(17), 525 [B(NI_20MHzTimebase)] = U(0), 526 [B(NI_100kHzTimebase)] = U(19), 527 [B(NI_LogicLow)] = U(31), 528 }, 529 [B(NI_AO_StartTrigger)] = { 530 [B(NI_PFI(0))] = I(1), 531 [B(NI_PFI(1))] = I(2), 532 [B(NI_PFI(2))] = I(3), 533 [B(NI_PFI(3))] = I(4), 534 [B(NI_PFI(4))] = I(5), 535 [B(NI_PFI(5))] = I(6), 536 [B(NI_PFI(6))] = I(7), 537 [B(NI_PFI(7))] = I(8), 538 [B(NI_PFI(8))] = I(9), 539 [B(NI_PFI(9))] = I(10), 540 [B(TRIGGER_LINE(0))] = I(11), 541 [B(TRIGGER_LINE(1))] = I(12), 542 [B(TRIGGER_LINE(2))] = I(13), 543 [B(TRIGGER_LINE(3))] = I(14), 544 [B(TRIGGER_LINE(4))] = I(15), 545 [B(TRIGGER_LINE(5))] = I(16), 546 [B(TRIGGER_LINE(6))] = I(17), 547 [B(PXI_Star)] = I(17), 548 /* 549 * for the signal route 550 * (NI_AI_StartTrigger->NI_AO_StartTrigger), MHDDK says 551 * used register value 18 and DAQ-STC says 19. 552 * Hoping that the MHDDK is correct--being a "working" 553 * example. 554 */ 555 [B(NI_AI_StartTrigger)] = I(18), 556 [B(NI_LogicLow)] = I(31), 557 }, 558 [B(NI_AO_PauseTrigger)] = { 559 /* These are not currently implemented in ni modules */ 560 [B(NI_PFI(0))] = U(1), 561 [B(NI_PFI(1))] = U(2), 562 [B(NI_PFI(2))] = U(3), 563 [B(NI_PFI(3))] = U(4), 564 [B(NI_PFI(4))] = U(5), 565 [B(NI_PFI(5))] = U(6), 566 [B(NI_PFI(6))] = U(7), 567 [B(NI_PFI(7))] = U(8), 568 [B(NI_PFI(8))] = U(9), 569 [B(NI_PFI(9))] = U(10), 570 [B(TRIGGER_LINE(0))] = U(11), 571 [B(TRIGGER_LINE(1))] = U(12), 572 [B(TRIGGER_LINE(2))] = U(13), 573 [B(TRIGGER_LINE(3))] = U(14), 574 [B(TRIGGER_LINE(4))] = U(15), 575 [B(TRIGGER_LINE(5))] = U(16), 576 [B(TRIGGER_LINE(6))] = U(17), 577 [B(PXI_Star)] = U(17), 578 [B(NI_LogicLow)] = U(31), 579 }, 580 [B(NI_MasterTimebase)] = { 581 /* These are not currently implemented in ni modules */ 582 [B(TRIGGER_LINE(7))] = U(1), 583 [B(PXI_Star)] = U(2), 584 [B(PXI_Clk10)] = U(3), 585 [B(NI_10MHzRefClock)] = U(0), 586 }, 587 /* 588 * This symbol is not defined and nothing for this is 589 * implemented--just including this because data was found in 590 * the NI-STC for it--can't remember where. 591 * [B(NI_FrequencyOutTimebase)] = { 592 * ** These are not currently implemented in ni modules ** 593 * [B(NI_20MHzTimebase)] = U(0), 594 * [B(NI_100kHzTimebase)] = U(1), 595 * }, 596 */ 597 [B(NI_RGOUT0)] = { 598 [B(NI_CtrInternalOutput(0))] = I(0), 599 [B(NI_CtrOut(0))] = I(1), 600 }, 601 }, 602 }; 603