1 /*
2 * TXx9 NAND flash memory controller driver
3 * Based on RBTX49xx patch from CELF patch archive.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * (C) Copyright TOSHIBA CORPORATION 2004-2007
10 * All Rights Reserved.
11 */
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/mtd/mtd.h>
18 #include <linux/mtd/nand.h>
19 #include <linux/mtd/nand_ecc.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/io.h>
22 #include <asm/txx9/ndfmc.h>
23
24 /* TXX9 NDFMC Registers */
25 #define TXX9_NDFDTR 0x00
26 #define TXX9_NDFMCR 0x04
27 #define TXX9_NDFSR 0x08
28 #define TXX9_NDFISR 0x0c
29 #define TXX9_NDFIMR 0x10
30 #define TXX9_NDFSPR 0x14
31 #define TXX9_NDFRSTR 0x18 /* not TX4939 */
32
33 /* NDFMCR : NDFMC Mode Control */
34 #define TXX9_NDFMCR_WE 0x80
35 #define TXX9_NDFMCR_ECC_ALL 0x60
36 #define TXX9_NDFMCR_ECC_RESET 0x60
37 #define TXX9_NDFMCR_ECC_READ 0x40
38 #define TXX9_NDFMCR_ECC_ON 0x20
39 #define TXX9_NDFMCR_ECC_OFF 0x00
40 #define TXX9_NDFMCR_CE 0x10
41 #define TXX9_NDFMCR_BSPRT 0x04 /* TX4925/TX4926 only */
42 #define TXX9_NDFMCR_ALE 0x02
43 #define TXX9_NDFMCR_CLE 0x01
44 /* TX4939 only */
45 #define TXX9_NDFMCR_X16 0x0400
46 #define TXX9_NDFMCR_DMAREQ_MASK 0x0300
47 #define TXX9_NDFMCR_DMAREQ_NODMA 0x0000
48 #define TXX9_NDFMCR_DMAREQ_128 0x0100
49 #define TXX9_NDFMCR_DMAREQ_256 0x0200
50 #define TXX9_NDFMCR_DMAREQ_512 0x0300
51 #define TXX9_NDFMCR_CS_MASK 0x0c
52 #define TXX9_NDFMCR_CS(ch) ((ch) << 2)
53
54 /* NDFMCR : NDFMC Status */
55 #define TXX9_NDFSR_BUSY 0x80
56 /* TX4939 only */
57 #define TXX9_NDFSR_DMARUN 0x40
58
59 /* NDFMCR : NDFMC Reset */
60 #define TXX9_NDFRSTR_RST 0x01
61
62 struct txx9ndfmc_priv {
63 struct platform_device *dev;
64 struct nand_chip chip;
65 struct mtd_info mtd;
66 int cs;
67 const char *mtdname;
68 };
69
70 #define MAX_TXX9NDFMC_DEV 4
71 struct txx9ndfmc_drvdata {
72 struct mtd_info *mtds[MAX_TXX9NDFMC_DEV];
73 void __iomem *base;
74 unsigned char hold; /* in gbusclock */
75 unsigned char spw; /* in gbusclock */
76 struct nand_hw_control hw_control;
77 };
78
mtd_to_platdev(struct mtd_info * mtd)79 static struct platform_device *mtd_to_platdev(struct mtd_info *mtd)
80 {
81 struct nand_chip *chip = mtd->priv;
82 struct txx9ndfmc_priv *txx9_priv = chip->priv;
83 return txx9_priv->dev;
84 }
85
ndregaddr(struct platform_device * dev,unsigned int reg)86 static void __iomem *ndregaddr(struct platform_device *dev, unsigned int reg)
87 {
88 struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
89 struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
90
91 return drvdata->base + (reg << plat->shift);
92 }
93
txx9ndfmc_read(struct platform_device * dev,unsigned int reg)94 static u32 txx9ndfmc_read(struct platform_device *dev, unsigned int reg)
95 {
96 return __raw_readl(ndregaddr(dev, reg));
97 }
98
txx9ndfmc_write(struct platform_device * dev,u32 val,unsigned int reg)99 static void txx9ndfmc_write(struct platform_device *dev,
100 u32 val, unsigned int reg)
101 {
102 __raw_writel(val, ndregaddr(dev, reg));
103 }
104
txx9ndfmc_read_byte(struct mtd_info * mtd)105 static uint8_t txx9ndfmc_read_byte(struct mtd_info *mtd)
106 {
107 struct platform_device *dev = mtd_to_platdev(mtd);
108
109 return txx9ndfmc_read(dev, TXX9_NDFDTR);
110 }
111
txx9ndfmc_write_buf(struct mtd_info * mtd,const uint8_t * buf,int len)112 static void txx9ndfmc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
113 int len)
114 {
115 struct platform_device *dev = mtd_to_platdev(mtd);
116 void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
117 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
118
119 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_WE, TXX9_NDFMCR);
120 while (len--)
121 __raw_writel(*buf++, ndfdtr);
122 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
123 }
124
txx9ndfmc_read_buf(struct mtd_info * mtd,uint8_t * buf,int len)125 static void txx9ndfmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
126 {
127 struct platform_device *dev = mtd_to_platdev(mtd);
128 void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
129
130 while (len--)
131 *buf++ = __raw_readl(ndfdtr);
132 }
133
txx9ndfmc_verify_buf(struct mtd_info * mtd,const uint8_t * buf,int len)134 static int txx9ndfmc_verify_buf(struct mtd_info *mtd, const uint8_t *buf,
135 int len)
136 {
137 struct platform_device *dev = mtd_to_platdev(mtd);
138 void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
139
140 while (len--)
141 if (*buf++ != (uint8_t)__raw_readl(ndfdtr))
142 return -EFAULT;
143 return 0;
144 }
145
txx9ndfmc_cmd_ctrl(struct mtd_info * mtd,int cmd,unsigned int ctrl)146 static void txx9ndfmc_cmd_ctrl(struct mtd_info *mtd, int cmd,
147 unsigned int ctrl)
148 {
149 struct nand_chip *chip = mtd->priv;
150 struct txx9ndfmc_priv *txx9_priv = chip->priv;
151 struct platform_device *dev = txx9_priv->dev;
152 struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
153
154 if (ctrl & NAND_CTRL_CHANGE) {
155 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
156
157 mcr &= ~(TXX9_NDFMCR_CLE | TXX9_NDFMCR_ALE | TXX9_NDFMCR_CE);
158 mcr |= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0;
159 mcr |= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0;
160 /* TXX9_NDFMCR_CE bit is 0:high 1:low */
161 mcr |= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0;
162 if (txx9_priv->cs >= 0 && (ctrl & NAND_NCE)) {
163 mcr &= ~TXX9_NDFMCR_CS_MASK;
164 mcr |= TXX9_NDFMCR_CS(txx9_priv->cs);
165 }
166 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
167 }
168 if (cmd != NAND_CMD_NONE)
169 txx9ndfmc_write(dev, cmd & 0xff, TXX9_NDFDTR);
170 if (plat->flags & NDFMC_PLAT_FLAG_DUMMYWRITE) {
171 /* dummy write to update external latch */
172 if ((ctrl & NAND_CTRL_CHANGE) && cmd == NAND_CMD_NONE)
173 txx9ndfmc_write(dev, 0, TXX9_NDFDTR);
174 }
175 mmiowb();
176 }
177
txx9ndfmc_dev_ready(struct mtd_info * mtd)178 static int txx9ndfmc_dev_ready(struct mtd_info *mtd)
179 {
180 struct platform_device *dev = mtd_to_platdev(mtd);
181
182 return !(txx9ndfmc_read(dev, TXX9_NDFSR) & TXX9_NDFSR_BUSY);
183 }
184
txx9ndfmc_calculate_ecc(struct mtd_info * mtd,const uint8_t * dat,uint8_t * ecc_code)185 static int txx9ndfmc_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
186 uint8_t *ecc_code)
187 {
188 struct platform_device *dev = mtd_to_platdev(mtd);
189 struct nand_chip *chip = mtd->priv;
190 int eccbytes;
191 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
192
193 mcr &= ~TXX9_NDFMCR_ECC_ALL;
194 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
195 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_READ, TXX9_NDFMCR);
196 for (eccbytes = chip->ecc.bytes; eccbytes > 0; eccbytes -= 3) {
197 ecc_code[1] = txx9ndfmc_read(dev, TXX9_NDFDTR);
198 ecc_code[0] = txx9ndfmc_read(dev, TXX9_NDFDTR);
199 ecc_code[2] = txx9ndfmc_read(dev, TXX9_NDFDTR);
200 ecc_code += 3;
201 }
202 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
203 return 0;
204 }
205
txx9ndfmc_correct_data(struct mtd_info * mtd,unsigned char * buf,unsigned char * read_ecc,unsigned char * calc_ecc)206 static int txx9ndfmc_correct_data(struct mtd_info *mtd, unsigned char *buf,
207 unsigned char *read_ecc, unsigned char *calc_ecc)
208 {
209 struct nand_chip *chip = mtd->priv;
210 int eccsize;
211 int corrected = 0;
212 int stat;
213
214 for (eccsize = chip->ecc.size; eccsize > 0; eccsize -= 256) {
215 stat = __nand_correct_data(buf, read_ecc, calc_ecc, 256);
216 if (stat < 0)
217 return stat;
218 corrected += stat;
219 buf += 256;
220 read_ecc += 3;
221 calc_ecc += 3;
222 }
223 return corrected;
224 }
225
txx9ndfmc_enable_hwecc(struct mtd_info * mtd,int mode)226 static void txx9ndfmc_enable_hwecc(struct mtd_info *mtd, int mode)
227 {
228 struct platform_device *dev = mtd_to_platdev(mtd);
229 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
230
231 mcr &= ~TXX9_NDFMCR_ECC_ALL;
232 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_RESET, TXX9_NDFMCR);
233 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
234 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_ON, TXX9_NDFMCR);
235 }
236
txx9ndfmc_initialize(struct platform_device * dev)237 static void txx9ndfmc_initialize(struct platform_device *dev)
238 {
239 struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
240 struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
241 int tmout = 100;
242
243 if (plat->flags & NDFMC_PLAT_FLAG_NO_RSTR)
244 ; /* no NDFRSTR. Write to NDFSPR resets the NDFMC. */
245 else {
246 /* reset NDFMC */
247 txx9ndfmc_write(dev,
248 txx9ndfmc_read(dev, TXX9_NDFRSTR) |
249 TXX9_NDFRSTR_RST,
250 TXX9_NDFRSTR);
251 while (txx9ndfmc_read(dev, TXX9_NDFRSTR) & TXX9_NDFRSTR_RST) {
252 if (--tmout == 0) {
253 dev_err(&dev->dev, "reset failed.\n");
254 break;
255 }
256 udelay(1);
257 }
258 }
259 /* setup Hold Time, Strobe Pulse Width */
260 txx9ndfmc_write(dev, (drvdata->hold << 4) | drvdata->spw, TXX9_NDFSPR);
261 txx9ndfmc_write(dev,
262 (plat->flags & NDFMC_PLAT_FLAG_USE_BSPRT) ?
263 TXX9_NDFMCR_BSPRT : 0, TXX9_NDFMCR);
264 }
265
266 #define TXX9NDFMC_NS_TO_CYC(gbusclk, ns) \
267 DIV_ROUND_UP((ns) * DIV_ROUND_UP(gbusclk, 1000), 1000000)
268
txx9ndfmc_nand_scan(struct mtd_info * mtd)269 static int txx9ndfmc_nand_scan(struct mtd_info *mtd)
270 {
271 struct nand_chip *chip = mtd->priv;
272 int ret;
273
274 ret = nand_scan_ident(mtd, 1, NULL);
275 if (!ret) {
276 if (mtd->writesize >= 512) {
277 /* Hardware ECC 6 byte ECC per 512 Byte data */
278 chip->ecc.size = 512;
279 chip->ecc.bytes = 6;
280 }
281 ret = nand_scan_tail(mtd);
282 }
283 return ret;
284 }
285
txx9ndfmc_probe(struct platform_device * dev)286 static int __init txx9ndfmc_probe(struct platform_device *dev)
287 {
288 struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
289 int hold, spw;
290 int i;
291 struct txx9ndfmc_drvdata *drvdata;
292 unsigned long gbusclk = plat->gbus_clock;
293 struct resource *res;
294
295 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
296 if (!res)
297 return -ENODEV;
298 drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL);
299 if (!drvdata)
300 return -ENOMEM;
301 drvdata->base = devm_request_and_ioremap(&dev->dev, res);
302 if (!drvdata->base)
303 return -EBUSY;
304
305 hold = plat->hold ?: 20; /* tDH */
306 spw = plat->spw ?: 90; /* max(tREADID, tWP, tRP) */
307
308 hold = TXX9NDFMC_NS_TO_CYC(gbusclk, hold);
309 spw = TXX9NDFMC_NS_TO_CYC(gbusclk, spw);
310 if (plat->flags & NDFMC_PLAT_FLAG_HOLDADD)
311 hold -= 2; /* actual hold time : (HOLD + 2) BUSCLK */
312 spw -= 1; /* actual wait time : (SPW + 1) BUSCLK */
313 hold = clamp(hold, 1, 15);
314 drvdata->hold = hold;
315 spw = clamp(spw, 1, 15);
316 drvdata->spw = spw;
317 dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n",
318 (gbusclk + 500000) / 1000000, hold, spw);
319
320 spin_lock_init(&drvdata->hw_control.lock);
321 init_waitqueue_head(&drvdata->hw_control.wq);
322
323 platform_set_drvdata(dev, drvdata);
324 txx9ndfmc_initialize(dev);
325
326 for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
327 struct txx9ndfmc_priv *txx9_priv;
328 struct nand_chip *chip;
329 struct mtd_info *mtd;
330
331 if (!(plat->ch_mask & (1 << i)))
332 continue;
333 txx9_priv = kzalloc(sizeof(struct txx9ndfmc_priv),
334 GFP_KERNEL);
335 if (!txx9_priv) {
336 dev_err(&dev->dev, "Unable to allocate "
337 "TXx9 NDFMC MTD device structure.\n");
338 continue;
339 }
340 chip = &txx9_priv->chip;
341 mtd = &txx9_priv->mtd;
342 mtd->owner = THIS_MODULE;
343
344 mtd->priv = chip;
345
346 chip->read_byte = txx9ndfmc_read_byte;
347 chip->read_buf = txx9ndfmc_read_buf;
348 chip->write_buf = txx9ndfmc_write_buf;
349 chip->verify_buf = txx9ndfmc_verify_buf;
350 chip->cmd_ctrl = txx9ndfmc_cmd_ctrl;
351 chip->dev_ready = txx9ndfmc_dev_ready;
352 chip->ecc.calculate = txx9ndfmc_calculate_ecc;
353 chip->ecc.correct = txx9ndfmc_correct_data;
354 chip->ecc.hwctl = txx9ndfmc_enable_hwecc;
355 chip->ecc.mode = NAND_ECC_HW;
356 /* txx9ndfmc_nand_scan will overwrite ecc.size and ecc.bytes */
357 chip->ecc.size = 256;
358 chip->ecc.bytes = 3;
359 chip->chip_delay = 100;
360 chip->controller = &drvdata->hw_control;
361
362 chip->priv = txx9_priv;
363 txx9_priv->dev = dev;
364
365 if (plat->ch_mask != 1) {
366 txx9_priv->cs = i;
367 txx9_priv->mtdname = kasprintf(GFP_KERNEL, "%s.%u",
368 dev_name(&dev->dev), i);
369 } else {
370 txx9_priv->cs = -1;
371 txx9_priv->mtdname = kstrdup(dev_name(&dev->dev),
372 GFP_KERNEL);
373 }
374 if (!txx9_priv->mtdname) {
375 kfree(txx9_priv);
376 dev_err(&dev->dev, "Unable to allocate MTD name.\n");
377 continue;
378 }
379 if (plat->wide_mask & (1 << i))
380 chip->options |= NAND_BUSWIDTH_16;
381
382 if (txx9ndfmc_nand_scan(mtd)) {
383 kfree(txx9_priv->mtdname);
384 kfree(txx9_priv);
385 continue;
386 }
387 mtd->name = txx9_priv->mtdname;
388
389 mtd_device_parse_register(mtd, NULL, 0, NULL, 0);
390 drvdata->mtds[i] = mtd;
391 }
392
393 return 0;
394 }
395
txx9ndfmc_remove(struct platform_device * dev)396 static int __exit txx9ndfmc_remove(struct platform_device *dev)
397 {
398 struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
399 int i;
400
401 platform_set_drvdata(dev, NULL);
402 if (!drvdata)
403 return 0;
404 for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
405 struct mtd_info *mtd = drvdata->mtds[i];
406 struct nand_chip *chip;
407 struct txx9ndfmc_priv *txx9_priv;
408
409 if (!mtd)
410 continue;
411 chip = mtd->priv;
412 txx9_priv = chip->priv;
413
414 nand_release(mtd);
415 kfree(txx9_priv->mtdname);
416 kfree(txx9_priv);
417 }
418 return 0;
419 }
420
421 #ifdef CONFIG_PM
txx9ndfmc_resume(struct platform_device * dev)422 static int txx9ndfmc_resume(struct platform_device *dev)
423 {
424 if (platform_get_drvdata(dev))
425 txx9ndfmc_initialize(dev);
426 return 0;
427 }
428 #else
429 #define txx9ndfmc_resume NULL
430 #endif
431
432 static struct platform_driver txx9ndfmc_driver = {
433 .remove = __exit_p(txx9ndfmc_remove),
434 .resume = txx9ndfmc_resume,
435 .driver = {
436 .name = "txx9ndfmc",
437 .owner = THIS_MODULE,
438 },
439 };
440
txx9ndfmc_init(void)441 static int __init txx9ndfmc_init(void)
442 {
443 return platform_driver_probe(&txx9ndfmc_driver, txx9ndfmc_probe);
444 }
445
txx9ndfmc_exit(void)446 static void __exit txx9ndfmc_exit(void)
447 {
448 platform_driver_unregister(&txx9ndfmc_driver);
449 }
450
451 module_init(txx9ndfmc_init);
452 module_exit(txx9ndfmc_exit);
453
454 MODULE_LICENSE("GPL");
455 MODULE_DESCRIPTION("TXx9 SoC NAND flash controller driver");
456 MODULE_ALIAS("platform:txx9ndfmc");
457