1 /* Freescale Integrated Flash Controller 2 * 3 * Copyright 2011 Freescale Semiconductor, Inc 4 * 5 * Author: Dipen Dudhat <dipen.dudhat@freescale.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 22 #ifndef __ASM_FSL_IFC_H 23 #define __ASM_FSL_IFC_H 24 25 #include <linux/compiler.h> 26 #include <linux/types.h> 27 #include <linux/io.h> 28 29 #include <linux/of_platform.h> 30 #include <linux/interrupt.h> 31 32 #define FSL_IFC_BANK_COUNT 4 33 34 /* 35 * CSPR - Chip Select Property Register 36 */ 37 #define CSPR_BA 0xFFFF0000 38 #define CSPR_BA_SHIFT 16 39 #define CSPR_PORT_SIZE 0x00000180 40 #define CSPR_PORT_SIZE_SHIFT 7 41 /* Port Size 8 bit */ 42 #define CSPR_PORT_SIZE_8 0x00000080 43 /* Port Size 16 bit */ 44 #define CSPR_PORT_SIZE_16 0x00000100 45 /* Port Size 32 bit */ 46 #define CSPR_PORT_SIZE_32 0x00000180 47 /* Write Protect */ 48 #define CSPR_WP 0x00000040 49 #define CSPR_WP_SHIFT 6 50 /* Machine Select */ 51 #define CSPR_MSEL 0x00000006 52 #define CSPR_MSEL_SHIFT 1 53 /* NOR */ 54 #define CSPR_MSEL_NOR 0x00000000 55 /* NAND */ 56 #define CSPR_MSEL_NAND 0x00000002 57 /* GPCM */ 58 #define CSPR_MSEL_GPCM 0x00000004 59 /* Bank Valid */ 60 #define CSPR_V 0x00000001 61 #define CSPR_V_SHIFT 0 62 63 /* 64 * Address Mask Register 65 */ 66 #define IFC_AMASK_MASK 0xFFFF0000 67 #define IFC_AMASK_SHIFT 16 68 #define IFC_AMASK(n) (IFC_AMASK_MASK << \ 69 (__ilog2(n) - IFC_AMASK_SHIFT)) 70 71 /* 72 * Chip Select Option Register IFC_NAND Machine 73 */ 74 /* Enable ECC Encoder */ 75 #define CSOR_NAND_ECC_ENC_EN 0x80000000 76 #define CSOR_NAND_ECC_MODE_MASK 0x30000000 77 /* 4 bit correction per 520 Byte sector */ 78 #define CSOR_NAND_ECC_MODE_4 0x00000000 79 /* 8 bit correction per 528 Byte sector */ 80 #define CSOR_NAND_ECC_MODE_8 0x10000000 81 /* Enable ECC Decoder */ 82 #define CSOR_NAND_ECC_DEC_EN 0x04000000 83 /* Row Address Length */ 84 #define CSOR_NAND_RAL_MASK 0x01800000 85 #define CSOR_NAND_RAL_SHIFT 20 86 #define CSOR_NAND_RAL_1 0x00000000 87 #define CSOR_NAND_RAL_2 0x00800000 88 #define CSOR_NAND_RAL_3 0x01000000 89 #define CSOR_NAND_RAL_4 0x01800000 90 /* Page Size 512b, 2k, 4k */ 91 #define CSOR_NAND_PGS_MASK 0x00180000 92 #define CSOR_NAND_PGS_SHIFT 16 93 #define CSOR_NAND_PGS_512 0x00000000 94 #define CSOR_NAND_PGS_2K 0x00080000 95 #define CSOR_NAND_PGS_4K 0x00100000 96 /* Spare region Size */ 97 #define CSOR_NAND_SPRZ_MASK 0x0000E000 98 #define CSOR_NAND_SPRZ_SHIFT 13 99 #define CSOR_NAND_SPRZ_16 0x00000000 100 #define CSOR_NAND_SPRZ_64 0x00002000 101 #define CSOR_NAND_SPRZ_128 0x00004000 102 #define CSOR_NAND_SPRZ_210 0x00006000 103 #define CSOR_NAND_SPRZ_218 0x00008000 104 #define CSOR_NAND_SPRZ_224 0x0000A000 105 /* Pages Per Block */ 106 #define CSOR_NAND_PB_MASK 0x00000700 107 #define CSOR_NAND_PB_SHIFT 8 108 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) 109 /* Time for Read Enable High to Output High Impedance */ 110 #define CSOR_NAND_TRHZ_MASK 0x0000001C 111 #define CSOR_NAND_TRHZ_SHIFT 2 112 #define CSOR_NAND_TRHZ_20 0x00000000 113 #define CSOR_NAND_TRHZ_40 0x00000004 114 #define CSOR_NAND_TRHZ_60 0x00000008 115 #define CSOR_NAND_TRHZ_80 0x0000000C 116 #define CSOR_NAND_TRHZ_100 0x00000010 117 /* Buffer control disable */ 118 #define CSOR_NAND_BCTLD 0x00000001 119 120 /* 121 * Chip Select Option Register - NOR Flash Mode 122 */ 123 /* Enable Address shift Mode */ 124 #define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 125 /* Page Read Enable from NOR device */ 126 #define CSOR_NOR_PGRD_EN 0x10000000 127 /* AVD Toggle Enable during Burst Program */ 128 #define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 129 /* Address Data Multiplexing Shift */ 130 #define CSOR_NOR_ADM_MASK 0x0003E000 131 #define CSOR_NOR_ADM_SHIFT_SHIFT 13 132 #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) 133 /* Type of the NOR device hooked */ 134 #define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000 135 #define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 136 /* Time for Read Enable High to Output High Impedance */ 137 #define CSOR_NOR_TRHZ_MASK 0x0000001C 138 #define CSOR_NOR_TRHZ_SHIFT 2 139 #define CSOR_NOR_TRHZ_20 0x00000000 140 #define CSOR_NOR_TRHZ_40 0x00000004 141 #define CSOR_NOR_TRHZ_60 0x00000008 142 #define CSOR_NOR_TRHZ_80 0x0000000C 143 #define CSOR_NOR_TRHZ_100 0x00000010 144 /* Buffer control disable */ 145 #define CSOR_NOR_BCTLD 0x00000001 146 147 /* 148 * Chip Select Option Register - GPCM Mode 149 */ 150 /* GPCM Mode - Normal */ 151 #define CSOR_GPCM_GPMODE_NORMAL 0x00000000 152 /* GPCM Mode - GenericASIC */ 153 #define CSOR_GPCM_GPMODE_ASIC 0x80000000 154 /* Parity Mode odd/even */ 155 #define CSOR_GPCM_PARITY_EVEN 0x40000000 156 /* Parity Checking enable/disable */ 157 #define CSOR_GPCM_PAR_EN 0x20000000 158 /* GPCM Timeout Count */ 159 #define CSOR_GPCM_GPTO_MASK 0x0F000000 160 #define CSOR_GPCM_GPTO_SHIFT 24 161 #define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) 162 /* GPCM External Access Termination mode for read access */ 163 #define CSOR_GPCM_RGETA_EXT 0x00080000 164 /* GPCM External Access Termination mode for write access */ 165 #define CSOR_GPCM_WGETA_EXT 0x00040000 166 /* Address Data Multiplexing Shift */ 167 #define CSOR_GPCM_ADM_MASK 0x0003E000 168 #define CSOR_GPCM_ADM_SHIFT_SHIFT 13 169 #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) 170 /* Generic ASIC Parity error indication delay */ 171 #define CSOR_GPCM_GAPERRD_MASK 0x00000180 172 #define CSOR_GPCM_GAPERRD_SHIFT 7 173 #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) 174 /* Time for Read Enable High to Output High Impedance */ 175 #define CSOR_GPCM_TRHZ_MASK 0x0000001C 176 #define CSOR_GPCM_TRHZ_20 0x00000000 177 #define CSOR_GPCM_TRHZ_40 0x00000004 178 #define CSOR_GPCM_TRHZ_60 0x00000008 179 #define CSOR_GPCM_TRHZ_80 0x0000000C 180 #define CSOR_GPCM_TRHZ_100 0x00000010 181 /* Buffer control disable */ 182 #define CSOR_GPCM_BCTLD 0x00000001 183 184 /* 185 * Ready Busy Status Register (RB_STAT) 186 */ 187 /* CSn is READY */ 188 #define IFC_RB_STAT_READY_CS0 0x80000000 189 #define IFC_RB_STAT_READY_CS1 0x40000000 190 #define IFC_RB_STAT_READY_CS2 0x20000000 191 #define IFC_RB_STAT_READY_CS3 0x10000000 192 193 /* 194 * General Control Register (GCR) 195 */ 196 #define IFC_GCR_MASK 0x8000F800 197 /* reset all IFC hardware */ 198 #define IFC_GCR_SOFT_RST_ALL 0x80000000 199 /* Turnaroud Time of external buffer */ 200 #define IFC_GCR_TBCTL_TRN_TIME 0x0000F800 201 #define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11 202 203 /* 204 * Common Event and Error Status Register (CM_EVTER_STAT) 205 */ 206 /* Chip select error */ 207 #define IFC_CM_EVTER_STAT_CSER 0x80000000 208 209 /* 210 * Common Event and Error Enable Register (CM_EVTER_EN) 211 */ 212 /* Chip select error checking enable */ 213 #define IFC_CM_EVTER_EN_CSEREN 0x80000000 214 215 /* 216 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN) 217 */ 218 /* Chip select error interrupt enable */ 219 #define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000 220 221 /* 222 * Common Transfer Error Attribute Register-0 (CM_ERATTR0) 223 */ 224 /* transaction type of error Read/Write */ 225 #define IFC_CM_ERATTR0_ERTYP_READ 0x80000000 226 #define IFC_CM_ERATTR0_ERAID 0x0FF00000 227 #define IFC_CM_ERATTR0_ERAID_SHIFT 20 228 #define IFC_CM_ERATTR0_ESRCID 0x0000FF00 229 #define IFC_CM_ERATTR0_ESRCID_SHIFT 8 230 231 /* 232 * Clock Control Register (CCR) 233 */ 234 #define IFC_CCR_MASK 0x0F0F8800 235 /* Clock division ratio */ 236 #define IFC_CCR_CLK_DIV_MASK 0x0F000000 237 #define IFC_CCR_CLK_DIV_SHIFT 24 238 #define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT) 239 /* IFC Clock Delay */ 240 #define IFC_CCR_CLK_DLY_MASK 0x000F0000 241 #define IFC_CCR_CLK_DLY_SHIFT 16 242 #define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT) 243 /* Invert IFC clock before sending out */ 244 #define IFC_CCR_INV_CLK_EN 0x00008000 245 /* Fedback IFC Clock */ 246 #define IFC_CCR_FB_IFC_CLK_SEL 0x00000800 247 248 /* 249 * Clock Status Register (CSR) 250 */ 251 /* Clk is stable */ 252 #define IFC_CSR_CLK_STAT_STABLE 0x80000000 253 254 /* 255 * IFC_NAND Machine Specific Registers 256 */ 257 /* 258 * NAND Configuration Register (NCFGR) 259 */ 260 /* Auto Boot Mode */ 261 #define IFC_NAND_NCFGR_BOOT 0x80000000 262 /* Addressing Mode-ROW0+n/COL0 */ 263 #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 264 /* Addressing Mode-ROW0+n/COL0+n */ 265 #define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000 266 /* Number of loop iterations of FIR sequences for multi page operations */ 267 #define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000 268 #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12 269 #define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT) 270 /* Number of wait cycles */ 271 #define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF 272 #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0 273 274 /* 275 * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) 276 */ 277 /* General purpose FCM flash command bytes CMD0-CMD7 */ 278 #define IFC_NAND_FCR0_CMD0 0xFF000000 279 #define IFC_NAND_FCR0_CMD0_SHIFT 24 280 #define IFC_NAND_FCR0_CMD1 0x00FF0000 281 #define IFC_NAND_FCR0_CMD1_SHIFT 16 282 #define IFC_NAND_FCR0_CMD2 0x0000FF00 283 #define IFC_NAND_FCR0_CMD2_SHIFT 8 284 #define IFC_NAND_FCR0_CMD3 0x000000FF 285 #define IFC_NAND_FCR0_CMD3_SHIFT 0 286 #define IFC_NAND_FCR1_CMD4 0xFF000000 287 #define IFC_NAND_FCR1_CMD4_SHIFT 24 288 #define IFC_NAND_FCR1_CMD5 0x00FF0000 289 #define IFC_NAND_FCR1_CMD5_SHIFT 16 290 #define IFC_NAND_FCR1_CMD6 0x0000FF00 291 #define IFC_NAND_FCR1_CMD6_SHIFT 8 292 #define IFC_NAND_FCR1_CMD7 0x000000FF 293 #define IFC_NAND_FCR1_CMD7_SHIFT 0 294 295 /* 296 * Flash ROW and COL Address Register (ROWn, COLn) 297 */ 298 /* Main/spare region locator */ 299 #define IFC_NAND_COL_MS 0x80000000 300 /* Column Address */ 301 #define IFC_NAND_COL_CA_MASK 0x00000FFF 302 303 /* 304 * NAND Flash Byte Count Register (NAND_BC) 305 */ 306 /* Byte Count for read/Write */ 307 #define IFC_NAND_BC 0x000001FF 308 309 /* 310 * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) 311 */ 312 /* NAND Machine specific opcodes OP0-OP14*/ 313 #define IFC_NAND_FIR0_OP0 0xFC000000 314 #define IFC_NAND_FIR0_OP0_SHIFT 26 315 #define IFC_NAND_FIR0_OP1 0x03F00000 316 #define IFC_NAND_FIR0_OP1_SHIFT 20 317 #define IFC_NAND_FIR0_OP2 0x000FC000 318 #define IFC_NAND_FIR0_OP2_SHIFT 14 319 #define IFC_NAND_FIR0_OP3 0x00003F00 320 #define IFC_NAND_FIR0_OP3_SHIFT 8 321 #define IFC_NAND_FIR0_OP4 0x000000FC 322 #define IFC_NAND_FIR0_OP4_SHIFT 2 323 #define IFC_NAND_FIR1_OP5 0xFC000000 324 #define IFC_NAND_FIR1_OP5_SHIFT 26 325 #define IFC_NAND_FIR1_OP6 0x03F00000 326 #define IFC_NAND_FIR1_OP6_SHIFT 20 327 #define IFC_NAND_FIR1_OP7 0x000FC000 328 #define IFC_NAND_FIR1_OP7_SHIFT 14 329 #define IFC_NAND_FIR1_OP8 0x00003F00 330 #define IFC_NAND_FIR1_OP8_SHIFT 8 331 #define IFC_NAND_FIR1_OP9 0x000000FC 332 #define IFC_NAND_FIR1_OP9_SHIFT 2 333 #define IFC_NAND_FIR2_OP10 0xFC000000 334 #define IFC_NAND_FIR2_OP10_SHIFT 26 335 #define IFC_NAND_FIR2_OP11 0x03F00000 336 #define IFC_NAND_FIR2_OP11_SHIFT 20 337 #define IFC_NAND_FIR2_OP12 0x000FC000 338 #define IFC_NAND_FIR2_OP12_SHIFT 14 339 #define IFC_NAND_FIR2_OP13 0x00003F00 340 #define IFC_NAND_FIR2_OP13_SHIFT 8 341 #define IFC_NAND_FIR2_OP14 0x000000FC 342 #define IFC_NAND_FIR2_OP14_SHIFT 2 343 344 /* 345 * Instruction opcodes to be programmed 346 * in FIR registers- 6bits 347 */ 348 enum ifc_nand_fir_opcodes { 349 IFC_FIR_OP_NOP, 350 IFC_FIR_OP_CA0, 351 IFC_FIR_OP_CA1, 352 IFC_FIR_OP_CA2, 353 IFC_FIR_OP_CA3, 354 IFC_FIR_OP_RA0, 355 IFC_FIR_OP_RA1, 356 IFC_FIR_OP_RA2, 357 IFC_FIR_OP_RA3, 358 IFC_FIR_OP_CMD0, 359 IFC_FIR_OP_CMD1, 360 IFC_FIR_OP_CMD2, 361 IFC_FIR_OP_CMD3, 362 IFC_FIR_OP_CMD4, 363 IFC_FIR_OP_CMD5, 364 IFC_FIR_OP_CMD6, 365 IFC_FIR_OP_CMD7, 366 IFC_FIR_OP_CW0, 367 IFC_FIR_OP_CW1, 368 IFC_FIR_OP_CW2, 369 IFC_FIR_OP_CW3, 370 IFC_FIR_OP_CW4, 371 IFC_FIR_OP_CW5, 372 IFC_FIR_OP_CW6, 373 IFC_FIR_OP_CW7, 374 IFC_FIR_OP_WBCD, 375 IFC_FIR_OP_RBCD, 376 IFC_FIR_OP_BTRD, 377 IFC_FIR_OP_RDSTAT, 378 IFC_FIR_OP_NWAIT, 379 IFC_FIR_OP_WFR, 380 IFC_FIR_OP_SBRD, 381 IFC_FIR_OP_UA, 382 IFC_FIR_OP_RB, 383 }; 384 385 /* 386 * NAND Chip Select Register (NAND_CSEL) 387 */ 388 #define IFC_NAND_CSEL 0x0C000000 389 #define IFC_NAND_CSEL_SHIFT 26 390 #define IFC_NAND_CSEL_CS0 0x00000000 391 #define IFC_NAND_CSEL_CS1 0x04000000 392 #define IFC_NAND_CSEL_CS2 0x08000000 393 #define IFC_NAND_CSEL_CS3 0x0C000000 394 395 /* 396 * NAND Operation Sequence Start (NANDSEQ_STRT) 397 */ 398 /* NAND Flash Operation Start */ 399 #define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000 400 /* Automatic Erase */ 401 #define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000 402 /* Automatic Program */ 403 #define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000 404 /* Automatic Copyback */ 405 #define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000 406 /* Automatic Read Operation */ 407 #define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000 408 /* Automatic Status Read */ 409 #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800 410 411 /* 412 * NAND Event and Error Status Register (NAND_EVTER_STAT) 413 */ 414 /* Operation Complete */ 415 #define IFC_NAND_EVTER_STAT_OPC 0x80000000 416 /* Flash Timeout Error */ 417 #define IFC_NAND_EVTER_STAT_FTOER 0x08000000 418 /* Write Protect Error */ 419 #define IFC_NAND_EVTER_STAT_WPER 0x04000000 420 /* ECC Error */ 421 #define IFC_NAND_EVTER_STAT_ECCER 0x02000000 422 /* RCW Load Done */ 423 #define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000 424 /* Boot Loadr Done */ 425 #define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000 426 /* Bad Block Indicator search select */ 427 #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800 428 429 /* 430 * NAND Flash Page Read Completion Event Status Register 431 * (PGRDCMPL_EVT_STAT) 432 */ 433 #define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000 434 /* Small Page 0-15 Done */ 435 #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n))) 436 /* Large Page(2K) 0-3 Done */ 437 #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4)) 438 /* Large Page(4K) 0-1 Done */ 439 #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8)) 440 441 /* 442 * NAND Event and Error Enable Register (NAND_EVTER_EN) 443 */ 444 /* Operation complete event enable */ 445 #define IFC_NAND_EVTER_EN_OPC_EN 0x80000000 446 /* Page read complete event enable */ 447 #define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 448 /* Flash Timeout error enable */ 449 #define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 450 /* Write Protect error enable */ 451 #define IFC_NAND_EVTER_EN_WPER_EN 0x04000000 452 /* ECC error logging enable */ 453 #define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000 454 455 /* 456 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN) 457 */ 458 /* Enable interrupt for operation complete */ 459 #define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000 460 /* Enable interrupt for Page read complete */ 461 #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000 462 /* Enable interrupt for Flash timeout error */ 463 #define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000 464 /* Enable interrupt for Write protect error */ 465 #define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000 466 /* Enable interrupt for ECC error*/ 467 #define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000 468 469 /* 470 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0) 471 */ 472 #define IFC_NAND_ERATTR0_MASK 0x0C080000 473 /* Error on CS0-3 for NAND */ 474 #define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000 475 #define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000 476 #define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000 477 #define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000 478 /* Transaction type of error Read/Write */ 479 #define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000 480 481 /* 482 * NAND Flash Status Register (NAND_FSR) 483 */ 484 /* First byte of data read from read status op */ 485 #define IFC_NAND_NFSR_RS0 0xFF000000 486 /* Second byte of data read from read status op */ 487 #define IFC_NAND_NFSR_RS1 0x00FF0000 488 489 /* 490 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3) 491 */ 492 /* Number of ECC errors on sector n (n = 0-15) */ 493 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000 494 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24 495 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000 496 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16 497 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00 498 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8 499 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F 500 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0 501 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000 502 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24 503 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000 504 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16 505 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00 506 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8 507 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F 508 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0 509 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000 510 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24 511 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000 512 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16 513 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00 514 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8 515 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F 516 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0 517 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000 518 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24 519 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000 520 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16 521 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00 522 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8 523 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F 524 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0 525 526 /* 527 * NAND Control Register (NANDCR) 528 */ 529 #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 530 #define IFC_NAND_NCR_FTOCNT_SHIFT 25 531 #define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) 532 533 /* 534 * NAND_AUTOBOOT_TRGR 535 */ 536 /* Trigger RCW load */ 537 #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000 538 /* Trigget Auto Boot */ 539 #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000 540 541 /* 542 * NAND_MDR 543 */ 544 /* 1st read data byte when opcode SBRD */ 545 #define IFC_NAND_MDR_RDATA0 0xFF000000 546 /* 2nd read data byte when opcode SBRD */ 547 #define IFC_NAND_MDR_RDATA1 0x00FF0000 548 549 /* 550 * NOR Machine Specific Registers 551 */ 552 /* 553 * NOR Event and Error Status Register (NOR_EVTER_STAT) 554 */ 555 /* NOR Command Sequence Operation Complete */ 556 #define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000 557 /* Write Protect Error */ 558 #define IFC_NOR_EVTER_STAT_WPER 0x04000000 559 /* Command Sequence Timeout Error */ 560 #define IFC_NOR_EVTER_STAT_STOER 0x01000000 561 562 /* 563 * NOR Event and Error Enable Register (NOR_EVTER_EN) 564 */ 565 /* NOR Command Seq complete event enable */ 566 #define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000 567 /* Write Protect Error Checking Enable */ 568 #define IFC_NOR_EVTER_EN_WPEREN 0x04000000 569 /* Timeout Error Enable */ 570 #define IFC_NOR_EVTER_EN_STOEREN 0x01000000 571 572 /* 573 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN) 574 */ 575 /* Enable interrupt for OPC complete */ 576 #define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000 577 /* Enable interrupt for write protect error */ 578 #define IFC_NOR_EVTER_INTR_WPEREN 0x04000000 579 /* Enable interrupt for timeout error */ 580 #define IFC_NOR_EVTER_INTR_STOEREN 0x01000000 581 582 /* 583 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0) 584 */ 585 /* Source ID for error transaction */ 586 #define IFC_NOR_ERATTR0_ERSRCID 0xFF000000 587 /* AXI ID for error transation */ 588 #define IFC_NOR_ERATTR0_ERAID 0x000FF000 589 /* Chip select corresponds to NOR error */ 590 #define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000 591 #define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010 592 #define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020 593 #define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030 594 /* Type of transaction read/write */ 595 #define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001 596 597 /* 598 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2) 599 */ 600 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000 601 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00 602 603 /* 604 * NOR Control Register (NORCR) 605 */ 606 #define IFC_NORCR_MASK 0x0F0F0000 607 /* No. of Address/Data Phase */ 608 #define IFC_NORCR_NUM_PHASE_MASK 0x0F000000 609 #define IFC_NORCR_NUM_PHASE_SHIFT 24 610 #define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT) 611 /* Sequence Timeout Count */ 612 #define IFC_NORCR_STOCNT_MASK 0x000F0000 613 #define IFC_NORCR_STOCNT_SHIFT 16 614 #define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) 615 616 /* 617 * GPCM Machine specific registers 618 */ 619 /* 620 * GPCM Event and Error Status Register (GPCM_EVTER_STAT) 621 */ 622 /* Timeout error */ 623 #define IFC_GPCM_EVTER_STAT_TOER 0x04000000 624 /* Parity error */ 625 #define IFC_GPCM_EVTER_STAT_PER 0x01000000 626 627 /* 628 * GPCM Event and Error Enable Register (GPCM_EVTER_EN) 629 */ 630 /* Timeout error enable */ 631 #define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000 632 /* Parity error enable */ 633 #define IFC_GPCM_EVTER_EN_PER_EN 0x01000000 634 635 /* 636 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN) 637 */ 638 /* Enable Interrupt for timeout error */ 639 #define IFC_GPCM_EEIER_TOERIR_EN 0x04000000 640 /* Enable Interrupt for Parity error */ 641 #define IFC_GPCM_EEIER_PERIR_EN 0x01000000 642 643 /* 644 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0) 645 */ 646 /* Source ID for error transaction */ 647 #define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000 648 /* AXI ID for error transaction */ 649 #define IFC_GPCM_ERATTR0_ERAID 0x000FF000 650 /* Chip select corresponds to GPCM error */ 651 #define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000 652 #define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040 653 #define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080 654 #define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0 655 /* Type of transaction read/Write */ 656 #define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001 657 658 /* 659 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2) 660 */ 661 /* On which beat of address/data parity error is observed */ 662 #define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00 663 /* Parity Error on byte */ 664 #define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0 665 /* Parity Error reported in addr or data phase */ 666 #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001 667 668 /* 669 * GPCM Status Register (GPCM_STAT) 670 */ 671 #define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */ 672 673 /* 674 * IFC Controller NAND Machine registers 675 */ 676 struct fsl_ifc_nand { 677 __be32 ncfgr; 678 u32 res1[0x4]; 679 __be32 nand_fcr0; 680 __be32 nand_fcr1; 681 u32 res2[0x8]; 682 __be32 row0; 683 u32 res3; 684 __be32 col0; 685 u32 res4; 686 __be32 row1; 687 u32 res5; 688 __be32 col1; 689 u32 res6; 690 __be32 row2; 691 u32 res7; 692 __be32 col2; 693 u32 res8; 694 __be32 row3; 695 u32 res9; 696 __be32 col3; 697 u32 res10[0x24]; 698 __be32 nand_fbcr; 699 u32 res11; 700 __be32 nand_fir0; 701 __be32 nand_fir1; 702 __be32 nand_fir2; 703 u32 res12[0x10]; 704 __be32 nand_csel; 705 u32 res13; 706 __be32 nandseq_strt; 707 u32 res14; 708 __be32 nand_evter_stat; 709 u32 res15; 710 __be32 pgrdcmpl_evt_stat; 711 u32 res16[0x2]; 712 __be32 nand_evter_en; 713 u32 res17[0x2]; 714 __be32 nand_evter_intr_en; 715 u32 res18[0x2]; 716 __be32 nand_erattr0; 717 __be32 nand_erattr1; 718 u32 res19[0x10]; 719 __be32 nand_fsr; 720 u32 res20; 721 __be32 nand_eccstat[4]; 722 u32 res21[0x20]; 723 __be32 nanndcr; 724 u32 res22[0x2]; 725 __be32 nand_autoboot_trgr; 726 u32 res23; 727 __be32 nand_mdr; 728 u32 res24[0x5C]; 729 }; 730 731 /* 732 * IFC controller NOR Machine registers 733 */ 734 struct fsl_ifc_nor { 735 __be32 nor_evter_stat; 736 u32 res1[0x2]; 737 __be32 nor_evter_en; 738 u32 res2[0x2]; 739 __be32 nor_evter_intr_en; 740 u32 res3[0x2]; 741 __be32 nor_erattr0; 742 __be32 nor_erattr1; 743 __be32 nor_erattr2; 744 u32 res4[0x4]; 745 __be32 norcr; 746 u32 res5[0xEF]; 747 }; 748 749 /* 750 * IFC controller GPCM Machine registers 751 */ 752 struct fsl_ifc_gpcm { 753 __be32 gpcm_evter_stat; 754 u32 res1[0x2]; 755 __be32 gpcm_evter_en; 756 u32 res2[0x2]; 757 __be32 gpcm_evter_intr_en; 758 u32 res3[0x2]; 759 __be32 gpcm_erattr0; 760 __be32 gpcm_erattr1; 761 __be32 gpcm_erattr2; 762 __be32 gpcm_stat; 763 u32 res4[0x1F3]; 764 }; 765 766 /* 767 * IFC Controller Registers 768 */ 769 struct fsl_ifc_regs { 770 __be32 ifc_rev; 771 u32 res1[0x3]; 772 struct { 773 __be32 cspr; 774 u32 res2[0x2]; 775 } cspr_cs[FSL_IFC_BANK_COUNT]; 776 u32 res3[0x18]; 777 struct { 778 __be32 amask; 779 u32 res4[0x2]; 780 } amask_cs[FSL_IFC_BANK_COUNT]; 781 u32 res5[0x18]; 782 struct { 783 __be32 csor; 784 u32 res6[0x2]; 785 } csor_cs[FSL_IFC_BANK_COUNT]; 786 u32 res7[0x18]; 787 struct { 788 __be32 ftim[4]; 789 u32 res8[0x8]; 790 } ftim_cs[FSL_IFC_BANK_COUNT]; 791 u32 res9[0x60]; 792 __be32 rb_stat; 793 u32 res10[0x2]; 794 __be32 ifc_gcr; 795 u32 res11[0x2]; 796 __be32 cm_evter_stat; 797 u32 res12[0x2]; 798 __be32 cm_evter_en; 799 u32 res13[0x2]; 800 __be32 cm_evter_intr_en; 801 u32 res14[0x2]; 802 __be32 cm_erattr0; 803 __be32 cm_erattr1; 804 u32 res15[0x2]; 805 __be32 ifc_ccr; 806 __be32 ifc_csr; 807 u32 res16[0x2EB]; 808 struct fsl_ifc_nand ifc_nand; 809 struct fsl_ifc_nor ifc_nor; 810 struct fsl_ifc_gpcm ifc_gpcm; 811 }; 812 813 extern unsigned int convert_ifc_address(phys_addr_t addr_base); 814 extern int fsl_ifc_find(phys_addr_t addr_base); 815 816 /* overview of the fsl ifc controller */ 817 818 struct fsl_ifc_ctrl { 819 /* device info */ 820 struct device *dev; 821 struct fsl_ifc_regs __iomem *regs; 822 int irq; 823 int nand_irq; 824 spinlock_t lock; 825 void *nand; 826 827 u32 nand_stat; 828 wait_queue_head_t nand_wait; 829 }; 830 831 extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev; 832 833 834 #endif /* __ASM_FSL_IFC_H */ 835