1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2018 MediaTek Inc.
4 *
5 * Author: Sean Wang <sean.wang@mediatek.com>
6 *
7 */
8
9 #include <dt-bindings/pinctrl/mt65xx.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/platform_device.h>
14 #include <linux/io.h>
15 #include <linux/module.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18
19 #include "mtk-eint.h"
20 #include "pinctrl-mtk-common-v2.h"
21
22 /**
23 * struct mtk_drive_desc - the structure that holds the information
24 * of the driving current
25 * @min: the minimum current of this group
26 * @max: the maximum current of this group
27 * @step: the step current of this group
28 * @scal: the weight factor
29 *
30 * formula: output = ((input) / step - 1) * scal
31 */
32 struct mtk_drive_desc {
33 u8 min;
34 u8 max;
35 u8 step;
36 u8 scal;
37 };
38
39 /* The groups of drive strength */
40 static const struct mtk_drive_desc mtk_drive[] = {
41 [DRV_GRP0] = { 4, 16, 4, 1 },
42 [DRV_GRP1] = { 4, 16, 4, 2 },
43 [DRV_GRP2] = { 2, 8, 2, 1 },
44 [DRV_GRP3] = { 2, 8, 2, 2 },
45 [DRV_GRP4] = { 2, 16, 2, 1 },
46 };
47
mtk_w32(struct mtk_pinctrl * pctl,u8 i,u32 reg,u32 val)48 static void mtk_w32(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 val)
49 {
50 writel_relaxed(val, pctl->base[i] + reg);
51 }
52
mtk_r32(struct mtk_pinctrl * pctl,u8 i,u32 reg)53 static u32 mtk_r32(struct mtk_pinctrl *pctl, u8 i, u32 reg)
54 {
55 return readl_relaxed(pctl->base[i] + reg);
56 }
57
mtk_rmw(struct mtk_pinctrl * pctl,u8 i,u32 reg,u32 mask,u32 set)58 void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set)
59 {
60 u32 val;
61 unsigned long flags;
62
63 spin_lock_irqsave(&pctl->lock, flags);
64
65 val = mtk_r32(pctl, i, reg);
66 val &= ~mask;
67 val |= set;
68 mtk_w32(pctl, i, reg, val);
69
70 spin_unlock_irqrestore(&pctl->lock, flags);
71 }
72
mtk_hw_pin_field_lookup(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,int field,struct mtk_pin_field * pfd)73 static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw,
74 const struct mtk_pin_desc *desc,
75 int field, struct mtk_pin_field *pfd)
76 {
77 const struct mtk_pin_field_calc *c;
78 const struct mtk_pin_reg_calc *rc;
79 int start = 0, end, check;
80 bool found = false;
81 u32 bits;
82
83 if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) {
84 rc = &hw->soc->reg_cal[field];
85 } else {
86 dev_dbg(hw->dev,
87 "Not support field %d for this soc\n", field);
88 return -ENOTSUPP;
89 }
90
91 end = rc->nranges - 1;
92
93 while (start <= end) {
94 check = (start + end) >> 1;
95 if (desc->number >= rc->range[check].s_pin
96 && desc->number <= rc->range[check].e_pin) {
97 found = true;
98 break;
99 } else if (start == end)
100 break;
101 else if (desc->number < rc->range[check].s_pin)
102 end = check - 1;
103 else
104 start = check + 1;
105 }
106
107 if (!found) {
108 dev_dbg(hw->dev, "Not support field %d for pin = %d (%s)\n",
109 field, desc->number, desc->name);
110 return -ENOTSUPP;
111 }
112
113 c = rc->range + check;
114
115 if (c->i_base > hw->nbase - 1) {
116 dev_err(hw->dev,
117 "Invalid base for field %d for pin = %d (%s)\n",
118 field, desc->number, desc->name);
119 return -EINVAL;
120 }
121
122 /* Calculated bits as the overall offset the pin is located at,
123 * if c->fixed is held, that determines the all the pins in the
124 * range use the same field with the s_pin.
125 */
126 bits = c->fixed ? c->s_bit : c->s_bit +
127 (desc->number - c->s_pin) * (c->x_bits);
128
129 /* Fill pfd from bits. For example 32-bit register applied is assumed
130 * when c->sz_reg is equal to 32.
131 */
132 pfd->index = c->i_base;
133 pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg);
134 pfd->bitpos = bits % c->sz_reg;
135 pfd->mask = (1 << c->x_bits) - 1;
136
137 /* pfd->next is used for indicating that bit wrapping-around happens
138 * which requires the manipulation for bit 0 starting in the next
139 * register to form the complete field read/write.
140 */
141 pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0;
142
143 return 0;
144 }
145
mtk_hw_pin_field_get(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,int field,struct mtk_pin_field * pfd)146 static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw,
147 const struct mtk_pin_desc *desc,
148 int field, struct mtk_pin_field *pfd)
149 {
150 if (field < 0 || field >= PINCTRL_PIN_REG_MAX) {
151 dev_err(hw->dev, "Invalid Field %d\n", field);
152 return -EINVAL;
153 }
154
155 return mtk_hw_pin_field_lookup(hw, desc, field, pfd);
156 }
157
mtk_hw_bits_part(struct mtk_pin_field * pf,int * h,int * l)158 static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
159 {
160 *l = 32 - pf->bitpos;
161 *h = get_count_order(pf->mask) - *l;
162 }
163
mtk_hw_write_cross_field(struct mtk_pinctrl * hw,struct mtk_pin_field * pf,int value)164 static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw,
165 struct mtk_pin_field *pf, int value)
166 {
167 int nbits_l, nbits_h;
168
169 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
170
171 mtk_rmw(hw, pf->index, pf->offset, pf->mask << pf->bitpos,
172 (value & pf->mask) << pf->bitpos);
173
174 mtk_rmw(hw, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1,
175 (value & pf->mask) >> nbits_l);
176 }
177
mtk_hw_read_cross_field(struct mtk_pinctrl * hw,struct mtk_pin_field * pf,int * value)178 static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw,
179 struct mtk_pin_field *pf, int *value)
180 {
181 int nbits_l, nbits_h, h, l;
182
183 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
184
185 l = (mtk_r32(hw, pf->index, pf->offset)
186 >> pf->bitpos) & (BIT(nbits_l) - 1);
187 h = (mtk_r32(hw, pf->index, pf->offset + pf->next))
188 & (BIT(nbits_h) - 1);
189
190 *value = (h << nbits_l) | l;
191 }
192
mtk_hw_set_value(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,int field,int value)193 int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
194 int field, int value)
195 {
196 struct mtk_pin_field pf;
197 int err;
198
199 err = mtk_hw_pin_field_get(hw, desc, field, &pf);
200 if (err)
201 return err;
202
203 if (value < 0 || value > pf.mask)
204 return -EINVAL;
205
206 if (!pf.next)
207 mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos,
208 (value & pf.mask) << pf.bitpos);
209 else
210 mtk_hw_write_cross_field(hw, &pf, value);
211
212 return 0;
213 }
214 EXPORT_SYMBOL_GPL(mtk_hw_set_value);
215
mtk_hw_get_value(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,int field,int * value)216 int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
217 int field, int *value)
218 {
219 struct mtk_pin_field pf;
220 int err;
221
222 err = mtk_hw_pin_field_get(hw, desc, field, &pf);
223 if (err)
224 return err;
225
226 if (!pf.next)
227 *value = (mtk_r32(hw, pf.index, pf.offset)
228 >> pf.bitpos) & pf.mask;
229 else
230 mtk_hw_read_cross_field(hw, &pf, value);
231
232 return 0;
233 }
234 EXPORT_SYMBOL_GPL(mtk_hw_get_value);
235
mtk_xt_find_eint_num(struct mtk_pinctrl * hw,unsigned long eint_n)236 static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n)
237 {
238 const struct mtk_pin_desc *desc;
239 int i = 0;
240
241 desc = (const struct mtk_pin_desc *)hw->soc->pins;
242
243 while (i < hw->soc->npins) {
244 if (desc[i].eint.eint_n == eint_n)
245 return desc[i].number;
246 i++;
247 }
248
249 return EINT_NA;
250 }
251
252 /*
253 * Virtual GPIO only used inside SOC and not being exported to outside SOC.
254 * Some modules use virtual GPIO as eint (e.g. pmif or usb).
255 * In MTK platform, external interrupt (EINT) and GPIO is 1-1 mapping
256 * and we can set GPIO as eint.
257 * But some modules use specific eint which doesn't have real GPIO pin.
258 * So we use virtual GPIO to map it.
259 */
260
mtk_is_virt_gpio(struct mtk_pinctrl * hw,unsigned int gpio_n)261 bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n)
262 {
263 const struct mtk_pin_desc *desc;
264 bool virt_gpio = false;
265
266 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
267
268 /* if the GPIO is not supported for eint mode */
269 if (desc->eint.eint_m == NO_EINT_SUPPORT)
270 return virt_gpio;
271
272 if (desc->funcs && !desc->funcs[desc->eint.eint_m].name)
273 virt_gpio = true;
274
275 return virt_gpio;
276 }
277 EXPORT_SYMBOL_GPL(mtk_is_virt_gpio);
278
mtk_xt_get_gpio_n(void * data,unsigned long eint_n,unsigned int * gpio_n,struct gpio_chip ** gpio_chip)279 static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
280 unsigned int *gpio_n,
281 struct gpio_chip **gpio_chip)
282 {
283 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
284 const struct mtk_pin_desc *desc;
285
286 desc = (const struct mtk_pin_desc *)hw->soc->pins;
287 *gpio_chip = &hw->chip;
288
289 /*
290 * Be greedy to guess first gpio_n is equal to eint_n.
291 * Only eint virtual eint number is greater than gpio number.
292 */
293 if (hw->soc->npins > eint_n &&
294 desc[eint_n].eint.eint_n == eint_n)
295 *gpio_n = eint_n;
296 else
297 *gpio_n = mtk_xt_find_eint_num(hw, eint_n);
298
299 return *gpio_n == EINT_NA ? -EINVAL : 0;
300 }
301
mtk_xt_get_gpio_state(void * data,unsigned long eint_n)302 static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
303 {
304 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
305 const struct mtk_pin_desc *desc;
306 struct gpio_chip *gpio_chip;
307 unsigned int gpio_n;
308 int value, err;
309
310 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
311 if (err)
312 return err;
313
314 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
315
316 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
317 if (err)
318 return err;
319
320 return !!value;
321 }
322
mtk_xt_set_gpio_as_eint(void * data,unsigned long eint_n)323 static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
324 {
325 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
326 const struct mtk_pin_desc *desc;
327 struct gpio_chip *gpio_chip;
328 unsigned int gpio_n;
329 int err;
330
331 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
332 if (err)
333 return err;
334
335 if (mtk_is_virt_gpio(hw, gpio_n))
336 return 0;
337
338 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
339
340 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
341 desc->eint.eint_m);
342 if (err)
343 return err;
344
345 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT);
346 if (err)
347 return err;
348
349 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, MTK_ENABLE);
350 /* SMT is supposed to be supported by every real GPIO and doesn't
351 * support virtual GPIOs, so the extra condition err != -ENOTSUPP
352 * is just for adding EINT support to these virtual GPIOs. It should
353 * add an extra flag in the pin descriptor when more pins with
354 * distinctive characteristic come out.
355 */
356 if (err && err != -ENOTSUPP)
357 return err;
358
359 return 0;
360 }
361
362 static const struct mtk_eint_xt mtk_eint_xt = {
363 .get_gpio_n = mtk_xt_get_gpio_n,
364 .get_gpio_state = mtk_xt_get_gpio_state,
365 .set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
366 };
367
mtk_build_eint(struct mtk_pinctrl * hw,struct platform_device * pdev)368 int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
369 {
370 struct device_node *np = pdev->dev.of_node;
371 int ret, i, j, count_reg_names;
372
373 if (!IS_ENABLED(CONFIG_EINT_MTK))
374 return 0;
375
376 if (!of_property_read_bool(np, "interrupt-controller"))
377 return -ENODEV;
378
379 hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL);
380 if (!hw->eint)
381 return -ENOMEM;
382
383 count_reg_names = of_property_count_strings(np, "reg-names");
384 if (count_reg_names < hw->soc->nbase_names)
385 return -EINVAL;
386
387 hw->eint->nbase = count_reg_names - hw->soc->nbase_names;
388 hw->eint->base = devm_kmalloc_array(&pdev->dev, hw->eint->nbase,
389 sizeof(*hw->eint->base), GFP_KERNEL | __GFP_ZERO);
390 if (!hw->eint->base) {
391 ret = -ENOMEM;
392 goto err_free_base;
393 }
394
395 for (i = hw->soc->nbase_names, j = 0; i < count_reg_names; i++, j++) {
396 hw->eint->base[j] = of_iomap(np, i);
397 if (IS_ERR(hw->eint->base[j])) {
398 ret = PTR_ERR(hw->eint->base[j]);
399 goto err_free_eint;
400 }
401 }
402
403 hw->eint->irq = irq_of_parse_and_map(np, 0);
404 if (!hw->eint->irq) {
405 ret = -EINVAL;
406 goto err_free_eint;
407 }
408
409 if (!hw->soc->eint_hw) {
410 ret = -ENODEV;
411 goto err_free_eint;
412 }
413
414 hw->eint->dev = &pdev->dev;
415 hw->eint->hw = hw->soc->eint_hw;
416 hw->eint->pctl = hw;
417 hw->eint->gpio_xlate = &mtk_eint_xt;
418
419 ret = mtk_eint_do_init(hw->eint);
420 if (ret)
421 goto err_free_eint;
422
423 return 0;
424
425 err_free_eint:
426 for (j = 0; j < hw->eint->nbase; j++) {
427 if (hw->eint->base[j])
428 iounmap(hw->eint->base[j]);
429 }
430 devm_kfree(hw->dev, hw->eint->base);
431 err_free_base:
432 devm_kfree(hw->dev, hw->eint);
433 hw->eint = NULL;
434 return ret;
435 }
436 EXPORT_SYMBOL_GPL(mtk_build_eint);
437
438 /* Revision 0 */
mtk_pinconf_bias_disable_set(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc)439 int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw,
440 const struct mtk_pin_desc *desc)
441 {
442 int err;
443
444 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU,
445 MTK_DISABLE);
446 if (err)
447 return err;
448
449 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
450 MTK_DISABLE);
451 if (err)
452 return err;
453
454 return 0;
455 }
456 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set);
457
mtk_pinconf_bias_disable_get(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,int * res)458 int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw,
459 const struct mtk_pin_desc *desc, int *res)
460 {
461 int v, v2;
462 int err;
463
464 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &v);
465 if (err)
466 return err;
467
468 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &v2);
469 if (err)
470 return err;
471
472 if (v == MTK_ENABLE || v2 == MTK_ENABLE)
473 return -EINVAL;
474
475 *res = 1;
476
477 return 0;
478 }
479 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get);
480
mtk_pinconf_bias_set(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,bool pullup)481 int mtk_pinconf_bias_set(struct mtk_pinctrl *hw,
482 const struct mtk_pin_desc *desc, bool pullup)
483 {
484 int err, arg;
485
486 arg = pullup ? 1 : 2;
487
488 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, arg & 1);
489 if (err)
490 return err;
491
492 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
493 !!(arg & 2));
494 if (err)
495 return err;
496
497 return 0;
498 }
499 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set);
500
mtk_pinconf_bias_get(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,bool pullup,int * res)501 int mtk_pinconf_bias_get(struct mtk_pinctrl *hw,
502 const struct mtk_pin_desc *desc, bool pullup, int *res)
503 {
504 int reg, err, v;
505
506 reg = pullup ? PINCTRL_PIN_REG_PU : PINCTRL_PIN_REG_PD;
507
508 err = mtk_hw_get_value(hw, desc, reg, &v);
509 if (err)
510 return err;
511
512 if (!v)
513 return -EINVAL;
514
515 *res = 1;
516
517 return 0;
518 }
519 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get);
520
521 /* Revision 1 */
mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc)522 int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw,
523 const struct mtk_pin_desc *desc)
524 {
525 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
526 MTK_DISABLE);
527 }
528 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set_rev1);
529
mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,int * res)530 int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw,
531 const struct mtk_pin_desc *desc, int *res)
532 {
533 int v, err;
534
535 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
536 if (err)
537 return err;
538
539 if (v == MTK_ENABLE)
540 return -EINVAL;
541
542 *res = 1;
543
544 return 0;
545 }
546 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get_rev1);
547
mtk_pinconf_bias_set_rev1(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,bool pullup)548 int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw,
549 const struct mtk_pin_desc *desc, bool pullup)
550 {
551 int err, arg;
552
553 arg = pullup ? MTK_PULLUP : MTK_PULLDOWN;
554
555 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
556 MTK_ENABLE);
557 if (err)
558 return err;
559
560 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, arg);
561 if (err)
562 return err;
563
564 return 0;
565 }
566 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_rev1);
567
mtk_pinconf_bias_get_rev1(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,bool pullup,int * res)568 int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw,
569 const struct mtk_pin_desc *desc, bool pullup,
570 int *res)
571 {
572 int err, v;
573
574 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
575 if (err)
576 return err;
577
578 if (v == MTK_DISABLE)
579 return -EINVAL;
580
581 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, &v);
582 if (err)
583 return err;
584
585 if (pullup ^ (v == MTK_PULLUP))
586 return -EINVAL;
587
588 *res = 1;
589
590 return 0;
591 }
592 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_rev1);
593
594 /* Combo for the following pull register type:
595 * 1. PU + PD
596 * 2. PULLSEL + PULLEN
597 * 3. PUPD + R0 + R1
598 */
mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,u32 pullup,u32 arg,bool pd_only)599 static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw,
600 const struct mtk_pin_desc *desc,
601 u32 pullup, u32 arg, bool pd_only)
602 {
603 int err, pu, pd;
604
605 if (arg == MTK_DISABLE) {
606 pu = 0;
607 pd = 0;
608 } else if ((arg == MTK_ENABLE) && pullup) {
609 pu = 1;
610 pd = 0;
611 } else if ((arg == MTK_ENABLE) && !pullup) {
612 pu = 0;
613 pd = 1;
614 } else {
615 return -EINVAL;
616 }
617
618 if (!pd_only) {
619 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu);
620 if (err)
621 return err;
622 }
623
624 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
625 }
626
mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,u32 pullup,u32 arg)627 static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
628 const struct mtk_pin_desc *desc,
629 u32 pullup, u32 arg)
630 {
631 int err, enable;
632
633 if (arg == MTK_DISABLE)
634 enable = 0;
635 else if (arg == MTK_ENABLE)
636 enable = 1;
637 else {
638 err = -EINVAL;
639 goto out;
640 }
641
642 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable);
643 if (err)
644 goto out;
645
646 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup);
647
648 out:
649 return err;
650 }
651
mtk_pinconf_bias_set_pupd_r1_r0(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,u32 pullup,u32 arg)652 static int mtk_pinconf_bias_set_pupd_r1_r0(struct mtk_pinctrl *hw,
653 const struct mtk_pin_desc *desc,
654 u32 pullup, u32 arg)
655 {
656 int err, r0, r1;
657
658 if ((arg == MTK_DISABLE) || (arg == MTK_PUPD_SET_R1R0_00)) {
659 pullup = 0;
660 r0 = 0;
661 r1 = 0;
662 } else if (arg == MTK_PUPD_SET_R1R0_01) {
663 r0 = 1;
664 r1 = 0;
665 } else if (arg == MTK_PUPD_SET_R1R0_10) {
666 r0 = 0;
667 r1 = 1;
668 } else if (arg == MTK_PUPD_SET_R1R0_11) {
669 r0 = 1;
670 r1 = 1;
671 } else {
672 err = -EINVAL;
673 goto out;
674 }
675
676 /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
677 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, !pullup);
678 if (err)
679 goto out;
680
681 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, r0);
682 if (err)
683 goto out;
684
685 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1, r1);
686
687 out:
688 return err;
689 }
690
mtk_hw_pin_rsel_lookup(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,u32 pullup,u32 arg,u32 * rsel_val)691 static int mtk_hw_pin_rsel_lookup(struct mtk_pinctrl *hw,
692 const struct mtk_pin_desc *desc,
693 u32 pullup, u32 arg, u32 *rsel_val)
694 {
695 const struct mtk_pin_rsel *rsel;
696 int check;
697 bool found = false;
698
699 rsel = hw->soc->pin_rsel;
700
701 for (check = 0; check <= hw->soc->npin_rsel - 1; check++) {
702 if (desc->number >= rsel[check].s_pin &&
703 desc->number <= rsel[check].e_pin) {
704 if (pullup) {
705 if (rsel[check].up_rsel == arg) {
706 found = true;
707 *rsel_val = rsel[check].rsel_index;
708 break;
709 }
710 } else {
711 if (rsel[check].down_rsel == arg) {
712 found = true;
713 *rsel_val = rsel[check].rsel_index;
714 break;
715 }
716 }
717 }
718 }
719
720 if (!found) {
721 dev_err(hw->dev, "Not support rsel value %d Ohm for pin = %d (%s)\n",
722 arg, desc->number, desc->name);
723 return -ENOTSUPP;
724 }
725
726 return 0;
727 }
728
mtk_pinconf_bias_set_rsel(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,u32 pullup,u32 arg)729 static int mtk_pinconf_bias_set_rsel(struct mtk_pinctrl *hw,
730 const struct mtk_pin_desc *desc,
731 u32 pullup, u32 arg)
732 {
733 int err, rsel_val;
734
735 if (hw->rsel_si_unit) {
736 /* find pin rsel_index from pin_rsel array*/
737 err = mtk_hw_pin_rsel_lookup(hw, desc, pullup, arg, &rsel_val);
738 if (err)
739 return err;
740 } else {
741 if (arg < MTK_PULL_SET_RSEL_000 || arg > MTK_PULL_SET_RSEL_111)
742 return -EINVAL;
743
744 rsel_val = arg - MTK_PULL_SET_RSEL_000;
745 }
746
747 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_RSEL, rsel_val);
748 }
749
mtk_pinconf_bias_set_pu_pd_rsel(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,u32 pullup,u32 arg)750 static int mtk_pinconf_bias_set_pu_pd_rsel(struct mtk_pinctrl *hw,
751 const struct mtk_pin_desc *desc,
752 u32 pullup, u32 arg)
753 {
754 u32 enable = arg == MTK_DISABLE ? MTK_DISABLE : MTK_ENABLE;
755 int err;
756
757 if (arg != MTK_DISABLE) {
758 err = mtk_pinconf_bias_set_rsel(hw, desc, pullup, arg);
759 if (err)
760 return err;
761 }
762
763 return mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, enable, false);
764 }
765
mtk_pinconf_bias_set_combo(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,u32 pullup,u32 arg)766 int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
767 const struct mtk_pin_desc *desc,
768 u32 pullup, u32 arg)
769 {
770 int err = -ENOTSUPP;
771 u32 try_all_type;
772
773 if (hw->soc->pull_type)
774 try_all_type = hw->soc->pull_type[desc->number];
775 else
776 try_all_type = MTK_PULL_TYPE_MASK;
777
778 if (try_all_type & MTK_PULL_RSEL_TYPE) {
779 err = mtk_pinconf_bias_set_pu_pd_rsel(hw, desc, pullup, arg);
780 if (!err)
781 return 0;
782 }
783
784 if (try_all_type & MTK_PULL_PD_TYPE) {
785 err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg, true);
786 if (!err)
787 return err;
788 }
789
790 if (try_all_type & MTK_PULL_PU_PD_TYPE) {
791 err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg, false);
792 if (!err)
793 return 0;
794 }
795
796 if (try_all_type & MTK_PULL_PULLSEL_TYPE) {
797 err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc,
798 pullup, arg);
799 if (!err)
800 return 0;
801 }
802
803 if (try_all_type & MTK_PULL_PUPD_R1R0_TYPE)
804 err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg);
805
806 if (err)
807 dev_err(hw->dev, "Invalid pull argument\n");
808
809 return err;
810 }
811 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo);
812
mtk_rsel_get_si_unit(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,u32 pullup,u32 rsel_val,u32 * si_unit)813 static int mtk_rsel_get_si_unit(struct mtk_pinctrl *hw,
814 const struct mtk_pin_desc *desc,
815 u32 pullup, u32 rsel_val, u32 *si_unit)
816 {
817 const struct mtk_pin_rsel *rsel;
818 int check;
819
820 rsel = hw->soc->pin_rsel;
821
822 for (check = 0; check <= hw->soc->npin_rsel - 1; check++) {
823 if (desc->number >= rsel[check].s_pin &&
824 desc->number <= rsel[check].e_pin) {
825 if (rsel_val == rsel[check].rsel_index) {
826 if (pullup)
827 *si_unit = rsel[check].up_rsel;
828 else
829 *si_unit = rsel[check].down_rsel;
830 break;
831 }
832 }
833 }
834
835 return 0;
836 }
837
mtk_pinconf_bias_get_pu_pd_rsel(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,u32 * pullup,u32 * enable)838 static int mtk_pinconf_bias_get_pu_pd_rsel(struct mtk_pinctrl *hw,
839 const struct mtk_pin_desc *desc,
840 u32 *pullup, u32 *enable)
841 {
842 int pu, pd, rsel, err;
843
844 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_RSEL, &rsel);
845 if (err)
846 goto out;
847
848 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu);
849 if (err)
850 goto out;
851
852 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
853 if (err)
854 goto out;
855
856 if (pu == 0 && pd == 0) {
857 *pullup = 0;
858 *enable = MTK_DISABLE;
859 } else if (pu == 1 && pd == 0) {
860 *pullup = 1;
861 if (hw->rsel_si_unit)
862 mtk_rsel_get_si_unit(hw, desc, *pullup, rsel, enable);
863 else
864 *enable = rsel + MTK_PULL_SET_RSEL_000;
865 } else if (pu == 0 && pd == 1) {
866 *pullup = 0;
867 if (hw->rsel_si_unit)
868 mtk_rsel_get_si_unit(hw, desc, *pullup, rsel, enable);
869 else
870 *enable = rsel + MTK_PULL_SET_RSEL_000;
871 } else {
872 err = -EINVAL;
873 goto out;
874 }
875
876 out:
877 return err;
878 }
879
mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,u32 * pullup,u32 * enable)880 static int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl *hw,
881 const struct mtk_pin_desc *desc,
882 u32 *pullup, u32 *enable)
883 {
884 int err, pu, pd;
885
886 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu);
887 if (err)
888 goto out;
889
890 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
891 if (err)
892 goto out;
893
894 if (pu == 0 && pd == 0) {
895 *pullup = 0;
896 *enable = MTK_DISABLE;
897 } else if (pu == 1 && pd == 0) {
898 *pullup = 1;
899 *enable = MTK_ENABLE;
900 } else if (pu == 0 && pd == 1) {
901 *pullup = 0;
902 *enable = MTK_ENABLE;
903 } else
904 err = -EINVAL;
905
906 out:
907 return err;
908 }
909
mtk_pinconf_bias_get_pd(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,u32 * pullup,u32 * enable)910 static int mtk_pinconf_bias_get_pd(struct mtk_pinctrl *hw,
911 const struct mtk_pin_desc *desc,
912 u32 *pullup, u32 *enable)
913 {
914 int err, pd;
915
916 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
917 if (err)
918 goto out;
919
920 if (pd == 0) {
921 *pullup = 0;
922 *enable = MTK_DISABLE;
923 } else if (pd == 1) {
924 *pullup = 0;
925 *enable = MTK_ENABLE;
926 } else
927 err = -EINVAL;
928
929 out:
930 return err;
931 }
932
mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,u32 * pullup,u32 * enable)933 static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw,
934 const struct mtk_pin_desc *desc,
935 u32 *pullup, u32 *enable)
936 {
937 int err;
938
939 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup);
940 if (err)
941 goto out;
942
943 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable);
944
945 out:
946 return err;
947 }
948
mtk_pinconf_bias_get_pupd_r1_r0(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,u32 * pullup,u32 * enable)949 static int mtk_pinconf_bias_get_pupd_r1_r0(struct mtk_pinctrl *hw,
950 const struct mtk_pin_desc *desc,
951 u32 *pullup, u32 *enable)
952 {
953 int err, r0, r1;
954
955 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, pullup);
956 if (err)
957 goto out;
958 /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
959 *pullup = !(*pullup);
960
961 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &r0);
962 if (err)
963 goto out;
964
965 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &r1);
966 if (err)
967 goto out;
968
969 if ((r1 == 0) && (r0 == 0))
970 *enable = MTK_PUPD_SET_R1R0_00;
971 else if ((r1 == 0) && (r0 == 1))
972 *enable = MTK_PUPD_SET_R1R0_01;
973 else if ((r1 == 1) && (r0 == 0))
974 *enable = MTK_PUPD_SET_R1R0_10;
975 else if ((r1 == 1) && (r0 == 1))
976 *enable = MTK_PUPD_SET_R1R0_11;
977 else
978 err = -EINVAL;
979
980 out:
981 return err;
982 }
983
mtk_pinconf_bias_get_combo(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,u32 * pullup,u32 * enable)984 int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw,
985 const struct mtk_pin_desc *desc,
986 u32 *pullup, u32 *enable)
987 {
988 int err = -ENOTSUPP;
989 u32 try_all_type;
990
991 if (hw->soc->pull_type)
992 try_all_type = hw->soc->pull_type[desc->number];
993 else
994 try_all_type = MTK_PULL_TYPE_MASK;
995
996 if (try_all_type & MTK_PULL_RSEL_TYPE) {
997 err = mtk_pinconf_bias_get_pu_pd_rsel(hw, desc, pullup, enable);
998 if (!err)
999 return 0;
1000 }
1001
1002 if (try_all_type & MTK_PULL_PD_TYPE) {
1003 err = mtk_pinconf_bias_get_pd(hw, desc, pullup, enable);
1004 if (!err)
1005 return err;
1006 }
1007
1008 if (try_all_type & MTK_PULL_PU_PD_TYPE) {
1009 err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
1010 if (!err)
1011 return 0;
1012 }
1013
1014 if (try_all_type & MTK_PULL_PULLSEL_TYPE) {
1015 err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc,
1016 pullup, enable);
1017 if (!err)
1018 return 0;
1019 }
1020
1021 if (try_all_type & MTK_PULL_PUPD_R1R0_TYPE)
1022 err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable);
1023
1024 return err;
1025 }
1026 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_combo);
1027
1028 /* Revision 0 */
mtk_pinconf_drive_set(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,u32 arg)1029 int mtk_pinconf_drive_set(struct mtk_pinctrl *hw,
1030 const struct mtk_pin_desc *desc, u32 arg)
1031 {
1032 const struct mtk_drive_desc *tb;
1033 int err = -ENOTSUPP;
1034
1035 tb = &mtk_drive[desc->drv_n];
1036 /* 4mA when (e8, e4) = (0, 0)
1037 * 8mA when (e8, e4) = (0, 1)
1038 * 12mA when (e8, e4) = (1, 0)
1039 * 16mA when (e8, e4) = (1, 1)
1040 */
1041 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
1042 arg = (arg / tb->step - 1) * tb->scal;
1043 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E4,
1044 arg & 0x1);
1045 if (err)
1046 return err;
1047
1048 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E8,
1049 (arg & 0x2) >> 1);
1050 if (err)
1051 return err;
1052 }
1053
1054 return err;
1055 }
1056 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set);
1057
mtk_pinconf_drive_get(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,int * val)1058 int mtk_pinconf_drive_get(struct mtk_pinctrl *hw,
1059 const struct mtk_pin_desc *desc, int *val)
1060 {
1061 const struct mtk_drive_desc *tb;
1062 int err, val1, val2;
1063
1064 tb = &mtk_drive[desc->drv_n];
1065
1066 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E4, &val1);
1067 if (err)
1068 return err;
1069
1070 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E8, &val2);
1071 if (err)
1072 return err;
1073
1074 /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1)
1075 * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1)
1076 */
1077 *val = (((val2 << 1) + val1) / tb->scal + 1) * tb->step;
1078
1079 return 0;
1080 }
1081 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get);
1082
1083 /* Revision 1 */
mtk_pinconf_drive_set_rev1(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,u32 arg)1084 int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw,
1085 const struct mtk_pin_desc *desc, u32 arg)
1086 {
1087 const struct mtk_drive_desc *tb;
1088 int err = -ENOTSUPP;
1089
1090 tb = &mtk_drive[desc->drv_n];
1091
1092 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
1093 arg = (arg / tb->step - 1) * tb->scal;
1094
1095 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV,
1096 arg);
1097 if (err)
1098 return err;
1099 }
1100
1101 return err;
1102 }
1103 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_rev1);
1104
mtk_pinconf_drive_get_rev1(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,int * val)1105 int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw,
1106 const struct mtk_pin_desc *desc, int *val)
1107 {
1108 const struct mtk_drive_desc *tb;
1109 int err, val1;
1110
1111 tb = &mtk_drive[desc->drv_n];
1112
1113 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, &val1);
1114 if (err)
1115 return err;
1116
1117 *val = ((val1 & 0x7) / tb->scal + 1) * tb->step;
1118
1119 return 0;
1120 }
1121 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_rev1);
1122
mtk_pinconf_drive_set_raw(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,u32 arg)1123 int mtk_pinconf_drive_set_raw(struct mtk_pinctrl *hw,
1124 const struct mtk_pin_desc *desc, u32 arg)
1125 {
1126 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, arg);
1127 }
1128 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_raw);
1129
mtk_pinconf_drive_get_raw(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,int * val)1130 int mtk_pinconf_drive_get_raw(struct mtk_pinctrl *hw,
1131 const struct mtk_pin_desc *desc, int *val)
1132 {
1133 return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, val);
1134 }
1135 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_raw);
1136
mtk_pinconf_adv_pull_set(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,bool pullup,u32 arg)1137 int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
1138 const struct mtk_pin_desc *desc, bool pullup,
1139 u32 arg)
1140 {
1141 int err;
1142
1143 /* 10K off & 50K (75K) off, when (R0, R1) = (0, 0);
1144 * 10K off & 50K (75K) on, when (R0, R1) = (0, 1);
1145 * 10K on & 50K (75K) off, when (R0, R1) = (1, 0);
1146 * 10K on & 50K (75K) on, when (R0, R1) = (1, 1)
1147 */
1148 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, arg & 1);
1149 if (err)
1150 return 0;
1151
1152 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1,
1153 !!(arg & 2));
1154 if (err)
1155 return 0;
1156
1157 arg = pullup ? 0 : 1;
1158
1159 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, arg);
1160
1161 /* If PUPD register is not supported for that pin, let's fallback to
1162 * general bias control.
1163 */
1164 if (err == -ENOTSUPP) {
1165 if (hw->soc->bias_set) {
1166 err = hw->soc->bias_set(hw, desc, pullup);
1167 if (err)
1168 return err;
1169 } else {
1170 err = mtk_pinconf_bias_set_rev1(hw, desc, pullup);
1171 if (err)
1172 err = mtk_pinconf_bias_set(hw, desc, pullup);
1173 }
1174 }
1175
1176 return err;
1177 }
1178 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_set);
1179
mtk_pinconf_adv_pull_get(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,bool pullup,u32 * val)1180 int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
1181 const struct mtk_pin_desc *desc, bool pullup,
1182 u32 *val)
1183 {
1184 u32 t, t2;
1185 int err;
1186
1187 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, &t);
1188
1189 /* If PUPD register is not supported for that pin, let's fallback to
1190 * general bias control.
1191 */
1192 if (err == -ENOTSUPP) {
1193 if (hw->soc->bias_get) {
1194 err = hw->soc->bias_get(hw, desc, pullup, val);
1195 if (err)
1196 return err;
1197 } else {
1198 return -ENOTSUPP;
1199 }
1200 } else {
1201 /* t == 0 supposes PULLUP for the customized PULL setup */
1202 if (err)
1203 return err;
1204
1205 if (pullup ^ !t)
1206 return -EINVAL;
1207 }
1208
1209 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &t);
1210 if (err)
1211 return err;
1212
1213 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &t2);
1214 if (err)
1215 return err;
1216
1217 *val = (t | t2 << 1) & 0x7;
1218
1219 return 0;
1220 }
1221 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_get);
1222
mtk_pinconf_adv_drive_set(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,u32 arg)1223 int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
1224 const struct mtk_pin_desc *desc, u32 arg)
1225 {
1226 int err;
1227 int en = arg & 1;
1228 int e0 = !!(arg & 2);
1229 int e1 = !!(arg & 4);
1230
1231 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, en);
1232 if (err)
1233 return err;
1234
1235 if (!en)
1236 return err;
1237
1238 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, e0);
1239 if (err)
1240 return err;
1241
1242 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1);
1243 if (err)
1244 return err;
1245
1246 return err;
1247 }
1248 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set);
1249
mtk_pinconf_adv_drive_get(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,u32 * val)1250 int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
1251 const struct mtk_pin_desc *desc, u32 *val)
1252 {
1253 u32 en, e0, e1;
1254 int err;
1255
1256 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, &en);
1257 if (err)
1258 return err;
1259
1260 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, &e0);
1261 if (err)
1262 return err;
1263
1264 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, &e1);
1265 if (err)
1266 return err;
1267
1268 *val = (en | e0 << 1 | e1 << 2) & 0x7;
1269
1270 return 0;
1271 }
1272 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get);
1273
mtk_pinconf_adv_drive_set_raw(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,u32 arg)1274 int mtk_pinconf_adv_drive_set_raw(struct mtk_pinctrl *hw,
1275 const struct mtk_pin_desc *desc, u32 arg)
1276 {
1277 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_ADV, arg);
1278 }
1279 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set_raw);
1280
mtk_pinconf_adv_drive_get_raw(struct mtk_pinctrl * hw,const struct mtk_pin_desc * desc,u32 * val)1281 int mtk_pinconf_adv_drive_get_raw(struct mtk_pinctrl *hw,
1282 const struct mtk_pin_desc *desc, u32 *val)
1283 {
1284 return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_ADV, val);
1285 }
1286 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get_raw);
1287
1288 MODULE_LICENSE("GPL v2");
1289 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
1290 MODULE_DESCRIPTION("Pin configuration library module for mediatek SoCs");
1291