1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/etherdevice.h> 7 #include <linux/of.h> 8 #include <linux/hwmon.h> 9 #include <linux/hwmon-sysfs.h> 10 #include <linux/thermal.h> 11 #include "mt7996.h" 12 #include "mac.h" 13 #include "mcu.h" 14 #include "coredump.h" 15 #include "eeprom.h" 16 17 static const struct ieee80211_iface_limit if_limits_global = { 18 .max = MT7996_MAX_INTERFACES * MT7996_MAX_RADIOS, 19 .types = BIT(NL80211_IFTYPE_STATION) 20 | BIT(NL80211_IFTYPE_ADHOC) 21 | BIT(NL80211_IFTYPE_AP) 22 #ifdef CONFIG_MAC80211_MESH 23 | BIT(NL80211_IFTYPE_MESH_POINT) 24 #endif 25 }; 26 27 static const struct ieee80211_iface_combination if_comb_global = { 28 .limits = &if_limits_global, 29 .n_limits = 1, 30 .max_interfaces = MT7996_MAX_INTERFACES * MT7996_MAX_RADIOS, 31 .num_different_channels = MT7996_MAX_RADIOS, 32 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 33 BIT(NL80211_CHAN_WIDTH_20) | 34 BIT(NL80211_CHAN_WIDTH_40) | 35 BIT(NL80211_CHAN_WIDTH_80) | 36 BIT(NL80211_CHAN_WIDTH_160), 37 .beacon_int_min_gcd = 100, 38 }; 39 40 static const struct ieee80211_iface_combination if_comb_global_7992 = { 41 .limits = &if_limits_global, 42 .n_limits = 1, 43 .max_interfaces = 32, 44 .num_different_channels = MT7996_MAX_RADIOS - 1, 45 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 46 BIT(NL80211_CHAN_WIDTH_20) | 47 BIT(NL80211_CHAN_WIDTH_40) | 48 BIT(NL80211_CHAN_WIDTH_80) | 49 BIT(NL80211_CHAN_WIDTH_160), 50 .beacon_int_min_gcd = 100, 51 }; 52 53 static const struct ieee80211_iface_limit if_limits[] = { 54 { 55 .max = 16, 56 .types = BIT(NL80211_IFTYPE_AP) 57 #ifdef CONFIG_MAC80211_MESH 58 | BIT(NL80211_IFTYPE_MESH_POINT) 59 #endif 60 }, { 61 .max = MT7996_MAX_INTERFACES, 62 .types = BIT(NL80211_IFTYPE_STATION) 63 } 64 }; 65 66 static const struct ieee80211_iface_combination if_comb = { 67 .limits = if_limits, 68 .n_limits = ARRAY_SIZE(if_limits), 69 .max_interfaces = MT7996_MAX_INTERFACES, 70 .num_different_channels = 1, 71 .beacon_int_infra_match = true, 72 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 73 BIT(NL80211_CHAN_WIDTH_20) | 74 BIT(NL80211_CHAN_WIDTH_40) | 75 BIT(NL80211_CHAN_WIDTH_80) | 76 BIT(NL80211_CHAN_WIDTH_160), 77 .beacon_int_min_gcd = 100, 78 }; 79 80 static const u8 if_types_ext_capa_ap[] = { 81 [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING, 82 [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT, 83 [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, 84 }; 85 86 static const struct wiphy_iftype_ext_capab iftypes_ext_capa[] = { 87 { 88 .iftype = NL80211_IFTYPE_AP, 89 .extended_capabilities = if_types_ext_capa_ap, 90 .extended_capabilities_mask = if_types_ext_capa_ap, 91 .extended_capabilities_len = sizeof(if_types_ext_capa_ap), 92 .eml_capabilities = IEEE80211_EML_CAP_EMLSR_SUPP, 93 .mld_capa_and_ops = 94 FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_MAX_SIMUL_LINKS, 95 MT7996_MAX_RADIOS - 1), 96 }, { 97 .iftype = NL80211_IFTYPE_STATION, 98 .extended_capabilities = if_types_ext_capa_ap, 99 .extended_capabilities_mask = if_types_ext_capa_ap, 100 .extended_capabilities_len = sizeof(if_types_ext_capa_ap), 101 .mld_capa_and_ops = 102 FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_FREQ_SEP_TYPE_IND, 1) | 103 FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_MAX_SIMUL_LINKS, 104 MT7996_MAX_RADIOS - 1), 105 }, 106 }; 107 108 static ssize_t mt7996_thermal_temp_show(struct device *dev, 109 struct device_attribute *attr, 110 char *buf) 111 { 112 struct mt7996_phy *phy = dev_get_drvdata(dev); 113 int i = to_sensor_dev_attr(attr)->index; 114 int temperature; 115 116 switch (i) { 117 case 0: 118 temperature = mt7996_mcu_get_temperature(phy); 119 if (temperature < 0) 120 return temperature; 121 /* display in millidegree celcius */ 122 return sprintf(buf, "%u\n", temperature * 1000); 123 case 1: 124 case 2: 125 return sprintf(buf, "%u\n", 126 phy->throttle_temp[i - 1] * 1000); 127 case 3: 128 return sprintf(buf, "%hhu\n", phy->throttle_state); 129 default: 130 return -EINVAL; 131 } 132 } 133 134 static ssize_t mt7996_thermal_temp_store(struct device *dev, 135 struct device_attribute *attr, 136 const char *buf, size_t count) 137 { 138 struct mt7996_phy *phy = dev_get_drvdata(dev); 139 int ret, i = to_sensor_dev_attr(attr)->index; 140 long val; 141 142 ret = kstrtol(buf, 10, &val); 143 if (ret < 0) 144 return ret; 145 146 mutex_lock(&phy->dev->mt76.mutex); 147 val = DIV_ROUND_CLOSEST(clamp_val(val, 40 * 1000, 130 * 1000), 1000); 148 149 /* add a safety margin ~10 */ 150 if ((i - 1 == MT7996_CRIT_TEMP_IDX && 151 val > phy->throttle_temp[MT7996_MAX_TEMP_IDX] - 10) || 152 (i - 1 == MT7996_MAX_TEMP_IDX && 153 val - 10 < phy->throttle_temp[MT7996_CRIT_TEMP_IDX])) { 154 dev_err(phy->dev->mt76.dev, 155 "temp1_max shall be 10 degrees higher than temp1_crit."); 156 mutex_unlock(&phy->dev->mt76.mutex); 157 return -EINVAL; 158 } 159 160 phy->throttle_temp[i - 1] = val; 161 mutex_unlock(&phy->dev->mt76.mutex); 162 163 ret = mt7996_mcu_set_thermal_protect(phy, true); 164 if (ret) 165 return ret; 166 167 return count; 168 } 169 170 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7996_thermal_temp, 0); 171 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7996_thermal_temp, 1); 172 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7996_thermal_temp, 2); 173 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7996_thermal_temp, 3); 174 175 static struct attribute *mt7996_hwmon_attrs[] = { 176 &sensor_dev_attr_temp1_input.dev_attr.attr, 177 &sensor_dev_attr_temp1_crit.dev_attr.attr, 178 &sensor_dev_attr_temp1_max.dev_attr.attr, 179 &sensor_dev_attr_throttle1.dev_attr.attr, 180 NULL, 181 }; 182 ATTRIBUTE_GROUPS(mt7996_hwmon); 183 184 static int 185 mt7996_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, 186 unsigned long *state) 187 { 188 *state = MT7996_CDEV_THROTTLE_MAX; 189 190 return 0; 191 } 192 193 static int 194 mt7996_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, 195 unsigned long *state) 196 { 197 struct mt7996_phy *phy = cdev->devdata; 198 199 *state = phy->cdev_state; 200 201 return 0; 202 } 203 204 static int 205 mt7996_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, 206 unsigned long state) 207 { 208 struct mt7996_phy *phy = cdev->devdata; 209 u8 throttling = MT7996_THERMAL_THROTTLE_MAX - state; 210 int ret; 211 212 if (state > MT7996_CDEV_THROTTLE_MAX) { 213 dev_err(phy->dev->mt76.dev, 214 "please specify a valid throttling state\n"); 215 return -EINVAL; 216 } 217 218 if (state == phy->cdev_state) 219 return 0; 220 221 /* cooling_device convention: 0 = no cooling, more = more cooling 222 * mcu convention: 1 = max cooling, more = less cooling 223 */ 224 ret = mt7996_mcu_set_thermal_throttling(phy, throttling); 225 if (ret) 226 return ret; 227 228 phy->cdev_state = state; 229 230 return 0; 231 } 232 233 static const struct thermal_cooling_device_ops mt7996_thermal_ops = { 234 .get_max_state = mt7996_thermal_get_max_throttle_state, 235 .get_cur_state = mt7996_thermal_get_cur_throttle_state, 236 .set_cur_state = mt7996_thermal_set_cur_throttle_state, 237 }; 238 239 static void mt7996_unregister_thermal(struct mt7996_phy *phy) 240 { 241 struct wiphy *wiphy = phy->mt76->hw->wiphy; 242 char name[sizeof("cooling_deviceXXX")]; 243 244 if (!phy->cdev) 245 return; 246 247 snprintf(name, sizeof(name), "cooling_device%d", phy->mt76->band_idx); 248 sysfs_remove_link(&wiphy->dev.kobj, name); 249 thermal_cooling_device_unregister(phy->cdev); 250 } 251 252 static int mt7996_thermal_init(struct mt7996_phy *phy) 253 { 254 struct wiphy *wiphy = phy->mt76->hw->wiphy; 255 char cname[sizeof("cooling_deviceXXX")]; 256 struct thermal_cooling_device *cdev; 257 struct device *hwmon; 258 const char *name; 259 260 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7996_%s.%d", 261 wiphy_name(wiphy), phy->mt76->band_idx); 262 if (!name) 263 return -ENOMEM; 264 265 snprintf(cname, sizeof(cname), "cooling_device%d", phy->mt76->band_idx); 266 267 cdev = thermal_cooling_device_register(name, phy, &mt7996_thermal_ops); 268 if (!IS_ERR(cdev)) { 269 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj, 270 cname) < 0) 271 thermal_cooling_device_unregister(cdev); 272 else 273 phy->cdev = cdev; 274 } 275 276 /* initialize critical/maximum high temperature */ 277 phy->throttle_temp[MT7996_CRIT_TEMP_IDX] = MT7996_CRIT_TEMP; 278 phy->throttle_temp[MT7996_MAX_TEMP_IDX] = MT7996_MAX_TEMP; 279 280 if (!IS_REACHABLE(CONFIG_HWMON)) 281 return 0; 282 283 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, 284 mt7996_hwmon_groups); 285 286 if (IS_ERR(hwmon)) 287 return PTR_ERR(hwmon); 288 289 return 0; 290 } 291 292 static void mt7996_led_set_config(struct led_classdev *led_cdev, 293 u8 delay_on, u8 delay_off) 294 { 295 struct mt7996_dev *dev; 296 struct mt76_phy *mphy; 297 u32 val; 298 299 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 300 dev = container_of(mphy->dev, struct mt7996_dev, mt76); 301 302 /* select TX blink mode, 2: only data frames */ 303 mt76_rmw_field(dev, MT_TMAC_TCR0(mphy->band_idx), MT_TMAC_TCR0_TX_BLINK, 2); 304 305 /* enable LED */ 306 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1); 307 308 /* set LED Tx blink on/off time */ 309 val = FIELD_PREP(MT_LED_TX_BLINK_ON_MASK, delay_on) | 310 FIELD_PREP(MT_LED_TX_BLINK_OFF_MASK, delay_off); 311 mt76_wr(dev, MT_LED_TX_BLINK(mphy->band_idx), val); 312 313 /* turn LED off */ 314 if (delay_off == 0xff && delay_on == 0x0) { 315 val = MT_LED_CTRL_POLARITY | MT_LED_CTRL_KICK; 316 } else { 317 /* control LED */ 318 val = MT_LED_CTRL_BLINK_MODE | MT_LED_CTRL_KICK; 319 if (mphy->band_idx == MT_BAND1) 320 val |= MT_LED_CTRL_BLINK_BAND_SEL; 321 } 322 323 if (mphy->leds.al) 324 val |= MT_LED_CTRL_POLARITY; 325 326 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val); 327 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK); 328 } 329 330 static int mt7996_led_set_blink(struct led_classdev *led_cdev, 331 unsigned long *delay_on, 332 unsigned long *delay_off) 333 { 334 u16 delta_on = 0, delta_off = 0; 335 336 #define HW_TICK 10 337 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 338 339 if (*delay_on) 340 delta_on = TO_HW_TICK(*delay_on); 341 if (*delay_off) 342 delta_off = TO_HW_TICK(*delay_off); 343 344 mt7996_led_set_config(led_cdev, delta_on, delta_off); 345 346 return 0; 347 } 348 349 static void mt7996_led_set_brightness(struct led_classdev *led_cdev, 350 enum led_brightness brightness) 351 { 352 if (!brightness) 353 mt7996_led_set_config(led_cdev, 0, 0xff); 354 else 355 mt7996_led_set_config(led_cdev, 0xff, 0); 356 } 357 358 static void __mt7996_init_txpower(struct mt7996_phy *phy, 359 struct ieee80211_supported_band *sband) 360 { 361 struct mt7996_dev *dev = phy->dev; 362 int i, n_chains = hweight16(phy->mt76->chainmask); 363 int path_delta = mt76_tx_power_path_delta(n_chains); 364 int pwr_delta = mt7996_eeprom_get_power_delta(dev, sband->band); 365 struct mt76_power_limits limits; 366 367 for (i = 0; i < sband->n_channels; i++) { 368 struct ieee80211_channel *chan = &sband->channels[i]; 369 int target_power = mt7996_eeprom_get_target_power(dev, chan); 370 371 target_power += pwr_delta; 372 target_power = mt76_get_rate_power_limits(phy->mt76, chan, 373 &limits, 374 target_power); 375 target_power += path_delta; 376 target_power = DIV_ROUND_UP(target_power, 2); 377 chan->max_power = min_t(int, chan->max_reg_power, 378 target_power); 379 chan->orig_mpwr = target_power; 380 } 381 } 382 383 void mt7996_init_txpower(struct mt7996_phy *phy) 384 { 385 if (!phy) 386 return; 387 388 if (phy->mt76->cap.has_2ghz) 389 __mt7996_init_txpower(phy, &phy->mt76->sband_2g.sband); 390 if (phy->mt76->cap.has_5ghz) 391 __mt7996_init_txpower(phy, &phy->mt76->sband_5g.sband); 392 if (phy->mt76->cap.has_6ghz) 393 __mt7996_init_txpower(phy, &phy->mt76->sband_6g.sband); 394 } 395 396 static void 397 mt7996_regd_notifier(struct wiphy *wiphy, 398 struct regulatory_request *request) 399 { 400 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 401 struct mt7996_dev *dev = mt7996_hw_dev(hw); 402 struct mt7996_phy *phy; 403 404 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 405 dev->mt76.region = request->dfs_region; 406 407 mt7996_for_each_phy(dev, phy) { 408 if (dev->mt76.region == NL80211_DFS_UNSET) 409 mt7996_mcu_rdd_background_enable(phy, NULL); 410 411 mt7996_init_txpower(phy); 412 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 413 mt7996_dfs_init_radar_detector(phy); 414 } 415 } 416 417 static void 418 mt7996_init_wiphy_band(struct ieee80211_hw *hw, struct mt7996_phy *phy) 419 { 420 struct mt7996_dev *dev = phy->dev; 421 struct wiphy *wiphy = hw->wiphy; 422 int n_radios = hw->wiphy->n_radio; 423 struct wiphy_radio_freq_range *freq = &dev->radio_freqs[n_radios]; 424 struct wiphy_radio *radio = &dev->radios[n_radios]; 425 426 phy->slottime = 9; 427 phy->beacon_rate = -1; 428 phy->rxfilter = MT_WF_RFCR_DROP_OTHER_UC; 429 430 if (phy->mt76->cap.has_2ghz) { 431 phy->mt76->sband_2g.sband.ht_cap.cap |= 432 IEEE80211_HT_CAP_LDPC_CODING | 433 IEEE80211_HT_CAP_MAX_AMSDU; 434 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 435 IEEE80211_HT_MPDU_DENSITY_2; 436 freq->start_freq = 2400000; 437 freq->end_freq = 2500000; 438 } else if (phy->mt76->cap.has_5ghz) { 439 phy->mt76->sband_5g.sband.ht_cap.cap |= 440 IEEE80211_HT_CAP_LDPC_CODING | 441 IEEE80211_HT_CAP_MAX_AMSDU; 442 443 phy->mt76->sband_5g.sband.vht_cap.cap |= 444 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 445 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 446 IEEE80211_VHT_CAP_SHORT_GI_160 | 447 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 448 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 449 IEEE80211_HT_MPDU_DENSITY_1; 450 451 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 452 freq->start_freq = 5000000; 453 freq->end_freq = 5900000; 454 } else if (phy->mt76->cap.has_6ghz) { 455 freq->start_freq = 5900000; 456 freq->end_freq = 7200000; 457 } else { 458 return; 459 } 460 461 dev->radio_phy[n_radios] = phy; 462 radio->freq_range = freq; 463 radio->n_freq_range = 1; 464 radio->iface_combinations = &if_comb; 465 radio->n_iface_combinations = 1; 466 hw->wiphy->n_radio++; 467 468 wiphy->available_antennas_rx |= phy->mt76->chainmask; 469 wiphy->available_antennas_tx |= phy->mt76->chainmask; 470 471 mt76_set_stream_caps(phy->mt76, true); 472 mt7996_set_stream_vht_txbf_caps(phy); 473 mt7996_set_stream_he_eht_caps(phy); 474 mt7996_init_txpower(phy); 475 } 476 477 static void 478 mt7996_init_wiphy(struct ieee80211_hw *hw, struct mtk_wed_device *wed) 479 { 480 struct mt7996_dev *dev = mt7996_hw_dev(hw); 481 struct mt76_dev *mdev = &dev->mt76; 482 struct wiphy *wiphy = hw->wiphy; 483 u16 max_subframes = dev->has_eht ? IEEE80211_MAX_AMPDU_BUF_EHT : 484 IEEE80211_MAX_AMPDU_BUF_HE; 485 486 hw->queues = 4; 487 hw->max_rx_aggregation_subframes = max_subframes; 488 hw->max_tx_aggregation_subframes = max_subframes; 489 if (is_mt7990(mdev) && dev->has_eht) 490 hw->max_tx_aggregation_subframes = 512; 491 492 hw->netdev_features = NETIF_F_RXCSUM; 493 if (mtk_wed_device_active(wed) || mt76_npu_device_active(mdev)) 494 hw->netdev_features |= NETIF_F_HW_TC; 495 496 hw->radiotap_timestamp.units_pos = 497 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 498 499 hw->sta_data_size = sizeof(struct mt7996_sta); 500 hw->vif_data_size = sizeof(struct mt7996_vif); 501 hw->chanctx_data_size = sizeof(struct mt76_chanctx); 502 503 wiphy->iface_combinations = is_mt7996(&dev->mt76) ? &if_comb_global : 504 &if_comb_global_7992; 505 wiphy->n_iface_combinations = 1; 506 507 wiphy->radio = dev->radios; 508 509 wiphy->reg_notifier = mt7996_regd_notifier; 510 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH | 511 WIPHY_FLAG_SUPPORTS_MLO; 512 wiphy->mbssid_max_interfaces = 16; 513 wiphy->iftype_ext_capab = iftypes_ext_capa; 514 wiphy->num_iftype_ext_capab = ARRAY_SIZE(iftypes_ext_capa); 515 516 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 517 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 518 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 519 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 520 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 521 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 522 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 523 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 524 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 525 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 526 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER); 527 528 if (mt7996_eeprom_has_background_radar(dev) && 529 (!mdev->dev->of_node || 530 !of_property_read_bool(mdev->dev->of_node, 531 "mediatek,disable-radar-background"))) 532 wiphy_ext_feature_set(wiphy, 533 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 534 535 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 536 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 537 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 538 ieee80211_hw_set(hw, NO_VIRTUAL_MONITOR); 539 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 540 ieee80211_hw_set(hw, CHANCTX_STA_CSA); 541 542 hw->max_tx_fragments = 4; 543 wiphy->txq_memory_limit = 32 << 20; /* 32 MiB */ 544 545 /* init led callbacks */ 546 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 547 dev->mphy.leds.cdev.brightness_set = mt7996_led_set_brightness; 548 dev->mphy.leds.cdev.blink_set = mt7996_led_set_blink; 549 } 550 551 wiphy->max_scan_ssids = 4; 552 wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; 553 554 mt7996_init_wiphy_band(hw, &dev->phy); 555 } 556 557 static void 558 mt7996_mac_init_band(struct mt7996_dev *dev, u8 band) 559 { 560 u32 mask, set; 561 562 /* clear estimated value of EIFS for Rx duration & OBSS time */ 563 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 564 565 /* clear backoff time for Rx duration */ 566 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 567 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 568 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 569 MT_WF_RMAC_MIB_QOS01_BACKOFF); 570 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 571 MT_WF_RMAC_MIB_QOS23_BACKOFF); 572 573 /* clear backoff time for Tx duration */ 574 mt76_clear(dev, MT_WTBLOFF_ACR(band), 575 MT_WTBLOFF_ADM_BACKOFFTIME); 576 577 /* clear backoff time and set software compensation for OBSS time */ 578 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 579 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 580 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 581 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 582 583 /* filter out non-resp frames and get instanstaeous signal reporting */ 584 mask = MT_WTBLOFF_RSCR_RCPI_MODE | MT_WTBLOFF_RSCR_RCPI_PARAM; 585 set = FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_MODE, 0) | 586 FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_PARAM, 0x3); 587 mt76_rmw(dev, MT_WTBLOFF_RSCR(band), mask, set); 588 589 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than 590 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set. 591 */ 592 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H); 593 } 594 595 static void mt7996_mac_init_basic_rates(struct mt7996_dev *dev) 596 { 597 int i; 598 599 for (i = 0; i < ARRAY_SIZE(mt76_rates); i++) { 600 u16 rate = mt76_rates[i].hw_value; 601 /* odd index for driver, even index for firmware */ 602 u16 idx = MT7996_BASIC_RATES_TBL + 2 * i; 603 604 rate = FIELD_PREP(MT_TX_RATE_MODE, rate >> 8) | 605 FIELD_PREP(MT_TX_RATE_IDX, rate & GENMASK(7, 0)); 606 mt7996_mcu_set_fixed_rate_table(&dev->phy, idx, rate, false); 607 } 608 } 609 610 void mt7996_mac_init(struct mt7996_dev *dev) 611 { 612 #define HIF_TXD_V2_1 0x21 613 int i, rx_path_type; 614 615 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 616 617 for (i = 0; i < mt7996_wtbl_size(dev); i++) 618 mt7996_mac_wtbl_update(dev, i, 619 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 620 621 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 622 i = dev->mphy.leds.pin ? MT_LED_GPIO_MUX3 : MT_LED_GPIO_MUX2; 623 mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4); 624 } 625 626 /* rro module init */ 627 if (dev->hif2) { 628 if (mt76_npu_device_active(&dev->mt76)) 629 rx_path_type = is_mt7996(&dev->mt76) ? 6 : 8; 630 else 631 rx_path_type = is_mt7996(&dev->mt76) ? 2 : 7; 632 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 633 rx_path_type); 634 } else { 635 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 0); 636 } 637 638 if (mt7996_has_hwrro(dev)) { 639 u16 timeout; 640 641 timeout = mt76_rr(dev, MT_HW_REV) == MT_HW_REV1 ? 512 : 128; 642 mt7996_mcu_set_rro(dev, UNI_RRO_SET_FLUSH_TIMEOUT, timeout); 643 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 644 is_mt7996(&dev->mt76) ? 1 : 2); 645 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 646 !is_mt7996(&dev->mt76)); 647 } else { 648 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 3); 649 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 1); 650 } 651 652 mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), 653 MCU_WA_PARAM_HW_PATH_HIF_VER, 654 HIF_TXD_V2_1, 0); 655 656 for (i = MT_BAND0; i <= MT_BAND2; i++) 657 mt7996_mac_init_band(dev, i); 658 659 mt7996_mac_init_basic_rates(dev); 660 } 661 662 int mt7996_txbf_init(struct mt7996_dev *dev) 663 { 664 int ret; 665 666 if (mt7996_band_valid(dev, MT_BAND1) || 667 mt7996_band_valid(dev, MT_BAND2)) { 668 ret = mt7996_mcu_set_txbf(dev, BF_MOD_EN_CTRL); 669 if (ret) 670 return ret; 671 } 672 673 /* trigger sounding packets */ 674 ret = mt7996_mcu_set_txbf(dev, BF_SOUNDING_ON); 675 if (ret) 676 return ret; 677 678 /* enable eBF */ 679 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE); 680 } 681 682 static int mt7996_register_phy(struct mt7996_dev *dev, enum mt76_band_id band) 683 { 684 struct mt7996_phy *phy; 685 struct mt76_phy *mphy; 686 u32 mac_ofs, hif1_ofs = 0; 687 int ret; 688 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 689 690 if (!mt7996_band_valid(dev, band)) 691 return 0; 692 693 if (dev->hif2 && 694 ((is_mt7992(&dev->mt76) && band == MT_BAND1) || 695 (is_mt7996(&dev->mt76) && band == MT_BAND2 && 696 !mt76_npu_device_active(&dev->mt76)))) { 697 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 698 wed = &dev->mt76.mmio.wed_hif2; 699 } 700 701 mphy = mt76_alloc_radio_phy(&dev->mt76, sizeof(*phy), band); 702 if (!mphy) 703 return -ENOMEM; 704 705 phy = mphy->priv; 706 phy->dev = dev; 707 phy->mt76 = mphy; 708 mphy->dev->phys[band] = mphy; 709 710 INIT_DELAYED_WORK(&mphy->mac_work, mt7996_mac_work); 711 712 ret = mt7996_eeprom_parse_hw_cap(dev, phy); 713 if (ret) 714 goto error; 715 716 mac_ofs = band == MT_BAND2 ? MT_EE_MAC_ADDR3 : MT_EE_MAC_ADDR2; 717 memcpy(mphy->macaddr, dev->mt76.eeprom.data + mac_ofs, ETH_ALEN); 718 /* Make the extra PHY MAC address local without overlapping with 719 * the usual MAC address allocation scheme on multiple virtual interfaces 720 */ 721 if (!is_valid_ether_addr(mphy->macaddr)) { 722 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 723 ETH_ALEN); 724 mphy->macaddr[0] |= 2; 725 mphy->macaddr[0] ^= BIT(7); 726 if (band == MT_BAND2) 727 mphy->macaddr[0] ^= BIT(6); 728 } 729 ret = mt76_eeprom_override(mphy); 730 if (ret) 731 goto error; 732 733 /* init wiphy according to mphy and phy */ 734 mt7996_init_wiphy_band(mphy->hw, phy); 735 736 if (is_mt7996(&dev->mt76) && 737 ((band == MT_BAND1 && !dev->hif2) || 738 (band == MT_BAND2 && mt76_npu_device_active(&dev->mt76)))) { 739 int i; 740 741 for (i = 0; i <= MT_TXQ_PSD; i++) 742 mphy->q_tx[i] = dev->mt76.phys[band - 1]->q_tx[0]; 743 } else { 744 int size = is_mt7996(&dev->mt76) && 745 mt76_npu_device_active(&dev->mt76) 746 ? MT7996_NPU_TX_RING_SIZE / 2 : MT7996_TX_RING_SIZE; 747 748 ret = mt7996_init_tx_queues(mphy->priv, MT_TXQ_ID(band), size, 749 MT_TXQ_RING_BASE(band) + hif1_ofs, 750 wed); 751 if (ret) 752 goto error; 753 } 754 755 ret = mt76_register_phy(mphy, true, mt76_rates, 756 ARRAY_SIZE(mt76_rates)); 757 if (ret) 758 goto error; 759 760 if (wed == &dev->mt76.mmio.wed_hif2 && mtk_wed_device_active(wed)) { 761 mt76_wr(dev, MT_INT_PCIE1_MASK_CSR, MT_INT_TX_RX_DONE_EXT); 762 mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, 763 MT_INT_TX_RX_DONE_EXT); 764 } 765 766 return 0; 767 768 error: 769 mphy->dev->phys[band] = NULL; 770 return ret; 771 } 772 773 static void 774 mt7996_unregister_phy(struct mt7996_phy *phy) 775 { 776 if (phy) 777 mt7996_unregister_thermal(phy); 778 } 779 780 static void mt7996_init_work(struct work_struct *work) 781 { 782 struct mt7996_dev *dev = container_of(work, struct mt7996_dev, 783 init_work); 784 785 mt7996_mcu_set_eeprom(dev); 786 mt7996_mac_init(dev); 787 mt7996_txbf_init(dev); 788 789 if (!is_mt7990(&dev->mt76)) 790 mt7996_mcu_set_dup_wtbl(dev); 791 } 792 793 void mt7996_wfsys_reset(struct mt7996_dev *dev) 794 { 795 if (!is_mt7990(&dev->mt76)) { 796 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 797 msleep(20); 798 799 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 800 msleep(20); 801 802 return; 803 } 804 805 if (!dev->recovery.hw_full_reset) 806 return; 807 808 mt76_set(dev, MT_WF_SUBSYS_RST, 809 MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT | 810 MT_WF_SUBSYS_RST_BYPASS_WFDMA_SLP_PROT | 811 MT_WF_SUBSYS_RST_BYPASS_WFDMA2_SLP_PROT); 812 mt76_rmw(dev, MT_WF_SUBSYS_RST, 813 MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT_CYCLE, 814 u32_encode_bits(0x20, MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT_CYCLE)); 815 mt76_clear(dev, MT_WF_L05_RST, MT_WF_L05_RST_WF_RST_MASK); 816 mt76_set(dev, MT_WF_SUBSYS_RST, MT_WF_SUBSYS_RST_WHOLE_PATH_RST); 817 msleep(20); 818 819 if (mt76_poll(dev, MT_WF_L05_RST, MT_WF_L05_RST_WF_RST_MASK, 0x1a, 1000)) 820 return; 821 822 dev_err(dev->mt76.dev, "wfsys reset fail\n"); 823 } 824 825 static void mt7996_rro_hw_init_v3(struct mt7996_dev *dev) 826 { 827 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 828 u32 session_id; 829 830 if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) 831 return; 832 833 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 834 if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) { 835 wed->wlan.ind_cmd.win_size = 836 ffs(MT7996_RRO_WINDOW_MAX_LEN) - 6; 837 if (is_mt7996(&dev->mt76)) 838 wed->wlan.ind_cmd.particular_sid = 839 MT7996_RRO_MAX_SESSION; 840 else 841 wed->wlan.ind_cmd.particular_sid = 1; 842 wed->wlan.ind_cmd.particular_se_phys = 843 dev->wed_rro.session.phy_addr; 844 wed->wlan.ind_cmd.se_group_nums = MT7996_RRO_ADDR_ELEM_LEN; 845 wed->wlan.ind_cmd.ack_sn_addr = MT_RRO_ACK_SN_CTRL; 846 } 847 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 848 849 if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) { 850 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0x15010e00); 851 mt76_set(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1, 852 MT_RRO_IND_CMD_SIGNATURE_BASE1_EN); 853 } else { 854 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0); 855 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1, 0); 856 } 857 858 /* particular session configure */ 859 /* use max session idx + 1 as particular session id */ 860 mt76_wr(dev, MT_RRO_PARTICULAR_CFG0, dev->wed_rro.session.phy_addr); 861 862 session_id = is_mt7996(&dev->mt76) ? MT7996_RRO_MAX_SESSION : 1; 863 mt76_wr(dev, MT_RRO_PARTICULAR_CFG1, 864 MT_RRO_PARTICULAR_CONFG_EN | 865 FIELD_PREP(MT_RRO_PARTICULAR_SID, session_id)); 866 } 867 868 void mt7996_rro_hw_init(struct mt7996_dev *dev) 869 { 870 u32 reg = MT_RRO_ADDR_ELEM_SEG_ADDR0; 871 int i; 872 873 if (!mt7996_has_hwrro(dev)) 874 return; 875 876 INIT_LIST_HEAD(&dev->wed_rro.page_cache); 877 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.page_map); i++) 878 INIT_LIST_HEAD(&dev->wed_rro.page_map[i]); 879 880 if (!is_mt7996(&dev->mt76)) { 881 reg = MT_RRO_MSDU_PG_SEG_ADDR0; 882 883 if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) { 884 mt76_clear(dev, MT_RRO_3_0_EMU_CONF, 885 MT_RRO_3_0_EMU_CONF_EN_MASK); 886 mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG, 887 MT_RRO_3_1_GLOBAL_CONFIG_RXDMAD_SEL); 888 if (!mtk_wed_device_active(&dev->mt76.mmio.wed) && 889 !mt76_npu_device_active(&dev->mt76)) { 890 mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG, 891 MT_RRO_3_1_GLOBAL_CONFIG_RX_DIDX_WR_EN | 892 MT_RRO_3_1_GLOBAL_CONFIG_RX_CIDX_RD_EN); 893 mt76_wr(dev, MT_RRO_RX_RING_AP_CIDX_ADDR, 894 dev->wed_rro.emi_rings_cpu.phy_addr >> 4); 895 mt76_wr(dev, MT_RRO_RX_RING_AP_DIDX_ADDR, 896 dev->wed_rro.emi_rings_dma.phy_addr >> 4); 897 } 898 } else { 899 /* set emul 3.0 function */ 900 mt76_set(dev, MT_RRO_3_0_EMU_CONF, MT_RRO_3_0_EMU_CONF_EN_MASK); 901 902 mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE0, 903 dev->wed_rro.addr_elem[0].phy_addr); 904 } 905 906 mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG, 907 MT_RRO_3_1_GLOBAL_CONFIG_INTERLEAVE_EN); 908 909 /* setup Msdu page address */ 910 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) { 911 mt76_wr(dev, reg, 912 dev->wed_rro.msdu_pg[i].phy_addr >> 4); 913 reg += 4; 914 } 915 } else { 916 /* TODO: remove line after WM has set */ 917 mt76_clear(dev, WF_RRO_AXI_MST_CFG, 918 WF_RRO_AXI_MST_CFG_DIDX_OK); 919 920 /* setup BA bitmap cache address */ 921 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE0, 922 dev->wed_rro.ba_bitmap[0].phy_addr); 923 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE1, 0); 924 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT0, 925 dev->wed_rro.ba_bitmap[1].phy_addr); 926 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT1, 0); 927 928 /* Setup Address element address */ 929 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 930 mt76_wr(dev, reg, 931 dev->wed_rro.addr_elem[i].phy_addr >> 4); 932 reg += 4; 933 } 934 935 /* Setup Address element address - separate address segment 936 * mode. 937 */ 938 mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE1, 939 MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE); 940 } 941 942 mt7996_rro_hw_init_v3(dev); 943 944 /* interrupt enable */ 945 mt76_wr(dev, MT_RRO_HOST_INT_ENA, 946 MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA); 947 } 948 949 static int mt7996_wed_rro_init(struct mt7996_dev *dev) 950 { 951 u32 val = FIELD_PREP(WED_RRO_ADDR_SIGNATURE_MASK, 0xff); 952 struct mt7996_wed_rro_addr *addr; 953 void *ptr; 954 int i; 955 956 if (!mt7996_has_hwrro(dev)) 957 return 0; 958 959 if (dev->mt76.hwrro_mode == MT76_HWRRO_V3) { 960 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { 961 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 962 MT7996_RRO_BA_BITMAP_CR_SIZE, 963 &dev->wed_rro.ba_bitmap[i].phy_addr, 964 GFP_KERNEL); 965 if (!ptr) 966 return -ENOMEM; 967 968 dev->wed_rro.ba_bitmap[i].ptr = ptr; 969 } 970 } 971 972 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 973 int j; 974 975 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 976 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr), 977 &dev->wed_rro.addr_elem[i].phy_addr, 978 GFP_KERNEL); 979 if (!ptr) 980 return -ENOMEM; 981 982 dev->wed_rro.addr_elem[i].ptr = ptr; 983 memset(dev->wed_rro.addr_elem[i].ptr, 0, 984 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr)); 985 986 addr = dev->wed_rro.addr_elem[i].ptr; 987 for (j = 0; j < MT7996_RRO_WINDOW_MAX_SIZE; j++) { 988 addr->data = cpu_to_le32(val); 989 addr++; 990 } 991 992 if (is_mt7996(&dev->mt76) && 993 mt76_npu_device_active(&dev->mt76)) 994 mt76_npu_send_txrx_addr(&dev->mt76, 0, i, 995 dev->wed_rro.addr_elem[i].phy_addr, 996 0, 0); 997 998 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 999 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && 1000 mtk_wed_get_rx_capa(&dev->mt76.mmio.wed)) { 1001 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 1002 1003 wed->wlan.ind_cmd.addr_elem_phys[i] = 1004 dev->wed_rro.addr_elem[i].phy_addr; 1005 } 1006 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 1007 } 1008 1009 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) { 1010 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 1011 MT7996_RRO_MSDU_PG_SIZE_PER_CR, 1012 &dev->wed_rro.msdu_pg[i].phy_addr, 1013 GFP_KERNEL); 1014 if (!ptr) 1015 return -ENOMEM; 1016 1017 dev->wed_rro.msdu_pg[i].ptr = ptr; 1018 1019 memset(dev->wed_rro.msdu_pg[i].ptr, 0, 1020 MT7996_RRO_MSDU_PG_SIZE_PER_CR); 1021 } 1022 1023 if (!mtk_wed_device_active(&dev->mt76.mmio.wed) && 1024 dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) { 1025 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 1026 sizeof(*dev->wed_rro.emi_rings_cpu.ptr), 1027 &dev->wed_rro.emi_rings_cpu.phy_addr, 1028 GFP_KERNEL); 1029 if (!ptr) 1030 return -ENOMEM; 1031 1032 dev->wed_rro.emi_rings_cpu.ptr = ptr; 1033 1034 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 1035 sizeof(*dev->wed_rro.emi_rings_dma.ptr), 1036 &dev->wed_rro.emi_rings_dma.phy_addr, 1037 GFP_KERNEL); 1038 if (!ptr) 1039 return -ENOMEM; 1040 1041 dev->wed_rro.emi_rings_dma.ptr = ptr; 1042 } 1043 1044 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 1045 MT7996_RRO_WINDOW_MAX_LEN * sizeof(*addr), 1046 &dev->wed_rro.session.phy_addr, 1047 GFP_KERNEL); 1048 if (!ptr) 1049 return -ENOMEM; 1050 1051 dev->wed_rro.session.ptr = ptr; 1052 addr = dev->wed_rro.session.ptr; 1053 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) { 1054 addr->data = cpu_to_le32(val); 1055 addr++; 1056 } 1057 1058 if (is_mt7996(&dev->mt76) && mt76_npu_device_active(&dev->mt76)) 1059 mt76_npu_send_txrx_addr(&dev->mt76, 1, 0, 1060 dev->wed_rro.session.phy_addr, 0, 0); 1061 1062 mt7996_rro_hw_init(dev); 1063 1064 return mt7996_dma_rro_init(dev); 1065 } 1066 1067 static void mt7996_wed_rro_free(struct mt7996_dev *dev) 1068 { 1069 int i; 1070 1071 if (!mt7996_has_hwrro(dev)) 1072 return; 1073 1074 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { 1075 if (!dev->wed_rro.ba_bitmap[i].ptr) 1076 continue; 1077 1078 dmam_free_coherent(dev->mt76.dma_dev, 1079 MT7996_RRO_BA_BITMAP_CR_SIZE, 1080 dev->wed_rro.ba_bitmap[i].ptr, 1081 dev->wed_rro.ba_bitmap[i].phy_addr); 1082 } 1083 1084 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 1085 if (!dev->wed_rro.addr_elem[i].ptr) 1086 continue; 1087 1088 dmam_free_coherent(dev->mt76.dma_dev, 1089 MT7996_RRO_WINDOW_MAX_SIZE * 1090 sizeof(struct mt7996_wed_rro_addr), 1091 dev->wed_rro.addr_elem[i].ptr, 1092 dev->wed_rro.addr_elem[i].phy_addr); 1093 } 1094 1095 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) { 1096 if (!dev->wed_rro.msdu_pg[i].ptr) 1097 continue; 1098 1099 dmam_free_coherent(dev->mt76.dma_dev, 1100 MT7996_RRO_MSDU_PG_SIZE_PER_CR, 1101 dev->wed_rro.msdu_pg[i].ptr, 1102 dev->wed_rro.msdu_pg[i].phy_addr); 1103 } 1104 1105 if (dev->wed_rro.emi_rings_cpu.ptr) 1106 dmam_free_coherent(dev->mt76.dma_dev, 1107 sizeof(*dev->wed_rro.emi_rings_cpu.ptr), 1108 dev->wed_rro.emi_rings_cpu.ptr, 1109 dev->wed_rro.emi_rings_cpu.phy_addr); 1110 1111 if (dev->wed_rro.emi_rings_dma.ptr) 1112 dmam_free_coherent(dev->mt76.dma_dev, 1113 sizeof(*dev->wed_rro.emi_rings_dma.ptr), 1114 dev->wed_rro.emi_rings_dma.ptr, 1115 dev->wed_rro.emi_rings_dma.phy_addr); 1116 1117 if (!dev->wed_rro.session.ptr) 1118 return; 1119 1120 dmam_free_coherent(dev->mt76.dma_dev, 1121 MT7996_RRO_WINDOW_MAX_LEN * 1122 sizeof(struct mt7996_wed_rro_addr), 1123 dev->wed_rro.session.ptr, 1124 dev->wed_rro.session.phy_addr); 1125 } 1126 1127 static void mt7996_wed_rro_work(struct work_struct *work) 1128 { 1129 u32 val = FIELD_PREP(WED_RRO_ADDR_SIGNATURE_MASK, 0xff); 1130 struct mt7996_dev *dev; 1131 LIST_HEAD(list); 1132 1133 dev = (struct mt7996_dev *)container_of(work, struct mt7996_dev, 1134 wed_rro.work); 1135 1136 spin_lock_bh(&dev->wed_rro.lock); 1137 list_splice_init(&dev->wed_rro.poll_list, &list); 1138 spin_unlock_bh(&dev->wed_rro.lock); 1139 1140 while (!list_empty(&list)) { 1141 struct mt7996_wed_rro_session_id *e; 1142 int i; 1143 1144 e = list_first_entry(&list, struct mt7996_wed_rro_session_id, 1145 list); 1146 list_del_init(&e->list); 1147 1148 if (mt76_npu_device_active(&dev->mt76)) { 1149 if (is_mt7996(&dev->mt76)) 1150 mt76_npu_send_txrx_addr(&dev->mt76, 3, e->id, 1151 0, 0, 0); 1152 goto reset_session; 1153 } 1154 1155 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) { 1156 void *ptr = dev->wed_rro.session.ptr; 1157 struct mt7996_wed_rro_addr *elem; 1158 u32 idx, elem_id = i; 1159 1160 if (e->id == MT7996_RRO_MAX_SESSION) 1161 goto reset; 1162 1163 idx = e->id / MT7996_RRO_BA_BITMAP_SESSION_SIZE; 1164 if (idx >= ARRAY_SIZE(dev->wed_rro.addr_elem)) 1165 goto out; 1166 1167 ptr = dev->wed_rro.addr_elem[idx].ptr; 1168 elem_id += 1169 (e->id % MT7996_RRO_BA_BITMAP_SESSION_SIZE) * 1170 MT7996_RRO_WINDOW_MAX_LEN; 1171 reset: 1172 elem = ptr + elem_id * sizeof(*elem); 1173 elem->data |= cpu_to_le32(val); 1174 } 1175 reset_session: 1176 mt7996_mcu_wed_rro_reset_sessions(dev, e->id); 1177 out: 1178 kfree(e); 1179 } 1180 } 1181 1182 static int mt7996_variant_type_init(struct mt7996_dev *dev) 1183 { 1184 u32 val = mt76_rr(dev, MT_PAD_GPIO); 1185 u8 var_type; 1186 1187 switch (mt76_chip(&dev->mt76)) { 1188 case MT7996_DEVICE_ID: 1189 if (val & MT_PAD_GPIO_2ADIE_TBTC) 1190 var_type = MT7996_VAR_TYPE_233; 1191 else 1192 var_type = MT7996_VAR_TYPE_444; 1193 break; 1194 case MT7992_DEVICE_ID: 1195 if (val & MT_PAD_GPIO_ADIE_SINGLE) 1196 var_type = MT7992_VAR_TYPE_23; 1197 else if (u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992)) 1198 var_type = MT7992_VAR_TYPE_44; 1199 else 1200 var_type = MT7992_VAR_TYPE_24; 1201 break; 1202 case MT7990_DEVICE_ID: 1203 var_type = MT7990_VAR_TYPE_23; 1204 break; 1205 default: 1206 return -EINVAL; 1207 } 1208 1209 dev->var.type = var_type; 1210 return 0; 1211 } 1212 1213 static int mt7996_variant_fem_init(struct mt7996_dev *dev) 1214 { 1215 #define MT7976C_EFUSE_OFFSET 0x470 1216 u8 buf[MT7996_EEPROM_BLOCK_SIZE], idx, adie_idx, adie_comb; 1217 u32 regval, val = mt76_rr(dev, MT_PAD_GPIO); 1218 u16 adie_id, adie_ver; 1219 bool is_7976c; 1220 int ret; 1221 1222 if (is_mt7992(&dev->mt76)) { 1223 adie_idx = (val & MT_PAD_GPIO_ADIE_SINGLE) ? 0 : 1; 1224 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992); 1225 } else { 1226 adie_idx = 0; 1227 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB); 1228 } 1229 1230 ret = mt7996_mcu_rf_regval(dev, MT_ADIE_CHIP_ID(adie_idx), ®val, false); 1231 if (ret) 1232 return ret; 1233 1234 ret = mt7996_mcu_get_eeprom(dev, MT7976C_EFUSE_OFFSET, buf, sizeof(buf), 1235 EEPROM_MODE_EFUSE); 1236 if (ret && ret != -EINVAL) 1237 return ret; 1238 1239 adie_ver = u32_get_bits(regval, MT_ADIE_VERSION_MASK); 1240 idx = MT7976C_EFUSE_OFFSET % MT7996_EEPROM_BLOCK_SIZE; 1241 is_7976c = adie_ver == 0x8a10 || adie_ver == 0x8b00 || 1242 adie_ver == 0x8c10 || buf[idx] == 0xc; 1243 1244 adie_id = u32_get_bits(regval, MT_ADIE_CHIP_ID_MASK); 1245 if (adie_id == 0x7975 || adie_id == 0x7979 || 1246 (adie_id == 0x7976 && is_7976c)) 1247 dev->var.fem = MT7996_FEM_INT; 1248 else if (adie_id == 0x7977 && adie_comb == 1) 1249 dev->var.fem = MT7996_FEM_MIX; 1250 else 1251 dev->var.fem = MT7996_FEM_EXT; 1252 1253 return 0; 1254 } 1255 1256 static int mt7996_init_hardware(struct mt7996_dev *dev) 1257 { 1258 int ret, idx; 1259 1260 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 1261 if (is_mt7992(&dev->mt76)) { 1262 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND0), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0); 1263 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND1), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0); 1264 } 1265 1266 INIT_WORK(&dev->init_work, mt7996_init_work); 1267 INIT_WORK(&dev->wed_rro.work, mt7996_wed_rro_work); 1268 INIT_LIST_HEAD(&dev->wed_rro.poll_list); 1269 spin_lock_init(&dev->wed_rro.lock); 1270 1271 ret = mt7996_variant_type_init(dev); 1272 if (ret) 1273 return ret; 1274 1275 ret = mt7996_dma_init(dev); 1276 if (ret) 1277 return ret; 1278 1279 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 1280 1281 ret = mt7996_mcu_init(dev); 1282 if (ret) 1283 return ret; 1284 1285 ret = mt7996_wed_rro_init(dev); 1286 if (ret) 1287 return ret; 1288 1289 ret = mt7996_variant_fem_init(dev); 1290 if (ret) 1291 return ret; 1292 1293 ret = mt7996_eeprom_init(dev); 1294 if (ret < 0) 1295 return ret; 1296 1297 /* Beacon and mgmt frames should occupy wcid 0 */ 1298 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7996_WTBL_STA); 1299 if (idx) 1300 return -ENOSPC; 1301 1302 dev->mt76.global_wcid.idx = idx; 1303 dev->mt76.global_wcid.hw_key_idx = -1; 1304 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 1305 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 1306 1307 return 0; 1308 } 1309 1310 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy) 1311 { 1312 int sts; 1313 u32 *cap; 1314 1315 if (!phy->mt76->cap.has_5ghz) 1316 return; 1317 1318 sts = hweight16(phy->mt76->chainmask); 1319 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 1320 1321 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 1322 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE; 1323 1324 if (is_mt7992(phy->mt76->dev)) 1325 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 4); 1326 else 1327 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 3); 1328 1329 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 1330 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 1331 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 1332 1333 if (sts < 2) 1334 return; 1335 1336 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 1337 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 1338 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, sts - 1); 1339 } 1340 1341 static void 1342 mt7996_set_stream_he_txbf_caps(struct mt7996_phy *phy, 1343 struct ieee80211_sta_he_cap *he_cap, int vif, 1344 enum nl80211_band band) 1345 { 1346 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 1347 int sts = hweight16(phy->mt76->chainmask); 1348 bool non_2g = band != NL80211_BAND_2GHZ; 1349 u8 c; 1350 1351 #ifdef CONFIG_MAC80211_MESH 1352 if (vif == NL80211_IFTYPE_MESH_POINT) 1353 return; 1354 #endif 1355 1356 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 1357 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 1358 1359 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK | 1360 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 1361 elem->phy_cap_info[5] &= ~c; 1362 1363 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 1364 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 1365 elem->phy_cap_info[6] &= ~c; 1366 1367 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 1368 1369 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 1370 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO; 1371 elem->phy_cap_info[2] |= c; 1372 1373 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE; 1374 1375 if (is_mt7992(phy->mt76->dev)) 1376 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_5 | 1377 (IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_5 * non_2g); 1378 else 1379 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 | 1380 (IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4 * non_2g); 1381 1382 elem->phy_cap_info[4] |= c; 1383 1384 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 1385 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 1386 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 1387 1388 if (vif == NL80211_IFTYPE_STATION) 1389 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 1390 1391 elem->phy_cap_info[6] |= c; 1392 1393 if (sts < 2) 1394 return; 1395 1396 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 1397 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 1398 1399 if (!(vif == NL80211_IFTYPE_AP || vif == NL80211_IFTYPE_STATION)) 1400 return; 1401 1402 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 1403 1404 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 1405 sts - 1) | 1406 (FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 1407 sts - 1) * non_2g); 1408 1409 elem->phy_cap_info[5] |= c; 1410 1411 if (vif != NL80211_IFTYPE_AP) 1412 return; 1413 1414 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 1415 1416 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 1417 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 1418 elem->phy_cap_info[6] |= c; 1419 1420 c = 0; 1421 if (non_2g) 1422 c |= IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 1423 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 1424 elem->phy_cap_info[7] |= c; 1425 } 1426 1427 static void 1428 mt7996_init_he_caps(struct mt7996_phy *phy, enum nl80211_band band, 1429 struct ieee80211_sband_iftype_data *data, 1430 enum nl80211_iftype iftype) 1431 { 1432 struct ieee80211_sta_he_cap *he_cap = &data->he_cap; 1433 struct ieee80211_he_cap_elem *he_cap_elem = &he_cap->he_cap_elem; 1434 struct ieee80211_he_mcs_nss_supp *he_mcs = &he_cap->he_mcs_nss_supp; 1435 int i, nss = hweight8(phy->mt76->antenna_mask); 1436 u16 mcs_map = 0; 1437 1438 for (i = 0; i < 8; i++) { 1439 if (i < nss) 1440 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 1441 else 1442 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 1443 } 1444 1445 he_cap->has_he = true; 1446 1447 he_cap_elem->mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 1448 he_cap_elem->mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 1449 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 1450 he_cap_elem->mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 1451 1452 if (band == NL80211_BAND_2GHZ) 1453 he_cap_elem->phy_cap_info[0] = 1454 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 1455 else 1456 he_cap_elem->phy_cap_info[0] = 1457 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 1458 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 1459 1460 he_cap_elem->phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 1461 he_cap_elem->phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 1462 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 1463 1464 he_cap_elem->phy_cap_info[7] = 1465 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 1466 1467 switch (iftype) { 1468 case NL80211_IFTYPE_AP: 1469 he_cap_elem->mac_cap_info[0] |= IEEE80211_HE_MAC_CAP0_TWT_RES; 1470 he_cap_elem->mac_cap_info[2] |= IEEE80211_HE_MAC_CAP2_BSR; 1471 he_cap_elem->mac_cap_info[4] |= IEEE80211_HE_MAC_CAP4_BQR; 1472 he_cap_elem->mac_cap_info[5] |= 1473 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 1474 he_cap_elem->phy_cap_info[3] |= 1475 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1476 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1477 he_cap_elem->phy_cap_info[6] |= 1478 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1479 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1480 he_cap_elem->phy_cap_info[9] |= 1481 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1482 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 1483 break; 1484 case NL80211_IFTYPE_STATION: 1485 he_cap_elem->mac_cap_info[1] |= 1486 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 1487 1488 if (band == NL80211_BAND_2GHZ) 1489 he_cap_elem->phy_cap_info[0] |= 1490 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 1491 else 1492 he_cap_elem->phy_cap_info[0] |= 1493 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 1494 1495 he_cap_elem->phy_cap_info[1] |= 1496 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 1497 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 1498 he_cap_elem->phy_cap_info[3] |= 1499 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1500 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1501 he_cap_elem->phy_cap_info[6] |= 1502 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 1503 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1504 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1505 he_cap_elem->phy_cap_info[7] |= 1506 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP; 1507 he_cap_elem->phy_cap_info[8] |= 1508 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 1509 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 1510 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 1511 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 1512 he_cap_elem->phy_cap_info[9] |= 1513 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 1514 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 1515 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1516 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 1517 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 1518 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 1519 break; 1520 default: 1521 break; 1522 } 1523 1524 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 1525 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 1526 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map); 1527 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map); 1528 1529 mt7996_set_stream_he_txbf_caps(phy, he_cap, iftype, band); 1530 1531 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 1532 if (he_cap_elem->phy_cap_info[6] & 1533 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 1534 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss, band); 1535 } else { 1536 he_cap_elem->phy_cap_info[9] |= 1537 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 1538 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 1539 } 1540 1541 if (band == NL80211_BAND_6GHZ) { 1542 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 1543 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 1544 1545 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_0_5, 1546 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 1547 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 1548 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 1549 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 1550 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 1551 1552 data->he_6ghz_capa.capa = cpu_to_le16(cap); 1553 } 1554 } 1555 1556 static void 1557 mt7996_init_eht_caps(struct mt7996_phy *phy, enum nl80211_band band, 1558 struct ieee80211_sband_iftype_data *data, 1559 enum nl80211_iftype iftype) 1560 { 1561 struct ieee80211_sta_eht_cap *eht_cap = &data->eht_cap; 1562 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem = &eht_cap->eht_cap_elem; 1563 struct ieee80211_eht_mcs_nss_supp *eht_nss = &eht_cap->eht_mcs_nss_supp; 1564 enum nl80211_chan_width width = phy->mt76->chandef.width; 1565 int nss = hweight8(phy->mt76->antenna_mask); 1566 int sts = hweight16(phy->mt76->chainmask); 1567 u8 val; 1568 1569 if (!phy->dev->has_eht) 1570 return; 1571 1572 eht_cap->has_eht = true; 1573 1574 eht_cap_elem->mac_cap_info[0] = 1575 IEEE80211_EHT_MAC_CAP0_OM_CONTROL | 1576 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454, 1577 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 1578 1579 eht_cap_elem->mac_cap_info[1] |= 1580 IEEE80211_EHT_MAC_CAP1_MAX_AMPDU_LEN_MASK; 1581 1582 eht_cap_elem->phy_cap_info[0] = 1583 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 1584 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMER | 1585 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 1586 1587 /* Set the maximum capability regardless of the antenna configuration. */ 1588 val = is_mt7992(phy->mt76->dev) ? 4 : 3; 1589 eht_cap_elem->phy_cap_info[0] |= 1590 u8_encode_bits(u8_get_bits(val, BIT(0)), 1591 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 1592 1593 eht_cap_elem->phy_cap_info[1] = 1594 u8_encode_bits(u8_get_bits(val, GENMASK(2, 1)), 1595 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK); 1596 1597 eht_cap_elem->phy_cap_info[2] = 1598 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_80MHZ_MASK); 1599 1600 if (band != NL80211_BAND_2GHZ) { 1601 eht_cap_elem->phy_cap_info[1] |= 1602 u8_encode_bits(val, 1603 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK); 1604 1605 eht_cap_elem->phy_cap_info[2] |= 1606 u8_encode_bits(sts - 1, 1607 IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_160MHZ_MASK); 1608 } 1609 1610 if (band == NL80211_BAND_6GHZ) { 1611 eht_cap_elem->phy_cap_info[0] |= 1612 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 1613 1614 eht_cap_elem->phy_cap_info[1] |= 1615 u8_encode_bits(val, 1616 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 1617 1618 eht_cap_elem->phy_cap_info[2] |= 1619 u8_encode_bits(sts - 1, 1620 IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_320MHZ_MASK); 1621 } 1622 1623 eht_cap_elem->phy_cap_info[3] = 1624 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK | 1625 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK | 1626 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 1627 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK; 1628 1629 eht_cap_elem->phy_cap_info[4] = 1630 IEEE80211_EHT_PHY_CAP4_EHT_MU_PPDU_4_EHT_LTF_08_GI | 1631 u8_encode_bits(min_t(int, sts - 1, 2), 1632 IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 1633 1634 eht_cap_elem->phy_cap_info[5] = 1635 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US, 1636 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK) | 1637 u8_encode_bits(u8_get_bits(1, GENMASK(1, 0)), 1638 IEEE80211_EHT_PHY_CAP5_MAX_NUM_SUPP_EHT_LTF_MASK); 1639 1640 val = width == NL80211_CHAN_WIDTH_320 ? 0xf : 1641 width == NL80211_CHAN_WIDTH_160 ? 0x7 : 1642 width == NL80211_CHAN_WIDTH_80 ? 0x3 : 0x1; 1643 eht_cap_elem->phy_cap_info[6] = 1644 u8_encode_bits(val, IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK); 1645 1646 val = u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_RX) | 1647 u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_TX); 1648 #define SET_EHT_MAX_NSS(_bw, _val) do { \ 1649 eht_nss->bw._##_bw.rx_tx_mcs9_max_nss = _val; \ 1650 eht_nss->bw._##_bw.rx_tx_mcs11_max_nss = _val; \ 1651 eht_nss->bw._##_bw.rx_tx_mcs13_max_nss = _val; \ 1652 } while (0) 1653 1654 SET_EHT_MAX_NSS(80, val); 1655 SET_EHT_MAX_NSS(160, val); 1656 if (band == NL80211_BAND_6GHZ) 1657 SET_EHT_MAX_NSS(320, val); 1658 #undef SET_EHT_MAX_NSS 1659 1660 if (iftype != NL80211_IFTYPE_AP) 1661 return; 1662 1663 eht_cap_elem->phy_cap_info[3] |= 1664 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 1665 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK; 1666 1667 eht_cap_elem->phy_cap_info[7] = 1668 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_80MHZ | 1669 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_80MHZ; 1670 1671 if (band == NL80211_BAND_2GHZ) 1672 return; 1673 1674 eht_cap_elem->phy_cap_info[7] |= 1675 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_160MHZ | 1676 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_160MHZ; 1677 1678 if (band != NL80211_BAND_6GHZ) 1679 return; 1680 1681 eht_cap_elem->phy_cap_info[7] |= 1682 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_320MHZ | 1683 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_320MHZ; 1684 } 1685 1686 static void 1687 __mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy, 1688 struct ieee80211_supported_band *sband, 1689 enum nl80211_band band) 1690 { 1691 struct ieee80211_sband_iftype_data *data = phy->iftype[band]; 1692 int i, n = 0; 1693 1694 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 1695 switch (i) { 1696 case NL80211_IFTYPE_STATION: 1697 case NL80211_IFTYPE_AP: 1698 #ifdef CONFIG_MAC80211_MESH 1699 case NL80211_IFTYPE_MESH_POINT: 1700 #endif 1701 break; 1702 default: 1703 continue; 1704 } 1705 1706 data[n].types_mask = BIT(i); 1707 mt7996_init_he_caps(phy, band, &data[n], i); 1708 mt7996_init_eht_caps(phy, band, &data[n], i); 1709 1710 n++; 1711 } 1712 1713 _ieee80211_set_sband_iftype_data(sband, data, n); 1714 } 1715 1716 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy) 1717 { 1718 if (phy->mt76->cap.has_2ghz) 1719 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_2g.sband, 1720 NL80211_BAND_2GHZ); 1721 1722 if (phy->mt76->cap.has_5ghz) 1723 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_5g.sband, 1724 NL80211_BAND_5GHZ); 1725 1726 if (phy->mt76->cap.has_6ghz) 1727 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_6g.sband, 1728 NL80211_BAND_6GHZ); 1729 } 1730 1731 int mt7996_register_device(struct mt7996_dev *dev) 1732 { 1733 struct ieee80211_hw *hw = mt76_hw(dev); 1734 struct mt7996_phy *phy; 1735 int ret; 1736 1737 dev->phy.dev = dev; 1738 dev->phy.mt76 = &dev->mt76.phy; 1739 dev->mt76.phy.priv = &dev->phy; 1740 INIT_WORK(&dev->rc_work, mt7996_mac_sta_rc_work); 1741 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7996_mac_work); 1742 INIT_LIST_HEAD(&dev->sta_rc_list); 1743 INIT_LIST_HEAD(&dev->twt_list); 1744 1745 init_waitqueue_head(&dev->reset_wait); 1746 INIT_WORK(&dev->reset_work, mt7996_mac_reset_work); 1747 INIT_WORK(&dev->dump_work, mt7996_mac_dump_work); 1748 mutex_init(&dev->dump_mutex); 1749 1750 ret = mt7996_init_hardware(dev); 1751 if (ret) 1752 return ret; 1753 1754 mt7996_init_wiphy(hw, &dev->mt76.mmio.wed); 1755 1756 ret = mt7996_register_phy(dev, MT_BAND1); 1757 if (ret) 1758 return ret; 1759 1760 ret = mt7996_register_phy(dev, MT_BAND2); 1761 if (ret) 1762 return ret; 1763 1764 ret = mt7996_npu_hw_init(dev); 1765 if (ret) 1766 return ret; 1767 1768 mt7996_dma_rro_start(dev); 1769 1770 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 1771 ARRAY_SIZE(mt76_rates)); 1772 if (ret) 1773 return ret; 1774 1775 mt7996_for_each_phy(dev, phy) 1776 mt7996_thermal_init(phy); 1777 1778 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 1779 1780 dev->recovery.hw_init_done = true; 1781 1782 ret = mt7996_init_debugfs(dev); 1783 if (ret) 1784 goto error; 1785 1786 ret = mt7996_coredump_register(dev); 1787 if (ret) 1788 goto error; 1789 1790 return 0; 1791 1792 error: 1793 cancel_work_sync(&dev->init_work); 1794 1795 return ret; 1796 } 1797 1798 void mt7996_unregister_device(struct mt7996_dev *dev) 1799 { 1800 cancel_work_sync(&dev->dump_work); 1801 cancel_work_sync(&dev->wed_rro.work); 1802 mt7996_unregister_phy(mt7996_phy3(dev)); 1803 mt7996_unregister_phy(mt7996_phy2(dev)); 1804 mt7996_unregister_thermal(&dev->phy); 1805 mt7996_coredump_unregister(dev); 1806 mt76_unregister_device(&dev->mt76); 1807 mt7996_wed_rro_free(dev); 1808 mt7996_mcu_exit(dev); 1809 mt7996_tx_token_put(dev); 1810 mt7996_dma_cleanup(dev); 1811 if (mt7996_has_hwrro(dev) && 1812 !mtk_wed_device_active(&dev->mt76.mmio.wed)) 1813 mt7996_rro_msdu_page_map_free(dev); 1814 tasklet_disable(&dev->mt76.irq_tasklet); 1815 1816 mt76_free_device(&dev->mt76); 1817 } 1818