1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (C) 2022 MediaTek Inc.
4 */
5
6 #include <linux/etherdevice.h>
7 #include <linux/of.h>
8 #include <linux/hwmon.h>
9 #include <linux/hwmon-sysfs.h>
10 #include <linux/thermal.h>
11 #include "mt7996.h"
12 #include "mac.h"
13 #include "mcu.h"
14 #include "coredump.h"
15 #include "eeprom.h"
16
17 static const struct ieee80211_iface_limit if_limits_global = {
18 .max = MT7996_MAX_INTERFACES * MT7996_MAX_RADIOS,
19 .types = BIT(NL80211_IFTYPE_STATION)
20 | BIT(NL80211_IFTYPE_ADHOC)
21 | BIT(NL80211_IFTYPE_AP)
22 #ifdef CONFIG_MAC80211_MESH
23 | BIT(NL80211_IFTYPE_MESH_POINT)
24 #endif
25 };
26
27 static const struct ieee80211_iface_combination if_comb_global = {
28 .limits = &if_limits_global,
29 .n_limits = 1,
30 .max_interfaces = MT7996_MAX_INTERFACES * MT7996_MAX_RADIOS,
31 .num_different_channels = MT7996_MAX_RADIOS,
32 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
33 BIT(NL80211_CHAN_WIDTH_20) |
34 BIT(NL80211_CHAN_WIDTH_40) |
35 BIT(NL80211_CHAN_WIDTH_80) |
36 BIT(NL80211_CHAN_WIDTH_160),
37 };
38
39 static const struct ieee80211_iface_limit if_limits[] = {
40 {
41 .max = 16,
42 .types = BIT(NL80211_IFTYPE_AP)
43 #ifdef CONFIG_MAC80211_MESH
44 | BIT(NL80211_IFTYPE_MESH_POINT)
45 #endif
46 }, {
47 .max = MT7996_MAX_INTERFACES,
48 .types = BIT(NL80211_IFTYPE_STATION)
49 }
50 };
51
52 static const struct ieee80211_iface_combination if_comb = {
53 .limits = if_limits,
54 .n_limits = ARRAY_SIZE(if_limits),
55 .max_interfaces = MT7996_MAX_INTERFACES,
56 .num_different_channels = 1,
57 .beacon_int_infra_match = true,
58 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
59 BIT(NL80211_CHAN_WIDTH_20) |
60 BIT(NL80211_CHAN_WIDTH_40) |
61 BIT(NL80211_CHAN_WIDTH_80) |
62 BIT(NL80211_CHAN_WIDTH_160),
63 .beacon_int_min_gcd = 100,
64 };
65
mt7996_thermal_temp_show(struct device * dev,struct device_attribute * attr,char * buf)66 static ssize_t mt7996_thermal_temp_show(struct device *dev,
67 struct device_attribute *attr,
68 char *buf)
69 {
70 struct mt7996_phy *phy = dev_get_drvdata(dev);
71 int i = to_sensor_dev_attr(attr)->index;
72 int temperature;
73
74 switch (i) {
75 case 0:
76 temperature = mt7996_mcu_get_temperature(phy);
77 if (temperature < 0)
78 return temperature;
79 /* display in millidegree celcius */
80 return sprintf(buf, "%u\n", temperature * 1000);
81 case 1:
82 case 2:
83 return sprintf(buf, "%u\n",
84 phy->throttle_temp[i - 1] * 1000);
85 case 3:
86 return sprintf(buf, "%hhu\n", phy->throttle_state);
87 default:
88 return -EINVAL;
89 }
90 }
91
mt7996_thermal_temp_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)92 static ssize_t mt7996_thermal_temp_store(struct device *dev,
93 struct device_attribute *attr,
94 const char *buf, size_t count)
95 {
96 struct mt7996_phy *phy = dev_get_drvdata(dev);
97 int ret, i = to_sensor_dev_attr(attr)->index;
98 long val;
99
100 ret = kstrtol(buf, 10, &val);
101 if (ret < 0)
102 return ret;
103
104 mutex_lock(&phy->dev->mt76.mutex);
105 val = DIV_ROUND_CLOSEST(clamp_val(val, 40 * 1000, 130 * 1000), 1000);
106
107 /* add a safety margin ~10 */
108 if ((i - 1 == MT7996_CRIT_TEMP_IDX &&
109 val > phy->throttle_temp[MT7996_MAX_TEMP_IDX] - 10) ||
110 (i - 1 == MT7996_MAX_TEMP_IDX &&
111 val - 10 < phy->throttle_temp[MT7996_CRIT_TEMP_IDX])) {
112 dev_err(phy->dev->mt76.dev,
113 "temp1_max shall be 10 degrees higher than temp1_crit.");
114 mutex_unlock(&phy->dev->mt76.mutex);
115 return -EINVAL;
116 }
117
118 phy->throttle_temp[i - 1] = val;
119 mutex_unlock(&phy->dev->mt76.mutex);
120
121 ret = mt7996_mcu_set_thermal_protect(phy, true);
122 if (ret)
123 return ret;
124
125 return count;
126 }
127
128 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7996_thermal_temp, 0);
129 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7996_thermal_temp, 1);
130 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7996_thermal_temp, 2);
131 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7996_thermal_temp, 3);
132
133 static struct attribute *mt7996_hwmon_attrs[] = {
134 &sensor_dev_attr_temp1_input.dev_attr.attr,
135 &sensor_dev_attr_temp1_crit.dev_attr.attr,
136 &sensor_dev_attr_temp1_max.dev_attr.attr,
137 &sensor_dev_attr_throttle1.dev_attr.attr,
138 NULL,
139 };
140 ATTRIBUTE_GROUPS(mt7996_hwmon);
141
142 static int
mt7996_thermal_get_max_throttle_state(struct thermal_cooling_device * cdev,unsigned long * state)143 mt7996_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev,
144 unsigned long *state)
145 {
146 *state = MT7996_CDEV_THROTTLE_MAX;
147
148 return 0;
149 }
150
151 static int
mt7996_thermal_get_cur_throttle_state(struct thermal_cooling_device * cdev,unsigned long * state)152 mt7996_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev,
153 unsigned long *state)
154 {
155 struct mt7996_phy *phy = cdev->devdata;
156
157 *state = phy->cdev_state;
158
159 return 0;
160 }
161
162 static int
mt7996_thermal_set_cur_throttle_state(struct thermal_cooling_device * cdev,unsigned long state)163 mt7996_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev,
164 unsigned long state)
165 {
166 struct mt7996_phy *phy = cdev->devdata;
167 u8 throttling = MT7996_THERMAL_THROTTLE_MAX - state;
168 int ret;
169
170 if (state > MT7996_CDEV_THROTTLE_MAX) {
171 dev_err(phy->dev->mt76.dev,
172 "please specify a valid throttling state\n");
173 return -EINVAL;
174 }
175
176 if (state == phy->cdev_state)
177 return 0;
178
179 /* cooling_device convention: 0 = no cooling, more = more cooling
180 * mcu convention: 1 = max cooling, more = less cooling
181 */
182 ret = mt7996_mcu_set_thermal_throttling(phy, throttling);
183 if (ret)
184 return ret;
185
186 phy->cdev_state = state;
187
188 return 0;
189 }
190
191 static const struct thermal_cooling_device_ops mt7996_thermal_ops = {
192 .get_max_state = mt7996_thermal_get_max_throttle_state,
193 .get_cur_state = mt7996_thermal_get_cur_throttle_state,
194 .set_cur_state = mt7996_thermal_set_cur_throttle_state,
195 };
196
mt7996_unregister_thermal(struct mt7996_phy * phy)197 static void mt7996_unregister_thermal(struct mt7996_phy *phy)
198 {
199 struct wiphy *wiphy = phy->mt76->hw->wiphy;
200 char name[sizeof("cooling_deviceXXX")];
201
202 if (!phy->cdev)
203 return;
204
205 snprintf(name, sizeof(name), "cooling_device%d", phy->mt76->band_idx);
206 sysfs_remove_link(&wiphy->dev.kobj, name);
207 thermal_cooling_device_unregister(phy->cdev);
208 }
209
mt7996_thermal_init(struct mt7996_phy * phy)210 static int mt7996_thermal_init(struct mt7996_phy *phy)
211 {
212 struct wiphy *wiphy = phy->mt76->hw->wiphy;
213 char cname[sizeof("cooling_deviceXXX")];
214 struct thermal_cooling_device *cdev;
215 struct device *hwmon;
216 const char *name;
217
218 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7996_%s.%d",
219 wiphy_name(wiphy), phy->mt76->band_idx);
220 if (!name)
221 return -ENOMEM;
222
223 snprintf(cname, sizeof(cname), "cooling_device%d", phy->mt76->band_idx);
224
225 cdev = thermal_cooling_device_register(name, phy, &mt7996_thermal_ops);
226 if (!IS_ERR(cdev)) {
227 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj,
228 cname) < 0)
229 thermal_cooling_device_unregister(cdev);
230 else
231 phy->cdev = cdev;
232 }
233
234 /* initialize critical/maximum high temperature */
235 phy->throttle_temp[MT7996_CRIT_TEMP_IDX] = MT7996_CRIT_TEMP;
236 phy->throttle_temp[MT7996_MAX_TEMP_IDX] = MT7996_MAX_TEMP;
237
238 if (!IS_REACHABLE(CONFIG_HWMON))
239 return 0;
240
241 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy,
242 mt7996_hwmon_groups);
243
244 if (IS_ERR(hwmon))
245 return PTR_ERR(hwmon);
246
247 return 0;
248 }
249
mt7996_led_set_config(struct led_classdev * led_cdev,u8 delay_on,u8 delay_off)250 static void mt7996_led_set_config(struct led_classdev *led_cdev,
251 u8 delay_on, u8 delay_off)
252 {
253 struct mt7996_dev *dev;
254 struct mt76_phy *mphy;
255 u32 val;
256
257 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev);
258 dev = container_of(mphy->dev, struct mt7996_dev, mt76);
259
260 /* select TX blink mode, 2: only data frames */
261 mt76_rmw_field(dev, MT_TMAC_TCR0(mphy->band_idx), MT_TMAC_TCR0_TX_BLINK, 2);
262
263 /* enable LED */
264 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1);
265
266 /* set LED Tx blink on/off time */
267 val = FIELD_PREP(MT_LED_TX_BLINK_ON_MASK, delay_on) |
268 FIELD_PREP(MT_LED_TX_BLINK_OFF_MASK, delay_off);
269 mt76_wr(dev, MT_LED_TX_BLINK(mphy->band_idx), val);
270
271 /* turn LED off */
272 if (delay_off == 0xff && delay_on == 0x0) {
273 val = MT_LED_CTRL_POLARITY | MT_LED_CTRL_KICK;
274 } else {
275 /* control LED */
276 val = MT_LED_CTRL_BLINK_MODE | MT_LED_CTRL_KICK;
277 if (mphy->band_idx == MT_BAND1)
278 val |= MT_LED_CTRL_BLINK_BAND_SEL;
279 }
280
281 if (mphy->leds.al)
282 val |= MT_LED_CTRL_POLARITY;
283
284 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val);
285 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK);
286 }
287
mt7996_led_set_blink(struct led_classdev * led_cdev,unsigned long * delay_on,unsigned long * delay_off)288 static int mt7996_led_set_blink(struct led_classdev *led_cdev,
289 unsigned long *delay_on,
290 unsigned long *delay_off)
291 {
292 u16 delta_on = 0, delta_off = 0;
293
294 #define HW_TICK 10
295 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK)
296
297 if (*delay_on)
298 delta_on = TO_HW_TICK(*delay_on);
299 if (*delay_off)
300 delta_off = TO_HW_TICK(*delay_off);
301
302 mt7996_led_set_config(led_cdev, delta_on, delta_off);
303
304 return 0;
305 }
306
mt7996_led_set_brightness(struct led_classdev * led_cdev,enum led_brightness brightness)307 static void mt7996_led_set_brightness(struct led_classdev *led_cdev,
308 enum led_brightness brightness)
309 {
310 if (!brightness)
311 mt7996_led_set_config(led_cdev, 0, 0xff);
312 else
313 mt7996_led_set_config(led_cdev, 0xff, 0);
314 }
315
__mt7996_init_txpower(struct mt7996_phy * phy,struct ieee80211_supported_band * sband)316 static void __mt7996_init_txpower(struct mt7996_phy *phy,
317 struct ieee80211_supported_band *sband)
318 {
319 struct mt7996_dev *dev = phy->dev;
320 int i, n_chains = hweight16(phy->mt76->chainmask);
321 int path_delta = mt76_tx_power_path_delta(n_chains);
322 int pwr_delta = mt7996_eeprom_get_power_delta(dev, sband->band);
323 struct mt76_power_limits limits;
324
325 for (i = 0; i < sband->n_channels; i++) {
326 struct ieee80211_channel *chan = &sband->channels[i];
327 int target_power = mt7996_eeprom_get_target_power(dev, chan);
328
329 target_power += pwr_delta;
330 target_power = mt76_get_rate_power_limits(phy->mt76, chan,
331 &limits,
332 target_power);
333 target_power += path_delta;
334 target_power = DIV_ROUND_UP(target_power, 2);
335 chan->max_power = min_t(int, chan->max_reg_power,
336 target_power);
337 chan->orig_mpwr = target_power;
338 }
339 }
340
mt7996_init_txpower(struct mt7996_phy * phy)341 void mt7996_init_txpower(struct mt7996_phy *phy)
342 {
343 if (!phy)
344 return;
345
346 if (phy->mt76->cap.has_2ghz)
347 __mt7996_init_txpower(phy, &phy->mt76->sband_2g.sband);
348 if (phy->mt76->cap.has_5ghz)
349 __mt7996_init_txpower(phy, &phy->mt76->sband_5g.sband);
350 if (phy->mt76->cap.has_6ghz)
351 __mt7996_init_txpower(phy, &phy->mt76->sband_6g.sband);
352 }
353
354 static void
mt7996_regd_notifier(struct wiphy * wiphy,struct regulatory_request * request)355 mt7996_regd_notifier(struct wiphy *wiphy,
356 struct regulatory_request *request)
357 {
358 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
359 struct mt7996_dev *dev = mt7996_hw_dev(hw);
360 struct mt7996_phy *phy;
361
362 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2));
363 dev->mt76.region = request->dfs_region;
364
365 mt7996_for_each_phy(dev, phy) {
366 if (dev->mt76.region == NL80211_DFS_UNSET)
367 mt7996_mcu_rdd_background_enable(phy, NULL);
368
369 mt7996_init_txpower(phy);
370 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN;
371 mt7996_dfs_init_radar_detector(phy);
372 }
373 }
374
375 static void
mt7996_init_wiphy_band(struct ieee80211_hw * hw,struct mt7996_phy * phy)376 mt7996_init_wiphy_band(struct ieee80211_hw *hw, struct mt7996_phy *phy)
377 {
378 struct mt7996_dev *dev = phy->dev;
379 struct wiphy *wiphy = hw->wiphy;
380 int n_radios = hw->wiphy->n_radio;
381 struct wiphy_radio_freq_range *freq = &dev->radio_freqs[n_radios];
382 struct wiphy_radio *radio = &dev->radios[n_radios];
383
384 phy->slottime = 9;
385 phy->beacon_rate = -1;
386
387 if (phy->mt76->cap.has_2ghz) {
388 phy->mt76->sband_2g.sband.ht_cap.cap |=
389 IEEE80211_HT_CAP_LDPC_CODING |
390 IEEE80211_HT_CAP_MAX_AMSDU;
391 phy->mt76->sband_2g.sband.ht_cap.ampdu_density =
392 IEEE80211_HT_MPDU_DENSITY_2;
393 freq->start_freq = 2400000;
394 freq->end_freq = 2500000;
395 } else if (phy->mt76->cap.has_5ghz) {
396 phy->mt76->sband_5g.sband.ht_cap.cap |=
397 IEEE80211_HT_CAP_LDPC_CODING |
398 IEEE80211_HT_CAP_MAX_AMSDU;
399
400 phy->mt76->sband_5g.sband.vht_cap.cap |=
401 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
402 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
403 IEEE80211_VHT_CAP_SHORT_GI_160 |
404 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ;
405 phy->mt76->sband_5g.sband.ht_cap.ampdu_density =
406 IEEE80211_HT_MPDU_DENSITY_1;
407
408 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW);
409 freq->start_freq = 5000000;
410 freq->end_freq = 5900000;
411 } else if (phy->mt76->cap.has_6ghz) {
412 freq->start_freq = 5900000;
413 freq->end_freq = 7200000;
414 } else {
415 return;
416 }
417
418 dev->radio_phy[n_radios] = phy;
419 radio->freq_range = freq;
420 radio->n_freq_range = 1;
421 radio->iface_combinations = &if_comb;
422 radio->n_iface_combinations = 1;
423 hw->wiphy->n_radio++;
424
425 wiphy->available_antennas_rx |= phy->mt76->chainmask;
426 wiphy->available_antennas_tx |= phy->mt76->chainmask;
427
428 mt76_set_stream_caps(phy->mt76, true);
429 mt7996_set_stream_vht_txbf_caps(phy);
430 mt7996_set_stream_he_eht_caps(phy);
431 mt7996_init_txpower(phy);
432 }
433
434 static void
mt7996_init_wiphy(struct ieee80211_hw * hw,struct mtk_wed_device * wed)435 mt7996_init_wiphy(struct ieee80211_hw *hw, struct mtk_wed_device *wed)
436 {
437 struct mt7996_dev *dev = mt7996_hw_dev(hw);
438 struct mt76_dev *mdev = &dev->mt76;
439 struct wiphy *wiphy = hw->wiphy;
440 u16 max_subframes = dev->has_eht ? IEEE80211_MAX_AMPDU_BUF_EHT :
441 IEEE80211_MAX_AMPDU_BUF_HE;
442
443 hw->queues = 4;
444 hw->max_rx_aggregation_subframes = max_subframes;
445 hw->max_tx_aggregation_subframes = max_subframes;
446 if (is_mt7990(mdev) && dev->has_eht)
447 hw->max_tx_aggregation_subframes = 512;
448
449 hw->netdev_features = NETIF_F_RXCSUM;
450 if (mtk_wed_device_active(wed))
451 hw->netdev_features |= NETIF_F_HW_TC;
452
453 hw->radiotap_timestamp.units_pos =
454 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US;
455
456 hw->sta_data_size = sizeof(struct mt7996_sta);
457 hw->vif_data_size = sizeof(struct mt7996_vif);
458 hw->chanctx_data_size = sizeof(struct mt76_chanctx);
459
460 wiphy->iface_combinations = &if_comb_global;
461 wiphy->n_iface_combinations = 1;
462
463 wiphy->radio = dev->radios;
464
465 wiphy->reg_notifier = mt7996_regd_notifier;
466 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
467 wiphy->mbssid_max_interfaces = 16;
468
469 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR);
470 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS);
471 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY);
472 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT);
473 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT);
474 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE);
475 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP);
476 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY);
477 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT);
478 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
479 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER);
480
481 if (mt7996_eeprom_has_background_radar(dev) &&
482 (!mdev->dev->of_node ||
483 !of_property_read_bool(mdev->dev->of_node,
484 "mediatek,disable-radar-background")))
485 wiphy_ext_feature_set(wiphy,
486 NL80211_EXT_FEATURE_RADAR_BACKGROUND);
487
488 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
489 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD);
490 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD);
491 ieee80211_hw_set(hw, NO_VIRTUAL_MONITOR);
492 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
493
494 hw->max_tx_fragments = 4;
495
496 /* init led callbacks */
497 if (IS_ENABLED(CONFIG_MT76_LEDS)) {
498 dev->mphy.leds.cdev.brightness_set = mt7996_led_set_brightness;
499 dev->mphy.leds.cdev.blink_set = mt7996_led_set_blink;
500 }
501
502 wiphy->max_scan_ssids = 4;
503 wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
504
505 mt7996_init_wiphy_band(hw, &dev->phy);
506 }
507
508 static void
mt7996_mac_init_band(struct mt7996_dev * dev,u8 band)509 mt7996_mac_init_band(struct mt7996_dev *dev, u8 band)
510 {
511 u32 mask, set;
512
513 /* clear estimated value of EIFS for Rx duration & OBSS time */
514 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR);
515
516 /* clear backoff time for Rx duration */
517 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band),
518 MT_WF_RMAC_MIB_NONQOSD_BACKOFF);
519 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band),
520 MT_WF_RMAC_MIB_QOS01_BACKOFF);
521 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band),
522 MT_WF_RMAC_MIB_QOS23_BACKOFF);
523
524 /* clear backoff time for Tx duration */
525 mt76_clear(dev, MT_WTBLOFF_ACR(band),
526 MT_WTBLOFF_ADM_BACKOFFTIME);
527
528 /* clear backoff time and set software compensation for OBSS time */
529 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET;
530 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) |
531 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4);
532 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set);
533
534 /* filter out non-resp frames and get instanstaeous signal reporting */
535 mask = MT_WTBLOFF_RSCR_RCPI_MODE | MT_WTBLOFF_RSCR_RCPI_PARAM;
536 set = FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_MODE, 0) |
537 FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_PARAM, 0x3);
538 mt76_rmw(dev, MT_WTBLOFF_RSCR(band), mask, set);
539
540 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than
541 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set.
542 */
543 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H);
544 }
545
mt7996_mac_init_basic_rates(struct mt7996_dev * dev)546 static void mt7996_mac_init_basic_rates(struct mt7996_dev *dev)
547 {
548 int i;
549
550 for (i = 0; i < ARRAY_SIZE(mt76_rates); i++) {
551 u16 rate = mt76_rates[i].hw_value;
552 /* odd index for driver, even index for firmware */
553 u16 idx = MT7996_BASIC_RATES_TBL + 2 * i;
554
555 rate = FIELD_PREP(MT_TX_RATE_MODE, rate >> 8) |
556 FIELD_PREP(MT_TX_RATE_IDX, rate & GENMASK(7, 0));
557 mt7996_mcu_set_fixed_rate_table(&dev->phy, idx, rate, false);
558 }
559 }
560
mt7996_mac_init(struct mt7996_dev * dev)561 void mt7996_mac_init(struct mt7996_dev *dev)
562 {
563 #define HIF_TXD_V2_1 0x21
564 int i;
565
566 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT);
567
568 for (i = 0; i < mt7996_wtbl_size(dev); i++)
569 mt7996_mac_wtbl_update(dev, i,
570 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
571
572 if (IS_ENABLED(CONFIG_MT76_LEDS)) {
573 i = dev->mphy.leds.pin ? MT_LED_GPIO_MUX3 : MT_LED_GPIO_MUX2;
574 mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4);
575 }
576
577 /* rro module init */
578 if (is_mt7996(&dev->mt76))
579 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 2);
580 else
581 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE,
582 dev->hif2 ? 7 : 0);
583
584 if (dev->has_rro) {
585 u16 timeout;
586
587 timeout = mt76_rr(dev, MT_HW_REV) == MT_HW_REV1 ? 512 : 128;
588 mt7996_mcu_set_rro(dev, UNI_RRO_SET_FLUSH_TIMEOUT, timeout);
589 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 1);
590 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 0);
591 } else {
592 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 3);
593 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 1);
594 }
595
596 mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
597 MCU_WA_PARAM_HW_PATH_HIF_VER,
598 HIF_TXD_V2_1, 0);
599
600 for (i = MT_BAND0; i <= MT_BAND2; i++)
601 mt7996_mac_init_band(dev, i);
602
603 mt7996_mac_init_basic_rates(dev);
604 }
605
mt7996_txbf_init(struct mt7996_dev * dev)606 int mt7996_txbf_init(struct mt7996_dev *dev)
607 {
608 int ret;
609
610 if (mt7996_band_valid(dev, MT_BAND1) ||
611 mt7996_band_valid(dev, MT_BAND2)) {
612 ret = mt7996_mcu_set_txbf(dev, BF_MOD_EN_CTRL);
613 if (ret)
614 return ret;
615 }
616
617 /* trigger sounding packets */
618 ret = mt7996_mcu_set_txbf(dev, BF_SOUNDING_ON);
619 if (ret)
620 return ret;
621
622 /* enable eBF */
623 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE);
624 }
625
mt7996_register_phy(struct mt7996_dev * dev,enum mt76_band_id band)626 static int mt7996_register_phy(struct mt7996_dev *dev, enum mt76_band_id band)
627 {
628 struct mt7996_phy *phy;
629 struct mt76_phy *mphy;
630 u32 mac_ofs, hif1_ofs = 0;
631 int ret;
632 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
633
634 if (!mt7996_band_valid(dev, band))
635 return 0;
636
637 if (is_mt7996(&dev->mt76) && band == MT_BAND2 && dev->hif2) {
638 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
639 wed = &dev->mt76.mmio.wed_hif2;
640 }
641
642 mphy = mt76_alloc_radio_phy(&dev->mt76, sizeof(*phy), band);
643 if (!mphy)
644 return -ENOMEM;
645
646 phy = mphy->priv;
647 phy->dev = dev;
648 phy->mt76 = mphy;
649 mphy->dev->phys[band] = mphy;
650
651 INIT_DELAYED_WORK(&mphy->mac_work, mt7996_mac_work);
652
653 ret = mt7996_eeprom_parse_hw_cap(dev, phy);
654 if (ret)
655 goto error;
656
657 mac_ofs = band == MT_BAND2 ? MT_EE_MAC_ADDR3 : MT_EE_MAC_ADDR2;
658 memcpy(mphy->macaddr, dev->mt76.eeprom.data + mac_ofs, ETH_ALEN);
659 /* Make the extra PHY MAC address local without overlapping with
660 * the usual MAC address allocation scheme on multiple virtual interfaces
661 */
662 if (!is_valid_ether_addr(mphy->macaddr)) {
663 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR,
664 ETH_ALEN);
665 mphy->macaddr[0] |= 2;
666 mphy->macaddr[0] ^= BIT(7);
667 if (band == MT_BAND2)
668 mphy->macaddr[0] ^= BIT(6);
669 }
670 mt76_eeprom_override(mphy);
671
672 /* init wiphy according to mphy and phy */
673 mt7996_init_wiphy_band(mphy->hw, phy);
674 ret = mt7996_init_tx_queues(mphy->priv,
675 MT_TXQ_ID(band),
676 MT7996_TX_RING_SIZE,
677 MT_TXQ_RING_BASE(band) + hif1_ofs,
678 wed);
679 if (ret)
680 goto error;
681
682 ret = mt76_register_phy(mphy, true, mt76_rates,
683 ARRAY_SIZE(mt76_rates));
684 if (ret)
685 goto error;
686
687 if (wed == &dev->mt76.mmio.wed_hif2 && mtk_wed_device_active(wed)) {
688 u32 irq_mask = dev->mt76.mmio.irqmask | MT_INT_TX_DONE_BAND2;
689
690 mt76_wr(dev, MT_INT1_MASK_CSR, irq_mask);
691 mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, irq_mask);
692 }
693
694 return 0;
695
696 error:
697 mphy->dev->phys[band] = NULL;
698 return ret;
699 }
700
701 static void
mt7996_unregister_phy(struct mt7996_phy * phy)702 mt7996_unregister_phy(struct mt7996_phy *phy)
703 {
704 if (phy)
705 mt7996_unregister_thermal(phy);
706 }
707
mt7996_init_work(struct work_struct * work)708 static void mt7996_init_work(struct work_struct *work)
709 {
710 struct mt7996_dev *dev = container_of(work, struct mt7996_dev,
711 init_work);
712
713 mt7996_mcu_set_eeprom(dev);
714 mt7996_mac_init(dev);
715 mt7996_txbf_init(dev);
716 }
717
mt7996_wfsys_reset(struct mt7996_dev * dev)718 void mt7996_wfsys_reset(struct mt7996_dev *dev)
719 {
720 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1);
721 msleep(20);
722
723 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1);
724 msleep(20);
725 }
726
mt7996_wed_rro_init(struct mt7996_dev * dev)727 static int mt7996_wed_rro_init(struct mt7996_dev *dev)
728 {
729 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
730 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
731 u32 reg = MT_RRO_ADDR_ELEM_SEG_ADDR0;
732 struct mt7996_wed_rro_addr *addr;
733 void *ptr;
734 int i;
735
736 if (!dev->has_rro)
737 return 0;
738
739 if (!mtk_wed_device_active(wed))
740 return 0;
741
742 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) {
743 ptr = dmam_alloc_coherent(dev->mt76.dma_dev,
744 MT7996_RRO_BA_BITMAP_CR_SIZE,
745 &dev->wed_rro.ba_bitmap[i].phy_addr,
746 GFP_KERNEL);
747 if (!ptr)
748 return -ENOMEM;
749
750 dev->wed_rro.ba_bitmap[i].ptr = ptr;
751 }
752
753 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) {
754 int j;
755
756 ptr = dmam_alloc_coherent(dev->mt76.dma_dev,
757 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr),
758 &dev->wed_rro.addr_elem[i].phy_addr,
759 GFP_KERNEL);
760 if (!ptr)
761 return -ENOMEM;
762
763 dev->wed_rro.addr_elem[i].ptr = ptr;
764 memset(dev->wed_rro.addr_elem[i].ptr, 0,
765 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr));
766
767 addr = dev->wed_rro.addr_elem[i].ptr;
768 for (j = 0; j < MT7996_RRO_WINDOW_MAX_SIZE; j++) {
769 addr->signature = 0xff;
770 addr++;
771 }
772
773 wed->wlan.ind_cmd.addr_elem_phys[i] =
774 dev->wed_rro.addr_elem[i].phy_addr;
775 }
776
777 ptr = dmam_alloc_coherent(dev->mt76.dma_dev,
778 MT7996_RRO_WINDOW_MAX_LEN * sizeof(*addr),
779 &dev->wed_rro.session.phy_addr,
780 GFP_KERNEL);
781 if (!ptr)
782 return -ENOMEM;
783
784 dev->wed_rro.session.ptr = ptr;
785 addr = dev->wed_rro.session.ptr;
786 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) {
787 addr->signature = 0xff;
788 addr++;
789 }
790
791 /* rro hw init */
792 /* TODO: remove line after WM has set */
793 mt76_clear(dev, WF_RRO_AXI_MST_CFG, WF_RRO_AXI_MST_CFG_DIDX_OK);
794
795 /* setup BA bitmap cache address */
796 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE0,
797 dev->wed_rro.ba_bitmap[0].phy_addr);
798 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE1, 0);
799 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT0,
800 dev->wed_rro.ba_bitmap[1].phy_addr);
801 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT1, 0);
802
803 /* setup Address element address */
804 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) {
805 mt76_wr(dev, reg, dev->wed_rro.addr_elem[i].phy_addr >> 4);
806 reg += 4;
807 }
808
809 /* setup Address element address - separate address segment mode */
810 mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE1,
811 MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE);
812
813 wed->wlan.ind_cmd.win_size = ffs(MT7996_RRO_WINDOW_MAX_LEN) - 6;
814 wed->wlan.ind_cmd.particular_sid = MT7996_RRO_MAX_SESSION;
815 wed->wlan.ind_cmd.particular_se_phys = dev->wed_rro.session.phy_addr;
816 wed->wlan.ind_cmd.se_group_nums = MT7996_RRO_ADDR_ELEM_LEN;
817 wed->wlan.ind_cmd.ack_sn_addr = MT_RRO_ACK_SN_CTRL;
818
819 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0x15010e00);
820 mt76_set(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1,
821 MT_RRO_IND_CMD_SIGNATURE_BASE1_EN);
822
823 /* particular session configure */
824 /* use max session idx + 1 as particular session id */
825 mt76_wr(dev, MT_RRO_PARTICULAR_CFG0, dev->wed_rro.session.phy_addr);
826 mt76_wr(dev, MT_RRO_PARTICULAR_CFG1,
827 MT_RRO_PARTICULAR_CONFG_EN |
828 FIELD_PREP(MT_RRO_PARTICULAR_SID, MT7996_RRO_MAX_SESSION));
829
830 /* interrupt enable */
831 mt76_wr(dev, MT_RRO_HOST_INT_ENA,
832 MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA);
833
834 /* rro ind cmd queue init */
835 return mt7996_dma_rro_init(dev);
836 #else
837 return 0;
838 #endif
839 }
840
mt7996_wed_rro_free(struct mt7996_dev * dev)841 static void mt7996_wed_rro_free(struct mt7996_dev *dev)
842 {
843 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
844 int i;
845
846 if (!dev->has_rro)
847 return;
848
849 if (!mtk_wed_device_active(&dev->mt76.mmio.wed))
850 return;
851
852 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) {
853 if (!dev->wed_rro.ba_bitmap[i].ptr)
854 continue;
855
856 dmam_free_coherent(dev->mt76.dma_dev,
857 MT7996_RRO_BA_BITMAP_CR_SIZE,
858 dev->wed_rro.ba_bitmap[i].ptr,
859 dev->wed_rro.ba_bitmap[i].phy_addr);
860 }
861
862 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) {
863 if (!dev->wed_rro.addr_elem[i].ptr)
864 continue;
865
866 dmam_free_coherent(dev->mt76.dma_dev,
867 MT7996_RRO_WINDOW_MAX_SIZE *
868 sizeof(struct mt7996_wed_rro_addr),
869 dev->wed_rro.addr_elem[i].ptr,
870 dev->wed_rro.addr_elem[i].phy_addr);
871 }
872
873 if (!dev->wed_rro.session.ptr)
874 return;
875
876 dmam_free_coherent(dev->mt76.dma_dev,
877 MT7996_RRO_WINDOW_MAX_LEN *
878 sizeof(struct mt7996_wed_rro_addr),
879 dev->wed_rro.session.ptr,
880 dev->wed_rro.session.phy_addr);
881 #endif
882 }
883
mt7996_wed_rro_work(struct work_struct * work)884 static void mt7996_wed_rro_work(struct work_struct *work)
885 {
886 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
887 struct mt7996_dev *dev;
888 LIST_HEAD(list);
889
890 dev = (struct mt7996_dev *)container_of(work, struct mt7996_dev,
891 wed_rro.work);
892
893 spin_lock_bh(&dev->wed_rro.lock);
894 list_splice_init(&dev->wed_rro.poll_list, &list);
895 spin_unlock_bh(&dev->wed_rro.lock);
896
897 while (!list_empty(&list)) {
898 struct mt7996_wed_rro_session_id *e;
899 int i;
900
901 e = list_first_entry(&list, struct mt7996_wed_rro_session_id,
902 list);
903 list_del_init(&e->list);
904
905 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) {
906 void *ptr = dev->wed_rro.session.ptr;
907 struct mt7996_wed_rro_addr *elem;
908 u32 idx, elem_id = i;
909
910 if (e->id == MT7996_RRO_MAX_SESSION)
911 goto reset;
912
913 idx = e->id / MT7996_RRO_BA_BITMAP_SESSION_SIZE;
914 if (idx >= ARRAY_SIZE(dev->wed_rro.addr_elem))
915 goto out;
916
917 ptr = dev->wed_rro.addr_elem[idx].ptr;
918 elem_id +=
919 (e->id % MT7996_RRO_BA_BITMAP_SESSION_SIZE) *
920 MT7996_RRO_WINDOW_MAX_LEN;
921 reset:
922 elem = ptr + elem_id * sizeof(*elem);
923 elem->signature = 0xff;
924 }
925 mt7996_mcu_wed_rro_reset_sessions(dev, e->id);
926 out:
927 kfree(e);
928 }
929 #endif
930 }
931
mt7996_variant_type_init(struct mt7996_dev * dev)932 static int mt7996_variant_type_init(struct mt7996_dev *dev)
933 {
934 u32 val = mt76_rr(dev, MT_PAD_GPIO);
935 u8 var_type;
936
937 switch (mt76_chip(&dev->mt76)) {
938 case MT7996_DEVICE_ID:
939 if (val & MT_PAD_GPIO_2ADIE_TBTC)
940 var_type = MT7996_VAR_TYPE_233;
941 else
942 var_type = MT7996_VAR_TYPE_444;
943 break;
944 case MT7992_DEVICE_ID:
945 if (val & MT_PAD_GPIO_ADIE_SINGLE)
946 var_type = MT7992_VAR_TYPE_23;
947 else if (u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992))
948 var_type = MT7992_VAR_TYPE_44;
949 else
950 return -EINVAL;
951 break;
952 case MT7990_DEVICE_ID:
953 var_type = MT7990_VAR_TYPE_23;
954 break;
955 default:
956 return -EINVAL;
957 }
958
959 dev->var.type = var_type;
960 return 0;
961 }
962
mt7996_variant_fem_init(struct mt7996_dev * dev)963 static int mt7996_variant_fem_init(struct mt7996_dev *dev)
964 {
965 #define MT7976C_EFUSE_OFFSET 0x470
966 u8 buf[MT7996_EEPROM_BLOCK_SIZE], idx, adie_idx, adie_comb;
967 u32 regval, val = mt76_rr(dev, MT_PAD_GPIO);
968 u16 adie_id, adie_ver;
969 bool is_7976c;
970 int ret;
971
972 if (is_mt7992(&dev->mt76)) {
973 adie_idx = (val & MT_PAD_GPIO_ADIE_SINGLE) ? 0 : 1;
974 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992);
975 } else {
976 adie_idx = 0;
977 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB);
978 }
979
980 ret = mt7996_mcu_rf_regval(dev, MT_ADIE_CHIP_ID(adie_idx), ®val, false);
981 if (ret)
982 return ret;
983
984 ret = mt7996_mcu_get_eeprom(dev, MT7976C_EFUSE_OFFSET, buf, sizeof(buf));
985 if (ret && ret != -EINVAL)
986 return ret;
987
988 adie_ver = u32_get_bits(regval, MT_ADIE_VERSION_MASK);
989 idx = MT7976C_EFUSE_OFFSET % MT7996_EEPROM_BLOCK_SIZE;
990 is_7976c = adie_ver == 0x8a10 || adie_ver == 0x8b00 ||
991 adie_ver == 0x8c10 || buf[idx] == 0xc;
992
993 adie_id = u32_get_bits(regval, MT_ADIE_CHIP_ID_MASK);
994 if (adie_id == 0x7975 || adie_id == 0x7979 ||
995 (adie_id == 0x7976 && is_7976c))
996 dev->var.fem = MT7996_FEM_INT;
997 else if (adie_id == 0x7977 && adie_comb == 1)
998 dev->var.fem = MT7996_FEM_MIX;
999 else
1000 dev->var.fem = MT7996_FEM_EXT;
1001
1002 return 0;
1003 }
1004
mt7996_init_hardware(struct mt7996_dev * dev)1005 static int mt7996_init_hardware(struct mt7996_dev *dev)
1006 {
1007 int ret, idx;
1008
1009 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0);
1010 if (is_mt7992(&dev->mt76)) {
1011 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND0), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0);
1012 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND1), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0);
1013 }
1014
1015 INIT_WORK(&dev->init_work, mt7996_init_work);
1016 INIT_WORK(&dev->wed_rro.work, mt7996_wed_rro_work);
1017 INIT_LIST_HEAD(&dev->wed_rro.poll_list);
1018 spin_lock_init(&dev->wed_rro.lock);
1019
1020 ret = mt7996_variant_type_init(dev);
1021 if (ret)
1022 return ret;
1023
1024 ret = mt7996_dma_init(dev);
1025 if (ret)
1026 return ret;
1027
1028 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
1029
1030 ret = mt7996_mcu_init(dev);
1031 if (ret)
1032 return ret;
1033
1034 ret = mt7996_wed_rro_init(dev);
1035 if (ret)
1036 return ret;
1037
1038 ret = mt7996_variant_fem_init(dev);
1039 if (ret)
1040 return ret;
1041
1042 ret = mt7996_eeprom_init(dev);
1043 if (ret < 0)
1044 return ret;
1045
1046 /* Beacon and mgmt frames should occupy wcid 0 */
1047 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7996_WTBL_STA);
1048 if (idx)
1049 return -ENOSPC;
1050
1051 dev->mt76.global_wcid.idx = idx;
1052 dev->mt76.global_wcid.hw_key_idx = -1;
1053 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET;
1054 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid);
1055
1056 return 0;
1057 }
1058
mt7996_set_stream_vht_txbf_caps(struct mt7996_phy * phy)1059 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy)
1060 {
1061 int sts;
1062 u32 *cap;
1063
1064 if (!phy->mt76->cap.has_5ghz)
1065 return;
1066
1067 sts = hweight16(phy->mt76->chainmask);
1068 cap = &phy->mt76->sband_5g.sband.vht_cap.cap;
1069
1070 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
1071 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
1072
1073 if (is_mt7992(phy->mt76->dev))
1074 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 4);
1075 else
1076 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 3);
1077
1078 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK |
1079 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
1080 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE);
1081
1082 if (sts < 2)
1083 return;
1084
1085 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
1086 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE |
1087 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, sts - 1);
1088 }
1089
1090 static void
mt7996_set_stream_he_txbf_caps(struct mt7996_phy * phy,struct ieee80211_sta_he_cap * he_cap,int vif,enum nl80211_band band)1091 mt7996_set_stream_he_txbf_caps(struct mt7996_phy *phy,
1092 struct ieee80211_sta_he_cap *he_cap, int vif,
1093 enum nl80211_band band)
1094 {
1095 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem;
1096 int sts = hweight16(phy->mt76->chainmask);
1097 bool non_2g = band != NL80211_BAND_2GHZ;
1098 u8 c;
1099
1100 #ifdef CONFIG_MAC80211_MESH
1101 if (vif == NL80211_IFTYPE_MESH_POINT)
1102 return;
1103 #endif
1104
1105 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
1106 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
1107
1108 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK |
1109 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK;
1110 elem->phy_cap_info[5] &= ~c;
1111
1112 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
1113 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
1114 elem->phy_cap_info[6] &= ~c;
1115
1116 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK;
1117
1118 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
1119 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO;
1120 elem->phy_cap_info[2] |= c;
1121
1122 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE;
1123
1124 if (is_mt7992(phy->mt76->dev))
1125 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_5 |
1126 (IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_5 * non_2g);
1127 else
1128 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 |
1129 (IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4 * non_2g);
1130
1131 elem->phy_cap_info[4] |= c;
1132
1133 /* do not support NG16 due to spec D4.0 changes subcarrier idx */
1134 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
1135 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU;
1136
1137 if (vif == NL80211_IFTYPE_STATION)
1138 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO;
1139
1140 elem->phy_cap_info[6] |= c;
1141
1142 if (sts < 2)
1143 return;
1144
1145 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */
1146 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3;
1147
1148 if (!(vif == NL80211_IFTYPE_AP || vif == NL80211_IFTYPE_STATION))
1149 return;
1150
1151 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
1152
1153 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK,
1154 sts - 1) |
1155 (FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK,
1156 sts - 1) * non_2g);
1157
1158 elem->phy_cap_info[5] |= c;
1159
1160 if (vif != NL80211_IFTYPE_AP)
1161 return;
1162
1163 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
1164
1165 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
1166 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
1167 elem->phy_cap_info[6] |= c;
1168
1169 c = 0;
1170 if (non_2g)
1171 c |= IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ |
1172 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ;
1173 elem->phy_cap_info[7] |= c;
1174 }
1175
1176 static void
mt7996_init_he_caps(struct mt7996_phy * phy,enum nl80211_band band,struct ieee80211_sband_iftype_data * data,enum nl80211_iftype iftype)1177 mt7996_init_he_caps(struct mt7996_phy *phy, enum nl80211_band band,
1178 struct ieee80211_sband_iftype_data *data,
1179 enum nl80211_iftype iftype)
1180 {
1181 struct ieee80211_sta_he_cap *he_cap = &data->he_cap;
1182 struct ieee80211_he_cap_elem *he_cap_elem = &he_cap->he_cap_elem;
1183 struct ieee80211_he_mcs_nss_supp *he_mcs = &he_cap->he_mcs_nss_supp;
1184 int i, nss = hweight8(phy->mt76->antenna_mask);
1185 u16 mcs_map = 0;
1186
1187 for (i = 0; i < 8; i++) {
1188 if (i < nss)
1189 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2));
1190 else
1191 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2));
1192 }
1193
1194 he_cap->has_he = true;
1195
1196 he_cap_elem->mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE;
1197 he_cap_elem->mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
1198 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3;
1199 he_cap_elem->mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU;
1200
1201 if (band == NL80211_BAND_2GHZ)
1202 he_cap_elem->phy_cap_info[0] =
1203 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
1204 else
1205 he_cap_elem->phy_cap_info[0] =
1206 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
1207 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
1208
1209 he_cap_elem->phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD;
1210 he_cap_elem->phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
1211 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ;
1212
1213 he_cap_elem->phy_cap_info[7] =
1214 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI;
1215
1216 switch (iftype) {
1217 case NL80211_IFTYPE_AP:
1218 he_cap_elem->mac_cap_info[0] |= IEEE80211_HE_MAC_CAP0_TWT_RES;
1219 he_cap_elem->mac_cap_info[2] |= IEEE80211_HE_MAC_CAP2_BSR;
1220 he_cap_elem->mac_cap_info[4] |= IEEE80211_HE_MAC_CAP4_BQR;
1221 he_cap_elem->mac_cap_info[5] |=
1222 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX;
1223 he_cap_elem->phy_cap_info[3] |=
1224 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
1225 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
1226 he_cap_elem->phy_cap_info[6] |=
1227 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
1228 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
1229 he_cap_elem->phy_cap_info[9] |=
1230 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
1231 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU;
1232 break;
1233 case NL80211_IFTYPE_STATION:
1234 he_cap_elem->mac_cap_info[1] |=
1235 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US;
1236
1237 if (band == NL80211_BAND_2GHZ)
1238 he_cap_elem->phy_cap_info[0] |=
1239 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G;
1240 else
1241 he_cap_elem->phy_cap_info[0] |=
1242 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G;
1243
1244 he_cap_elem->phy_cap_info[1] |=
1245 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
1246 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US;
1247 he_cap_elem->phy_cap_info[3] |=
1248 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
1249 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
1250 he_cap_elem->phy_cap_info[6] |=
1251 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB |
1252 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
1253 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
1254 he_cap_elem->phy_cap_info[7] |=
1255 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP;
1256 he_cap_elem->phy_cap_info[8] |=
1257 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
1258 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
1259 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
1260 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484;
1261 he_cap_elem->phy_cap_info[9] |=
1262 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM |
1263 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK |
1264 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
1265 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU |
1266 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
1267 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB;
1268 break;
1269 default:
1270 break;
1271 }
1272
1273 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map);
1274 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map);
1275 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map);
1276 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map);
1277
1278 mt7996_set_stream_he_txbf_caps(phy, he_cap, iftype, band);
1279
1280 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres));
1281 if (he_cap_elem->phy_cap_info[6] &
1282 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) {
1283 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss, band);
1284 } else {
1285 he_cap_elem->phy_cap_info[9] |=
1286 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US,
1287 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK);
1288 }
1289
1290 if (band == NL80211_BAND_6GHZ) {
1291 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS |
1292 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS;
1293
1294 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_0_5,
1295 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
1296 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
1297 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
1298 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
1299 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
1300
1301 data->he_6ghz_capa.capa = cpu_to_le16(cap);
1302 }
1303 }
1304
1305 static void
mt7996_init_eht_caps(struct mt7996_phy * phy,enum nl80211_band band,struct ieee80211_sband_iftype_data * data,enum nl80211_iftype iftype)1306 mt7996_init_eht_caps(struct mt7996_phy *phy, enum nl80211_band band,
1307 struct ieee80211_sband_iftype_data *data,
1308 enum nl80211_iftype iftype)
1309 {
1310 struct ieee80211_sta_eht_cap *eht_cap = &data->eht_cap;
1311 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem = &eht_cap->eht_cap_elem;
1312 struct ieee80211_eht_mcs_nss_supp *eht_nss = &eht_cap->eht_mcs_nss_supp;
1313 enum nl80211_chan_width width = phy->mt76->chandef.width;
1314 int nss = hweight8(phy->mt76->antenna_mask);
1315 int sts = hweight16(phy->mt76->chainmask);
1316 u8 val;
1317
1318 if (!phy->dev->has_eht)
1319 return;
1320
1321 eht_cap->has_eht = true;
1322
1323 eht_cap_elem->mac_cap_info[0] =
1324 IEEE80211_EHT_MAC_CAP0_EPCS_PRIO_ACCESS |
1325 IEEE80211_EHT_MAC_CAP0_OM_CONTROL |
1326 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454,
1327 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK);
1328
1329 eht_cap_elem->mac_cap_info[1] |=
1330 IEEE80211_EHT_MAC_CAP1_MAX_AMPDU_LEN_MASK;
1331
1332 eht_cap_elem->phy_cap_info[0] =
1333 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI |
1334 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMER |
1335 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE;
1336
1337 /* Set the maximum capability regardless of the antenna configuration. */
1338 val = is_mt7992(phy->mt76->dev) ? 4 : 3;
1339 eht_cap_elem->phy_cap_info[0] |=
1340 u8_encode_bits(u8_get_bits(val, BIT(0)),
1341 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK);
1342
1343 eht_cap_elem->phy_cap_info[1] =
1344 u8_encode_bits(u8_get_bits(val, GENMASK(2, 1)),
1345 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK);
1346
1347 eht_cap_elem->phy_cap_info[2] =
1348 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_80MHZ_MASK);
1349
1350 if (band != NL80211_BAND_2GHZ) {
1351 eht_cap_elem->phy_cap_info[1] |=
1352 u8_encode_bits(val,
1353 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK);
1354
1355 eht_cap_elem->phy_cap_info[2] |=
1356 u8_encode_bits(sts - 1,
1357 IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_160MHZ_MASK);
1358 }
1359
1360 if (band == NL80211_BAND_6GHZ) {
1361 eht_cap_elem->phy_cap_info[0] |=
1362 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ;
1363
1364 eht_cap_elem->phy_cap_info[1] |=
1365 u8_encode_bits(val,
1366 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK);
1367
1368 eht_cap_elem->phy_cap_info[2] |=
1369 u8_encode_bits(sts - 1,
1370 IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_320MHZ_MASK);
1371 }
1372
1373 eht_cap_elem->phy_cap_info[3] =
1374 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK |
1375 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK |
1376 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
1377 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK;
1378
1379 eht_cap_elem->phy_cap_info[4] =
1380 IEEE80211_EHT_PHY_CAP4_EHT_MU_PPDU_4_EHT_LTF_08_GI |
1381 u8_encode_bits(min_t(int, sts - 1, 2),
1382 IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK);
1383
1384 eht_cap_elem->phy_cap_info[5] =
1385 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US,
1386 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK) |
1387 u8_encode_bits(u8_get_bits(1, GENMASK(1, 0)),
1388 IEEE80211_EHT_PHY_CAP5_MAX_NUM_SUPP_EHT_LTF_MASK);
1389
1390 val = width == NL80211_CHAN_WIDTH_320 ? 0xf :
1391 width == NL80211_CHAN_WIDTH_160 ? 0x7 :
1392 width == NL80211_CHAN_WIDTH_80 ? 0x3 : 0x1;
1393 eht_cap_elem->phy_cap_info[6] =
1394 u8_encode_bits(val, IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK);
1395
1396 val = u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_RX) |
1397 u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_TX);
1398 #define SET_EHT_MAX_NSS(_bw, _val) do { \
1399 eht_nss->bw._##_bw.rx_tx_mcs9_max_nss = _val; \
1400 eht_nss->bw._##_bw.rx_tx_mcs11_max_nss = _val; \
1401 eht_nss->bw._##_bw.rx_tx_mcs13_max_nss = _val; \
1402 } while (0)
1403
1404 SET_EHT_MAX_NSS(80, val);
1405 SET_EHT_MAX_NSS(160, val);
1406 if (band == NL80211_BAND_6GHZ)
1407 SET_EHT_MAX_NSS(320, val);
1408 #undef SET_EHT_MAX_NSS
1409
1410 if (iftype != NL80211_IFTYPE_AP)
1411 return;
1412
1413 eht_cap_elem->phy_cap_info[3] |=
1414 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK |
1415 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK;
1416
1417 eht_cap_elem->phy_cap_info[7] =
1418 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_80MHZ |
1419 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_80MHZ;
1420
1421 if (band == NL80211_BAND_2GHZ)
1422 return;
1423
1424 eht_cap_elem->phy_cap_info[7] |=
1425 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_160MHZ |
1426 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_160MHZ;
1427
1428 if (band != NL80211_BAND_6GHZ)
1429 return;
1430
1431 eht_cap_elem->phy_cap_info[7] |=
1432 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_320MHZ |
1433 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_320MHZ;
1434 }
1435
1436 static void
__mt7996_set_stream_he_eht_caps(struct mt7996_phy * phy,struct ieee80211_supported_band * sband,enum nl80211_band band)1437 __mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy,
1438 struct ieee80211_supported_band *sband,
1439 enum nl80211_band band)
1440 {
1441 struct ieee80211_sband_iftype_data *data = phy->iftype[band];
1442 int i, n = 0;
1443
1444 for (i = 0; i < NUM_NL80211_IFTYPES; i++) {
1445 switch (i) {
1446 case NL80211_IFTYPE_STATION:
1447 case NL80211_IFTYPE_AP:
1448 #ifdef CONFIG_MAC80211_MESH
1449 case NL80211_IFTYPE_MESH_POINT:
1450 #endif
1451 break;
1452 default:
1453 continue;
1454 }
1455
1456 data[n].types_mask = BIT(i);
1457 mt7996_init_he_caps(phy, band, &data[n], i);
1458 mt7996_init_eht_caps(phy, band, &data[n], i);
1459
1460 n++;
1461 }
1462
1463 _ieee80211_set_sband_iftype_data(sband, data, n);
1464 }
1465
mt7996_set_stream_he_eht_caps(struct mt7996_phy * phy)1466 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy)
1467 {
1468 if (phy->mt76->cap.has_2ghz)
1469 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_2g.sband,
1470 NL80211_BAND_2GHZ);
1471
1472 if (phy->mt76->cap.has_5ghz)
1473 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_5g.sband,
1474 NL80211_BAND_5GHZ);
1475
1476 if (phy->mt76->cap.has_6ghz)
1477 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_6g.sband,
1478 NL80211_BAND_6GHZ);
1479 }
1480
mt7996_register_device(struct mt7996_dev * dev)1481 int mt7996_register_device(struct mt7996_dev *dev)
1482 {
1483 struct ieee80211_hw *hw = mt76_hw(dev);
1484 struct mt7996_phy *phy;
1485 int ret;
1486
1487 dev->phy.dev = dev;
1488 dev->phy.mt76 = &dev->mt76.phy;
1489 dev->mt76.phy.priv = &dev->phy;
1490 INIT_WORK(&dev->rc_work, mt7996_mac_sta_rc_work);
1491 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7996_mac_work);
1492 INIT_LIST_HEAD(&dev->sta_rc_list);
1493 INIT_LIST_HEAD(&dev->twt_list);
1494
1495 init_waitqueue_head(&dev->reset_wait);
1496 INIT_WORK(&dev->reset_work, mt7996_mac_reset_work);
1497 INIT_WORK(&dev->dump_work, mt7996_mac_dump_work);
1498 mutex_init(&dev->dump_mutex);
1499
1500 ret = mt7996_init_hardware(dev);
1501 if (ret)
1502 return ret;
1503
1504 mt7996_init_wiphy(hw, &dev->mt76.mmio.wed);
1505
1506 ret = mt7996_register_phy(dev, MT_BAND1);
1507 if (ret)
1508 return ret;
1509
1510 ret = mt7996_register_phy(dev, MT_BAND2);
1511 if (ret)
1512 return ret;
1513
1514 ret = mt76_register_device(&dev->mt76, true, mt76_rates,
1515 ARRAY_SIZE(mt76_rates));
1516 if (ret)
1517 return ret;
1518
1519 mt7996_for_each_phy(dev, phy)
1520 mt7996_thermal_init(phy);
1521
1522 ieee80211_queue_work(mt76_hw(dev), &dev->init_work);
1523
1524 dev->recovery.hw_init_done = true;
1525
1526 ret = mt7996_init_debugfs(dev);
1527 if (ret)
1528 goto error;
1529
1530 ret = mt7996_coredump_register(dev);
1531 if (ret)
1532 goto error;
1533
1534 return 0;
1535
1536 error:
1537 cancel_work_sync(&dev->init_work);
1538
1539 return ret;
1540 }
1541
mt7996_unregister_device(struct mt7996_dev * dev)1542 void mt7996_unregister_device(struct mt7996_dev *dev)
1543 {
1544 cancel_work_sync(&dev->wed_rro.work);
1545 mt7996_unregister_phy(mt7996_phy3(dev));
1546 mt7996_unregister_phy(mt7996_phy2(dev));
1547 mt7996_unregister_thermal(&dev->phy);
1548 mt7996_coredump_unregister(dev);
1549 mt76_unregister_device(&dev->mt76);
1550 mt7996_wed_rro_free(dev);
1551 mt7996_mcu_exit(dev);
1552 mt7996_tx_token_put(dev);
1553 mt7996_dma_cleanup(dev);
1554 tasklet_disable(&dev->mt76.irq_tasklet);
1555
1556 mt76_free_device(&dev->mt76);
1557 }
1558