1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/relay.h> 7 #include "mt7996.h" 8 #include "eeprom.h" 9 #include "mcu.h" 10 #include "mac.h" 11 12 #define FW_BIN_LOG_MAGIC 0x44d9c99a 13 14 /** global debugfs **/ 15 16 struct hw_queue_map { 17 const char *name; 18 u8 index; 19 u8 pid; 20 u8 qid; 21 }; 22 23 static int 24 mt7996_implicit_txbf_set(void *data, u64 val) 25 { 26 struct mt7996_dev *dev = data; 27 28 /* The existing connected stations shall reconnect to apply 29 * new implicit txbf configuration. 30 */ 31 dev->ibf = !!val; 32 33 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE); 34 } 35 36 static int 37 mt7996_implicit_txbf_get(void *data, u64 *val) 38 { 39 struct mt7996_dev *dev = data; 40 41 *val = dev->ibf; 42 43 return 0; 44 } 45 46 DEFINE_DEBUGFS_ATTRIBUTE(fops_implicit_txbf, mt7996_implicit_txbf_get, 47 mt7996_implicit_txbf_set, "%lld\n"); 48 49 /* test knob of system error recovery */ 50 static ssize_t 51 mt7996_sys_recovery_set(struct file *file, const char __user *user_buf, 52 size_t count, loff_t *ppos) 53 { 54 struct mt7996_dev *dev = file->private_data; 55 char buf[16], *sep; 56 int ret = 0; 57 u16 band, val; 58 59 if (count >= sizeof(buf)) 60 return -EINVAL; 61 62 if (copy_from_user(buf, user_buf, count)) 63 return -EFAULT; 64 65 if (count && buf[count - 1] == '\n') 66 buf[count - 1] = '\0'; 67 else 68 buf[count] = '\0'; 69 70 sep = strchr(buf, ','); 71 if (!sep) 72 return -EINVAL; 73 74 *sep = 0; 75 if (kstrtou16(buf, 0, &band) || kstrtou16(sep + 1, 0, &val)) 76 return -EINVAL; 77 78 switch (val) { 79 /* 80 * <band>,0: grab firmware current SER state. 81 * <band>,1: trigger & enable system error L1 recovery. 82 * <band>,2: trigger & enable system error L2 recovery. 83 * <band>,3: trigger & enable system error L3 rx abort. 84 * <band>,4: trigger & enable system error L3 tx abort 85 * <band>,5: trigger & enable system error L3 tx disable. 86 * <band>,6: trigger & enable system error L3 bf recovery. 87 * <band>,7: trigger & enable system error L4 mdp recovery. 88 * <band>,8: trigger & enable system error full recovery. 89 * <band>,9: trigger firmware crash. 90 */ 91 case UNI_CMD_SER_QUERY: 92 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_QUERY, 0, band); 93 break; 94 case UNI_CMD_SER_SET_RECOVER_L1: 95 case UNI_CMD_SER_SET_RECOVER_L2: 96 case UNI_CMD_SER_SET_RECOVER_L3_RX_ABORT: 97 case UNI_CMD_SER_SET_RECOVER_L3_TX_ABORT: 98 case UNI_CMD_SER_SET_RECOVER_L3_TX_DISABLE: 99 case UNI_CMD_SER_SET_RECOVER_L3_BF: 100 case UNI_CMD_SER_SET_RECOVER_L4_MDP: 101 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_SET, BIT(val), band); 102 if (ret) 103 return ret; 104 105 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_TRIGGER, val, band); 106 break; 107 108 /* enable full chip reset */ 109 case UNI_CMD_SER_SET_RECOVER_FULL: 110 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK); 111 dev->recovery.state |= MT_MCU_CMD_WDT_MASK; 112 mt7996_reset(dev); 113 break; 114 115 /* WARNING: trigger firmware crash */ 116 case UNI_CMD_SER_SET_SYSTEM_ASSERT: 117 ret = mt7996_mcu_trigger_assert(dev); 118 if (ret) 119 return ret; 120 break; 121 default: 122 break; 123 } 124 125 return ret ? ret : count; 126 } 127 128 static ssize_t 129 mt7996_sys_recovery_get(struct file *file, char __user *user_buf, 130 size_t count, loff_t *ppos) 131 { 132 struct mt7996_dev *dev = file->private_data; 133 char *buff; 134 int desc = 0; 135 ssize_t ret; 136 static const size_t bufsz = 1024; 137 138 buff = kmalloc(bufsz, GFP_KERNEL); 139 if (!buff) 140 return -ENOMEM; 141 142 /* HELP */ 143 desc += scnprintf(buff + desc, bufsz - desc, 144 "Please echo the correct value ...\n"); 145 desc += scnprintf(buff + desc, bufsz - desc, 146 "<band>,0: grab firmware transient SER state\n"); 147 desc += scnprintf(buff + desc, bufsz - desc, 148 "<band>,1: trigger system error L1 recovery\n"); 149 desc += scnprintf(buff + desc, bufsz - desc, 150 "<band>,2: trigger system error L2 recovery\n"); 151 desc += scnprintf(buff + desc, bufsz - desc, 152 "<band>,3: trigger system error L3 rx abort\n"); 153 desc += scnprintf(buff + desc, bufsz - desc, 154 "<band>,4: trigger system error L3 tx abort\n"); 155 desc += scnprintf(buff + desc, bufsz - desc, 156 "<band>,5: trigger system error L3 tx disable\n"); 157 desc += scnprintf(buff + desc, bufsz - desc, 158 "<band>,6: trigger system error L3 bf recovery\n"); 159 desc += scnprintf(buff + desc, bufsz - desc, 160 "<band>,7: trigger system error L4 mdp recovery\n"); 161 desc += scnprintf(buff + desc, bufsz - desc, 162 "<band>,8: trigger system error full recovery\n"); 163 desc += scnprintf(buff + desc, bufsz - desc, 164 "<band>,9: trigger firmware crash\n"); 165 166 /* SER statistics */ 167 desc += scnprintf(buff + desc, bufsz - desc, 168 "\nlet's dump firmware SER statistics...\n"); 169 desc += scnprintf(buff + desc, bufsz - desc, 170 "::E R , SER_STATUS = 0x%08x\n", 171 mt76_rr(dev, MT_SWDEF_SER_STATS)); 172 desc += scnprintf(buff + desc, bufsz - desc, 173 "::E R , SER_PLE_ERR = 0x%08x\n", 174 mt76_rr(dev, MT_SWDEF_PLE_STATS)); 175 desc += scnprintf(buff + desc, bufsz - desc, 176 "::E R , SER_PLE_ERR_1 = 0x%08x\n", 177 mt76_rr(dev, MT_SWDEF_PLE1_STATS)); 178 desc += scnprintf(buff + desc, bufsz - desc, 179 "::E R , SER_PLE_ERR_AMSDU = 0x%08x\n", 180 mt76_rr(dev, MT_SWDEF_PLE_AMSDU_STATS)); 181 desc += scnprintf(buff + desc, bufsz - desc, 182 "::E R , SER_PSE_ERR = 0x%08x\n", 183 mt76_rr(dev, MT_SWDEF_PSE_STATS)); 184 desc += scnprintf(buff + desc, bufsz - desc, 185 "::E R , SER_PSE_ERR_1 = 0x%08x\n", 186 mt76_rr(dev, MT_SWDEF_PSE1_STATS)); 187 desc += scnprintf(buff + desc, bufsz - desc, 188 "::E R , SER_LMAC_WISR6_B0 = 0x%08x\n", 189 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN0_STATS)); 190 desc += scnprintf(buff + desc, bufsz - desc, 191 "::E R , SER_LMAC_WISR6_B1 = 0x%08x\n", 192 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN1_STATS)); 193 desc += scnprintf(buff + desc, bufsz - desc, 194 "::E R , SER_LMAC_WISR6_B2 = 0x%08x\n", 195 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN2_STATS)); 196 desc += scnprintf(buff + desc, bufsz - desc, 197 "::E R , SER_LMAC_WISR7_B0 = 0x%08x\n", 198 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN0_STATS)); 199 desc += scnprintf(buff + desc, bufsz - desc, 200 "::E R , SER_LMAC_WISR7_B1 = 0x%08x\n", 201 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN1_STATS)); 202 desc += scnprintf(buff + desc, bufsz - desc, 203 "::E R , SER_LMAC_WISR7_B2 = 0x%08x\n", 204 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN2_STATS)); 205 desc += scnprintf(buff + desc, bufsz - desc, 206 "\nSYS_RESET_COUNT: WM %d, WA %d\n", 207 dev->recovery.wm_reset_count, 208 dev->recovery.wa_reset_count); 209 210 ret = simple_read_from_buffer(user_buf, count, ppos, buff, desc); 211 kfree(buff); 212 return ret; 213 } 214 215 static const struct file_operations mt7996_sys_recovery_ops = { 216 .write = mt7996_sys_recovery_set, 217 .read = mt7996_sys_recovery_get, 218 .open = simple_open, 219 .llseek = default_llseek, 220 }; 221 222 static int 223 mt7996_radar_trigger(void *data, u64 val) 224 { 225 #define RADAR_MAIN_CHAIN 1 226 #define RADAR_BACKGROUND 2 227 struct mt7996_dev *dev = data; 228 struct mt7996_phy *phy = mt7996_band_phy(dev, NL80211_BAND_5GHZ); 229 struct cfg80211_chan_def *chandef; 230 int rdd_idx, ret; 231 232 if (!phy || !val || val > RADAR_BACKGROUND) 233 return -EINVAL; 234 235 if (test_bit(MT76_SCANNING, &phy->mt76->state)) 236 return -EBUSY; 237 238 if (val == RADAR_BACKGROUND) { 239 if (!dev->rdd2_phy || !cfg80211_chandef_valid(&dev->rdd2_chandef)) { 240 dev_err(dev->mt76.dev, "Background radar is not enabled\n"); 241 return -EINVAL; 242 } 243 chandef = &dev->rdd2_chandef; 244 } else { 245 chandef = &phy->mt76->chandef; 246 } 247 248 rdd_idx = mt7996_get_rdd_idx(phy, val == RADAR_BACKGROUND); 249 if (rdd_idx < 0) { 250 dev_err(dev->mt76.dev, "No RDD found\n"); 251 return -EINVAL; 252 } 253 254 ret = cfg80211_chandef_dfs_required(dev->mt76.hw->wiphy, chandef, 255 NL80211_IFTYPE_AP); 256 if (ret <= 0) 257 return ret; 258 259 return mt7996_mcu_rdd_cmd(dev, RDD_RADAR_EMULATE, rdd_idx, 0); 260 } 261 262 DEFINE_DEBUGFS_ATTRIBUTE(fops_radar_trigger, NULL, 263 mt7996_radar_trigger, "%lld\n"); 264 265 static int 266 mt7996_rdd_monitor(struct seq_file *s, void *data) 267 { 268 struct mt7996_dev *dev = dev_get_drvdata(s->private); 269 struct cfg80211_chan_def *chandef = &dev->rdd2_chandef; 270 const char *bw; 271 int ret = 0; 272 273 mutex_lock(&dev->mt76.mutex); 274 275 if (!cfg80211_chandef_valid(chandef)) { 276 ret = -EINVAL; 277 goto out; 278 } 279 280 if (!dev->rdd2_phy) { 281 seq_puts(s, "not running\n"); 282 goto out; 283 } 284 285 switch (chandef->width) { 286 case NL80211_CHAN_WIDTH_40: 287 bw = "40"; 288 break; 289 case NL80211_CHAN_WIDTH_80: 290 bw = "80"; 291 break; 292 case NL80211_CHAN_WIDTH_160: 293 bw = "160"; 294 break; 295 case NL80211_CHAN_WIDTH_80P80: 296 bw = "80P80"; 297 break; 298 default: 299 bw = "20"; 300 break; 301 } 302 303 seq_printf(s, "channel %d (%d MHz) width %s MHz center1: %d MHz\n", 304 chandef->chan->hw_value, chandef->chan->center_freq, 305 bw, chandef->center_freq1); 306 out: 307 mutex_unlock(&dev->mt76.mutex); 308 309 return ret; 310 } 311 312 static int 313 mt7996_fw_debug_wm_set(void *data, u64 val) 314 { 315 struct mt7996_dev *dev = data; 316 enum { 317 DEBUG_TXCMD = 62, 318 DEBUG_CMD_RPT_TX, 319 DEBUG_CMD_RPT_TRIG, 320 DEBUG_SPL, 321 DEBUG_RPT_RX, 322 DEBUG_RPT_RA = 68, 323 } debug; 324 bool tx, rx, en; 325 int ret; 326 327 dev->fw_debug_wm = val ? MCU_FW_LOG_TO_HOST : 0; 328 329 if (dev->fw_debug_bin) 330 val = MCU_FW_LOG_RELAY; 331 else 332 val = dev->fw_debug_wm; 333 334 tx = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(1)); 335 rx = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(2)); 336 en = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(0)); 337 338 ret = mt7996_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, val); 339 if (ret) 340 return ret; 341 342 for (debug = DEBUG_TXCMD; debug <= DEBUG_RPT_RA; debug++) { 343 if (debug == 67) 344 continue; 345 346 if (debug == DEBUG_RPT_RX) 347 val = en && rx; 348 else 349 val = en && tx; 350 351 ret = mt7996_mcu_fw_dbg_ctrl(dev, debug, val); 352 if (ret) 353 return ret; 354 } 355 356 return 0; 357 } 358 359 static int 360 mt7996_fw_debug_wm_get(void *data, u64 *val) 361 { 362 struct mt7996_dev *dev = data; 363 364 *val = dev->fw_debug_wm; 365 366 return 0; 367 } 368 369 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wm, mt7996_fw_debug_wm_get, 370 mt7996_fw_debug_wm_set, "%lld\n"); 371 372 static int 373 mt7996_fw_debug_wa_set(void *data, u64 val) 374 { 375 struct mt7996_dev *dev = data; 376 int ret; 377 378 dev->fw_debug_wa = val ? MCU_FW_LOG_TO_HOST : 0; 379 380 ret = mt7996_mcu_fw_log_2_host(dev, MCU_FW_LOG_WA, dev->fw_debug_wa); 381 if (ret) 382 return ret; 383 384 return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), MCU_WA_PARAM_PDMA_RX, 385 !!dev->fw_debug_wa, 0); 386 } 387 388 static int 389 mt7996_fw_debug_wa_get(void *data, u64 *val) 390 { 391 struct mt7996_dev *dev = data; 392 393 *val = dev->fw_debug_wa; 394 395 return 0; 396 } 397 398 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wa, mt7996_fw_debug_wa_get, 399 mt7996_fw_debug_wa_set, "%lld\n"); 400 401 static struct dentry * 402 create_buf_file_cb(const char *filename, struct dentry *parent, umode_t mode, 403 struct rchan_buf *buf, int *is_global) 404 { 405 struct dentry *f; 406 407 f = debugfs_create_file("fwlog_data", mode, parent, buf, 408 &relay_file_operations); 409 if (IS_ERR(f)) 410 return NULL; 411 412 *is_global = 1; 413 414 return f; 415 } 416 417 static int 418 remove_buf_file_cb(struct dentry *f) 419 { 420 debugfs_remove(f); 421 422 return 0; 423 } 424 425 static int 426 mt7996_fw_debug_bin_set(void *data, u64 val) 427 { 428 static struct rchan_callbacks relay_cb = { 429 .create_buf_file = create_buf_file_cb, 430 .remove_buf_file = remove_buf_file_cb, 431 }; 432 struct mt7996_dev *dev = data; 433 434 if (!dev->relay_fwlog) 435 dev->relay_fwlog = relay_open("fwlog_data", dev->debugfs_dir, 436 1500, 512, &relay_cb, NULL); 437 if (!dev->relay_fwlog) 438 return -ENOMEM; 439 440 dev->fw_debug_bin = val; 441 442 relay_reset(dev->relay_fwlog); 443 444 return mt7996_fw_debug_wm_set(dev, dev->fw_debug_wm); 445 } 446 447 static int 448 mt7996_fw_debug_bin_get(void *data, u64 *val) 449 { 450 struct mt7996_dev *dev = data; 451 452 *val = dev->fw_debug_bin; 453 454 return 0; 455 } 456 457 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_bin, mt7996_fw_debug_bin_get, 458 mt7996_fw_debug_bin_set, "%lld\n"); 459 460 static int 461 mt7996_fw_util_wa_show(struct seq_file *file, void *data) 462 { 463 struct mt7996_dev *dev = file->private; 464 465 if (dev->fw_debug_wa) 466 return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY), 467 MCU_WA_PARAM_CPU_UTIL, 0, 0); 468 469 return 0; 470 } 471 472 DEFINE_SHOW_ATTRIBUTE(mt7996_fw_util_wa); 473 474 static void 475 mt7996_ampdu_stat_read_phy(struct mt7996_phy *phy, struct seq_file *file) 476 { 477 struct mt7996_dev *dev = phy->dev; 478 int bound[15], range[8], i; 479 u8 band_idx = phy->mt76->band_idx; 480 481 /* Tx ampdu stat */ 482 for (i = 0; i < ARRAY_SIZE(range); i++) 483 range[i] = mt76_rr(dev, MT_MIB_ARNG(band_idx, i)); 484 485 for (i = 0; i < ARRAY_SIZE(bound); i++) 486 bound[i] = MT_MIB_ARNCR_RANGE(range[i / 2], i % 2) + 1; 487 488 seq_printf(file, "\nPhy %s, Phy band %d\n", 489 wiphy_name(phy->mt76->hw->wiphy), band_idx); 490 491 seq_printf(file, "Length: %8d | ", bound[0]); 492 for (i = 0; i < ARRAY_SIZE(bound) - 1; i++) 493 seq_printf(file, "%3d -%3d | ", 494 bound[i] + 1, bound[i + 1]); 495 496 seq_puts(file, "\nCount: "); 497 for (i = 0; i < ARRAY_SIZE(bound); i++) 498 seq_printf(file, "%8d | ", phy->mt76->aggr_stats[i]); 499 seq_puts(file, "\n"); 500 501 seq_printf(file, "BA miss count: %d\n", phy->mib.ba_miss_cnt); 502 } 503 504 static void 505 mt7996_txbf_stat_read_phy(struct mt7996_phy *phy, struct seq_file *s) 506 { 507 struct mt76_mib_stats *mib = &phy->mib; 508 static const char * const bw[] = { 509 "BW20", "BW40", "BW80", "BW160", "BW320" 510 }; 511 512 /* Tx Beamformer monitor */ 513 seq_puts(s, "\nTx Beamformer applied PPDU counts: "); 514 515 seq_printf(s, "iBF: %d, eBF: %d\n", 516 mib->tx_bf_ibf_ppdu_cnt, 517 mib->tx_bf_ebf_ppdu_cnt); 518 519 /* Tx Beamformer Rx feedback monitor */ 520 seq_puts(s, "Tx Beamformer Rx feedback statistics: "); 521 522 seq_printf(s, "All: %d, EHT: %d, HE: %d, VHT: %d, HT: %d, ", 523 mib->tx_bf_rx_fb_all_cnt, 524 mib->tx_bf_rx_fb_eht_cnt, 525 mib->tx_bf_rx_fb_he_cnt, 526 mib->tx_bf_rx_fb_vht_cnt, 527 mib->tx_bf_rx_fb_ht_cnt); 528 529 seq_printf(s, "%s, NC: %d, NR: %d\n", 530 bw[mib->tx_bf_rx_fb_bw], 531 mib->tx_bf_rx_fb_nc_cnt, 532 mib->tx_bf_rx_fb_nr_cnt); 533 534 /* Tx Beamformee Rx NDPA & Tx feedback report */ 535 seq_printf(s, "Tx Beamformee successful feedback frames: %d\n", 536 mib->tx_bf_fb_cpl_cnt); 537 seq_printf(s, "Tx Beamformee feedback triggered counts: %d\n", 538 mib->tx_bf_fb_trig_cnt); 539 540 /* Tx SU & MU counters */ 541 seq_printf(s, "Tx multi-user Beamforming counts: %d\n", 542 mib->tx_mu_bf_cnt); 543 seq_printf(s, "Tx multi-user MPDU counts: %d\n", mib->tx_mu_mpdu_cnt); 544 seq_printf(s, "Tx multi-user successful MPDU counts: %d\n", 545 mib->tx_mu_acked_mpdu_cnt); 546 seq_printf(s, "Tx single-user successful MPDU counts: %d\n", 547 mib->tx_su_acked_mpdu_cnt); 548 549 seq_puts(s, "\n"); 550 } 551 552 static void 553 mt7996_tx_stats_show_phy(struct seq_file *file, struct mt7996_phy *phy) 554 { 555 struct mt76_mib_stats *mib = &phy->mib; 556 u32 attempts, success, per; 557 int i; 558 559 mt7996_mac_update_stats(phy); 560 mt7996_ampdu_stat_read_phy(phy, file); 561 562 attempts = mib->tx_mpdu_attempts_cnt; 563 success = mib->tx_mpdu_success_cnt; 564 per = attempts ? 100 - success * 100 / attempts : 100; 565 seq_printf(file, "Tx attempts: %8u (MPDUs)\n", attempts); 566 seq_printf(file, "Tx success: %8u (MPDUs)\n", success); 567 seq_printf(file, "Tx PER: %u%%\n", per); 568 569 mt7996_txbf_stat_read_phy(phy, file); 570 571 /* Tx amsdu info */ 572 seq_puts(file, "Tx MSDU statistics:\n"); 573 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 574 seq_printf(file, "AMSDU pack count of %d MSDU in TXD: %8d ", 575 i + 1, mib->tx_amsdu[i]); 576 if (mib->tx_amsdu_cnt) 577 seq_printf(file, "(%3d%%)\n", 578 mib->tx_amsdu[i] * 100 / mib->tx_amsdu_cnt); 579 else 580 seq_puts(file, "\n"); 581 } 582 } 583 584 static int 585 mt7996_tx_stats_show(struct seq_file *file, void *data) 586 { 587 struct mt7996_dev *dev = file->private; 588 struct mt7996_phy *phy = &dev->phy; 589 590 mutex_lock(&dev->mt76.mutex); 591 592 mt7996_tx_stats_show_phy(file, phy); 593 phy = mt7996_phy2(dev); 594 if (phy) 595 mt7996_tx_stats_show_phy(file, phy); 596 phy = mt7996_phy3(dev); 597 if (phy) 598 mt7996_tx_stats_show_phy(file, phy); 599 600 mutex_unlock(&dev->mt76.mutex); 601 602 return 0; 603 } 604 605 DEFINE_SHOW_ATTRIBUTE(mt7996_tx_stats); 606 607 static void 608 mt7996_hw_queue_read(struct seq_file *s, u32 size, 609 const struct hw_queue_map *map) 610 { 611 struct mt7996_phy *phy = s->private; 612 struct mt7996_dev *dev = phy->dev; 613 u32 i, val; 614 615 val = mt76_rr(dev, MT_FL_Q_EMPTY); 616 for (i = 0; i < size; i++) { 617 u32 ctrl, head, tail, queued; 618 619 if (val & BIT(map[i].index)) 620 continue; 621 622 ctrl = BIT(31) | (map[i].pid << 10) | ((u32)map[i].qid << 24); 623 mt76_wr(dev, MT_FL_Q0_CTRL, ctrl); 624 625 head = mt76_get_field(dev, MT_FL_Q2_CTRL, 626 GENMASK(11, 0)); 627 tail = mt76_get_field(dev, MT_FL_Q2_CTRL, 628 GENMASK(27, 16)); 629 queued = mt76_get_field(dev, MT_FL_Q3_CTRL, 630 GENMASK(11, 0)); 631 632 seq_printf(s, "\t%s: ", map[i].name); 633 seq_printf(s, "queued:0x%03x head:0x%03x tail:0x%03x\n", 634 queued, head, tail); 635 } 636 } 637 638 static void 639 mt7996_sta_hw_queue_read(void *data, struct ieee80211_sta *sta) 640 { 641 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 642 struct mt7996_vif *mvif = msta->vif; 643 struct mt7996_phy *phy = mt7996_vif_link_phy(&mvif->deflink); 644 struct ieee80211_link_sta *link_sta; 645 struct seq_file *s = data; 646 struct ieee80211_vif *vif; 647 struct mt7996_dev *dev; 648 unsigned int link_id; 649 650 if (!phy) 651 return; 652 653 vif = container_of((void *)mvif, struct ieee80211_vif, drv_priv); 654 dev = phy->dev; 655 656 rcu_read_lock(); 657 658 for_each_sta_active_link(vif, sta, link_sta, link_id) { 659 struct mt7996_sta_link *msta_link; 660 struct mt76_vif_link *mlink; 661 u8 ac; 662 663 mlink = rcu_dereference(mvif->mt76.link[link_id]); 664 if (!mlink) 665 continue; 666 667 msta_link = rcu_dereference(msta->link[link_id]); 668 if (!msta_link) 669 continue; 670 671 for (ac = 0; ac < 4; ac++) { 672 u32 idx = msta_link->wcid.idx >> 5, qlen, ctrl, val; 673 u8 offs = msta_link->wcid.idx & GENMASK(4, 0); 674 675 ctrl = BIT(31) | BIT(11) | (ac << 24); 676 val = mt76_rr(dev, MT_PLE_AC_QEMPTY(ac, idx)); 677 678 if (val & BIT(offs)) 679 continue; 680 681 mt76_wr(dev, 682 MT_FL_Q0_CTRL, ctrl | msta_link->wcid.idx); 683 qlen = mt76_get_field(dev, MT_FL_Q3_CTRL, 684 GENMASK(11, 0)); 685 seq_printf(s, "\tSTA %pM wcid %d: AC%d%d queued:%d\n", 686 sta->addr, msta_link->wcid.idx, 687 mlink->wmm_idx, ac, qlen); 688 } 689 } 690 691 rcu_read_unlock(); 692 } 693 694 static int 695 mt7996_hw_queues_show(struct seq_file *file, void *data) 696 { 697 struct mt7996_dev *dev = file->private; 698 struct mt7996_phy *phy = &dev->phy; 699 static const struct hw_queue_map ple_queue_map[] = { 700 { "CPU_Q0", 0, 1, MT_CTX0 }, 701 { "CPU_Q1", 1, 1, MT_CTX0 + 1 }, 702 { "CPU_Q2", 2, 1, MT_CTX0 + 2 }, 703 { "CPU_Q3", 3, 1, MT_CTX0 + 3 }, 704 { "ALTX_Q0", 8, 2, MT_LMAC_ALTX0 }, 705 { "BMC_Q0", 9, 2, MT_LMAC_BMC0 }, 706 { "BCN_Q0", 10, 2, MT_LMAC_BCN0 }, 707 { "PSMP_Q0", 11, 2, MT_LMAC_PSMP0 }, 708 { "ALTX_Q1", 12, 2, MT_LMAC_ALTX0 + 4 }, 709 { "BMC_Q1", 13, 2, MT_LMAC_BMC0 + 4 }, 710 { "BCN_Q1", 14, 2, MT_LMAC_BCN0 + 4 }, 711 { "PSMP_Q1", 15, 2, MT_LMAC_PSMP0 + 4 }, 712 }; 713 static const struct hw_queue_map pse_queue_map[] = { 714 { "CPU Q0", 0, 1, MT_CTX0 }, 715 { "CPU Q1", 1, 1, MT_CTX0 + 1 }, 716 { "CPU Q2", 2, 1, MT_CTX0 + 2 }, 717 { "CPU Q3", 3, 1, MT_CTX0 + 3 }, 718 { "HIF_Q0", 8, 0, MT_HIF0 }, 719 { "HIF_Q1", 9, 0, MT_HIF0 + 1 }, 720 { "HIF_Q2", 10, 0, MT_HIF0 + 2 }, 721 { "HIF_Q3", 11, 0, MT_HIF0 + 3 }, 722 { "HIF_Q4", 12, 0, MT_HIF0 + 4 }, 723 { "HIF_Q5", 13, 0, MT_HIF0 + 5 }, 724 { "LMAC_Q", 16, 2, 0 }, 725 { "MDP_TXQ", 17, 2, 1 }, 726 { "MDP_RXQ", 18, 2, 2 }, 727 { "SEC_TXQ", 19, 2, 3 }, 728 { "SEC_RXQ", 20, 2, 4 }, 729 }; 730 u32 val, head, tail; 731 732 /* ple queue */ 733 val = mt76_rr(dev, MT_PLE_FREEPG_CNT); 734 head = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(11, 0)); 735 tail = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(27, 16)); 736 seq_puts(file, "PLE page info:\n"); 737 seq_printf(file, 738 "\tTotal free page: 0x%08x head: 0x%03x tail: 0x%03x\n", 739 val, head, tail); 740 741 val = mt76_rr(dev, MT_PLE_PG_HIF_GROUP); 742 head = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(11, 0)); 743 tail = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(27, 16)); 744 seq_printf(file, "\tHIF free page: 0x%03x res: 0x%03x used: 0x%03x\n", 745 val, head, tail); 746 747 seq_puts(file, "PLE non-empty queue info:\n"); 748 mt7996_hw_queue_read(file, ARRAY_SIZE(ple_queue_map), 749 &ple_queue_map[0]); 750 751 /* iterate per-sta ple queue */ 752 ieee80211_iterate_stations_atomic(phy->mt76->hw, 753 mt7996_sta_hw_queue_read, file); 754 phy = mt7996_phy2(dev); 755 if (phy) 756 ieee80211_iterate_stations_atomic(phy->mt76->hw, 757 mt7996_sta_hw_queue_read, file); 758 phy = mt7996_phy3(dev); 759 if (phy) 760 ieee80211_iterate_stations_atomic(phy->mt76->hw, 761 mt7996_sta_hw_queue_read, file); 762 763 /* pse queue */ 764 seq_puts(file, "PSE non-empty queue info:\n"); 765 mt7996_hw_queue_read(file, ARRAY_SIZE(pse_queue_map), 766 &pse_queue_map[0]); 767 768 return 0; 769 } 770 771 DEFINE_SHOW_ATTRIBUTE(mt7996_hw_queues); 772 773 static int 774 mt7996_xmit_queues_show(struct seq_file *file, void *data) 775 { 776 struct mt7996_dev *dev = file->private; 777 struct mt7996_phy *phy; 778 struct { 779 struct mt76_queue *q; 780 char *queue; 781 } queue_map[] = { 782 { dev->mphy.q_tx[MT_TXQ_BE], " MAIN0" }, 783 { NULL, " MAIN1" }, 784 { NULL, " MAIN2" }, 785 { dev->mt76.q_mcu[MT_MCUQ_WM], " MCUWM" }, 786 { dev->mt76.q_mcu[MT_MCUQ_WA], " MCUWA" }, 787 { dev->mt76.q_mcu[MT_MCUQ_FWDL], "MCUFWDL" }, 788 }; 789 int i; 790 791 phy = mt7996_phy2(dev); 792 if (phy) 793 queue_map[1].q = phy->mt76->q_tx[MT_TXQ_BE]; 794 795 phy = mt7996_phy3(dev); 796 if (phy) 797 queue_map[2].q = phy->mt76->q_tx[MT_TXQ_BE]; 798 799 seq_puts(file, " queue | hw-queued | head | tail |\n"); 800 for (i = 0; i < ARRAY_SIZE(queue_map); i++) { 801 struct mt76_queue *q = queue_map[i].q; 802 803 if (!q) 804 continue; 805 806 seq_printf(file, " %s | %9d | %9d | %9d |\n", 807 queue_map[i].queue, q->queued, q->head, 808 q->tail); 809 } 810 811 return 0; 812 } 813 814 DEFINE_SHOW_ATTRIBUTE(mt7996_xmit_queues); 815 816 static int 817 mt7996_twt_stats(struct seq_file *s, void *data) 818 { 819 struct mt7996_dev *dev = dev_get_drvdata(s->private); 820 struct mt7996_twt_flow *iter; 821 822 rcu_read_lock(); 823 824 seq_puts(s, " wcid | id | flags | exp | mantissa"); 825 seq_puts(s, " | duration | tsf |\n"); 826 list_for_each_entry_rcu(iter, &dev->twt_list, list) 827 seq_printf(s, 828 "%9d | %8d | %5c%c%c%c | %8d | %8d | %8d | %14lld |\n", 829 iter->wcid, iter->id, 830 iter->sched ? 's' : 'u', 831 iter->protection ? 'p' : '-', 832 iter->trigger ? 't' : '-', 833 iter->flowtype ? '-' : 'a', 834 iter->exp, iter->mantissa, 835 iter->duration, iter->tsf); 836 837 rcu_read_unlock(); 838 839 return 0; 840 } 841 842 /* The index of RF registers use the generic regidx, combined with two parts: 843 * WF selection [31:24] and offset [23:0]. 844 */ 845 static int 846 mt7996_rf_regval_get(void *data, u64 *val) 847 { 848 struct mt7996_dev *dev = data; 849 u32 regval; 850 int ret; 851 852 ret = mt7996_mcu_rf_regval(dev, dev->mt76.debugfs_reg, ®val, false); 853 if (ret) 854 return ret; 855 856 *val = regval; 857 858 return 0; 859 } 860 861 static int 862 mt7996_rf_regval_set(void *data, u64 val) 863 { 864 struct mt7996_dev *dev = data; 865 u32 val32 = val; 866 867 return mt7996_mcu_rf_regval(dev, dev->mt76.debugfs_reg, &val32, true); 868 } 869 870 DEFINE_DEBUGFS_ATTRIBUTE(fops_rf_regval, mt7996_rf_regval_get, 871 mt7996_rf_regval_set, "0x%08llx\n"); 872 873 int mt7996_init_debugfs(struct mt7996_dev *dev) 874 { 875 struct dentry *dir; 876 877 dir = mt76_register_debugfs_fops(&dev->mphy, NULL); 878 if (!dir) 879 return -ENOMEM; 880 881 debugfs_create_file("hw-queues", 0400, dir, dev, 882 &mt7996_hw_queues_fops); 883 debugfs_create_file("xmit-queues", 0400, dir, dev, 884 &mt7996_xmit_queues_fops); 885 debugfs_create_file("tx_stats", 0400, dir, dev, &mt7996_tx_stats_fops); 886 debugfs_create_file("sys_recovery", 0600, dir, dev, 887 &mt7996_sys_recovery_ops); 888 debugfs_create_file("fw_debug_wm", 0600, dir, dev, &fops_fw_debug_wm); 889 debugfs_create_file("fw_debug_wa", 0600, dir, dev, &fops_fw_debug_wa); 890 debugfs_create_file("fw_debug_bin", 0600, dir, dev, &fops_fw_debug_bin); 891 /* TODO: wm fw cpu utilization */ 892 debugfs_create_file("fw_util_wa", 0400, dir, dev, 893 &mt7996_fw_util_wa_fops); 894 debugfs_create_file("implicit_txbf", 0600, dir, dev, 895 &fops_implicit_txbf); 896 debugfs_create_devm_seqfile(dev->mt76.dev, "twt_stats", dir, 897 mt7996_twt_stats); 898 debugfs_create_file("rf_regval", 0600, dir, dev, &fops_rf_regval); 899 900 debugfs_create_u32("dfs_hw_pattern", 0400, dir, &dev->hw_pattern); 901 debugfs_create_file("radar_trigger", 0200, dir, dev, 902 &fops_radar_trigger); 903 debugfs_create_devm_seqfile(dev->mt76.dev, "rdd_monitor", dir, 904 mt7996_rdd_monitor); 905 906 dev->debugfs_dir = dir; 907 908 return 0; 909 } 910 911 static void 912 mt7996_debugfs_write_fwlog(struct mt7996_dev *dev, const void *hdr, int hdrlen, 913 const void *data, int len) 914 { 915 static DEFINE_SPINLOCK(lock); 916 unsigned long flags; 917 void *dest; 918 919 spin_lock_irqsave(&lock, flags); 920 dest = relay_reserve(dev->relay_fwlog, hdrlen + len + 4); 921 if (dest) { 922 *(u32 *)dest = hdrlen + len; 923 dest += 4; 924 925 if (hdrlen) { 926 memcpy(dest, hdr, hdrlen); 927 dest += hdrlen; 928 } 929 930 memcpy(dest, data, len); 931 relay_flush(dev->relay_fwlog); 932 } 933 spin_unlock_irqrestore(&lock, flags); 934 } 935 936 void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len) 937 { 938 struct { 939 __le32 magic; 940 u8 version; 941 u8 _rsv; 942 __le16 serial_id; 943 __le32 timestamp; 944 __le16 msg_type; 945 __le16 len; 946 } hdr = { 947 .version = 0x1, 948 .magic = cpu_to_le32(FW_BIN_LOG_MAGIC), 949 .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR), 950 }; 951 952 if (!dev->relay_fwlog) 953 return; 954 955 hdr.serial_id = cpu_to_le16(dev->fw_debug_seq++); 956 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0))); 957 hdr.len = *(__le16 *)data; 958 mt7996_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len); 959 } 960 961 bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len) 962 { 963 if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC) 964 return false; 965 966 if (dev->relay_fwlog) 967 mt7996_debugfs_write_fwlog(dev, NULL, 0, data, len); 968 969 return true; 970 } 971 972 #ifdef CONFIG_MAC80211_DEBUGFS 973 /** per-station debugfs **/ 974 975 static int 976 mt7996_queues_show(struct seq_file *s, void *data) 977 { 978 struct ieee80211_sta *sta = s->private; 979 980 mt7996_sta_hw_queue_read(s, sta); 981 982 return 0; 983 } 984 985 DEFINE_SHOW_ATTRIBUTE(mt7996_queues); 986 987 void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 988 struct ieee80211_sta *sta, struct dentry *dir) 989 { 990 debugfs_create_file("hw-queues", 0400, dir, sta, &mt7996_queues_fops); 991 } 992 993 static ssize_t mt7996_link_sta_fixed_rate_set(struct file *file, 994 const char __user *user_buf, 995 size_t count, loff_t *ppos) 996 { 997 #define SHORT_PREAMBLE 0 998 #define LONG_PREAMBLE 1 999 struct ieee80211_link_sta *link_sta = file->private_data; 1000 struct mt7996_sta *msta = (struct mt7996_sta *)link_sta->sta->drv_priv; 1001 struct mt7996_phy *link_phy = mt7996_vif_link_phy(&msta->vif->deflink); 1002 struct mt7996_sta_link *msta_link; 1003 struct ra_rate phy = {}; 1004 struct mt7996_dev *dev; 1005 char buf[100]; 1006 int ret; 1007 u16 gi, ltf; 1008 1009 if (!link_phy) 1010 return -EINVAL; 1011 1012 if (count >= sizeof(buf)) 1013 return -EINVAL; 1014 1015 if (copy_from_user(buf, user_buf, count)) 1016 return -EFAULT; 1017 1018 if (count && buf[count - 1] == '\n') 1019 buf[count - 1] = '\0'; 1020 else 1021 buf[count] = '\0'; 1022 1023 /* mode - cck: 0, ofdm: 1, ht: 2, gf: 3, vht: 4, he_su: 8, he_er: 9 EHT: 15 1024 * bw - bw20: 0, bw40: 1, bw80: 2, bw160: 3, BW320: 4 1025 * mcs - cck: 0~4, ofdm: 0~7, ht: 0~32, vht: 0~9, he_su: 0~11, he_er: 0~2, eht: 0~13 1026 * nss - vht: 1~4, he: 1~4, eht: 1~4, others: ignore 1027 * gi - (ht/vht) lgi: 0, sgi: 1; (he) 0.8us: 0, 1.6us: 1, 3.2us: 2 1028 * preamble - short: 1, long: 0 1029 * stbc - off: 0, on: 1 1030 * ldpc - off: 0, on: 1 1031 * spe - off: 0, on: 1 1032 * ltf - 1xltf: 0, 2xltf: 1, 4xltf: 2 1033 */ 1034 dev = link_phy->dev; 1035 if (sscanf(buf, "%hhu %hhu %hhu %hhu %hu %hhu %hhu %hhu %hhu %hu", 1036 &phy.mode, &phy.bw, &phy.mcs, &phy.nss, &gi, 1037 &phy.preamble, &phy.stbc, &phy.ldpc, &phy.spe, <f) != 10) { 1038 dev_warn(dev->mt76.dev, 1039 "format: Mode BW MCS NSS GI Preamble STBC LDPC SPE ltf\n"); 1040 return -EINVAL; 1041 } 1042 1043 mutex_lock(&dev->mt76.mutex); 1044 1045 msta_link = mt76_dereference(msta->link[link_sta->link_id], &dev->mt76); 1046 if (!msta_link) { 1047 ret = -EINVAL; 1048 goto out; 1049 } 1050 phy.wlan_idx = cpu_to_le16(msta_link->wcid.idx); 1051 phy.gi = cpu_to_le16(gi); 1052 phy.ltf = cpu_to_le16(ltf); 1053 phy.ldpc = phy.ldpc ? 7 : 0; 1054 phy.preamble = phy.preamble ? SHORT_PREAMBLE : LONG_PREAMBLE; 1055 1056 ret = mt7996_mcu_set_fixed_rate_ctrl(dev, &phy, 0); 1057 if (ret) 1058 goto out; 1059 1060 ret = count; 1061 out: 1062 mutex_unlock(&dev->mt76.mutex); 1063 return ret; 1064 } 1065 1066 static const struct file_operations fops_fixed_rate = { 1067 .write = mt7996_link_sta_fixed_rate_set, 1068 .open = simple_open, 1069 .owner = THIS_MODULE, 1070 .llseek = default_llseek, 1071 }; 1072 1073 void mt7996_link_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1074 struct ieee80211_link_sta *link_sta, 1075 struct dentry *dir) 1076 { 1077 debugfs_create_file("fixed_rate", 0600, dir, link_sta, &fops_fixed_rate); 1078 } 1079 1080 #endif 1081