1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #include <linux/etherdevice.h>
5 #include <linux/hwmon.h>
6 #include <linux/hwmon-sysfs.h>
7 #include <linux/of.h>
8 #include <linux/thermal.h>
9 #include "mt7915.h"
10 #include "mac.h"
11 #include "mcu.h"
12 #include "coredump.h"
13 #include "eeprom.h"
14
15 static const struct ieee80211_iface_limit if_limits[] = {
16 {
17 .max = 1,
18 .types = BIT(NL80211_IFTYPE_ADHOC)
19 }, {
20 .max = 16,
21 .types = BIT(NL80211_IFTYPE_AP)
22 #ifdef CONFIG_MAC80211_MESH
23 | BIT(NL80211_IFTYPE_MESH_POINT)
24 #endif
25 }, {
26 .max = MT7915_MAX_INTERFACES,
27 .types = BIT(NL80211_IFTYPE_STATION)
28 }
29 };
30
31 static const struct ieee80211_iface_combination if_comb[] = {
32 {
33 .limits = if_limits,
34 .n_limits = ARRAY_SIZE(if_limits),
35 .max_interfaces = MT7915_MAX_INTERFACES,
36 .num_different_channels = 1,
37 .beacon_int_infra_match = true,
38 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
39 BIT(NL80211_CHAN_WIDTH_20) |
40 BIT(NL80211_CHAN_WIDTH_40) |
41 BIT(NL80211_CHAN_WIDTH_80) |
42 BIT(NL80211_CHAN_WIDTH_160),
43 }
44 };
45
mt7915_thermal_temp_show(struct device * dev,struct device_attribute * attr,char * buf)46 static ssize_t mt7915_thermal_temp_show(struct device *dev,
47 struct device_attribute *attr,
48 char *buf)
49 {
50 struct mt7915_phy *phy = dev_get_drvdata(dev);
51 int i = to_sensor_dev_attr(attr)->index;
52 int temperature;
53
54 switch (i) {
55 case 0:
56 mutex_lock(&phy->dev->mt76.mutex);
57 temperature = mt7915_mcu_get_temperature(phy);
58 mutex_unlock(&phy->dev->mt76.mutex);
59 if (temperature < 0)
60 return temperature;
61 /* display in millidegree celcius */
62 return sprintf(buf, "%u\n", temperature * 1000);
63 case 1:
64 case 2:
65 return sprintf(buf, "%u\n",
66 phy->throttle_temp[i - 1] * 1000);
67 case 3:
68 return sprintf(buf, "%hhu\n", phy->throttle_state);
69 default:
70 return -EINVAL;
71 }
72 }
73
mt7915_thermal_temp_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)74 static ssize_t mt7915_thermal_temp_store(struct device *dev,
75 struct device_attribute *attr,
76 const char *buf, size_t count)
77 {
78 struct mt7915_phy *phy = dev_get_drvdata(dev);
79 int ret, i = to_sensor_dev_attr(attr)->index;
80 long val;
81
82 ret = kstrtol(buf, 10, &val);
83 if (ret < 0)
84 return ret;
85
86 mutex_lock(&phy->dev->mt76.mutex);
87 val = DIV_ROUND_CLOSEST(clamp_val(val, 60 * 1000, 130 * 1000), 1000);
88
89 if ((i - 1 == MT7915_CRIT_TEMP_IDX &&
90 val > phy->throttle_temp[MT7915_MAX_TEMP_IDX]) ||
91 (i - 1 == MT7915_MAX_TEMP_IDX &&
92 val < phy->throttle_temp[MT7915_CRIT_TEMP_IDX])) {
93 dev_err(phy->dev->mt76.dev,
94 "temp1_max shall be greater than temp1_crit.");
95 mutex_unlock(&phy->dev->mt76.mutex);
96 return -EINVAL;
97 }
98
99 phy->throttle_temp[i - 1] = val;
100 ret = mt7915_mcu_set_thermal_protect(phy);
101 mutex_unlock(&phy->dev->mt76.mutex);
102 if (ret)
103 return ret;
104
105 return count;
106 }
107
108 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7915_thermal_temp, 0);
109 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7915_thermal_temp, 1);
110 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7915_thermal_temp, 2);
111 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7915_thermal_temp, 3);
112
113 static struct attribute *mt7915_hwmon_attrs[] = {
114 &sensor_dev_attr_temp1_input.dev_attr.attr,
115 &sensor_dev_attr_temp1_crit.dev_attr.attr,
116 &sensor_dev_attr_temp1_max.dev_attr.attr,
117 &sensor_dev_attr_throttle1.dev_attr.attr,
118 NULL,
119 };
120 ATTRIBUTE_GROUPS(mt7915_hwmon);
121
122 static int
mt7915_thermal_get_max_throttle_state(struct thermal_cooling_device * cdev,unsigned long * state)123 mt7915_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev,
124 unsigned long *state)
125 {
126 *state = MT7915_CDEV_THROTTLE_MAX;
127
128 return 0;
129 }
130
131 static int
mt7915_thermal_get_cur_throttle_state(struct thermal_cooling_device * cdev,unsigned long * state)132 mt7915_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev,
133 unsigned long *state)
134 {
135 struct mt7915_phy *phy = cdev->devdata;
136
137 *state = phy->cdev_state;
138
139 return 0;
140 }
141
142 static int
mt7915_thermal_set_cur_throttle_state(struct thermal_cooling_device * cdev,unsigned long state)143 mt7915_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev,
144 unsigned long state)
145 {
146 struct mt7915_phy *phy = cdev->devdata;
147 u8 throttling = MT7915_THERMAL_THROTTLE_MAX - state;
148 int ret;
149
150 if (state > MT7915_CDEV_THROTTLE_MAX) {
151 dev_err(phy->dev->mt76.dev,
152 "please specify a valid throttling state\n");
153 return -EINVAL;
154 }
155
156 if (state == phy->cdev_state)
157 return 0;
158
159 /*
160 * cooling_device convention: 0 = no cooling, more = more cooling
161 * mcu convention: 1 = max cooling, more = less cooling
162 */
163 mutex_lock(&phy->dev->mt76.mutex);
164 ret = mt7915_mcu_set_thermal_throttling(phy, throttling);
165 mutex_unlock(&phy->dev->mt76.mutex);
166 if (ret)
167 return ret;
168
169 phy->cdev_state = state;
170
171 return 0;
172 }
173
174 static const struct thermal_cooling_device_ops mt7915_thermal_ops = {
175 .get_max_state = mt7915_thermal_get_max_throttle_state,
176 .get_cur_state = mt7915_thermal_get_cur_throttle_state,
177 .set_cur_state = mt7915_thermal_set_cur_throttle_state,
178 };
179
mt7915_unregister_thermal(struct mt7915_phy * phy)180 static void mt7915_unregister_thermal(struct mt7915_phy *phy)
181 {
182 struct wiphy *wiphy = phy->mt76->hw->wiphy;
183
184 if (!phy->cdev)
185 return;
186
187 sysfs_remove_link(&wiphy->dev.kobj, "cooling_device");
188 thermal_cooling_device_unregister(phy->cdev);
189 }
190
mt7915_thermal_init(struct mt7915_phy * phy)191 static int mt7915_thermal_init(struct mt7915_phy *phy)
192 {
193 struct wiphy *wiphy = phy->mt76->hw->wiphy;
194 struct thermal_cooling_device *cdev;
195 struct device *hwmon;
196 const char *name;
197
198 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7915_%s",
199 wiphy_name(wiphy));
200 if (!name)
201 return -ENOMEM;
202
203 cdev = thermal_cooling_device_register(name, phy, &mt7915_thermal_ops);
204 if (!IS_ERR(cdev)) {
205 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj,
206 "cooling_device") < 0)
207 thermal_cooling_device_unregister(cdev);
208 else
209 phy->cdev = cdev;
210 }
211
212 /* initialize critical/maximum high temperature */
213 phy->throttle_temp[MT7915_CRIT_TEMP_IDX] = MT7915_CRIT_TEMP;
214 phy->throttle_temp[MT7915_MAX_TEMP_IDX] = MT7915_MAX_TEMP;
215
216 if (!IS_REACHABLE(CONFIG_HWMON))
217 return 0;
218
219 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy,
220 mt7915_hwmon_groups);
221 return PTR_ERR_OR_ZERO(hwmon);
222 }
223
mt7915_led_set_config(struct led_classdev * led_cdev,u8 delay_on,u8 delay_off)224 static void mt7915_led_set_config(struct led_classdev *led_cdev,
225 u8 delay_on, u8 delay_off)
226 {
227 struct mt7915_dev *dev;
228 struct mt76_phy *mphy;
229 u32 val;
230
231 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev);
232 dev = container_of(mphy->dev, struct mt7915_dev, mt76);
233
234 /* set PWM mode */
235 val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) |
236 FIELD_PREP(MT_LED_STATUS_OFF, delay_off) |
237 FIELD_PREP(MT_LED_STATUS_ON, delay_on);
238 mt76_wr(dev, MT_LED_STATUS_0(mphy->band_idx), val);
239 mt76_wr(dev, MT_LED_STATUS_1(mphy->band_idx), val);
240
241 /* enable LED */
242 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1);
243
244 /* control LED */
245 val = MT_LED_CTRL_KICK;
246 if (dev->mphy.leds.al)
247 val |= MT_LED_CTRL_POLARITY;
248 if (mphy->band_idx)
249 val |= MT_LED_CTRL_BAND;
250
251 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val);
252 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK);
253 }
254
mt7915_led_set_blink(struct led_classdev * led_cdev,unsigned long * delay_on,unsigned long * delay_off)255 static int mt7915_led_set_blink(struct led_classdev *led_cdev,
256 unsigned long *delay_on,
257 unsigned long *delay_off)
258 {
259 u16 delta_on = 0, delta_off = 0;
260
261 #define HW_TICK 10
262 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK)
263
264 if (*delay_on)
265 delta_on = TO_HW_TICK(*delay_on);
266 if (*delay_off)
267 delta_off = TO_HW_TICK(*delay_off);
268
269 mt7915_led_set_config(led_cdev, delta_on, delta_off);
270
271 return 0;
272 }
273
mt7915_led_set_brightness(struct led_classdev * led_cdev,enum led_brightness brightness)274 static void mt7915_led_set_brightness(struct led_classdev *led_cdev,
275 enum led_brightness brightness)
276 {
277 if (!brightness)
278 mt7915_led_set_config(led_cdev, 0, 0xff);
279 else
280 mt7915_led_set_config(led_cdev, 0xff, 0);
281 }
282
__mt7915_init_txpower(struct mt7915_phy * phy,struct ieee80211_supported_band * sband)283 static void __mt7915_init_txpower(struct mt7915_phy *phy,
284 struct ieee80211_supported_band *sband)
285 {
286 struct mt7915_dev *dev = phy->dev;
287 int i, n_chains = hweight16(phy->mt76->chainmask);
288 int path_delta = mt76_tx_power_path_delta(n_chains);
289 int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band);
290 struct mt76_power_limits limits;
291
292 phy->sku_limit_en = true;
293 phy->sku_path_en = true;
294 for (i = 0; i < sband->n_channels; i++) {
295 struct ieee80211_channel *chan = &sband->channels[i];
296 u32 target_power = 0;
297 int j;
298
299 for (j = 0; j < n_chains; j++) {
300 u32 val;
301
302 val = mt7915_eeprom_get_target_power(dev, chan, j);
303 target_power = max(target_power, val);
304 }
305
306 target_power += pwr_delta;
307 target_power = mt76_get_rate_power_limits(phy->mt76, chan,
308 &limits,
309 target_power);
310
311 /* MT7915N can not enable Backoff table without setting value in dts */
312 if (!limits.path.ofdm[0])
313 phy->sku_path_en = false;
314
315 target_power += path_delta;
316 target_power = DIV_ROUND_UP(target_power, 2);
317 chan->max_power = min_t(int, chan->max_reg_power,
318 target_power);
319 chan->orig_mpwr = target_power;
320 }
321 }
322
mt7915_init_txpower(struct mt7915_phy * phy)323 void mt7915_init_txpower(struct mt7915_phy *phy)
324 {
325 if (!phy)
326 return;
327
328 if (phy->mt76->cap.has_2ghz)
329 __mt7915_init_txpower(phy, &phy->mt76->sband_2g.sband);
330 if (phy->mt76->cap.has_5ghz)
331 __mt7915_init_txpower(phy, &phy->mt76->sband_5g.sband);
332 if (phy->mt76->cap.has_6ghz)
333 __mt7915_init_txpower(phy, &phy->mt76->sband_6g.sband);
334 }
335
336 static void
mt7915_regd_notifier(struct wiphy * wiphy,struct regulatory_request * request)337 mt7915_regd_notifier(struct wiphy *wiphy,
338 struct regulatory_request *request)
339 {
340 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
341 struct mt7915_dev *dev = mt7915_hw_dev(hw);
342 struct mt76_phy *mphy = hw->priv;
343 struct mt7915_phy *phy = mphy->priv;
344
345 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2));
346 dev->mt76.region = request->dfs_region;
347
348 if (dev->mt76.region == NL80211_DFS_UNSET)
349 mt7915_mcu_rdd_background_enable(phy, NULL);
350
351 mt7915_init_txpower(phy);
352
353 mphy->dfs_state = MT_DFS_STATE_UNKNOWN;
354 mt7915_dfs_init_radar_detector(phy);
355 }
356
357 static void
mt7915_init_wiphy(struct mt7915_phy * phy)358 mt7915_init_wiphy(struct mt7915_phy *phy)
359 {
360 struct mt76_phy *mphy = phy->mt76;
361 struct ieee80211_hw *hw = mphy->hw;
362 struct mt76_dev *mdev = &phy->dev->mt76;
363 struct wiphy *wiphy = hw->wiphy;
364 struct mt7915_dev *dev = phy->dev;
365
366 hw->queues = 4;
367 hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE;
368 hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE;
369 hw->netdev_features = NETIF_F_RXCSUM;
370
371 if (mtk_wed_device_active(&mdev->mmio.wed))
372 hw->netdev_features |= NETIF_F_HW_TC;
373
374 hw->radiotap_timestamp.units_pos =
375 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US;
376
377 phy->slottime = 9;
378
379 hw->sta_data_size = sizeof(struct mt7915_sta);
380 hw->vif_data_size = sizeof(struct mt7915_vif);
381
382 wiphy->iface_combinations = if_comb;
383 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
384 wiphy->reg_notifier = mt7915_regd_notifier;
385 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
386 wiphy->mbssid_max_interfaces = 16;
387
388 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR);
389 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS);
390 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY);
391 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT);
392 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT);
393 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE);
394 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP);
395 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY);
396 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT);
397 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
398
399 if (!is_mt7915(&dev->mt76))
400 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_STA_TX_PWR);
401
402 if (mt7915_eeprom_has_background_radar(phy->dev) &&
403 (!mdev->dev->of_node ||
404 !of_property_read_bool(mdev->dev->of_node,
405 "mediatek,disable-radar-background")))
406 wiphy_ext_feature_set(wiphy,
407 NL80211_EXT_FEATURE_RADAR_BACKGROUND);
408
409 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
410 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD);
411 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD);
412 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
413 ieee80211_hw_set(hw, WANT_MONITOR_VIF);
414 ieee80211_hw_set(hw, SUPPORTS_TX_FRAG);
415
416 hw->max_tx_fragments = 4;
417
418 if (phy->mt76->cap.has_2ghz) {
419 phy->mt76->sband_2g.sband.ht_cap.cap |=
420 IEEE80211_HT_CAP_LDPC_CODING |
421 IEEE80211_HT_CAP_MAX_AMSDU;
422 if (is_mt7915(&dev->mt76))
423 phy->mt76->sband_2g.sband.ht_cap.ampdu_density =
424 IEEE80211_HT_MPDU_DENSITY_4;
425 else
426 phy->mt76->sband_2g.sband.ht_cap.ampdu_density =
427 IEEE80211_HT_MPDU_DENSITY_2;
428 }
429
430 if (phy->mt76->cap.has_5ghz) {
431 struct ieee80211_sta_vht_cap *vht_cap;
432
433 vht_cap = &phy->mt76->sband_5g.sband.vht_cap;
434 phy->mt76->sband_5g.sband.ht_cap.cap |=
435 IEEE80211_HT_CAP_LDPC_CODING |
436 IEEE80211_HT_CAP_MAX_AMSDU;
437
438 if (is_mt7915(&dev->mt76)) {
439 phy->mt76->sband_5g.sband.ht_cap.ampdu_density =
440 IEEE80211_HT_MPDU_DENSITY_4;
441
442 vht_cap->cap |=
443 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 |
444 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK;
445
446 if (!dev->dbdc_support)
447 vht_cap->cap |=
448 IEEE80211_VHT_CAP_SHORT_GI_160 |
449 FIELD_PREP(IEEE80211_VHT_CAP_EXT_NSS_BW_MASK, 1);
450 } else {
451 phy->mt76->sband_5g.sband.ht_cap.ampdu_density =
452 IEEE80211_HT_MPDU_DENSITY_2;
453
454 vht_cap->cap |=
455 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
456 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK;
457
458 /* mt7916 dbdc with 2g 2x2 bw40 and 5g 2x2 bw160c */
459 vht_cap->cap |=
460 IEEE80211_VHT_CAP_SHORT_GI_160 |
461 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ;
462 }
463
464 if (!is_mt7915(&dev->mt76) || !dev->dbdc_support)
465 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW);
466 }
467
468 mt76_set_stream_caps(phy->mt76, true);
469 mt7915_set_stream_vht_txbf_caps(phy);
470 mt7915_set_stream_he_caps(phy);
471 mt7915_init_txpower(phy);
472
473 wiphy->available_antennas_rx = phy->mt76->antenna_mask;
474 wiphy->available_antennas_tx = phy->mt76->antenna_mask;
475
476 /* init led callbacks */
477 if (IS_ENABLED(CONFIG_MT76_LEDS)) {
478 mphy->leds.cdev.brightness_set = mt7915_led_set_brightness;
479 mphy->leds.cdev.blink_set = mt7915_led_set_blink;
480 }
481 }
482
483 static void
mt7915_mac_init_band(struct mt7915_dev * dev,u8 band)484 mt7915_mac_init_band(struct mt7915_dev *dev, u8 band)
485 {
486 u32 mask, set;
487
488 mt76_rmw_field(dev, MT_TMAC_CTCR0(band),
489 MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f);
490 mt76_set(dev, MT_TMAC_CTCR0(band),
491 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN |
492 MT_TMAC_CTCR0_INS_DDLMT_EN);
493
494 mask = MT_MDP_RCFR0_MCU_RX_MGMT |
495 MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR |
496 MT_MDP_RCFR0_MCU_RX_CTL_BAR;
497 set = FIELD_PREP(MT_MDP_RCFR0_MCU_RX_MGMT, MT_MDP_TO_HIF) |
498 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR, MT_MDP_TO_HIF) |
499 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_BAR, MT_MDP_TO_HIF);
500 mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set);
501
502 mask = MT_MDP_RCFR1_MCU_RX_BYPASS |
503 MT_MDP_RCFR1_RX_DROPPED_UCAST |
504 MT_MDP_RCFR1_RX_DROPPED_MCAST;
505 set = FIELD_PREP(MT_MDP_RCFR1_MCU_RX_BYPASS, MT_MDP_TO_HIF) |
506 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_UCAST, MT_MDP_TO_HIF) |
507 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_MCAST, MT_MDP_TO_HIF);
508 mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set);
509
510 mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680);
511
512 /* mt7915: disable rx rate report by default due to hw issues */
513 mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN);
514
515 /* clear estimated value of EIFS for Rx duration & OBSS time */
516 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR);
517
518 /* clear backoff time for Rx duration */
519 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band),
520 MT_WF_RMAC_MIB_NONQOSD_BACKOFF);
521 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band),
522 MT_WF_RMAC_MIB_QOS01_BACKOFF);
523 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band),
524 MT_WF_RMAC_MIB_QOS23_BACKOFF);
525
526 /* clear backoff time for Tx duration */
527 mt76_clear(dev, MT_WTBLOFF_TOP_ACR(band),
528 MT_WTBLOFF_TOP_ADM_BACKOFFTIME);
529
530 /* exclude estimated backoff time for Tx duration on MT7915 */
531 if (is_mt7915(&dev->mt76))
532 mt76_set(dev, MT_AGG_ATCR0(band),
533 MT_AGG_ATCR_MAC_BFF_TIME_EN);
534
535 /* clear backoff time and set software compensation for OBSS time */
536 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET;
537 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) |
538 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4);
539 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set);
540
541 /* filter out non-resp frames and get instanstaeous signal reporting */
542 mask = MT_WTBLOFF_TOP_RSCR_RCPI_MODE | MT_WTBLOFF_TOP_RSCR_RCPI_PARAM;
543 set = FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_MODE, 0) |
544 FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_PARAM, 0x3);
545 mt76_rmw(dev, MT_WTBLOFF_TOP_RSCR(band), mask, set);
546
547 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than
548 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set.
549 */
550 if (mtk_wed_device_active(&dev->mt76.mmio.wed))
551 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H);
552 }
553
554 static void
mt7915_init_led_mux(struct mt7915_dev * dev)555 mt7915_init_led_mux(struct mt7915_dev *dev)
556 {
557 if (!IS_ENABLED(CONFIG_MT76_LEDS))
558 return;
559
560 if (dev->dbdc_support) {
561 switch (mt76_chip(&dev->mt76)) {
562 case 0x7915:
563 mt76_rmw_field(dev, MT_LED_GPIO_MUX2,
564 GENMASK(11, 8), 4);
565 mt76_rmw_field(dev, MT_LED_GPIO_MUX3,
566 GENMASK(11, 8), 4);
567 break;
568 case 0x7986:
569 mt76_rmw_field(dev, MT_LED_GPIO_MUX0,
570 GENMASK(7, 4), 1);
571 mt76_rmw_field(dev, MT_LED_GPIO_MUX0,
572 GENMASK(11, 8), 1);
573 break;
574 case 0x7916:
575 mt76_rmw_field(dev, MT_LED_GPIO_MUX1,
576 GENMASK(27, 24), 3);
577 mt76_rmw_field(dev, MT_LED_GPIO_MUX1,
578 GENMASK(31, 28), 3);
579 break;
580 default:
581 break;
582 }
583 } else if (dev->mphy.leds.pin) {
584 switch (mt76_chip(&dev->mt76)) {
585 case 0x7915:
586 mt76_rmw_field(dev, MT_LED_GPIO_MUX3,
587 GENMASK(11, 8), 4);
588 break;
589 case 0x7986:
590 mt76_rmw_field(dev, MT_LED_GPIO_MUX0,
591 GENMASK(11, 8), 1);
592 break;
593 case 0x7916:
594 mt76_rmw_field(dev, MT_LED_GPIO_MUX1,
595 GENMASK(31, 28), 3);
596 break;
597 default:
598 break;
599 }
600 } else {
601 switch (mt76_chip(&dev->mt76)) {
602 case 0x7915:
603 mt76_rmw_field(dev, MT_LED_GPIO_MUX2,
604 GENMASK(11, 8), 4);
605 break;
606 case 0x7986:
607 mt76_rmw_field(dev, MT_LED_GPIO_MUX0,
608 GENMASK(7, 4), 1);
609 break;
610 case 0x7916:
611 mt76_rmw_field(dev, MT_LED_GPIO_MUX1,
612 GENMASK(27, 24), 3);
613 break;
614 default:
615 break;
616 }
617 }
618 }
619
mt7915_mac_init(struct mt7915_dev * dev)620 void mt7915_mac_init(struct mt7915_dev *dev)
621 {
622 int i;
623 u32 rx_len = is_mt7915(&dev->mt76) ? 0x400 : 0x680;
624
625 /* config pse qid6 wfdma port selection */
626 if (!is_mt7915(&dev->mt76) && dev->hif2)
627 mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0,
628 MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK);
629
630 mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, rx_len);
631
632 if (!is_mt7915(&dev->mt76))
633 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT);
634 else
635 mt76_clear(dev, MT_PLE_HOST_RPT0, MT_PLE_HOST_RPT0_TX_LATENCY);
636
637 /* enable hardware de-agg */
638 mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN);
639
640 for (i = 0; i < mt7915_wtbl_size(dev); i++)
641 mt7915_mac_wtbl_update(dev, i,
642 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
643 for (i = 0; i < 2; i++)
644 mt7915_mac_init_band(dev, i);
645
646 mt7915_init_led_mux(dev);
647 }
648
mt7915_txbf_init(struct mt7915_dev * dev)649 int mt7915_txbf_init(struct mt7915_dev *dev)
650 {
651 int ret;
652
653 if (dev->dbdc_support) {
654 ret = mt7915_mcu_set_txbf(dev, MT_BF_MODULE_UPDATE);
655 if (ret)
656 return ret;
657 }
658
659 /* trigger sounding packets */
660 ret = mt7915_mcu_set_txbf(dev, MT_BF_SOUNDING_ON);
661 if (ret)
662 return ret;
663
664 /* enable eBF */
665 return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE);
666 }
667
668 static struct mt7915_phy *
mt7915_alloc_ext_phy(struct mt7915_dev * dev)669 mt7915_alloc_ext_phy(struct mt7915_dev *dev)
670 {
671 struct mt7915_phy *phy;
672 struct mt76_phy *mphy;
673
674 if (!dev->dbdc_support)
675 return NULL;
676
677 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7915_ops, MT_BAND1);
678 if (!mphy)
679 return ERR_PTR(-ENOMEM);
680
681 phy = mphy->priv;
682 phy->dev = dev;
683 phy->mt76 = mphy;
684
685 /* Bind main phy to band0 and ext_phy to band1 for dbdc case */
686 phy->mt76->band_idx = 1;
687
688 return phy;
689 }
690
691 static int
mt7915_register_ext_phy(struct mt7915_dev * dev,struct mt7915_phy * phy)692 mt7915_register_ext_phy(struct mt7915_dev *dev, struct mt7915_phy *phy)
693 {
694 struct mt76_phy *mphy = phy->mt76;
695 int ret;
696
697 INIT_DELAYED_WORK(&mphy->mac_work, mt7915_mac_work);
698
699 mt7915_eeprom_parse_hw_cap(dev, phy);
700
701 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR2,
702 ETH_ALEN);
703 /* Make the secondary PHY MAC address local without overlapping with
704 * the usual MAC address allocation scheme on multiple virtual interfaces
705 */
706 if (!is_valid_ether_addr(mphy->macaddr)) {
707 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR,
708 ETH_ALEN);
709 mphy->macaddr[0] |= 2;
710 mphy->macaddr[0] ^= BIT(7);
711 }
712 ret = mt76_eeprom_override(mphy);
713 if (ret)
714 return ret;
715
716 /* init wiphy according to mphy and phy */
717 mt7915_init_wiphy(phy);
718
719 ret = mt76_register_phy(mphy, true, mt76_rates,
720 ARRAY_SIZE(mt76_rates));
721 if (ret)
722 return ret;
723
724 ret = mt7915_thermal_init(phy);
725 if (ret)
726 goto unreg;
727
728 mt7915_init_debugfs(phy);
729
730 return 0;
731
732 unreg:
733 mt76_unregister_phy(mphy);
734 return ret;
735 }
736
mt7915_init_work(struct work_struct * work)737 static void mt7915_init_work(struct work_struct *work)
738 {
739 struct mt7915_dev *dev = container_of(work, struct mt7915_dev,
740 init_work);
741
742 mt7915_mcu_set_eeprom(dev);
743 mt7915_mac_init(dev);
744 mt7915_txbf_init(dev);
745 }
746
mt7915_wfsys_reset(struct mt7915_dev * dev)747 void mt7915_wfsys_reset(struct mt7915_dev *dev)
748 {
749 #define MT_MCU_DUMMY_RANDOM GENMASK(15, 0)
750 #define MT_MCU_DUMMY_DEFAULT GENMASK(31, 16)
751
752 if (is_mt7915(&dev->mt76)) {
753 u32 val = MT_TOP_PWR_KEY | MT_TOP_PWR_SW_PWR_ON | MT_TOP_PWR_PWR_ON;
754
755 mt76_wr(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_RANDOM);
756
757 /* change to software control */
758 val |= MT_TOP_PWR_SW_RST;
759 mt76_wr(dev, MT_TOP_PWR_CTRL, val);
760
761 /* reset wfsys */
762 val &= ~MT_TOP_PWR_SW_RST;
763 mt76_wr(dev, MT_TOP_PWR_CTRL, val);
764
765 /* release wfsys then mcu re-executes romcode */
766 val |= MT_TOP_PWR_SW_RST;
767 mt76_wr(dev, MT_TOP_PWR_CTRL, val);
768
769 /* switch to hw control */
770 val &= ~MT_TOP_PWR_SW_RST;
771 val |= MT_TOP_PWR_HW_CTRL;
772 mt76_wr(dev, MT_TOP_PWR_CTRL, val);
773
774 /* check whether mcu resets to default */
775 if (!mt76_poll_msec(dev, MT_MCU_WFDMA0_DUMMY_CR,
776 MT_MCU_DUMMY_DEFAULT, MT_MCU_DUMMY_DEFAULT,
777 1000)) {
778 dev_err(dev->mt76.dev, "wifi subsystem reset failure\n");
779 return;
780 }
781
782 /* wfsys reset won't clear host registers */
783 mt76_clear(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE);
784
785 msleep(100);
786 } else if (is_mt798x(&dev->mt76)) {
787 mt7986_wmac_disable(dev);
788 msleep(20);
789
790 mt7986_wmac_enable(dev);
791 msleep(20);
792 } else {
793 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1);
794 msleep(20);
795
796 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1);
797 msleep(20);
798 }
799 }
800
mt7915_band_config(struct mt7915_dev * dev)801 static bool mt7915_band_config(struct mt7915_dev *dev)
802 {
803 bool ret = true;
804
805 dev->phy.mt76->band_idx = 0;
806
807 if (is_mt798x(&dev->mt76)) {
808 u32 sku = mt7915_check_adie(dev, true);
809
810 /*
811 * for mt7986, dbdc support is determined by the number
812 * of adie chips and the main phy is bound to band1 when
813 * dbdc is disabled.
814 */
815 if (sku == MT7975_ONE_ADIE || sku == MT7976_ONE_ADIE) {
816 dev->phy.mt76->band_idx = 1;
817 ret = false;
818 }
819 } else {
820 ret = is_mt7915(&dev->mt76) ?
821 !!(mt76_rr(dev, MT_HW_BOUND) & BIT(5)) : true;
822 }
823
824 return ret;
825 }
826
827 static int
mt7915_init_hardware(struct mt7915_dev * dev,struct mt7915_phy * phy2)828 mt7915_init_hardware(struct mt7915_dev *dev, struct mt7915_phy *phy2)
829 {
830 int ret, idx;
831
832 mt76_wr(dev, MT_INT_MASK_CSR, 0);
833 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0);
834
835 INIT_WORK(&dev->init_work, mt7915_init_work);
836
837 ret = mt7915_dma_init(dev, phy2);
838 if (ret)
839 return ret;
840
841 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
842
843 ret = mt7915_mcu_init(dev);
844 if (ret)
845 return ret;
846
847 ret = mt7915_eeprom_init(dev);
848 if (ret < 0)
849 return ret;
850
851 if (dev->cal) {
852 ret = mt7915_mcu_apply_group_cal(dev);
853 if (ret)
854 return ret;
855 }
856
857 /* Beacon and mgmt frames should occupy wcid 0 */
858 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA);
859 if (idx)
860 return -ENOSPC;
861
862 dev->mt76.global_wcid.idx = idx;
863 dev->mt76.global_wcid.hw_key_idx = -1;
864 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET;
865 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid);
866
867 return 0;
868 }
869
mt7915_set_stream_vht_txbf_caps(struct mt7915_phy * phy)870 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy)
871 {
872 int sts;
873 u32 *cap;
874
875 if (!phy->mt76->cap.has_5ghz)
876 return;
877
878 sts = hweight8(phy->mt76->chainmask);
879 cap = &phy->mt76->sband_5g.sband.vht_cap.cap;
880
881 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
882 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
883 FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK,
884 sts - 1);
885
886 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK |
887 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
888 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE);
889
890 if (sts < 2)
891 return;
892
893 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
894 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE |
895 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK,
896 sts - 1);
897 }
898
899 static void
mt7915_set_stream_he_txbf_caps(struct mt7915_phy * phy,struct ieee80211_sta_he_cap * he_cap,int vif)900 mt7915_set_stream_he_txbf_caps(struct mt7915_phy *phy,
901 struct ieee80211_sta_he_cap *he_cap, int vif)
902 {
903 struct mt7915_dev *dev = phy->dev;
904 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem;
905 int sts = hweight8(phy->mt76->chainmask);
906 u8 c, sts_160 = sts;
907
908 /* Can do 1/2 of STS in 160Mhz mode for mt7915 */
909 if (is_mt7915(&dev->mt76)) {
910 if (!dev->dbdc_support)
911 sts_160 /= 2;
912 else
913 sts_160 = 0;
914 }
915
916 #ifdef CONFIG_MAC80211_MESH
917 if (vif == NL80211_IFTYPE_MESH_POINT)
918 return;
919 #endif
920
921 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
922 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
923
924 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK;
925 if (sts_160)
926 c |= IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK;
927 elem->phy_cap_info[5] &= ~c;
928
929 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
930 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
931 elem->phy_cap_info[6] &= ~c;
932
933 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK;
934
935 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US;
936 if (!is_mt7915(&dev->mt76))
937 c |= IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO;
938 elem->phy_cap_info[2] |= c;
939
940 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
941 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4;
942 if (sts_160)
943 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4;
944 elem->phy_cap_info[4] |= c;
945
946 /* do not support NG16 due to spec D4.0 changes subcarrier idx */
947 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
948 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU;
949
950 if (vif == NL80211_IFTYPE_STATION)
951 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO;
952
953 elem->phy_cap_info[6] |= c;
954
955 if (sts < 2)
956 return;
957
958 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */
959 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3;
960
961 if (vif != NL80211_IFTYPE_AP && vif != NL80211_IFTYPE_STATION)
962 return;
963
964 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
965
966 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK,
967 sts - 1);
968 if (sts_160)
969 c |= FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK,
970 sts_160 - 1);
971 elem->phy_cap_info[5] |= c;
972
973 if (vif != NL80211_IFTYPE_AP)
974 return;
975
976 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
977
978 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
979 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
980 elem->phy_cap_info[6] |= c;
981
982 if (!is_mt7915(&dev->mt76)) {
983 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ |
984 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ;
985 elem->phy_cap_info[7] |= c;
986 }
987 }
988
989 static int
mt7915_init_he_caps(struct mt7915_phy * phy,enum nl80211_band band,struct ieee80211_sband_iftype_data * data)990 mt7915_init_he_caps(struct mt7915_phy *phy, enum nl80211_band band,
991 struct ieee80211_sband_iftype_data *data)
992 {
993 struct mt7915_dev *dev = phy->dev;
994 int i, idx = 0, nss = hweight8(phy->mt76->antenna_mask);
995 u16 mcs_map = 0;
996 u16 mcs_map_160 = 0;
997 u8 nss_160;
998
999 if (!is_mt7915(&dev->mt76))
1000 nss_160 = nss;
1001 else if (!dev->dbdc_support)
1002 /* Can do 1/2 of NSS streams in 160Mhz mode for mt7915 */
1003 nss_160 = nss / 2;
1004 else
1005 /* Can't do 160MHz with mt7915 dbdc */
1006 nss_160 = 0;
1007
1008 for (i = 0; i < 8; i++) {
1009 if (i < nss)
1010 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2));
1011 else
1012 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2));
1013
1014 if (i < nss_160)
1015 mcs_map_160 |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2));
1016 else
1017 mcs_map_160 |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2));
1018 }
1019
1020 for (i = 0; i < NUM_NL80211_IFTYPES; i++) {
1021 struct ieee80211_sta_he_cap *he_cap = &data[idx].he_cap;
1022 struct ieee80211_he_cap_elem *he_cap_elem =
1023 &he_cap->he_cap_elem;
1024 struct ieee80211_he_mcs_nss_supp *he_mcs =
1025 &he_cap->he_mcs_nss_supp;
1026
1027 switch (i) {
1028 case NL80211_IFTYPE_STATION:
1029 case NL80211_IFTYPE_AP:
1030 #ifdef CONFIG_MAC80211_MESH
1031 case NL80211_IFTYPE_MESH_POINT:
1032 #endif
1033 break;
1034 default:
1035 continue;
1036 }
1037
1038 data[idx].types_mask = BIT(i);
1039 he_cap->has_he = true;
1040
1041 he_cap_elem->mac_cap_info[0] =
1042 IEEE80211_HE_MAC_CAP0_HTC_HE;
1043 he_cap_elem->mac_cap_info[3] =
1044 IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
1045 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3;
1046 he_cap_elem->mac_cap_info[4] =
1047 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU;
1048
1049 if (band == NL80211_BAND_2GHZ)
1050 he_cap_elem->phy_cap_info[0] =
1051 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
1052 else if (nss_160)
1053 he_cap_elem->phy_cap_info[0] =
1054 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
1055 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
1056 else
1057 he_cap_elem->phy_cap_info[0] =
1058 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G;
1059
1060 he_cap_elem->phy_cap_info[1] =
1061 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD;
1062 he_cap_elem->phy_cap_info[2] =
1063 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
1064 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ;
1065
1066 switch (i) {
1067 case NL80211_IFTYPE_AP:
1068 he_cap_elem->mac_cap_info[0] |=
1069 IEEE80211_HE_MAC_CAP0_TWT_RES;
1070 he_cap_elem->mac_cap_info[2] |=
1071 IEEE80211_HE_MAC_CAP2_BSR;
1072 he_cap_elem->mac_cap_info[4] |=
1073 IEEE80211_HE_MAC_CAP4_BQR;
1074 he_cap_elem->mac_cap_info[5] |=
1075 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX;
1076 he_cap_elem->phy_cap_info[3] |=
1077 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
1078 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
1079 he_cap_elem->phy_cap_info[6] |=
1080 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
1081 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
1082 he_cap_elem->phy_cap_info[9] |=
1083 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
1084 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU;
1085 break;
1086 case NL80211_IFTYPE_STATION:
1087 he_cap_elem->mac_cap_info[1] |=
1088 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US;
1089
1090 if (band == NL80211_BAND_2GHZ)
1091 he_cap_elem->phy_cap_info[0] |=
1092 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G;
1093 else
1094 he_cap_elem->phy_cap_info[0] |=
1095 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G;
1096
1097 he_cap_elem->phy_cap_info[1] |=
1098 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
1099 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US;
1100 he_cap_elem->phy_cap_info[3] |=
1101 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
1102 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
1103 he_cap_elem->phy_cap_info[6] |=
1104 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB |
1105 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
1106 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
1107 he_cap_elem->phy_cap_info[7] |=
1108 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
1109 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI;
1110 he_cap_elem->phy_cap_info[8] |=
1111 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
1112 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484;
1113 if (nss_160)
1114 he_cap_elem->phy_cap_info[8] |=
1115 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
1116 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU;
1117 he_cap_elem->phy_cap_info[9] |=
1118 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM |
1119 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK |
1120 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
1121 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU |
1122 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
1123 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB;
1124 break;
1125 }
1126
1127 memset(he_mcs, 0, sizeof(*he_mcs));
1128 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map);
1129 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map);
1130 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map_160);
1131 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map_160);
1132
1133 mt7915_set_stream_he_txbf_caps(phy, he_cap, i);
1134
1135 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres));
1136 if (he_cap_elem->phy_cap_info[6] &
1137 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) {
1138 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss, band);
1139 } else {
1140 he_cap_elem->phy_cap_info[9] |=
1141 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US,
1142 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK);
1143 }
1144
1145 if (band == NL80211_BAND_6GHZ) {
1146 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS |
1147 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS;
1148
1149 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_2,
1150 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
1151 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
1152 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
1153 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
1154 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
1155
1156 data[idx].he_6ghz_capa.capa = cpu_to_le16(cap);
1157 }
1158
1159 idx++;
1160 }
1161
1162 return idx;
1163 }
1164
mt7915_set_stream_he_caps(struct mt7915_phy * phy)1165 void mt7915_set_stream_he_caps(struct mt7915_phy *phy)
1166 {
1167 struct ieee80211_sband_iftype_data *data;
1168 struct ieee80211_supported_band *band;
1169 int n;
1170
1171 if (phy->mt76->cap.has_2ghz) {
1172 data = phy->iftype[NL80211_BAND_2GHZ];
1173 n = mt7915_init_he_caps(phy, NL80211_BAND_2GHZ, data);
1174
1175 band = &phy->mt76->sband_2g.sband;
1176 _ieee80211_set_sband_iftype_data(band, data, n);
1177 }
1178
1179 if (phy->mt76->cap.has_5ghz) {
1180 data = phy->iftype[NL80211_BAND_5GHZ];
1181 n = mt7915_init_he_caps(phy, NL80211_BAND_5GHZ, data);
1182
1183 band = &phy->mt76->sband_5g.sband;
1184 _ieee80211_set_sband_iftype_data(band, data, n);
1185 }
1186
1187 if (phy->mt76->cap.has_6ghz) {
1188 data = phy->iftype[NL80211_BAND_6GHZ];
1189 n = mt7915_init_he_caps(phy, NL80211_BAND_6GHZ, data);
1190
1191 band = &phy->mt76->sband_6g.sband;
1192 _ieee80211_set_sband_iftype_data(band, data, n);
1193 }
1194 }
1195
mt7915_unregister_ext_phy(struct mt7915_dev * dev)1196 static void mt7915_unregister_ext_phy(struct mt7915_dev *dev)
1197 {
1198 struct mt7915_phy *phy = mt7915_ext_phy(dev);
1199 struct mt76_phy *mphy = dev->mt76.phys[MT_BAND1];
1200
1201 if (!phy)
1202 return;
1203
1204 mt7915_unregister_thermal(phy);
1205 mt76_unregister_phy(mphy);
1206 ieee80211_free_hw(mphy->hw);
1207 }
1208
mt7915_stop_hardware(struct mt7915_dev * dev)1209 static void mt7915_stop_hardware(struct mt7915_dev *dev)
1210 {
1211 mt7915_mcu_exit(dev);
1212 mt76_connac2_tx_token_put(&dev->mt76);
1213 mt7915_dma_cleanup(dev);
1214 tasklet_disable(&dev->mt76.irq_tasklet);
1215
1216 if (is_mt798x(&dev->mt76))
1217 mt7986_wmac_disable(dev);
1218 }
1219
mt7915_register_device(struct mt7915_dev * dev)1220 int mt7915_register_device(struct mt7915_dev *dev)
1221 {
1222 struct mt7915_phy *phy2;
1223 int ret;
1224
1225 dev->phy.dev = dev;
1226 dev->phy.mt76 = &dev->mt76.phy;
1227 dev->mt76.phy.priv = &dev->phy;
1228 INIT_WORK(&dev->rc_work, mt7915_mac_sta_rc_work);
1229 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7915_mac_work);
1230 INIT_LIST_HEAD(&dev->sta_rc_list);
1231 INIT_LIST_HEAD(&dev->twt_list);
1232
1233 init_waitqueue_head(&dev->reset_wait);
1234 INIT_WORK(&dev->reset_work, mt7915_mac_reset_work);
1235 INIT_WORK(&dev->dump_work, mt7915_mac_dump_work);
1236 mutex_init(&dev->dump_mutex);
1237
1238 dev->dbdc_support = mt7915_band_config(dev);
1239
1240 phy2 = mt7915_alloc_ext_phy(dev);
1241 if (IS_ERR(phy2))
1242 return PTR_ERR(phy2);
1243
1244 ret = mt7915_init_hardware(dev, phy2);
1245 if (ret)
1246 goto free_phy2;
1247
1248 mt7915_init_wiphy(&dev->phy);
1249
1250 #ifdef CONFIG_NL80211_TESTMODE
1251 dev->mt76.test_ops = &mt7915_testmode_ops;
1252 #endif
1253
1254 ret = mt76_register_device(&dev->mt76, true, mt76_rates,
1255 ARRAY_SIZE(mt76_rates));
1256 if (ret)
1257 goto stop_hw;
1258
1259 ret = mt7915_thermal_init(&dev->phy);
1260 if (ret)
1261 goto unreg_dev;
1262
1263 if (phy2) {
1264 ret = mt7915_register_ext_phy(dev, phy2);
1265 if (ret)
1266 goto unreg_thermal;
1267 }
1268
1269 ieee80211_queue_work(mt76_hw(dev), &dev->init_work);
1270
1271 dev->recovery.hw_init_done = true;
1272
1273 ret = mt7915_init_debugfs(&dev->phy);
1274 if (ret)
1275 goto unreg_thermal;
1276
1277 ret = mt7915_coredump_register(dev);
1278 if (ret)
1279 goto unreg_thermal;
1280
1281 return 0;
1282
1283 unreg_thermal:
1284 mt7915_unregister_thermal(&dev->phy);
1285 unreg_dev:
1286 mt76_unregister_device(&dev->mt76);
1287 stop_hw:
1288 mt7915_stop_hardware(dev);
1289 free_phy2:
1290 if (phy2)
1291 ieee80211_free_hw(phy2->mt76->hw);
1292 return ret;
1293 }
1294
mt7915_unregister_device(struct mt7915_dev * dev)1295 void mt7915_unregister_device(struct mt7915_dev *dev)
1296 {
1297 mt7915_unregister_ext_phy(dev);
1298 mt7915_coredump_unregister(dev);
1299 mt7915_unregister_thermal(&dev->phy);
1300 mt76_unregister_device(&dev->mt76);
1301 mt7915_stop_hardware(dev);
1302
1303 mt76_free_device(&dev->mt76);
1304 }
1305