1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25
26 #ifndef __INTEL_DISPLAY_TYPES_H__
27 #define __INTEL_DISPLAY_TYPES_H__
28
29 #include <linux/pm_qos.h>
30 #include <linux/pwm.h>
31
32 #include <drm/display/drm_dp_dual_mode_helper.h>
33 #include <drm/display/drm_dp_mst_helper.h>
34 #include <drm/display/drm_dp_tunnel.h>
35 #include <drm/display/drm_dsc.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_framebuffer.h>
40 #include <drm/drm_rect.h>
41 #include <drm/drm_vblank_work.h>
42 #include <drm/intel/i915_hdcp_interface.h>
43 #include <uapi/drm/i915_drm.h>
44
45 #include "i915_gtt_view_types.h"
46 #include "intel_bios.h"
47 #include "intel_display.h"
48 #include "intel_display_conversion.h"
49 #include "intel_display_limits.h"
50 #include "intel_display_power.h"
51 #include "intel_dpll_mgr.h"
52 #include "intel_wm_types.h"
53
54 struct cec_notifier;
55 struct drm_printer;
56 struct __intel_global_objs_state;
57 struct intel_connector;
58 struct intel_ddi_buf_trans;
59 struct intel_fbc;
60 struct intel_hdcp_shim;
61 struct intel_tc_port;
62
63 /*
64 * Display related stuff
65 */
66
67 /* these are outputs from the chip - integrated only
68 external chips are via DVO or SDVO output */
69 enum intel_output_type {
70 INTEL_OUTPUT_UNUSED = 0,
71 INTEL_OUTPUT_ANALOG = 1,
72 INTEL_OUTPUT_DVO = 2,
73 INTEL_OUTPUT_SDVO = 3,
74 INTEL_OUTPUT_LVDS = 4,
75 INTEL_OUTPUT_TVOUT = 5,
76 INTEL_OUTPUT_HDMI = 6,
77 INTEL_OUTPUT_DP = 7,
78 INTEL_OUTPUT_EDP = 8,
79 INTEL_OUTPUT_DSI = 9,
80 INTEL_OUTPUT_DDI = 10,
81 INTEL_OUTPUT_DP_MST = 11,
82 };
83
84 enum hdmi_force_audio {
85 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
86 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
87 HDMI_AUDIO_AUTO, /* trust EDID */
88 HDMI_AUDIO_ON, /* force turn on HDMI audio */
89 };
90
91 /* "Broadcast RGB" property */
92 enum intel_broadcast_rgb {
93 INTEL_BROADCAST_RGB_AUTO,
94 INTEL_BROADCAST_RGB_FULL,
95 INTEL_BROADCAST_RGB_LIMITED,
96 };
97
98 struct intel_fb_view {
99 /*
100 * The remap information used in the remapped and rotated views to
101 * create the DMA scatter-gather list for each FB color plane. This sg
102 * list is created along with the view type (gtt.type) specific
103 * i915_vma object and contains the list of FB object pages (reordered
104 * in the rotated view) that are visible in the view.
105 * In the normal view the FB object's backing store sg list is used
106 * directly and hence the remap information here is not used.
107 */
108 struct i915_gtt_view gtt;
109
110 /*
111 * The GTT view (gtt.type) specific information for each FB color
112 * plane. In the normal GTT view all formats (up to 4 color planes),
113 * in the rotated and remapped GTT view all no-CCS formats (up to 2
114 * color planes) are supported.
115 *
116 * The view information shared by all FB color planes in the FB,
117 * like dst x/y and src/dst width, is stored separately in
118 * intel_plane_state.
119 */
120 struct i915_color_plane_view {
121 u32 offset;
122 unsigned int x, y;
123 /*
124 * Plane stride in:
125 * bytes for 0/180 degree rotation
126 * pixels for 90/270 degree rotation
127 */
128 unsigned int mapping_stride;
129 unsigned int scanout_stride;
130 } color_plane[4];
131 };
132
133 struct intel_framebuffer {
134 struct drm_framebuffer base;
135 struct intel_frontbuffer *frontbuffer;
136
137 /* Params to remap the FB pages and program the plane registers in each view. */
138 struct intel_fb_view normal_view;
139 union {
140 struct intel_fb_view rotated_view;
141 struct intel_fb_view remapped_view;
142 };
143
144 struct i915_address_space *dpt_vm;
145
146 unsigned int min_alignment;
147 unsigned int vtd_guard;
148 };
149
150 enum intel_hotplug_state {
151 INTEL_HOTPLUG_UNCHANGED,
152 INTEL_HOTPLUG_CHANGED,
153 INTEL_HOTPLUG_RETRY,
154 };
155
156 struct intel_encoder {
157 struct drm_encoder base;
158
159 enum intel_output_type type;
160 enum port port;
161 u16 cloneable;
162 u8 pipe_mask;
163
164 /* Check and recover a bad link state. */
165 struct delayed_work link_check_work;
166 void (*link_check)(struct intel_encoder *encoder);
167
168 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
169 struct intel_connector *connector);
170 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
171 struct intel_crtc_state *,
172 struct drm_connector_state *);
173 int (*compute_config)(struct intel_encoder *,
174 struct intel_crtc_state *,
175 struct drm_connector_state *);
176 int (*compute_config_late)(struct intel_encoder *,
177 struct intel_crtc_state *,
178 struct drm_connector_state *);
179 void (*pre_pll_enable)(struct intel_atomic_state *,
180 struct intel_encoder *,
181 const struct intel_crtc_state *,
182 const struct drm_connector_state *);
183 void (*pre_enable)(struct intel_atomic_state *,
184 struct intel_encoder *,
185 const struct intel_crtc_state *,
186 const struct drm_connector_state *);
187 void (*enable)(struct intel_atomic_state *,
188 struct intel_encoder *,
189 const struct intel_crtc_state *,
190 const struct drm_connector_state *);
191 void (*disable)(struct intel_atomic_state *,
192 struct intel_encoder *,
193 const struct intel_crtc_state *,
194 const struct drm_connector_state *);
195 void (*post_disable)(struct intel_atomic_state *,
196 struct intel_encoder *,
197 const struct intel_crtc_state *,
198 const struct drm_connector_state *);
199 void (*post_pll_disable)(struct intel_atomic_state *,
200 struct intel_encoder *,
201 const struct intel_crtc_state *,
202 const struct drm_connector_state *);
203 void (*update_pipe)(struct intel_atomic_state *,
204 struct intel_encoder *,
205 const struct intel_crtc_state *,
206 const struct drm_connector_state *);
207 void (*audio_enable)(struct intel_encoder *encoder,
208 const struct intel_crtc_state *crtc_state,
209 const struct drm_connector_state *conn_state);
210 void (*audio_disable)(struct intel_encoder *encoder,
211 const struct intel_crtc_state *old_crtc_state,
212 const struct drm_connector_state *old_conn_state);
213 /* Read out the current hw state of this connector, returning true if
214 * the encoder is active. If the encoder is enabled it also set the pipe
215 * it is connected to in the pipe parameter. */
216 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
217 /* Reconstructs the equivalent mode flags for the current hardware
218 * state. This must be called _after_ display->get_pipe_config has
219 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
220 * be set correctly before calling this function. */
221 void (*get_config)(struct intel_encoder *,
222 struct intel_crtc_state *pipe_config);
223
224 /*
225 * Optional hook called during init/resume to sync any state
226 * stored in the encoder (eg. DP link parameters) wrt. the HW state.
227 */
228 void (*sync_state)(struct intel_encoder *encoder,
229 const struct intel_crtc_state *crtc_state);
230
231 /*
232 * Optional hook, returning true if this encoder allows a fastset
233 * during the initial commit, false otherwise.
234 */
235 bool (*initial_fastset_check)(struct intel_encoder *encoder,
236 struct intel_crtc_state *crtc_state);
237
238 /*
239 * Acquires the power domains needed for an active encoder during
240 * hardware state readout.
241 */
242 void (*get_power_domains)(struct intel_encoder *encoder,
243 struct intel_crtc_state *crtc_state);
244 /*
245 * Called during system suspend after all pending requests for the
246 * encoder are flushed (for example for DP AUX transactions) and
247 * device interrupts are disabled.
248 * All modeset locks are held while the hook is called.
249 */
250 void (*suspend)(struct intel_encoder *);
251 /*
252 * Called without the modeset locks held after the suspend() hook for
253 * all encoders have been called.
254 */
255 void (*suspend_complete)(struct intel_encoder *encoder);
256 /*
257 * Called during system reboot/shutdown after all the
258 * encoders have been disabled and suspended.
259 * All modeset locks are held while the hook is called.
260 */
261 void (*shutdown)(struct intel_encoder *encoder);
262 /*
263 * Called without the modeset locks held after the shutdown() hook for
264 * all encoders have been called.
265 */
266 void (*shutdown_complete)(struct intel_encoder *encoder);
267 /*
268 * Enable/disable the clock to the port.
269 */
270 void (*enable_clock)(struct intel_encoder *encoder,
271 const struct intel_crtc_state *crtc_state);
272 void (*disable_clock)(struct intel_encoder *encoder);
273 /*
274 * Returns whether the port clock is enabled or not.
275 */
276 bool (*is_clock_enabled)(struct intel_encoder *encoder);
277 /*
278 * Returns the PLL type the port uses.
279 */
280 enum icl_port_dpll_id (*port_pll_type)(struct intel_encoder *encoder,
281 const struct intel_crtc_state *crtc_state);
282 const struct intel_ddi_buf_trans *(*get_buf_trans)(struct intel_encoder *encoder,
283 const struct intel_crtc_state *crtc_state,
284 int *n_entries);
285 void (*set_signal_levels)(struct intel_encoder *encoder,
286 const struct intel_crtc_state *crtc_state);
287
288 enum hpd_pin hpd_pin;
289 enum intel_display_power_domain power_domain;
290
291 /* VBT information for this encoder (may be NULL for older platforms) */
292 const struct intel_bios_encoder_data *devdata;
293 };
294
295 struct intel_panel_bl_funcs {
296 /* Connector and platform specific backlight functions */
297 int (*setup)(struct intel_connector *connector, enum pipe pipe);
298 u32 (*get)(struct intel_connector *connector, enum pipe pipe);
299 void (*set)(const struct drm_connector_state *conn_state, u32 level);
300 void (*disable)(const struct drm_connector_state *conn_state, u32 level);
301 void (*enable)(const struct intel_crtc_state *crtc_state,
302 const struct drm_connector_state *conn_state, u32 level);
303 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
304 };
305
306 /* in 100us units */
307 struct intel_pps_delays {
308 u16 power_up; /* eDP: T1+T3, LVDS: T1+T2 */
309 u16 backlight_on; /* eDP: T8, LVDS: T5 */
310 u16 backlight_off; /* eDP: T9, LVDS: T6/TX */
311 u16 power_down; /* eDP: T10, LVDS: T3 */
312 u16 power_cycle; /* eDP: T11+T12, LVDS: T7+T4 */
313 };
314
315 enum drrs_type {
316 DRRS_TYPE_NONE,
317 DRRS_TYPE_STATIC,
318 DRRS_TYPE_SEAMLESS,
319 };
320
321 struct intel_vbt_panel_data {
322 struct drm_display_mode *lfp_vbt_mode; /* if any */
323 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
324
325 /* Feature bits */
326 int panel_type;
327 unsigned int lvds_dither:1;
328 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
329
330 bool vrr;
331
332 u8 seamless_drrs_min_refresh_rate;
333 enum drrs_type drrs_type;
334
335 struct {
336 int max_link_rate;
337 int rate;
338 int lanes;
339 int preemphasis;
340 int vswing;
341 int bpp;
342 struct intel_pps_delays pps;
343 u8 drrs_msa_timing_delay;
344 bool low_vswing;
345 bool hobl;
346 bool dsc_disable;
347 } edp;
348
349 struct {
350 bool enable;
351 bool full_link;
352 bool require_aux_wakeup;
353 int idle_frames;
354 int tp1_wakeup_time_us;
355 int tp2_tp3_wakeup_time_us;
356 int psr2_tp2_tp3_wakeup_time_us;
357 } psr;
358
359 struct {
360 u16 pwm_freq_hz;
361 u16 brightness_precision_bits;
362 u16 hdr_dpcd_refresh_timeout;
363 bool present;
364 bool active_low_pwm;
365 u8 min_brightness; /* min_brightness/255 of max */
366 s8 controller; /* brightness controller number */
367 enum intel_backlight_type type;
368 } backlight;
369
370 /* MIPI DSI */
371 struct {
372 u16 panel_id;
373 struct mipi_config *config;
374 struct mipi_pps_data *pps;
375 u16 bl_ports;
376 u16 cabc_ports;
377 u8 seq_version;
378 u32 size;
379 u8 *data;
380 const u8 *sequence[MIPI_SEQ_MAX];
381 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
382 enum drm_panel_orientation orientation;
383 } dsi;
384 };
385
386 struct intel_panel {
387 /* Fixed EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
388 const struct drm_edid *fixed_edid;
389
390 struct list_head fixed_modes;
391
392 /* backlight */
393 struct {
394 bool present;
395 u32 level;
396 u32 min;
397 u32 max;
398 bool enabled;
399 bool combination_mode; /* gen 2/4 only */
400 bool active_low_pwm;
401 bool alternate_pwm_increment; /* lpt+ */
402
403 /* PWM chip */
404 u32 pwm_level_min;
405 u32 pwm_level_max;
406 bool pwm_enabled;
407 bool util_pin_active_low; /* bxt+ */
408 u8 controller; /* bxt+ only */
409 struct pwm_device *pwm;
410 struct pwm_state pwm_state;
411
412 /* DPCD backlight */
413 union {
414 struct {
415 struct drm_edp_backlight_info info;
416 bool luminance_control_support;
417 } vesa;
418 struct {
419 bool sdr_uses_aux;
420 bool supports_2084_decode;
421 bool supports_2020_gamut;
422 bool supports_segmented_backlight;
423 bool supports_sdp_colorimetry;
424 bool supports_tone_mapping;
425 } intel_cap;
426 } edp;
427
428 struct backlight_device *device;
429
430 const struct intel_panel_bl_funcs *funcs;
431 const struct intel_panel_bl_funcs *pwm_funcs;
432 void (*power)(struct intel_connector *, bool enable);
433 } backlight;
434
435 struct intel_vbt_panel_data vbt;
436 };
437
438 struct intel_digital_port;
439
440 struct intel_hdcp {
441 const struct intel_hdcp_shim *shim;
442 /* Mutex for hdcp state of the connector */
443 struct mutex mutex;
444 u64 value;
445 struct delayed_work check_work;
446 struct work_struct prop_work;
447
448 /* HDCP1.4 Encryption status */
449 bool hdcp_encrypted;
450
451 /* HDCP2.2 related definitions */
452 /* Flag indicates whether this connector supports HDCP2.2 or not. */
453 bool hdcp2_supported;
454
455 /* HDCP2.2 Encryption status */
456 bool hdcp2_encrypted;
457
458 /*
459 * Content Stream Type defined by content owner. TYPE0(0x0) content can
460 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
461 * content can flow only through a link protected by HDCP2.2.
462 */
463 u8 content_type;
464
465 bool is_paired;
466 bool is_repeater;
467
468 /*
469 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
470 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
471 * When it rolls over re-auth has to be triggered.
472 */
473 u32 seq_num_v;
474
475 /*
476 * Count of RepeaterAuth_Stream_Manage msg propagated.
477 * Initialized to 0 on AKE_INIT. Incremented after every successful
478 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
479 * over re-Auth has to be triggered.
480 */
481 u32 seq_num_m;
482
483 /*
484 * Work queue to signal the CP_IRQ. Used for the waiters to read the
485 * available information from HDCP DP sink.
486 */
487 wait_queue_head_t cp_irq_queue;
488 atomic_t cp_irq_count;
489 int cp_irq_count_cached;
490
491 /*
492 * HDCP register access for gen12+ need the transcoder associated.
493 * Transcoder attached to the connector could be changed at modeset.
494 * Hence caching the transcoder here.
495 */
496 enum transcoder cpu_transcoder;
497 /* Only used for DP MST stream encryption */
498 enum transcoder stream_transcoder;
499 /* Used to force HDCP 1.4 bypassing HDCP 2.x */
500 bool force_hdcp14;
501 };
502
503 struct intel_connector {
504 struct drm_connector base;
505 /*
506 * The fixed encoder this connector is connected to.
507 */
508 struct intel_encoder *encoder;
509
510 /* ACPI device id for ACPI and driver cooperation */
511 u32 acpi_device_id;
512
513 /* Reads out the current hw, returning true if the connector is enabled
514 * and active (i.e. dpms ON state). */
515 bool (*get_hw_state)(struct intel_connector *);
516
517 /*
518 * Optional hook called during init/resume to sync any state
519 * stored in the connector (eg. DSC state) wrt. the HW state.
520 */
521 void (*sync_state)(struct intel_connector *connector,
522 const struct intel_crtc_state *crtc_state);
523
524 /* Panel info for eDP and LVDS */
525 struct intel_panel panel;
526
527 /* Cached EDID for detect. */
528 const struct drm_edid *detect_edid;
529
530 /* Number of times hotplug detection was tried after an HPD interrupt */
531 int hotplug_retries;
532
533 /* since POLL and HPD connectors may use the same HPD line keep the native
534 state of connector->polled in case hotplug storm detection changes it */
535 u8 polled;
536
537 int force_joined_pipes;
538
539 struct {
540 struct drm_dp_aux *dsc_decompression_aux;
541 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
542 u8 fec_capability;
543
544 u8 dsc_hblank_expansion_quirk:1;
545 u8 dsc_decompression_enabled:1;
546 } dp;
547
548 struct {
549 struct drm_dp_mst_port *port;
550 struct intel_dp *dp;
551 } mst;
552
553 /* Work struct to schedule a uevent on link train failure */
554 struct work_struct modeset_retry_work;
555
556 struct intel_hdcp hdcp;
557 };
558
559 struct intel_digital_connector_state {
560 struct drm_connector_state base;
561
562 enum hdmi_force_audio force_audio;
563 int broadcast_rgb;
564 };
565
566 #define to_intel_digital_connector_state(conn_state) \
567 container_of_const((conn_state), struct intel_digital_connector_state, base)
568
569 struct dpll {
570 /* given values */
571 int n;
572 int m1, m2;
573 int p1, p2;
574 /* derived values */
575 int dot;
576 int vco;
577 int m;
578 int p;
579 };
580
581 struct intel_atomic_state {
582 struct drm_atomic_state base;
583
584 intel_wakeref_t wakeref;
585
586 struct __intel_global_objs_state *global_objs;
587 int num_global_objs;
588
589 /* Internal commit, as opposed to userspace/client initiated one */
590 bool internal;
591
592 bool dpll_set, modeset;
593
594 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
595
596 struct intel_dp_tunnel_inherited_state *inherited_dp_tunnels;
597
598 /*
599 * Current watermarks can't be trusted during hardware readout, so
600 * don't bother calculating intermediate watermarks.
601 */
602 bool skip_intermediate_wm;
603
604 bool rps_interactive;
605
606 struct work_struct cleanup_work;
607 };
608
609 struct intel_plane_state {
610 struct drm_plane_state uapi;
611
612 /*
613 * actual hardware state, the state we program to the hardware.
614 * The following members are used to verify the hardware state:
615 * During initial hw readout, they need to be copied from uapi.
616 */
617 struct {
618 struct drm_crtc *crtc;
619 struct drm_framebuffer *fb;
620
621 u16 alpha;
622 u16 pixel_blend_mode;
623 unsigned int rotation;
624 enum drm_color_encoding color_encoding;
625 enum drm_color_range color_range;
626 enum drm_scaling_filter scaling_filter;
627 } hw;
628
629 struct i915_vma *ggtt_vma;
630 struct i915_vma *dpt_vma;
631 unsigned long flags;
632 #define PLANE_HAS_FENCE BIT(0)
633
634 struct intel_fb_view view;
635 u32 phys_dma_addr; /* for cursor_needs_physical */
636
637 /* for legacy cursor fb unpin */
638 struct drm_vblank_work unpin_work;
639
640 /* Plane pxp decryption state */
641 bool decrypt;
642
643 /* Plane state to display black pixels when pxp is borked */
644 bool force_black;
645
646 /* Acting as Y plane for another UV plane? */
647 bool is_y_plane;
648
649 /* plane control register */
650 u32 ctl;
651
652 /* plane color control register */
653 u32 color_ctl;
654
655 /* chroma upsampler control register */
656 u32 cus_ctl;
657
658 /*
659 * scaler_id
660 * = -1 : not using a scaler
661 * >= 0 : using a scalers
662 *
663 * plane requiring a scaler:
664 * - During check_plane, its bit is set in
665 * crtc_state->scaler_state.scaler_users by calling helper function
666 * update_scaler_plane.
667 * - scaler_id indicates the scaler it got assigned.
668 *
669 * plane doesn't require a scaler:
670 * - this can happen when scaling is no more required or plane simply
671 * got disabled.
672 * - During check_plane, corresponding bit is reset in
673 * crtc_state->scaler_state.scaler_users by calling helper function
674 * update_scaler_plane.
675 */
676 int scaler_id;
677
678 /*
679 * planar_linked_plane:
680 *
681 * ICL planar formats require 2 planes that are updated as pairs.
682 * This member is used to make sure the other plane is also updated
683 * when required, and for update_slave() to find the correct
684 * plane_state to pass as argument.
685 */
686 struct intel_plane *planar_linked_plane;
687
688 struct drm_intel_sprite_colorkey ckey;
689
690 struct drm_rect psr2_sel_fetch_area;
691
692 /* Clear Color Value */
693 u64 ccval;
694
695 const char *no_fbc_reason;
696
697 struct drm_rect damage;
698 };
699
700 struct intel_initial_plane_config {
701 struct intel_framebuffer *fb;
702 struct intel_memory_region *mem;
703 resource_size_t phys_base;
704 struct i915_vma *vma;
705 unsigned int tiling;
706 int size;
707 u32 base;
708 u8 rotation;
709 };
710
711 struct intel_scaler {
712 u32 mode;
713 bool in_use;
714 int hscale;
715 int vscale;
716 };
717
718 struct intel_crtc_scaler_state {
719 #define SKL_NUM_SCALERS 2
720 struct intel_scaler scalers[SKL_NUM_SCALERS];
721
722 /*
723 * scaler_users: keeps track of users requesting scalers on this crtc.
724 *
725 * If a bit is set, a user is using a scaler.
726 * Here user can be a plane or crtc as defined below:
727 * bits 0-30 - plane (bit position is index from drm_plane_index)
728 * bit 31 - crtc
729 *
730 * Instead of creating a new index to cover planes and crtc, using
731 * existing drm_plane_index for planes which is well less than 31
732 * planes and bit 31 for crtc. This should be fine to cover all
733 * our platforms.
734 *
735 * intel_atomic_setup_scalers will setup available scalers to users
736 * requesting scalers. It will gracefully fail if request exceeds
737 * availability.
738 */
739 #define SKL_CRTC_INDEX 31
740 unsigned scaler_users;
741
742 /* scaler used by crtc for panel fitting purpose */
743 int scaler_id;
744 };
745
746 /* {crtc,crtc_state}->mode_flags */
747 /* Flag to get scanline using frame time stamps */
748 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
749 /* Flag to use the scanline counter instead of the pixel counter */
750 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
751 /*
752 * TE0 or TE1 flag is set if the crtc has a DSI encoder which
753 * is operating in command mode.
754 * Flag to use TE from DSI0 instead of VBI in command mode
755 */
756 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
757 /* Flag to use TE from DSI1 instead of VBI in command mode */
758 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
759 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */
760 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
761 /* Do tricks to make vblank timestamps sane with VRR? */
762 #define I915_MODE_FLAG_VRR (1<<6)
763
764 struct intel_wm_level {
765 bool enable;
766 u32 pri_val;
767 u32 spr_val;
768 u32 cur_val;
769 u32 fbc_val;
770 };
771
772 struct intel_pipe_wm {
773 struct intel_wm_level wm[5];
774 bool fbc_wm_enabled;
775 bool pipe_enabled;
776 bool sprites_enabled;
777 bool sprites_scaled;
778 };
779
780 struct skl_wm_level {
781 u16 min_ddb_alloc;
782 u16 blocks;
783 u8 lines;
784 bool enable;
785 bool ignore_lines;
786 bool auto_min_alloc_wm_enable;
787 bool can_sagv;
788 };
789
790 struct skl_plane_wm {
791 struct skl_wm_level wm[8];
792 struct skl_wm_level uv_wm[8];
793 struct skl_wm_level trans_wm;
794 struct {
795 struct skl_wm_level wm0;
796 struct skl_wm_level trans_wm;
797 } sagv;
798 bool is_planar;
799 };
800
801 struct skl_pipe_wm {
802 struct skl_plane_wm planes[I915_MAX_PLANES];
803 bool use_sagv_wm;
804 };
805
806 enum vlv_wm_level {
807 VLV_WM_LEVEL_PM2,
808 VLV_WM_LEVEL_PM5,
809 VLV_WM_LEVEL_DDR_DVFS,
810 NUM_VLV_WM_LEVELS,
811 };
812
813 struct vlv_wm_state {
814 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
815 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
816 u8 num_levels;
817 bool cxsr;
818 };
819
820 struct vlv_fifo_state {
821 u16 plane[I915_MAX_PLANES];
822 };
823
824 enum g4x_wm_level {
825 G4X_WM_LEVEL_NORMAL,
826 G4X_WM_LEVEL_SR,
827 G4X_WM_LEVEL_HPLL,
828 NUM_G4X_WM_LEVELS,
829 };
830
831 struct g4x_wm_state {
832 struct g4x_pipe_wm wm;
833 struct g4x_sr_wm sr;
834 struct g4x_sr_wm hpll;
835 bool cxsr;
836 bool hpll_en;
837 bool fbc_en;
838 };
839
840 struct intel_crtc_wm_state {
841 union {
842 /*
843 * raw:
844 * The "raw" watermark values produced by the formula
845 * given the plane's current state. They do not consider
846 * how much FIFO is actually allocated for each plane.
847 *
848 * optimal:
849 * The "optimal" watermark values given the current
850 * state of the planes and the amount of FIFO
851 * allocated to each, ignoring any previous state
852 * of the planes.
853 *
854 * intermediate:
855 * The "intermediate" watermark values when transitioning
856 * between the old and new "optimal" values. Used when
857 * the watermark registers are single buffered and hence
858 * their state changes asynchronously with regards to the
859 * actual plane registers. These are essentially the
860 * worst case combination of the old and new "optimal"
861 * watermarks, which are therefore safe to use when the
862 * plane is in either its old or new state.
863 */
864 struct {
865 struct intel_pipe_wm intermediate;
866 struct intel_pipe_wm optimal;
867 } ilk;
868
869 struct {
870 struct skl_pipe_wm raw;
871 /* gen9+ only needs 1-step wm programming */
872 struct skl_pipe_wm optimal;
873 struct skl_ddb_entry ddb;
874 /*
875 * pre-icl: for packed/planar CbCr
876 * icl+: for everything
877 */
878 struct skl_ddb_entry plane_ddb[I915_MAX_PLANES];
879 /* pre-icl: for planar Y */
880 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
881
882 /*
883 * xe3: Minimum amount of display blocks and minimum
884 * sagv allocation required for async flip
885 */
886 u16 plane_min_ddb[I915_MAX_PLANES];
887 u16 plane_interim_ddb[I915_MAX_PLANES];
888 } skl;
889
890 struct {
891 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */
892 struct vlv_wm_state intermediate; /* inverted */
893 struct vlv_wm_state optimal; /* inverted */
894 struct vlv_fifo_state fifo_state;
895 } vlv;
896
897 struct {
898 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
899 struct g4x_wm_state intermediate;
900 struct g4x_wm_state optimal;
901 } g4x;
902 };
903
904 /*
905 * Platforms with two-step watermark programming will need to
906 * update watermark programming post-vblank to switch from the
907 * safe intermediate watermarks to the optimal final
908 * watermarks.
909 */
910 bool need_postvbl_update;
911 };
912
913 enum intel_output_format {
914 INTEL_OUTPUT_FORMAT_RGB,
915 INTEL_OUTPUT_FORMAT_YCBCR420,
916 INTEL_OUTPUT_FORMAT_YCBCR444,
917 };
918
919 /* Used by dp and fdi links */
920 struct intel_link_m_n {
921 u32 tu;
922 u32 data_m;
923 u32 data_n;
924 u32 link_m;
925 u32 link_n;
926 };
927
928 struct intel_csc_matrix {
929 u16 coeff[9];
930 u16 preoff[3];
931 u16 postoff[3];
932 };
933
934 void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val);
935
936 typedef void (*intel_io_reg_write)(void *ctx, i915_reg_t reg, u32 val);
937
938 struct intel_crtc_state {
939 /*
940 * uapi (drm) state. This is the software state shown to userspace.
941 * In particular, the following members are used for bookkeeping:
942 * - crtc
943 * - state
944 * - *_changed
945 * - event
946 * - commit
947 * - mode_blob
948 */
949 struct drm_crtc_state uapi;
950
951 /*
952 * actual hardware state, the state we program to the hardware.
953 * The following members are used to verify the hardware state:
954 * - enable
955 * - active
956 * - mode / pipe_mode / adjusted_mode
957 * - color property blobs.
958 *
959 * During initial hw readout, they need to be copied to uapi.
960 *
961 * Joiner will allow a transcoder mode that spans 2 pipes;
962 * Use the pipe_mode for calculations like watermarks, pipe
963 * scaler, and bandwidth.
964 *
965 * Use adjusted_mode for things that need to know the full
966 * mode on the transcoder, which spans all pipes.
967 */
968 struct {
969 bool active, enable;
970 /* logical state of LUTs */
971 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
972 struct drm_display_mode mode, pipe_mode, adjusted_mode;
973 enum drm_scaling_filter scaling_filter;
974 } hw;
975
976 /* actual state of LUTs */
977 struct drm_property_blob *pre_csc_lut, *post_csc_lut;
978
979 struct intel_csc_matrix csc, output_csc;
980
981 /**
982 * quirks - bitfield with hw state readout quirks
983 *
984 * For various reasons the hw state readout code might not be able to
985 * completely faithfully read out the current state. These cases are
986 * tracked with quirk flags so that fastboot and state checker can act
987 * accordingly.
988 */
989 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
990 unsigned long quirks;
991
992 unsigned fb_bits; /* framebuffers to flip */
993 bool update_pipe; /* can a fast modeset be performed? */
994 bool update_m_n; /* update M/N seamlessly during fastset? */
995 bool update_lrr; /* update TRANS_VTOTAL/etc. during fastset? */
996 bool disable_cxsr;
997 bool update_wm_pre, update_wm_post; /* watermarks are updated */
998 bool fifo_changed; /* FIFO split is changed */
999 bool preload_luts;
1000 bool inherited; /* state inherited from BIOS? */
1001
1002 /* Ask the hardware to actually async flip? */
1003 bool do_async_flip;
1004
1005 /* Pipe source size (ie. panel fitter input size)
1006 * All planes will be positioned inside this space,
1007 * and get clipped at the edges. */
1008 struct drm_rect pipe_src;
1009
1010 /*
1011 * Pipe pixel rate, adjusted for
1012 * panel fitter/pipe scaler downscaling.
1013 */
1014 unsigned int pixel_rate;
1015
1016 /* Whether to set up the PCH/FDI. Note that we never allow sharing
1017 * between pch encoders and cpu encoders. */
1018 bool has_pch_encoder;
1019
1020 /* Are we sending infoframes on the attached port */
1021 bool has_infoframe;
1022
1023 /* CPU Transcoder for the pipe. Currently this can only differ from the
1024 * pipe on Haswell and later (where we have a special eDP transcoder)
1025 * and Broxton (where we have special DSI transcoders). */
1026 enum transcoder cpu_transcoder;
1027
1028 /*
1029 * Use reduced/limited/broadcast rbg range, compressing from the full
1030 * range fed into the crtcs.
1031 */
1032 bool limited_color_range;
1033
1034 /* Bitmask of encoder types (enum intel_output_type)
1035 * driven by the pipe.
1036 */
1037 unsigned int output_types;
1038
1039 /* Whether we should send NULL infoframes. Required for audio. */
1040 bool has_hdmi_sink;
1041
1042 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
1043 * has_dp_encoder is set. */
1044 bool has_audio;
1045
1046 /*
1047 * Enable dithering, used when the selected pipe bpp doesn't match the
1048 * plane bpp.
1049 */
1050 bool dither;
1051
1052 /*
1053 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
1054 * compliance video pattern tests.
1055 * Disable dither only if it is a compliance test request for
1056 * 18bpp.
1057 */
1058 bool dither_force_disable;
1059
1060 /* Controls for the clock computation, to override various stages. */
1061 bool clock_set;
1062
1063 /* SDVO TV has a bunch of special case. To make multifunction encoders
1064 * work correctly, we need to track this at runtime.*/
1065 bool sdvo_tv_clock;
1066
1067 /*
1068 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
1069 * required. This is set in the 2nd loop of calling encoder's
1070 * ->compute_config if the first pick doesn't work out.
1071 */
1072 bool bw_constrained;
1073
1074 /* Settings for the intel dpll used on pretty much everything but
1075 * haswell. */
1076 struct dpll dpll;
1077
1078 /* Selected dpll when shared or NULL. */
1079 struct intel_shared_dpll *shared_dpll;
1080
1081 /* Actual register state of the dpll, for shared dpll cross-checking. */
1082 struct intel_dpll_hw_state dpll_hw_state;
1083
1084 /*
1085 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
1086 * setting shared_dpll and dpll_hw_state to one of these reserved ones.
1087 */
1088 struct icl_port_dpll {
1089 struct intel_shared_dpll *pll;
1090 struct intel_dpll_hw_state hw_state;
1091 } icl_port_dplls[ICL_PORT_DPLL_COUNT];
1092
1093 /* DSI PLL registers */
1094 struct {
1095 u32 ctrl, div;
1096 } dsi_pll;
1097
1098 int max_link_bpp_x16; /* in 1/16 bpp units */
1099 int pipe_bpp; /* in 1 bpp units */
1100 int min_hblank;
1101 struct intel_link_m_n dp_m_n;
1102
1103 /* m2_n2 for eDP downclock */
1104 struct intel_link_m_n dp_m2_n2;
1105 bool has_drrs;
1106
1107 /* PSR is supported but might not be enabled due the lack of enabled planes */
1108 bool has_psr;
1109 bool has_sel_update;
1110 bool enable_psr2_sel_fetch;
1111 bool enable_psr2_su_region_et;
1112 bool req_psr2_sdp_prior_scanline;
1113 bool has_panel_replay;
1114 bool wm_level_disabled;
1115 u32 dc3co_exitline;
1116 u16 su_y_granularity;
1117
1118 /*
1119 * Frequency the dpll for the port should run at. Differs from the
1120 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
1121 * already multiplied by pixel_multiplier.
1122 */
1123 int port_clock;
1124
1125 /* Used by SDVO (and if we ever fix it, HDMI). */
1126 unsigned pixel_multiplier;
1127
1128 /* I915_MODE_FLAG_* */
1129 u8 mode_flags;
1130
1131 u8 lane_count;
1132
1133 /*
1134 * Used by platforms having DP/HDMI PHY with programmable lane
1135 * latency optimization.
1136 */
1137 u8 lane_lat_optim_mask;
1138
1139 /* minimum acceptable voltage level */
1140 u8 min_voltage_level;
1141
1142 /* Panel fitter controls for gen2-gen4 + VLV */
1143 struct {
1144 u32 control;
1145 u32 pgm_ratios;
1146 u32 lvds_border_bits;
1147 } gmch_pfit;
1148
1149 /* Panel fitter placement and size for Ironlake+ */
1150 struct {
1151 struct drm_rect dst;
1152 bool enabled;
1153 bool force_thru;
1154 } pch_pfit;
1155
1156 /* FDI configuration, only valid if has_pch_encoder is set. */
1157 int fdi_lanes;
1158 struct intel_link_m_n fdi_m_n;
1159
1160 bool ips_enabled;
1161
1162 bool crc_enabled;
1163
1164 bool double_wide;
1165
1166 struct intel_crtc_scaler_state scaler_state;
1167
1168 /* w/a for waiting 2 vblanks during crtc enable */
1169 enum pipe hsw_workaround_pipe;
1170
1171 struct intel_crtc_wm_state wm;
1172
1173 int min_cdclk[I915_MAX_PLANES];
1174
1175 /* for packed/planar CbCr */
1176 u32 data_rate[I915_MAX_PLANES];
1177 /* for planar Y */
1178 u32 data_rate_y[I915_MAX_PLANES];
1179
1180 /* FIXME unify with data_rate[]? */
1181 u64 rel_data_rate[I915_MAX_PLANES];
1182 u64 rel_data_rate_y[I915_MAX_PLANES];
1183
1184 /* Gamma mode programmed on the pipe */
1185 u32 gamma_mode;
1186
1187 union {
1188 /* CSC mode programmed on the pipe */
1189 u32 csc_mode;
1190
1191 /* CHV CGM mode */
1192 u32 cgm_mode;
1193 };
1194
1195 /* bitmask of logically enabled planes (enum plane_id) */
1196 u8 enabled_planes;
1197
1198 /* bitmask of actually visible planes (enum plane_id) */
1199 u8 active_planes;
1200 u8 scaled_planes;
1201 u8 nv12_planes;
1202 u8 c8_planes;
1203
1204 /* bitmask of planes that will be updated during the commit */
1205 u8 update_planes;
1206
1207 /* bitmask of planes with async flip active */
1208 u8 async_flip_planes;
1209
1210 u8 framestart_delay; /* 1-4 */
1211 u8 msa_timing_delay; /* 0-3 */
1212
1213 struct {
1214 u32 enable;
1215 u32 gcp;
1216 union hdmi_infoframe avi;
1217 union hdmi_infoframe spd;
1218 union hdmi_infoframe hdmi;
1219 union hdmi_infoframe drm;
1220 struct drm_dp_vsc_sdp vsc;
1221 struct drm_dp_as_sdp as_sdp;
1222 } infoframes;
1223
1224 u8 eld[MAX_ELD_BYTES];
1225
1226 /* HDMI scrambling status */
1227 bool hdmi_scrambling;
1228
1229 /* HDMI High TMDS char rate ratio */
1230 bool hdmi_high_tmds_clock_ratio;
1231
1232 /*
1233 * Output format RGB/YCBCR etc., that is coming out
1234 * at the end of the pipe.
1235 */
1236 enum intel_output_format output_format;
1237
1238 /*
1239 * Sink output format RGB/YCBCR etc., that is going
1240 * into the sink.
1241 */
1242 enum intel_output_format sink_format;
1243
1244 /* enable pipe gamma? */
1245 bool gamma_enable;
1246
1247 /* enable pipe csc? */
1248 bool csc_enable;
1249
1250 /* enable vlv/chv wgc csc? */
1251 bool wgc_enable;
1252
1253 /* joiner pipe bitmask */
1254 u8 joiner_pipes;
1255
1256 /* Display Stream compression state */
1257 struct {
1258 bool compression_enable;
1259 int num_streams;
1260 /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
1261 u16 compressed_bpp_x16;
1262 u8 slice_count;
1263 struct drm_dsc_config config;
1264 } dsc;
1265
1266 /* DP tunnel used for BW allocation. */
1267 struct drm_dp_tunnel_ref dp_tunnel_ref;
1268
1269 /* HSW+ linetime watermarks */
1270 u16 linetime;
1271 u16 ips_linetime;
1272
1273 bool enhanced_framing;
1274
1275 /*
1276 * Forward Error Correction.
1277 *
1278 * Note: This will be false for 128b/132b, which will always have FEC
1279 * enabled automatically.
1280 */
1281 bool fec_enable;
1282
1283 bool sdp_split_enable;
1284
1285 /* Pointer to master transcoder in case of tiled displays */
1286 enum transcoder master_transcoder;
1287
1288 /* Bitmask to indicate slaves attached */
1289 u8 sync_mode_slaves_mask;
1290
1291 /* Only valid on TGL+ */
1292 enum transcoder mst_master_transcoder;
1293
1294 /* For DSB based pipe updates */
1295 struct intel_dsb *dsb_color_vblank, *dsb_commit;
1296 bool use_dsb;
1297
1298 u32 psr2_man_track_ctl;
1299
1300 u32 pipe_srcsz_early_tpt;
1301
1302 struct drm_rect psr2_su_area;
1303
1304 /* Variable Refresh Rate state */
1305 struct {
1306 bool enable, in_range;
1307 u8 pipeline_full;
1308 u16 flipline, vmin, vmax, guardband;
1309 u32 vsync_end, vsync_start;
1310 } vrr;
1311
1312 /* Content Match Refresh Rate state */
1313 struct {
1314 bool enable;
1315 u64 cmrr_n, cmrr_m;
1316 } cmrr;
1317
1318 /* Stream Splitter for eDP MSO */
1319 struct {
1320 bool enable;
1321 u8 link_count;
1322 u8 pixel_overlap;
1323 } splitter;
1324
1325 /* for loading single buffered registers during vblank */
1326 struct drm_vblank_work vblank_work;
1327
1328 /* LOBF flag */
1329 bool has_lobf;
1330 };
1331
1332 enum intel_pipe_crc_source {
1333 INTEL_PIPE_CRC_SOURCE_NONE,
1334 INTEL_PIPE_CRC_SOURCE_PLANE1,
1335 INTEL_PIPE_CRC_SOURCE_PLANE2,
1336 INTEL_PIPE_CRC_SOURCE_PLANE3,
1337 INTEL_PIPE_CRC_SOURCE_PLANE4,
1338 INTEL_PIPE_CRC_SOURCE_PLANE5,
1339 INTEL_PIPE_CRC_SOURCE_PLANE6,
1340 INTEL_PIPE_CRC_SOURCE_PLANE7,
1341 INTEL_PIPE_CRC_SOURCE_PIPE,
1342 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1343 INTEL_PIPE_CRC_SOURCE_TV,
1344 INTEL_PIPE_CRC_SOURCE_DP_B,
1345 INTEL_PIPE_CRC_SOURCE_DP_C,
1346 INTEL_PIPE_CRC_SOURCE_DP_D,
1347 INTEL_PIPE_CRC_SOURCE_AUTO,
1348 INTEL_PIPE_CRC_SOURCE_MAX,
1349 };
1350
1351 enum drrs_refresh_rate {
1352 DRRS_REFRESH_RATE_HIGH,
1353 DRRS_REFRESH_RATE_LOW,
1354 };
1355
1356 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1357 struct intel_pipe_crc {
1358 spinlock_t lock;
1359 int skipped;
1360 enum intel_pipe_crc_source source;
1361 };
1362
1363 struct intel_crtc {
1364 struct drm_crtc base;
1365 enum pipe pipe;
1366 /*
1367 * Whether the crtc and the connected output pipeline is active. Implies
1368 * that crtc->enabled is set, i.e. the current mode configuration has
1369 * some outputs connected to this crtc.
1370 */
1371 bool active;
1372 u8 plane_ids_mask;
1373
1374 /* I915_MODE_FLAG_* */
1375 u8 mode_flags;
1376
1377 u16 vmax_vblank_start;
1378
1379 struct intel_display_power_domain_set enabled_power_domains;
1380 struct intel_display_power_domain_set hw_readout_power_domains;
1381 struct intel_overlay *overlay;
1382
1383 struct intel_crtc_state *config;
1384
1385 /* armed event for async flip */
1386 struct drm_pending_vblank_event *flip_done_event;
1387 /* armed event for DSB based updates */
1388 struct drm_pending_vblank_event *dsb_event;
1389
1390 /* Access to these should be protected by dev_priv->irq_lock. */
1391 bool cpu_fifo_underrun_disabled;
1392 bool pch_fifo_underrun_disabled;
1393
1394 /* per-pipe watermark state */
1395 struct {
1396 /* watermarks currently being used */
1397 union {
1398 struct intel_pipe_wm ilk;
1399 struct vlv_wm_state vlv;
1400 struct g4x_wm_state g4x;
1401 } active;
1402 } wm;
1403
1404 struct {
1405 struct mutex mutex;
1406 struct delayed_work work;
1407 enum drrs_refresh_rate refresh_rate;
1408 unsigned int frontbuffer_bits;
1409 unsigned int busy_frontbuffer_bits;
1410 enum transcoder cpu_transcoder;
1411 struct intel_link_m_n m_n, m2_n2;
1412 } drrs;
1413
1414 int scanline_offset;
1415
1416 struct {
1417 unsigned start_vbl_count;
1418 ktime_t start_vbl_time;
1419 int min_vbl, max_vbl;
1420 int scanline_start;
1421 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
1422 struct {
1423 u64 min;
1424 u64 max;
1425 u64 sum;
1426 unsigned int over;
1427 unsigned int times[17]; /* [1us, 16ms] */
1428 } vbl;
1429 #endif
1430 } debug;
1431
1432 /* scalers available on this crtc */
1433 int num_scalers;
1434
1435 /* for loading single buffered registers during vblank */
1436 struct pm_qos_request vblank_pm_qos;
1437
1438 #ifdef CONFIG_DEBUG_FS
1439 struct intel_pipe_crc pipe_crc;
1440 #endif
1441
1442 bool block_dc_for_vblank;
1443 };
1444
1445 struct intel_plane_error {
1446 u32 ctl, surf, surflive;
1447 };
1448
1449 struct intel_plane {
1450 struct drm_plane base;
1451 enum i9xx_plane_id i9xx_plane;
1452 enum plane_id id;
1453 enum pipe pipe;
1454 bool need_async_flip_toggle_wa;
1455 u8 vtd_guard;
1456 u32 frontbuffer_bit;
1457
1458 struct {
1459 u32 base, cntl, size;
1460 } cursor;
1461
1462 struct intel_fbc *fbc;
1463
1464 /*
1465 * NOTE: Do not place new plane state fields here (e.g., when adding
1466 * new plane properties). New runtime state should now be placed in
1467 * the intel_plane_state structure and accessed via plane_state.
1468 */
1469
1470 int (*min_width)(const struct drm_framebuffer *fb,
1471 int color_plane,
1472 unsigned int rotation);
1473 int (*max_width)(const struct drm_framebuffer *fb,
1474 int color_plane,
1475 unsigned int rotation);
1476 int (*max_height)(const struct drm_framebuffer *fb,
1477 int color_plane,
1478 unsigned int rotation);
1479 unsigned int (*min_alignment)(struct intel_plane *plane,
1480 const struct drm_framebuffer *fb,
1481 int color_plane);
1482 unsigned int (*max_stride)(struct intel_plane *plane,
1483 u32 pixel_format, u64 modifier,
1484 unsigned int rotation);
1485 bool (*can_async_flip)(u64 modifier);
1486 /* Write all non-self arming plane registers */
1487 void (*update_noarm)(struct intel_dsb *dsb,
1488 struct intel_plane *plane,
1489 const struct intel_crtc_state *crtc_state,
1490 const struct intel_plane_state *plane_state);
1491 /* Write all self-arming plane registers */
1492 void (*update_arm)(struct intel_dsb *dsb,
1493 struct intel_plane *plane,
1494 const struct intel_crtc_state *crtc_state,
1495 const struct intel_plane_state *plane_state);
1496 /* Disable the plane, must arm */
1497 void (*disable_arm)(struct intel_dsb *dsb,
1498 struct intel_plane *plane,
1499 const struct intel_crtc_state *crtc_state);
1500 void (*capture_error)(struct intel_crtc *crtc,
1501 struct intel_plane *plane,
1502 struct intel_plane_error *error);
1503 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1504 int (*check_plane)(struct intel_crtc_state *crtc_state,
1505 struct intel_plane_state *plane_state);
1506 int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1507 const struct intel_plane_state *plane_state);
1508 void (*async_flip)(struct intel_dsb *dsb,
1509 struct intel_plane *plane,
1510 const struct intel_crtc_state *crtc_state,
1511 const struct intel_plane_state *plane_state,
1512 bool async_flip);
1513 void (*enable_flip_done)(struct intel_plane *plane);
1514 void (*disable_flip_done)(struct intel_plane *plane);
1515 };
1516
1517 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1518 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1519 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1520 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1521 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1522
1523 #define to_intel_crtc_state(crtc_state) \
1524 container_of_const((crtc_state), struct intel_crtc_state, uapi)
1525 #define to_intel_plane_state(plane_state) \
1526 container_of_const((plane_state), struct intel_plane_state, uapi)
1527 #define to_intel_framebuffer(fb) \
1528 container_of_const((fb), struct intel_framebuffer, base)
1529
1530 struct intel_hdmi {
1531 i915_reg_t hdmi_reg;
1532 struct {
1533 enum drm_dp_dual_mode_type type;
1534 int max_tmds_clock;
1535 } dp_dual_mode;
1536 struct intel_connector *attached_connector;
1537 struct cec_notifier *cec_notifier;
1538 };
1539
1540 struct intel_dp_mst_encoder;
1541
1542 struct intel_dp_compliance_data {
1543 unsigned long edid;
1544 u8 video_pattern;
1545 u16 hdisplay, vdisplay;
1546 u8 bpc;
1547 struct drm_dp_phy_test_params phytest;
1548 };
1549
1550 struct intel_dp_compliance {
1551 unsigned long test_type;
1552 struct intel_dp_compliance_data test_data;
1553 bool test_active;
1554 int test_link_rate;
1555 u8 test_lane_count;
1556 };
1557
1558 struct intel_dp_pcon_frl {
1559 bool is_trained;
1560 int trained_rate_gbps;
1561 };
1562
1563 struct intel_pps {
1564 int panel_power_up_delay;
1565 int panel_power_down_delay;
1566 int panel_power_cycle_delay;
1567 int backlight_on_delay;
1568 int backlight_off_delay;
1569 struct delayed_work panel_vdd_work;
1570 bool want_panel_vdd;
1571 bool initializing;
1572 unsigned long last_power_on;
1573 unsigned long last_backlight_off;
1574 ktime_t panel_power_off_time;
1575 intel_wakeref_t vdd_wakeref;
1576
1577 union {
1578 /*
1579 * Pipe whose power sequencer is currently locked into
1580 * this port. Only relevant on VLV/CHV.
1581 */
1582 enum pipe vlv_pps_pipe;
1583
1584 /*
1585 * Power sequencer index. Only relevant on BXT+.
1586 */
1587 int pps_idx;
1588 };
1589
1590 /*
1591 * Pipe currently driving the port. Used for preventing
1592 * the use of the PPS for any pipe currentrly driving
1593 * external DP as that will mess things up on VLV.
1594 */
1595 enum pipe vlv_active_pipe;
1596 /*
1597 * Set if the sequencer may be reset due to a power transition,
1598 * requiring a reinitialization. Only relevant on BXT+.
1599 */
1600 bool bxt_pps_reset;
1601 struct intel_pps_delays pps_delays;
1602 struct intel_pps_delays bios_pps_delays;
1603 };
1604
1605 struct intel_psr {
1606 /* Mutex for PSR state of the transcoder */
1607 struct mutex lock;
1608
1609 #define I915_PSR_DEBUG_MODE_MASK 0x0f
1610 #define I915_PSR_DEBUG_DEFAULT 0x00
1611 #define I915_PSR_DEBUG_DISABLE 0x01
1612 #define I915_PSR_DEBUG_ENABLE 0x02
1613 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
1614 #define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4
1615 #define I915_PSR_DEBUG_IRQ 0x10
1616 #define I915_PSR_DEBUG_SU_REGION_ET_DISABLE 0x20
1617 #define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
1618
1619 u32 debug;
1620 bool sink_support;
1621 bool source_support;
1622 bool enabled;
1623 bool paused;
1624 enum pipe pipe;
1625 enum transcoder transcoder;
1626 bool active;
1627 struct work_struct work;
1628 unsigned int busy_frontbuffer_bits;
1629 bool sink_psr2_support;
1630 bool link_standby;
1631 bool sel_update_enabled;
1632 bool psr2_sel_fetch_enabled;
1633 bool psr2_sel_fetch_cff_enabled;
1634 bool su_region_et_enabled;
1635 bool req_psr2_sdp_prior_scanline;
1636 u8 sink_sync_latency;
1637 ktime_t last_entry_attempt;
1638 ktime_t last_exit;
1639 bool sink_not_reliable;
1640 bool irq_aux_error;
1641 u16 su_w_granularity;
1642 u16 su_y_granularity;
1643 bool source_panel_replay_support;
1644 bool sink_panel_replay_support;
1645 bool sink_panel_replay_su_support;
1646 bool panel_replay_enabled;
1647 u32 dc3co_exitline;
1648 u32 dc3co_exit_delay;
1649 struct delayed_work dc3co_work;
1650 u8 entry_setup_frames;
1651
1652 bool link_ok;
1653 };
1654
1655 struct intel_dp {
1656 i915_reg_t output_reg;
1657 u32 DP;
1658 int link_rate;
1659 u8 lane_count;
1660 u8 sink_count;
1661 bool link_trained;
1662 bool needs_modeset_retry;
1663 bool use_max_params;
1664 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1665 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1666 u8 pr_dpcd;
1667 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1668 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1669 u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
1670 u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
1671 u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
1672 /* source rates */
1673 int num_source_rates;
1674 const int *source_rates;
1675 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1676 int num_sink_rates;
1677 int sink_rates[DP_MAX_SUPPORTED_RATES];
1678 bool use_rate_select;
1679 /* Max sink lane count as reported by DP_MAX_LANE_COUNT */
1680 int max_sink_lane_count;
1681 /* intersection of source and sink rates */
1682 int num_common_rates;
1683 int common_rates[DP_MAX_SUPPORTED_RATES];
1684 struct {
1685 /* TODO: move the rest of link specific fields to here */
1686 /* common rate,lane_count configs in bw order */
1687 int num_configs;
1688 #define INTEL_DP_MAX_LANE_COUNT 4
1689 #define INTEL_DP_MAX_SUPPORTED_LANE_CONFIGS (ilog2(INTEL_DP_MAX_LANE_COUNT) + 1)
1690 #define INTEL_DP_LANE_COUNT_EXP_BITS order_base_2(INTEL_DP_MAX_SUPPORTED_LANE_CONFIGS)
1691 #define INTEL_DP_LINK_RATE_IDX_BITS (BITS_PER_TYPE(u8) - INTEL_DP_LANE_COUNT_EXP_BITS)
1692 #define INTEL_DP_MAX_LINK_CONFIGS (DP_MAX_SUPPORTED_RATES * \
1693 INTEL_DP_MAX_SUPPORTED_LANE_CONFIGS)
1694 struct intel_dp_link_config {
1695 u8 link_rate_idx:INTEL_DP_LINK_RATE_IDX_BITS;
1696 u8 lane_count_exp:INTEL_DP_LANE_COUNT_EXP_BITS;
1697 } configs[INTEL_DP_MAX_LINK_CONFIGS];
1698 /* Max lane count for the current link */
1699 int max_lane_count;
1700 /* Max rate for the current link */
1701 int max_rate;
1702 /*
1703 * Link parameters for which the MST topology was probed.
1704 * Tracking these ensures that the MST path resources are
1705 * re-enumerated whenever the link is retrained with new link
1706 * parameters, as required by the DP standard.
1707 */
1708 int mst_probed_lane_count;
1709 int mst_probed_rate;
1710 int force_lane_count;
1711 int force_rate;
1712 bool retrain_disabled;
1713 /* Sequential link training failures after a passing LT */
1714 int seq_train_failures;
1715 int force_train_failure;
1716 bool force_retrain;
1717 } link;
1718 bool reset_link_params;
1719 int mso_link_count;
1720 int mso_pixel_overlap;
1721 /* sink or branch descriptor */
1722 struct drm_dp_desc desc;
1723 struct drm_dp_aux aux;
1724 u32 aux_busy_last_status;
1725 u8 train_set[4];
1726
1727 struct intel_pps pps;
1728
1729 bool is_mst;
1730 enum drm_dp_mst_mode mst_detect;
1731
1732 /* connector directly attached - won't be use for modeset in mst world */
1733 struct intel_connector *attached_connector;
1734 bool as_sdp_supported;
1735
1736 struct drm_dp_tunnel *tunnel;
1737 bool tunnel_suspended:1;
1738
1739 struct {
1740 struct intel_dp_mst_encoder *stream_encoders[I915_MAX_PIPES];
1741 struct drm_dp_mst_topology_mgr mgr;
1742 int active_links;
1743 } mst;
1744
1745 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1746 /*
1747 * This function returns the value we have to program the AUX_CTL
1748 * register with to kick off an AUX transaction.
1749 */
1750 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1751 u32 aux_clock_divider);
1752
1753 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1754 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1755
1756 /* This is called before a link training is starterd */
1757 void (*prepare_link_retrain)(struct intel_dp *intel_dp,
1758 const struct intel_crtc_state *crtc_state);
1759 void (*set_link_train)(struct intel_dp *intel_dp,
1760 const struct intel_crtc_state *crtc_state,
1761 u8 dp_train_pat);
1762 void (*set_idle_link_train)(struct intel_dp *intel_dp,
1763 const struct intel_crtc_state *crtc_state);
1764
1765 u8 (*preemph_max)(struct intel_dp *intel_dp);
1766 u8 (*voltage_max)(struct intel_dp *intel_dp,
1767 const struct intel_crtc_state *crtc_state);
1768
1769 /* Displayport compliance testing */
1770 struct intel_dp_compliance compliance;
1771
1772 /* Downstream facing port caps */
1773 struct {
1774 int min_tmds_clock, max_tmds_clock;
1775 int max_dotclock;
1776 int pcon_max_frl_bw;
1777 u8 max_bpc;
1778 bool ycbcr_444_to_420;
1779 bool ycbcr420_passthrough;
1780 bool rgb_to_ycbcr;
1781 } dfp;
1782
1783 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1784 struct pm_qos_request pm_qos;
1785
1786 /* Display stream compression testing */
1787 bool force_dsc_en;
1788 int force_dsc_output_format;
1789 bool force_dsc_fractional_bpp_en;
1790 int force_dsc_bpc;
1791
1792 bool hobl_failed;
1793 bool hobl_active;
1794
1795 struct intel_dp_pcon_frl frl;
1796
1797 struct intel_psr psr;
1798
1799 /* When we last wrote the OUI for eDP */
1800 unsigned long last_oui_write;
1801 bool oui_valid;
1802
1803 bool colorimetry_support;
1804
1805 struct {
1806 u8 io_wake_lines;
1807 u8 fast_wake_lines;
1808
1809 /* LNL and beyond */
1810 u8 check_entry_lines;
1811 u8 aux_less_wake_lines;
1812 u8 silence_period_sym_clocks;
1813 u8 lfps_half_cycle_num_of_syms;
1814 } alpm_parameters;
1815
1816 u8 alpm_dpcd;
1817
1818 struct {
1819 unsigned long mask;
1820 } quirks;
1821 };
1822
1823 enum lspcon_vendor {
1824 LSPCON_VENDOR_MCA,
1825 LSPCON_VENDOR_PARADE
1826 };
1827
1828 struct intel_lspcon {
1829 bool active;
1830 bool hdr_supported;
1831 enum drm_lspcon_mode mode;
1832 enum lspcon_vendor vendor;
1833 };
1834
1835 struct intel_digital_port {
1836 struct intel_encoder base;
1837 struct intel_dp dp;
1838 struct intel_hdmi hdmi;
1839 struct intel_lspcon lspcon;
1840 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1841
1842 bool lane_reversal;
1843 bool ddi_a_4_lanes;
1844 bool release_cl2_override;
1845 u8 max_lanes;
1846 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1847 enum aux_ch aux_ch;
1848 enum intel_display_power_domain ddi_io_power_domain;
1849 intel_wakeref_t ddi_io_wakeref;
1850 intel_wakeref_t aux_wakeref;
1851
1852 struct intel_tc_port *tc;
1853
1854 struct {
1855 /* protects num_streams reference count, port_data and auth_status */
1856 struct mutex mutex;
1857 /* the number of pipes using HDCP signalling out of this port */
1858 unsigned int num_streams;
1859 /* port HDCP auth status */
1860 bool auth_status;
1861 /* HDCP port data need to pass to security f/w */
1862 struct hdcp_port_data port_data;
1863 /* Whether the MST topology supports HDCP Type 1 Content */
1864 bool mst_type1_capable;
1865 } hdcp;
1866
1867 void (*write_infoframe)(struct intel_encoder *encoder,
1868 const struct intel_crtc_state *crtc_state,
1869 unsigned int type,
1870 const void *frame, ssize_t len);
1871 void (*read_infoframe)(struct intel_encoder *encoder,
1872 const struct intel_crtc_state *crtc_state,
1873 unsigned int type,
1874 void *frame, ssize_t len);
1875 void (*set_infoframes)(struct intel_encoder *encoder,
1876 bool enable,
1877 const struct intel_crtc_state *crtc_state,
1878 const struct drm_connector_state *conn_state);
1879 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1880 const struct intel_crtc_state *pipe_config);
1881 bool (*connected)(struct intel_encoder *encoder);
1882
1883 void (*lock)(struct intel_digital_port *dig_port);
1884 void (*unlock)(struct intel_digital_port *dig_port);
1885 };
1886
1887 struct intel_dp_mst_encoder {
1888 struct intel_encoder base;
1889 enum pipe pipe;
1890 struct intel_digital_port *primary;
1891 struct intel_connector *connector;
1892 };
1893
1894 static inline struct intel_encoder *
intel_attached_encoder(struct intel_connector * connector)1895 intel_attached_encoder(struct intel_connector *connector)
1896 {
1897 return connector->encoder;
1898 }
1899
intel_encoder_is_dig_port(struct intel_encoder * encoder)1900 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1901 {
1902 switch (encoder->type) {
1903 case INTEL_OUTPUT_DDI:
1904 case INTEL_OUTPUT_DP:
1905 case INTEL_OUTPUT_EDP:
1906 case INTEL_OUTPUT_HDMI:
1907 return true;
1908 default:
1909 return false;
1910 }
1911 }
1912
intel_encoder_is_mst(struct intel_encoder * encoder)1913 static inline bool intel_encoder_is_mst(struct intel_encoder *encoder)
1914 {
1915 return encoder->type == INTEL_OUTPUT_DP_MST;
1916 }
1917
1918 static inline struct intel_dp_mst_encoder *
enc_to_mst(struct intel_encoder * encoder)1919 enc_to_mst(struct intel_encoder *encoder)
1920 {
1921 return container_of(&encoder->base, struct intel_dp_mst_encoder,
1922 base.base);
1923 }
1924
1925 static inline struct intel_digital_port *
enc_to_dig_port(struct intel_encoder * encoder)1926 enc_to_dig_port(struct intel_encoder *encoder)
1927 {
1928 struct intel_encoder *intel_encoder = encoder;
1929
1930 if (intel_encoder_is_dig_port(intel_encoder))
1931 return container_of(&encoder->base, struct intel_digital_port,
1932 base.base);
1933 else if (intel_encoder_is_mst(intel_encoder))
1934 return enc_to_mst(encoder)->primary;
1935 else
1936 return NULL;
1937 }
1938
1939 static inline struct intel_digital_port *
intel_attached_dig_port(struct intel_connector * connector)1940 intel_attached_dig_port(struct intel_connector *connector)
1941 {
1942 return enc_to_dig_port(intel_attached_encoder(connector));
1943 }
1944
1945 static inline struct intel_hdmi *
enc_to_intel_hdmi(struct intel_encoder * encoder)1946 enc_to_intel_hdmi(struct intel_encoder *encoder)
1947 {
1948 return &enc_to_dig_port(encoder)->hdmi;
1949 }
1950
1951 static inline struct intel_hdmi *
intel_attached_hdmi(struct intel_connector * connector)1952 intel_attached_hdmi(struct intel_connector *connector)
1953 {
1954 return enc_to_intel_hdmi(intel_attached_encoder(connector));
1955 }
1956
enc_to_intel_dp(struct intel_encoder * encoder)1957 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)
1958 {
1959 return &enc_to_dig_port(encoder)->dp;
1960 }
1961
intel_attached_dp(struct intel_connector * connector)1962 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector)
1963 {
1964 if (connector->mst.dp)
1965 return connector->mst.dp;
1966 else
1967 return enc_to_intel_dp(intel_attached_encoder(connector));
1968 }
1969
intel_encoder_is_dp(struct intel_encoder * encoder)1970 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1971 {
1972 switch (encoder->type) {
1973 case INTEL_OUTPUT_DP:
1974 case INTEL_OUTPUT_EDP:
1975 return true;
1976 case INTEL_OUTPUT_DDI:
1977 /* Skip pure HDMI/DVI DDI encoders */
1978 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg);
1979 default:
1980 return false;
1981 }
1982 }
1983
intel_encoder_is_hdmi(struct intel_encoder * encoder)1984 static inline bool intel_encoder_is_hdmi(struct intel_encoder *encoder)
1985 {
1986 switch (encoder->type) {
1987 case INTEL_OUTPUT_HDMI:
1988 return true;
1989 case INTEL_OUTPUT_DDI:
1990 /* See if the HDMI encoder is valid. */
1991 return i915_mmio_reg_valid(enc_to_intel_hdmi(encoder)->hdmi_reg);
1992 default:
1993 return false;
1994 }
1995 }
1996
1997 static inline struct intel_digital_port *
dp_to_dig_port(struct intel_dp * intel_dp)1998 dp_to_dig_port(struct intel_dp *intel_dp)
1999 {
2000 return container_of(intel_dp, struct intel_digital_port, dp);
2001 }
2002
2003 static inline struct intel_digital_port *
hdmi_to_dig_port(struct intel_hdmi * intel_hdmi)2004 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
2005 {
2006 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
2007 }
2008
2009 static inline struct intel_plane_state *
intel_atomic_get_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)2010 intel_atomic_get_plane_state(struct intel_atomic_state *state,
2011 struct intel_plane *plane)
2012 {
2013 struct drm_plane_state *ret =
2014 drm_atomic_get_plane_state(&state->base, &plane->base);
2015
2016 if (IS_ERR(ret))
2017 return ERR_CAST(ret);
2018
2019 return to_intel_plane_state(ret);
2020 }
2021
2022 static inline struct intel_plane_state *
intel_atomic_get_old_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)2023 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
2024 struct intel_plane *plane)
2025 {
2026 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
2027 &plane->base));
2028 }
2029
2030 static inline struct intel_plane_state *
intel_atomic_get_new_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)2031 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
2032 struct intel_plane *plane)
2033 {
2034 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
2035 &plane->base));
2036 }
2037
2038 static inline struct intel_crtc_state *
intel_atomic_get_old_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)2039 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
2040 struct intel_crtc *crtc)
2041 {
2042 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
2043 &crtc->base));
2044 }
2045
2046 static inline struct intel_crtc_state *
intel_atomic_get_new_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)2047 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
2048 struct intel_crtc *crtc)
2049 {
2050 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
2051 &crtc->base));
2052 }
2053
2054 static inline struct intel_digital_connector_state *
intel_atomic_get_new_connector_state(struct intel_atomic_state * state,struct intel_connector * connector)2055 intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
2056 struct intel_connector *connector)
2057 {
2058 return to_intel_digital_connector_state(
2059 drm_atomic_get_new_connector_state(&state->base,
2060 &connector->base));
2061 }
2062
2063 static inline struct intel_digital_connector_state *
intel_atomic_get_old_connector_state(struct intel_atomic_state * state,struct intel_connector * connector)2064 intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
2065 struct intel_connector *connector)
2066 {
2067 return to_intel_digital_connector_state(
2068 drm_atomic_get_old_connector_state(&state->base,
2069 &connector->base));
2070 }
2071
2072 /* intel_display.c */
2073 static inline bool
intel_crtc_has_type(const struct intel_crtc_state * crtc_state,enum intel_output_type type)2074 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
2075 enum intel_output_type type)
2076 {
2077 return crtc_state->output_types & BIT(type);
2078 }
2079
2080 static inline bool
intel_crtc_has_dp_encoder(const struct intel_crtc_state * crtc_state)2081 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
2082 {
2083 return crtc_state->output_types &
2084 (BIT(INTEL_OUTPUT_DP) |
2085 BIT(INTEL_OUTPUT_DP_MST) |
2086 BIT(INTEL_OUTPUT_EDP));
2087 }
2088
2089 static inline bool
intel_crtc_needs_modeset(const struct intel_crtc_state * crtc_state)2090 intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state)
2091 {
2092 return drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
2093 }
2094
2095 static inline bool
intel_crtc_needs_fastset(const struct intel_crtc_state * crtc_state)2096 intel_crtc_needs_fastset(const struct intel_crtc_state *crtc_state)
2097 {
2098 return crtc_state->update_pipe;
2099 }
2100
2101 static inline bool
intel_crtc_needs_color_update(const struct intel_crtc_state * crtc_state)2102 intel_crtc_needs_color_update(const struct intel_crtc_state *crtc_state)
2103 {
2104 return crtc_state->uapi.color_mgmt_changed ||
2105 intel_crtc_needs_fastset(crtc_state) ||
2106 intel_crtc_needs_modeset(crtc_state);
2107 }
2108
2109 static inline struct intel_frontbuffer *
to_intel_frontbuffer(struct drm_framebuffer * fb)2110 to_intel_frontbuffer(struct drm_framebuffer *fb)
2111 {
2112 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
2113 }
2114
2115 /*
2116 * Conversion functions/macros from various pointer types to struct
2117 * intel_display pointer.
2118 */
2119 #define __drm_device_to_intel_display(p) \
2120 ((p) ? __drm_to_display(p) : NULL)
2121 #define __device_to_intel_display(p) \
2122 __drm_device_to_intel_display(dev_get_drvdata(p))
2123 #define __pci_dev_to_intel_display(p) \
2124 __drm_device_to_intel_display(pci_get_drvdata(p))
2125 #define __intel_atomic_state_to_intel_display(p) \
2126 __drm_device_to_intel_display((p)->base.dev)
2127 #define __intel_connector_to_intel_display(p) \
2128 __drm_device_to_intel_display((p)->base.dev)
2129 #define __intel_crtc_to_intel_display(p) \
2130 __drm_device_to_intel_display((p)->base.dev)
2131 #define __intel_crtc_state_to_intel_display(p) \
2132 __drm_device_to_intel_display((p)->uapi.crtc->dev)
2133 #define __intel_digital_port_to_intel_display(p) \
2134 __drm_device_to_intel_display((p)->base.base.dev)
2135 #define __intel_dp_to_intel_display(p) \
2136 __drm_device_to_intel_display(dp_to_dig_port(p)->base.base.dev)
2137 #define __intel_encoder_to_intel_display(p) \
2138 __drm_device_to_intel_display((p)->base.dev)
2139 #define __intel_hdmi_to_intel_display(p) \
2140 __drm_device_to_intel_display(hdmi_to_dig_port(p)->base.base.dev)
2141 #define __intel_plane_to_intel_display(p) \
2142 __drm_device_to_intel_display((p)->base.dev)
2143 #define __intel_plane_state_to_intel_display(p) \
2144 __drm_device_to_intel_display((p)->uapi.plane->dev)
2145
2146 /* Helper for generic association. Map types to conversion functions/macros. */
2147 #define __assoc(type, p) \
2148 struct type: __##type##_to_intel_display((struct type *)(p))
2149
2150 /* Convert various pointer types to struct intel_display pointer. */
2151 #define to_intel_display(p) \
2152 _Generic(*p, \
2153 __assoc(drm_device, p), \
2154 __assoc(device, p), \
2155 __assoc(pci_dev, p), \
2156 __assoc(intel_atomic_state, p), \
2157 __assoc(intel_connector, p), \
2158 __assoc(intel_crtc, p), \
2159 __assoc(intel_crtc_state, p), \
2160 __assoc(intel_digital_port, p), \
2161 __assoc(intel_dp, p), \
2162 __assoc(intel_encoder, p), \
2163 __assoc(intel_hdmi, p), \
2164 __assoc(intel_plane, p), \
2165 __assoc(intel_plane_state, p))
2166
2167 #endif /* __INTEL_DISPLAY_TYPES_H__ */
2168