1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7 #include <drm/display/drm_hdmi_state_helper.h>
8
9 #include <linux/hdmi.h>
10
11 #include <sound/hdmi-codec.h>
12
13 #include "hdmi.h"
14
15 /* Supported HDMI Audio sample rates */
16 #define MSM_HDMI_SAMPLE_RATE_32KHZ 0
17 #define MSM_HDMI_SAMPLE_RATE_44_1KHZ 1
18 #define MSM_HDMI_SAMPLE_RATE_48KHZ 2
19 #define MSM_HDMI_SAMPLE_RATE_88_2KHZ 3
20 #define MSM_HDMI_SAMPLE_RATE_96KHZ 4
21 #define MSM_HDMI_SAMPLE_RATE_176_4KHZ 5
22 #define MSM_HDMI_SAMPLE_RATE_192KHZ 6
23 #define MSM_HDMI_SAMPLE_RATE_MAX 7
24
25
26 struct hdmi_msm_audio_acr {
27 uint32_t n; /* N parameter for clock regeneration */
28 uint32_t cts; /* CTS parameter for clock regeneration */
29 };
30
31 struct hdmi_msm_audio_arcs {
32 unsigned long int pixclock;
33 struct hdmi_msm_audio_acr lut[MSM_HDMI_SAMPLE_RATE_MAX];
34 };
35
36 #define HDMI_MSM_AUDIO_ARCS(pclk, ...) { (1000 * (pclk)), __VA_ARGS__ }
37
38 /* Audio constants lookup table for hdmi_msm_audio_acr_setup */
39 /* Valid Pixel-Clock rates: 25.2MHz, 27MHz, 27.03MHz, 74.25MHz, 148.5MHz */
40 static const struct hdmi_msm_audio_arcs acr_lut[] = {
41 /* 25.200MHz */
42 HDMI_MSM_AUDIO_ARCS(25200, {
43 {4096, 25200}, {6272, 28000}, {6144, 25200}, {12544, 28000},
44 {12288, 25200}, {25088, 28000}, {24576, 25200} }),
45 /* 27.000MHz */
46 HDMI_MSM_AUDIO_ARCS(27000, {
47 {4096, 27000}, {6272, 30000}, {6144, 27000}, {12544, 30000},
48 {12288, 27000}, {25088, 30000}, {24576, 27000} }),
49 /* 27.027MHz */
50 HDMI_MSM_AUDIO_ARCS(27030, {
51 {4096, 27027}, {6272, 30030}, {6144, 27027}, {12544, 30030},
52 {12288, 27027}, {25088, 30030}, {24576, 27027} }),
53 /* 74.250MHz */
54 HDMI_MSM_AUDIO_ARCS(74250, {
55 {4096, 74250}, {6272, 82500}, {6144, 74250}, {12544, 82500},
56 {12288, 74250}, {25088, 82500}, {24576, 74250} }),
57 /* 148.500MHz */
58 HDMI_MSM_AUDIO_ARCS(148500, {
59 {4096, 148500}, {6272, 165000}, {6144, 148500}, {12544, 165000},
60 {12288, 148500}, {25088, 165000}, {24576, 148500} }),
61 };
62
get_arcs(unsigned long int pixclock)63 static const struct hdmi_msm_audio_arcs *get_arcs(unsigned long int pixclock)
64 {
65 int i;
66
67 for (i = 0; i < ARRAY_SIZE(acr_lut); i++) {
68 const struct hdmi_msm_audio_arcs *arcs = &acr_lut[i];
69 if (arcs->pixclock == pixclock)
70 return arcs;
71 }
72
73 return NULL;
74 }
75
msm_hdmi_audio_update(struct hdmi * hdmi)76 int msm_hdmi_audio_update(struct hdmi *hdmi)
77 {
78 struct hdmi_audio *audio = &hdmi->audio;
79 const struct hdmi_msm_audio_arcs *arcs = NULL;
80 bool enabled = audio->enabled;
81 uint32_t acr_pkt_ctrl, vbi_pkt_ctrl, aud_pkt_ctrl;
82 uint32_t audio_config;
83
84 if (!hdmi->connector->display_info.is_hdmi)
85 return -EINVAL;
86
87 DBG("audio: enabled=%d, channels=%d, rate=%d",
88 audio->enabled, audio->channels, audio->rate);
89
90 DBG("video: power_on=%d, pixclock=%lu", hdmi->power_on, hdmi->pixclock);
91
92 if (enabled && !(hdmi->power_on && hdmi->pixclock)) {
93 DBG("disabling audio: no video");
94 enabled = false;
95 }
96
97 if (enabled) {
98 arcs = get_arcs(hdmi->pixclock);
99 if (!arcs) {
100 DBG("disabling audio: unsupported pixclock: %lu",
101 hdmi->pixclock);
102 enabled = false;
103 }
104 }
105
106 /* Read first before writing */
107 acr_pkt_ctrl = hdmi_read(hdmi, REG_HDMI_ACR_PKT_CTRL);
108 vbi_pkt_ctrl = hdmi_read(hdmi, REG_HDMI_VBI_PKT_CTRL);
109 aud_pkt_ctrl = hdmi_read(hdmi, REG_HDMI_AUDIO_PKT_CTRL1);
110 audio_config = hdmi_read(hdmi, REG_HDMI_AUDIO_CFG);
111
112 /* Clear N/CTS selection bits */
113 acr_pkt_ctrl &= ~HDMI_ACR_PKT_CTRL_SELECT__MASK;
114
115 if (enabled) {
116 uint32_t n, cts, multiplier;
117 enum hdmi_acr_cts select;
118
119 n = arcs->lut[audio->rate].n;
120 cts = arcs->lut[audio->rate].cts;
121
122 if ((MSM_HDMI_SAMPLE_RATE_192KHZ == audio->rate) ||
123 (MSM_HDMI_SAMPLE_RATE_176_4KHZ == audio->rate)) {
124 multiplier = 4;
125 n >>= 2; /* divide N by 4 and use multiplier */
126 } else if ((MSM_HDMI_SAMPLE_RATE_96KHZ == audio->rate) ||
127 (MSM_HDMI_SAMPLE_RATE_88_2KHZ == audio->rate)) {
128 multiplier = 2;
129 n >>= 1; /* divide N by 2 and use multiplier */
130 } else {
131 multiplier = 1;
132 }
133
134 DBG("n=%u, cts=%u, multiplier=%u", n, cts, multiplier);
135
136 acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_SOURCE;
137 acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY;
138 acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_N_MULTIPLIER(multiplier);
139
140 if ((MSM_HDMI_SAMPLE_RATE_48KHZ == audio->rate) ||
141 (MSM_HDMI_SAMPLE_RATE_96KHZ == audio->rate) ||
142 (MSM_HDMI_SAMPLE_RATE_192KHZ == audio->rate))
143 select = ACR_48;
144 else if ((MSM_HDMI_SAMPLE_RATE_44_1KHZ == audio->rate) ||
145 (MSM_HDMI_SAMPLE_RATE_88_2KHZ == audio->rate) ||
146 (MSM_HDMI_SAMPLE_RATE_176_4KHZ == audio->rate))
147 select = ACR_44;
148 else /* default to 32k */
149 select = ACR_32;
150
151 acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_SELECT(select);
152
153 hdmi_write(hdmi, REG_HDMI_ACR_0(select - 1),
154 HDMI_ACR_0_CTS(cts));
155 hdmi_write(hdmi, REG_HDMI_ACR_1(select - 1),
156 HDMI_ACR_1_N(n));
157
158 hdmi_write(hdmi, REG_HDMI_AUDIO_PKT_CTRL2,
159 COND(audio->channels != 2, HDMI_AUDIO_PKT_CTRL2_LAYOUT) |
160 HDMI_AUDIO_PKT_CTRL2_OVERRIDE);
161
162 acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_CONT;
163 acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_SEND;
164
165 hdmi_write(hdmi, REG_HDMI_GC, 0);
166
167 vbi_pkt_ctrl |= HDMI_VBI_PKT_CTRL_GC_ENABLE;
168 vbi_pkt_ctrl |= HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME;
169
170 aud_pkt_ctrl |= HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND;
171
172 audio_config &= ~HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK;
173 audio_config |= HDMI_AUDIO_CFG_FIFO_WATERMARK(4);
174 audio_config |= HDMI_AUDIO_CFG_ENGINE_ENABLE;
175 } else {
176 acr_pkt_ctrl &= ~HDMI_ACR_PKT_CTRL_CONT;
177 acr_pkt_ctrl &= ~HDMI_ACR_PKT_CTRL_SEND;
178 vbi_pkt_ctrl &= ~HDMI_VBI_PKT_CTRL_GC_ENABLE;
179 vbi_pkt_ctrl &= ~HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME;
180 aud_pkt_ctrl &= ~HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND;
181 audio_config &= ~HDMI_AUDIO_CFG_ENGINE_ENABLE;
182 }
183
184 hdmi_write(hdmi, REG_HDMI_ACR_PKT_CTRL, acr_pkt_ctrl);
185 hdmi_write(hdmi, REG_HDMI_VBI_PKT_CTRL, vbi_pkt_ctrl);
186 hdmi_write(hdmi, REG_HDMI_AUDIO_PKT_CTRL1, aud_pkt_ctrl);
187
188 hdmi_write(hdmi, REG_HDMI_AUD_INT,
189 COND(enabled, HDMI_AUD_INT_AUD_FIFO_URUN_INT) |
190 COND(enabled, HDMI_AUD_INT_AUD_SAM_DROP_INT));
191
192 hdmi_write(hdmi, REG_HDMI_AUDIO_CFG, audio_config);
193
194
195 DBG("audio %sabled", enabled ? "en" : "dis");
196
197 return 0;
198 }
199
msm_hdmi_bridge_audio_prepare(struct drm_connector * connector,struct drm_bridge * bridge,struct hdmi_codec_daifmt * daifmt,struct hdmi_codec_params * params)200 int msm_hdmi_bridge_audio_prepare(struct drm_connector *connector,
201 struct drm_bridge *bridge,
202 struct hdmi_codec_daifmt *daifmt,
203 struct hdmi_codec_params *params)
204 {
205 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
206 struct hdmi *hdmi = hdmi_bridge->hdmi;
207 unsigned int rate;
208 int ret;
209
210 drm_dbg_driver(bridge->dev, "%u Hz, %d bit, %d channels\n",
211 params->sample_rate,
212 params->sample_width,
213 params->cea.channels);
214
215 switch (params->sample_rate) {
216 case 32000:
217 rate = MSM_HDMI_SAMPLE_RATE_32KHZ;
218 break;
219 case 44100:
220 rate = MSM_HDMI_SAMPLE_RATE_44_1KHZ;
221 break;
222 case 48000:
223 rate = MSM_HDMI_SAMPLE_RATE_48KHZ;
224 break;
225 case 88200:
226 rate = MSM_HDMI_SAMPLE_RATE_88_2KHZ;
227 break;
228 case 96000:
229 rate = MSM_HDMI_SAMPLE_RATE_96KHZ;
230 break;
231 case 176400:
232 rate = MSM_HDMI_SAMPLE_RATE_176_4KHZ;
233 break;
234 case 192000:
235 rate = MSM_HDMI_SAMPLE_RATE_192KHZ;
236 break;
237 default:
238 drm_err(bridge->dev, "rate[%d] not supported!\n",
239 params->sample_rate);
240 return -EINVAL;
241 }
242
243 ret = drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector,
244 ¶ms->cea);
245 if (ret)
246 return ret;
247
248 hdmi->audio.rate = rate;
249 hdmi->audio.channels = params->cea.channels;
250 hdmi->audio.enabled = true;
251
252 return msm_hdmi_audio_update(hdmi);
253 }
254
msm_hdmi_bridge_audio_shutdown(struct drm_connector * connector,struct drm_bridge * bridge)255 void msm_hdmi_bridge_audio_shutdown(struct drm_connector *connector,
256 struct drm_bridge *bridge)
257 {
258 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
259 struct hdmi *hdmi = hdmi_bridge->hdmi;
260
261 drm_atomic_helper_connector_hdmi_clear_audio_infoframe(connector);
262
263 hdmi->audio.rate = 0;
264 hdmi->audio.channels = 2;
265 hdmi->audio.enabled = false;
266
267 msm_hdmi_audio_update(hdmi);
268 }
269