1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "reg_helper.h"
27 #include "dcn30/dcn30_mpc.h"
28 #include "dcn30/dcn30_cm_common.h"
29 #include "dcn32_mpc.h"
30 #include "basics/conversion.h"
31 #include "dcn10/dcn10_cm_common.h"
32 #include "dc.h"
33
34 #define REG(reg)\
35 mpc30->mpc_regs->reg
36
37 #define CTX \
38 mpc30->base.ctx
39
40 #undef FN
41 #define FN(reg_name, field_name) \
42 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
43
44
mpc32_mpc_init(struct mpc * mpc)45 void mpc32_mpc_init(struct mpc *mpc)
46 {
47 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
48 int mpcc_id;
49
50 mpc3_mpc_init(mpc);
51
52 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
53 if (mpc30->mpc_mask->MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE) {
54 for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) {
55 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, 3);
56 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, 3);
57 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, 3);
58 }
59 }
60 if (mpc30->mpc_mask->MPCC_OGAM_MEM_LOW_PWR_MODE) {
61 for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++)
62 REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_LOW_PWR_MODE, 3);
63 }
64 }
65 }
66
mpc32_power_on_blnd_lut(struct mpc * mpc,uint32_t mpcc_id,bool power_on)67 void mpc32_power_on_blnd_lut(
68 struct mpc *mpc,
69 uint32_t mpcc_id,
70 bool power_on)
71 {
72 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
73
74 REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, MPCC_MCM_1DLUT_MEM_PWR_DIS, power_on);
75
76 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm) {
77 if (power_on) {
78 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0);
79 REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5);
80 } else if (!mpc->ctx->dc->debug.disable_mem_low_power) {
81 /* TODO: change to mpc
82 * dpp_base->ctx->dc->optimized_required = true;
83 * dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;
84 */
85 }
86 } else {
87 REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
88 MPCC_MCM_1DLUT_MEM_PWR_FORCE, power_on == true ? 0 : 1);
89 }
90 }
91
mpc32_get_post1dlut_current(struct mpc * mpc,uint32_t mpcc_id)92 static enum dc_lut_mode mpc32_get_post1dlut_current(struct mpc *mpc, uint32_t mpcc_id)
93 {
94 enum dc_lut_mode mode;
95 uint32_t mode_current = 0;
96 uint32_t in_use = 0;
97
98 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
99
100 REG_GET(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
101 MPCC_MCM_1DLUT_MODE_CURRENT, &mode_current);
102 REG_GET(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
103 MPCC_MCM_1DLUT_SELECT_CURRENT, &in_use);
104
105 switch (mode_current) {
106 case 0:
107 case 1:
108 mode = LUT_BYPASS;
109 break;
110
111 case 2:
112 if (in_use == 0)
113 mode = LUT_RAM_A;
114 else
115 mode = LUT_RAM_B;
116 break;
117 default:
118 mode = LUT_BYPASS;
119 break;
120 }
121 return mode;
122 }
123
mpc32_configure_post1dlut(struct mpc * mpc,uint32_t mpcc_id,bool is_ram_a)124 void mpc32_configure_post1dlut(
125 struct mpc *mpc,
126 uint32_t mpcc_id,
127 bool is_ram_a)
128 {
129 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
130
131 //TODO: this
132 REG_UPDATE_2(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id],
133 MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 7,
134 MPCC_MCM_1DLUT_LUT_HOST_SEL, is_ram_a == true ? 0 : 1);
135
136 REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
137 }
138
mpc32_post1dlut_get_reg_field(struct dcn30_mpc * mpc,struct dcn3_xfer_func_reg * reg)139 static void mpc32_post1dlut_get_reg_field(
140 struct dcn30_mpc *mpc,
141 struct dcn3_xfer_func_reg *reg)
142 {
143 reg->shifts.exp_region0_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;
144 reg->masks.exp_region0_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;
145 reg->shifts.exp_region0_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;
146 reg->masks.exp_region0_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;
147 reg->shifts.exp_region1_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;
148 reg->masks.exp_region1_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;
149 reg->shifts.exp_region1_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS;
150 reg->masks.exp_region1_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS;
151
152 reg->shifts.field_region_end = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;
153 reg->masks.field_region_end = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;
154 reg->shifts.field_region_end_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;
155 reg->masks.field_region_end_slope = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;
156 reg->shifts.field_region_end_base = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;
157 reg->masks.field_region_end_base = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;
158 reg->shifts.field_region_linear_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;
159 reg->masks.field_region_linear_slope = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;
160 reg->shifts.exp_region_start = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;
161 reg->masks.exp_region_start = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;
162 reg->shifts.exp_resion_start_segment = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;
163 reg->masks.exp_resion_start_segment = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;
164 }
165
166 /*program blnd lut RAM A*/
mpc32_program_post1dluta_settings(struct mpc * mpc,uint32_t mpcc_id,const struct pwl_params * params)167 void mpc32_program_post1dluta_settings(
168 struct mpc *mpc,
169 uint32_t mpcc_id,
170 const struct pwl_params *params)
171 {
172 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
173 struct dcn3_xfer_func_reg gam_regs;
174
175 mpc32_post1dlut_get_reg_field(mpc30, &gam_regs);
176
177 gam_regs.start_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_B[mpcc_id]);
178 gam_regs.start_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_G[mpcc_id]);
179 gam_regs.start_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_R[mpcc_id]);
180 gam_regs.start_slope_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B[mpcc_id]);
181 gam_regs.start_slope_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G[mpcc_id]);
182 gam_regs.start_slope_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R[mpcc_id]);
183 gam_regs.start_end_cntl1_b = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_B[mpcc_id]);
184 gam_regs.start_end_cntl2_b = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_B[mpcc_id]);
185 gam_regs.start_end_cntl1_g = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_G[mpcc_id]);
186 gam_regs.start_end_cntl2_g = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_G[mpcc_id]);
187 gam_regs.start_end_cntl1_r = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_R[mpcc_id]);
188 gam_regs.start_end_cntl2_r = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_R[mpcc_id]);
189 gam_regs.region_start = REG(MPCC_MCM_1DLUT_RAMA_REGION_0_1[mpcc_id]);
190 gam_regs.region_end = REG(MPCC_MCM_1DLUT_RAMA_REGION_32_33[mpcc_id]);
191
192 cm_helper_program_gamcor_xfer_func(mpc->ctx, params, &gam_regs);
193 }
194
195 /*program blnd lut RAM B*/
mpc32_program_post1dlutb_settings(struct mpc * mpc,uint32_t mpcc_id,const struct pwl_params * params)196 void mpc32_program_post1dlutb_settings(
197 struct mpc *mpc,
198 uint32_t mpcc_id,
199 const struct pwl_params *params)
200 {
201 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
202 struct dcn3_xfer_func_reg gam_regs;
203
204 mpc32_post1dlut_get_reg_field(mpc30, &gam_regs);
205
206 gam_regs.start_cntl_b = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_B[mpcc_id]);
207 gam_regs.start_cntl_g = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_G[mpcc_id]);
208 gam_regs.start_cntl_r = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_R[mpcc_id]);
209 gam_regs.start_slope_cntl_b = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B[mpcc_id]);
210 gam_regs.start_slope_cntl_g = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G[mpcc_id]);
211 gam_regs.start_slope_cntl_r = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R[mpcc_id]);
212 gam_regs.start_end_cntl1_b = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_B[mpcc_id]);
213 gam_regs.start_end_cntl2_b = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_B[mpcc_id]);
214 gam_regs.start_end_cntl1_g = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_G[mpcc_id]);
215 gam_regs.start_end_cntl2_g = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_G[mpcc_id]);
216 gam_regs.start_end_cntl1_r = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_R[mpcc_id]);
217 gam_regs.start_end_cntl2_r = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_R[mpcc_id]);
218 gam_regs.region_start = REG(MPCC_MCM_1DLUT_RAMB_REGION_0_1[mpcc_id]);
219 gam_regs.region_end = REG(MPCC_MCM_1DLUT_RAMB_REGION_32_33[mpcc_id]);
220
221 cm_helper_program_gamcor_xfer_func(mpc->ctx, params, &gam_regs);
222 }
223
mpc32_program_post1dlut_pwl(struct mpc * mpc,uint32_t mpcc_id,const struct pwl_result_data * rgb,uint32_t num)224 void mpc32_program_post1dlut_pwl(
225 struct mpc *mpc,
226 uint32_t mpcc_id,
227 const struct pwl_result_data *rgb,
228 uint32_t num)
229 {
230 uint32_t i;
231 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
232 uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
233 uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
234 uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
235
236 if (is_rgb_equal(rgb, num)) {
237 for (i = 0 ; i < num; i++)
238 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].red_reg);
239 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_red);
240 } else {
241 REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
242 REG_UPDATE(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 4);
243 for (i = 0 ; i < num; i++)
244 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].red_reg);
245 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_red);
246
247 REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
248 REG_UPDATE(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 2);
249 for (i = 0 ; i < num; i++)
250 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].green_reg);
251 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_green);
252
253 REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
254 REG_UPDATE(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 1);
255 for (i = 0 ; i < num; i++)
256 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].blue_reg);
257 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_blue);
258 }
259 }
260
mpc32_program_post1dlut(struct mpc * mpc,const struct pwl_params * params,uint32_t mpcc_id)261 bool mpc32_program_post1dlut(
262 struct mpc *mpc,
263 const struct pwl_params *params,
264 uint32_t mpcc_id)
265 {
266 enum dc_lut_mode current_mode;
267 enum dc_lut_mode next_mode;
268 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
269
270 if (params == NULL) {
271 REG_SET(MPCC_MCM_1DLUT_CONTROL[mpcc_id], 0, MPCC_MCM_1DLUT_MODE, 0);
272 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm)
273 mpc32_power_on_blnd_lut(mpc, mpcc_id, false);
274 return false;
275 }
276
277 current_mode = mpc32_get_post1dlut_current(mpc, mpcc_id);
278 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_B)
279 next_mode = LUT_RAM_A;
280 else
281 next_mode = LUT_RAM_B;
282
283 mpc32_power_on_blnd_lut(mpc, mpcc_id, true);
284 mpc32_configure_post1dlut(mpc, mpcc_id, next_mode == LUT_RAM_A);
285
286 if (next_mode == LUT_RAM_A)
287 mpc32_program_post1dluta_settings(mpc, mpcc_id, params);
288 else
289 mpc32_program_post1dlutb_settings(mpc, mpcc_id, params);
290
291 mpc32_program_post1dlut_pwl(
292 mpc, mpcc_id, params->rgb_resulted, params->hw_points_num);
293
294 REG_UPDATE_2(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
295 MPCC_MCM_1DLUT_MODE, 2,
296 MPCC_MCM_1DLUT_SELECT, next_mode == LUT_RAM_A ? 0 : 1);
297
298 return true;
299 }
300
mpc32_get_shaper_current(struct mpc * mpc,uint32_t mpcc_id)301 static enum dc_lut_mode mpc32_get_shaper_current(struct mpc *mpc, uint32_t mpcc_id)
302 {
303 enum dc_lut_mode mode;
304 uint32_t state_mode;
305 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
306
307 REG_GET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_MODE_CURRENT, &state_mode);
308
309 switch (state_mode) {
310 case 0:
311 mode = LUT_BYPASS;
312 break;
313 case 1:
314 mode = LUT_RAM_A;
315 break;
316 case 2:
317 mode = LUT_RAM_B;
318 break;
319 default:
320 mode = LUT_BYPASS;
321 break;
322 }
323
324 return mode;
325 }
326
327
mpc32_configure_shaper_lut(struct mpc * mpc,bool is_ram_a,uint32_t mpcc_id)328 void mpc32_configure_shaper_lut(
329 struct mpc *mpc,
330 bool is_ram_a,
331 uint32_t mpcc_id)
332 {
333 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
334
335 REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id],
336 MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, 7);
337 REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id],
338 MPCC_MCM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
339 REG_SET(MPCC_MCM_SHAPER_LUT_INDEX[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_INDEX, 0);
340 }
341
342
mpc32_program_shaper_luta_settings(struct mpc * mpc,const struct pwl_params * params,uint32_t mpcc_id)343 void mpc32_program_shaper_luta_settings(
344 struct mpc *mpc,
345 const struct pwl_params *params,
346 uint32_t mpcc_id)
347 {
348 const struct gamma_curve *curve;
349 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
350
351 REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_B[mpcc_id], 0,
352 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
353 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
354 REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_G[mpcc_id], 0,
355 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x,
356 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
357 REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_R[mpcc_id], 0,
358 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x,
359 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
360
361 REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_B[mpcc_id], 0,
362 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
363 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
364 REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_G[mpcc_id], 0,
365 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x,
366 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y);
367 REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_R[mpcc_id], 0,
368 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x,
369 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y);
370
371 curve = params->arr_curve_points;
372 if (curve) {
373 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_0_1[mpcc_id], 0,
374 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
375 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
376 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
377 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
378
379 curve += 2;
380 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_2_3[mpcc_id], 0,
381 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
382 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
383 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
384 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
385
386 curve += 2;
387 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_4_5[mpcc_id], 0,
388 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
389 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
390 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
391 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
392
393 curve += 2;
394 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_6_7[mpcc_id], 0,
395 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
396 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
397 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
398 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
399
400 curve += 2;
401 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_8_9[mpcc_id], 0,
402 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
403 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
404 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
405 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
406
407 curve += 2;
408 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_10_11[mpcc_id], 0,
409 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
410 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
411 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
412 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
413
414 curve += 2;
415 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_12_13[mpcc_id], 0,
416 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
417 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
418 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
419 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
420
421 curve += 2;
422 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_14_15[mpcc_id], 0,
423 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
424 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
425 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
426 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
427
428
429 curve += 2;
430 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_16_17[mpcc_id], 0,
431 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
432 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
433 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
434 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
435
436 curve += 2;
437 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_18_19[mpcc_id], 0,
438 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
439 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
440 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
441 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
442
443 curve += 2;
444 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_20_21[mpcc_id], 0,
445 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
446 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
447 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
448 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
449
450 curve += 2;
451 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_22_23[mpcc_id], 0,
452 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
453 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
454 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
455 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
456
457 curve += 2;
458 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_24_25[mpcc_id], 0,
459 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
460 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
461 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
462 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
463
464 curve += 2;
465 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_26_27[mpcc_id], 0,
466 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
467 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
468 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
469 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
470
471 curve += 2;
472 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_28_29[mpcc_id], 0,
473 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
474 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
475 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
476 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
477
478 curve += 2;
479 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_30_31[mpcc_id], 0,
480 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
481 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
482 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
483 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
484
485 curve += 2;
486 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_32_33[mpcc_id], 0,
487 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
488 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
489 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
490 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
491 }
492 }
493
494
mpc32_program_shaper_lutb_settings(struct mpc * mpc,const struct pwl_params * params,uint32_t mpcc_id)495 void mpc32_program_shaper_lutb_settings(
496 struct mpc *mpc,
497 const struct pwl_params *params,
498 uint32_t mpcc_id)
499 {
500 const struct gamma_curve *curve;
501 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
502
503 REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_B[mpcc_id], 0,
504 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
505 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
506 REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_G[mpcc_id], 0,
507 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x,
508 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
509 REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_R[mpcc_id], 0,
510 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x,
511 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
512
513 REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_B[mpcc_id], 0,
514 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
515 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
516 REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_G[mpcc_id], 0,
517 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x,
518 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y);
519 REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_R[mpcc_id], 0,
520 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x,
521 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y);
522
523 curve = params->arr_curve_points;
524 if (curve) {
525 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_0_1[mpcc_id], 0,
526 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
527 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
528 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
529 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
530
531 curve += 2;
532 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_2_3[mpcc_id], 0,
533 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
534 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
535 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
536 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
537
538
539 curve += 2;
540 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_4_5[mpcc_id], 0,
541 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
542 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
543 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
544 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
545
546 curve += 2;
547 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_6_7[mpcc_id], 0,
548 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
549 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
550 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
551 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
552
553 curve += 2;
554 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_8_9[mpcc_id], 0,
555 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
556 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
557 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
558 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
559
560 curve += 2;
561 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_10_11[mpcc_id], 0,
562 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
563 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
564 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
565 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
566
567 curve += 2;
568 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_12_13[mpcc_id], 0,
569 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
570 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
571 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
572 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
573
574 curve += 2;
575 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_14_15[mpcc_id], 0,
576 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
577 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
578 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
579 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
580
581
582 curve += 2;
583 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_16_17[mpcc_id], 0,
584 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
585 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
586 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
587 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
588
589 curve += 2;
590 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_18_19[mpcc_id], 0,
591 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
592 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
593 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
594 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
595
596 curve += 2;
597 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_20_21[mpcc_id], 0,
598 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
599 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
600 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
601 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
602
603 curve += 2;
604 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_22_23[mpcc_id], 0,
605 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
606 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
607 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
608 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
609
610 curve += 2;
611 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_24_25[mpcc_id], 0,
612 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
613 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
614 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
615 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
616
617 curve += 2;
618 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_26_27[mpcc_id], 0,
619 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
620 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
621 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
622 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
623
624 curve += 2;
625 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_28_29[mpcc_id], 0,
626 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
627 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
628 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
629 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
630
631 curve += 2;
632 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_30_31[mpcc_id], 0,
633 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
634 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
635 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
636 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
637
638 curve += 2;
639 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_32_33[mpcc_id], 0,
640 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
641 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
642 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
643 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
644 }
645 }
646
647
mpc32_program_shaper_lut(struct mpc * mpc,const struct pwl_result_data * rgb,uint32_t num,uint32_t mpcc_id)648 void mpc32_program_shaper_lut(
649 struct mpc *mpc,
650 const struct pwl_result_data *rgb,
651 uint32_t num,
652 uint32_t mpcc_id)
653 {
654 uint32_t i, red, green, blue;
655 uint32_t red_delta, green_delta, blue_delta;
656 uint32_t red_value, green_value, blue_value;
657
658 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
659
660 for (i = 0 ; i < num; i++) {
661
662 red = rgb[i].red_reg;
663 green = rgb[i].green_reg;
664 blue = rgb[i].blue_reg;
665
666 red_delta = rgb[i].delta_red_reg;
667 green_delta = rgb[i].delta_green_reg;
668 blue_delta = rgb[i].delta_blue_reg;
669
670 red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff);
671 green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff);
672 blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff);
673
674 REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, red_value);
675 REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, green_value);
676 REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, blue_value);
677 }
678
679 }
680
681
mpc32_power_on_shaper_3dlut(struct mpc * mpc,uint32_t mpcc_id,bool power_on)682 void mpc32_power_on_shaper_3dlut(
683 struct mpc *mpc,
684 uint32_t mpcc_id,
685 bool power_on)
686 {
687 uint32_t power_status_shaper = 2;
688 uint32_t power_status_3dlut = 2;
689 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
690 int max_retries = 10;
691
692 REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
693 MPCC_MCM_3DLUT_MEM_PWR_DIS, power_on == true ? 1:0);
694 /* wait for memory to fully power up */
695 if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
696 REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, 0, 1, max_retries);
697 REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, 0, 1, max_retries);
698 }
699
700 /*read status is not mandatory, it is just for debugging*/
701 REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, &power_status_shaper);
702 REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, &power_status_3dlut);
703
704 if (power_status_shaper != 0 && power_on == true)
705 BREAK_TO_DEBUGGER();
706
707 if (power_status_3dlut != 0 && power_on == true)
708 BREAK_TO_DEBUGGER();
709 }
710
711
mpc32_program_shaper(struct mpc * mpc,const struct pwl_params * params,uint32_t mpcc_id)712 bool mpc32_program_shaper(
713 struct mpc *mpc,
714 const struct pwl_params *params,
715 uint32_t mpcc_id)
716 {
717 enum dc_lut_mode current_mode;
718 enum dc_lut_mode next_mode;
719
720 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
721
722 if (params == NULL) {
723 REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, 0);
724 return false;
725 }
726
727 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)
728 mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);
729
730 current_mode = mpc32_get_shaper_current(mpc, mpcc_id);
731
732 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
733 next_mode = LUT_RAM_B;
734 else
735 next_mode = LUT_RAM_A;
736
737 mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id);
738
739 if (next_mode == LUT_RAM_A)
740 mpc32_program_shaper_luta_settings(mpc, params, mpcc_id);
741 else
742 mpc32_program_shaper_lutb_settings(mpc, params, mpcc_id);
743
744 mpc32_program_shaper_lut(
745 mpc, params->rgb_resulted, params->hw_points_num, mpcc_id);
746
747 REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);
748 mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);
749
750 return true;
751 }
752
753
get3dlut_config(struct mpc * mpc,bool * is_17x17x17,bool * is_12bits_color_channel,int mpcc_id)754 static enum dc_lut_mode get3dlut_config(
755 struct mpc *mpc,
756 bool *is_17x17x17,
757 bool *is_12bits_color_channel,
758 int mpcc_id)
759 {
760 uint32_t i_mode, i_enable_10bits, lut_size;
761 enum dc_lut_mode mode;
762 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
763
764 REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id],
765 MPCC_MCM_3DLUT_MODE_CURRENT, &i_mode);
766
767 REG_GET(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id],
768 MPCC_MCM_3DLUT_30BIT_EN, &i_enable_10bits);
769
770 switch (i_mode) {
771 case 0:
772 mode = LUT_BYPASS;
773 break;
774 case 1:
775 mode = LUT_RAM_A;
776 break;
777 case 2:
778 mode = LUT_RAM_B;
779 break;
780 default:
781 mode = LUT_BYPASS;
782 break;
783 }
784 if (i_enable_10bits > 0)
785 *is_12bits_color_channel = false;
786 else
787 *is_12bits_color_channel = true;
788
789 REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &lut_size);
790
791 if (lut_size == 0)
792 *is_17x17x17 = true;
793 else
794 *is_17x17x17 = false;
795
796 return mode;
797 }
798
799
mpc32_select_3dlut_ram(struct mpc * mpc,enum dc_lut_mode mode,bool is_color_channel_12bits,uint32_t mpcc_id)800 void mpc32_select_3dlut_ram(
801 struct mpc *mpc,
802 enum dc_lut_mode mode,
803 bool is_color_channel_12bits,
804 uint32_t mpcc_id)
805 {
806 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
807
808 REG_UPDATE_2(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id],
809 MPCC_MCM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,
810 MPCC_MCM_3DLUT_30BIT_EN, is_color_channel_12bits == true ? 0:1);
811 }
812
813
mpc32_select_3dlut_ram_mask(struct mpc * mpc,uint32_t ram_selection_mask,uint32_t mpcc_id)814 void mpc32_select_3dlut_ram_mask(
815 struct mpc *mpc,
816 uint32_t ram_selection_mask,
817 uint32_t mpcc_id)
818 {
819 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
820
821 REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_WRITE_EN_MASK,
822 ram_selection_mask);
823 REG_SET(MPCC_MCM_3DLUT_INDEX[mpcc_id], 0, MPCC_MCM_3DLUT_INDEX, 0);
824 }
825
826
mpc32_set3dlut_ram12(struct mpc * mpc,const struct dc_rgb * lut,uint32_t entries,uint32_t mpcc_id)827 void mpc32_set3dlut_ram12(
828 struct mpc *mpc,
829 const struct dc_rgb *lut,
830 uint32_t entries,
831 uint32_t mpcc_id)
832 {
833 uint32_t i, red, green, blue, red1, green1, blue1;
834 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
835
836 for (i = 0 ; i < entries; i += 2) {
837 red = lut[i].red<<4;
838 green = lut[i].green<<4;
839 blue = lut[i].blue<<4;
840 red1 = lut[i+1].red<<4;
841 green1 = lut[i+1].green<<4;
842 blue1 = lut[i+1].blue<<4;
843
844 REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
845 MPCC_MCM_3DLUT_DATA0, red,
846 MPCC_MCM_3DLUT_DATA1, red1);
847
848 REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
849 MPCC_MCM_3DLUT_DATA0, green,
850 MPCC_MCM_3DLUT_DATA1, green1);
851
852 REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
853 MPCC_MCM_3DLUT_DATA0, blue,
854 MPCC_MCM_3DLUT_DATA1, blue1);
855 }
856 }
857
858
mpc32_set3dlut_ram10(struct mpc * mpc,const struct dc_rgb * lut,uint32_t entries,uint32_t mpcc_id)859 void mpc32_set3dlut_ram10(
860 struct mpc *mpc,
861 const struct dc_rgb *lut,
862 uint32_t entries,
863 uint32_t mpcc_id)
864 {
865 uint32_t i, red, green, blue, value;
866 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
867
868 for (i = 0; i < entries; i++) {
869 red = lut[i].red;
870 green = lut[i].green;
871 blue = lut[i].blue;
872 //should we shift red 22bit and green 12?
873 value = (red<<20) | (green<<10) | blue;
874
875 REG_SET(MPCC_MCM_3DLUT_DATA_30BIT[mpcc_id], 0, MPCC_MCM_3DLUT_DATA_30BIT, value);
876 }
877
878 }
879
880
mpc32_set_3dlut_mode(struct mpc * mpc,enum dc_lut_mode mode,bool is_color_channel_12bits,bool is_lut_size17x17x17,uint32_t mpcc_id)881 void mpc32_set_3dlut_mode(
882 struct mpc *mpc,
883 enum dc_lut_mode mode,
884 bool is_color_channel_12bits,
885 bool is_lut_size17x17x17,
886 uint32_t mpcc_id)
887 {
888 uint32_t lut_mode;
889 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
890
891 // set default 3DLUT to pre-blend
892 // TODO: implement movable CM location
893 REG_UPDATE(MPCC_MOVABLE_CM_LOCATION_CONTROL[mpcc_id], MPCC_MOVABLE_CM_LOCATION_CNTL, 0);
894
895 if (mode == LUT_BYPASS)
896 lut_mode = 0;
897 else if (mode == LUT_RAM_A)
898 lut_mode = 1;
899 else
900 lut_mode = 2;
901
902 REG_UPDATE_2(MPCC_MCM_3DLUT_MODE[mpcc_id],
903 MPCC_MCM_3DLUT_MODE, lut_mode,
904 MPCC_MCM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);
905 }
906
907
mpc32_program_3dlut(struct mpc * mpc,const struct tetrahedral_params * params,int mpcc_id)908 bool mpc32_program_3dlut(
909 struct mpc *mpc,
910 const struct tetrahedral_params *params,
911 int mpcc_id)
912 {
913 enum dc_lut_mode mode;
914 bool is_17x17x17;
915 bool is_12bits_color_channel;
916 const struct dc_rgb *lut0;
917 const struct dc_rgb *lut1;
918 const struct dc_rgb *lut2;
919 const struct dc_rgb *lut3;
920 int lut_size0;
921 int lut_size;
922
923 if (params == NULL) {
924 mpc32_set_3dlut_mode(mpc, LUT_BYPASS, false, false, mpcc_id);
925 return false;
926 }
927 mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);
928
929 mode = get3dlut_config(mpc, &is_17x17x17, &is_12bits_color_channel, mpcc_id);
930
931 if (mode == LUT_BYPASS || mode == LUT_RAM_B)
932 mode = LUT_RAM_A;
933 else
934 mode = LUT_RAM_B;
935
936 is_17x17x17 = !params->use_tetrahedral_9;
937 is_12bits_color_channel = params->use_12bits;
938 if (is_17x17x17) {
939 lut0 = params->tetrahedral_17.lut0;
940 lut1 = params->tetrahedral_17.lut1;
941 lut2 = params->tetrahedral_17.lut2;
942 lut3 = params->tetrahedral_17.lut3;
943 lut_size0 = sizeof(params->tetrahedral_17.lut0)/
944 sizeof(params->tetrahedral_17.lut0[0]);
945 lut_size = sizeof(params->tetrahedral_17.lut1)/
946 sizeof(params->tetrahedral_17.lut1[0]);
947 } else {
948 lut0 = params->tetrahedral_9.lut0;
949 lut1 = params->tetrahedral_9.lut1;
950 lut2 = params->tetrahedral_9.lut2;
951 lut3 = params->tetrahedral_9.lut3;
952 lut_size0 = sizeof(params->tetrahedral_9.lut0)/
953 sizeof(params->tetrahedral_9.lut0[0]);
954 lut_size = sizeof(params->tetrahedral_9.lut1)/
955 sizeof(params->tetrahedral_9.lut1[0]);
956 }
957
958 mpc32_select_3dlut_ram(mpc, mode,
959 is_12bits_color_channel, mpcc_id);
960 mpc32_select_3dlut_ram_mask(mpc, 0x1, mpcc_id);
961 if (is_12bits_color_channel)
962 mpc32_set3dlut_ram12(mpc, lut0, lut_size0, mpcc_id);
963 else
964 mpc32_set3dlut_ram10(mpc, lut0, lut_size0, mpcc_id);
965
966 mpc32_select_3dlut_ram_mask(mpc, 0x2, mpcc_id);
967 if (is_12bits_color_channel)
968 mpc32_set3dlut_ram12(mpc, lut1, lut_size, mpcc_id);
969 else
970 mpc32_set3dlut_ram10(mpc, lut1, lut_size, mpcc_id);
971
972 mpc32_select_3dlut_ram_mask(mpc, 0x4, mpcc_id);
973 if (is_12bits_color_channel)
974 mpc32_set3dlut_ram12(mpc, lut2, lut_size, mpcc_id);
975 else
976 mpc32_set3dlut_ram10(mpc, lut2, lut_size, mpcc_id);
977
978 mpc32_select_3dlut_ram_mask(mpc, 0x8, mpcc_id);
979 if (is_12bits_color_channel)
980 mpc32_set3dlut_ram12(mpc, lut3, lut_size, mpcc_id);
981 else
982 mpc32_set3dlut_ram10(mpc, lut3, lut_size, mpcc_id);
983
984 mpc32_set_3dlut_mode(mpc, mode, is_12bits_color_channel,
985 is_17x17x17, mpcc_id);
986
987 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)
988 mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);
989
990 return true;
991 }
992
993 static const struct mpc_funcs dcn32_mpc_funcs = {
994 .read_mpcc_state = mpc1_read_mpcc_state,
995 .insert_plane = mpc1_insert_plane,
996 .remove_mpcc = mpc1_remove_mpcc,
997 .mpc_init = mpc32_mpc_init,
998 .mpc_init_single_inst = mpc3_mpc_init_single_inst,
999 .update_blending = mpc2_update_blending,
1000 .cursor_lock = mpc1_cursor_lock,
1001 .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
1002 .wait_for_idle = mpc2_assert_idle_mpcc,
1003 .assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect,
1004 .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
1005 .set_denorm = mpc3_set_denorm,
1006 .set_denorm_clamp = mpc3_set_denorm_clamp,
1007 .set_output_csc = mpc3_set_output_csc,
1008 .set_ocsc_default = mpc3_set_ocsc_default,
1009 .set_output_gamma = mpc3_set_output_gamma,
1010 .insert_plane_to_secondary = NULL,
1011 .remove_mpcc_from_secondary = NULL,
1012 .set_dwb_mux = mpc3_set_dwb_mux,
1013 .disable_dwb_mux = mpc3_disable_dwb_mux,
1014 .is_dwb_idle = mpc3_is_dwb_idle,
1015 .set_gamut_remap = mpc3_set_gamut_remap,
1016 .program_shaper = mpc32_program_shaper,
1017 .program_3dlut = mpc32_program_3dlut,
1018 .program_1dlut = mpc32_program_post1dlut,
1019 .acquire_rmu = NULL,
1020 .release_rmu = NULL,
1021 .power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut,
1022 .get_mpc_out_mux = mpc1_get_mpc_out_mux,
1023 .set_bg_color = mpc1_set_bg_color,
1024 };
1025
1026
dcn32_mpc_construct(struct dcn30_mpc * mpc30,struct dc_context * ctx,const struct dcn30_mpc_registers * mpc_regs,const struct dcn30_mpc_shift * mpc_shift,const struct dcn30_mpc_mask * mpc_mask,int num_mpcc,int num_rmu)1027 void dcn32_mpc_construct(struct dcn30_mpc *mpc30,
1028 struct dc_context *ctx,
1029 const struct dcn30_mpc_registers *mpc_regs,
1030 const struct dcn30_mpc_shift *mpc_shift,
1031 const struct dcn30_mpc_mask *mpc_mask,
1032 int num_mpcc,
1033 int num_rmu)
1034 {
1035 int i;
1036
1037 mpc30->base.ctx = ctx;
1038
1039 mpc30->base.funcs = &dcn32_mpc_funcs;
1040
1041 mpc30->mpc_regs = mpc_regs;
1042 mpc30->mpc_shift = mpc_shift;
1043 mpc30->mpc_mask = mpc_mask;
1044
1045 mpc30->mpcc_in_use_mask = 0;
1046 mpc30->num_mpcc = num_mpcc;
1047 mpc30->num_rmu = num_rmu;
1048
1049 for (i = 0; i < MAX_MPCC; i++)
1050 mpc3_init_mpcc(&mpc30->base.mpcc_array[i], i);
1051 }
1052