1 /*
2 * Marvell Wireless LAN device driver: SDIO specific definitions
3 *
4 * Copyright (C) 2011, Marvell International Ltd.
5 *
6 * This software file (the "File") is distributed by Marvell International
7 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
8 * (the "License"). You may use, redistribute and/or modify this File in
9 * accordance with the terms and conditions of the License, a copy of which
10 * is available by writing to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
13 *
14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
17 * this warranty disclaimer.
18 */
19
20 #ifndef _MWIFIEX_SDIO_H
21 #define _MWIFIEX_SDIO_H
22
23
24 #include <linux/mmc/sdio.h>
25 #include <linux/mmc/sdio_ids.h>
26 #include <linux/mmc/sdio_func.h>
27 #include <linux/mmc/card.h>
28
29 #include "main.h"
30
31 #define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
32 #define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
33
34 #define BLOCK_MODE 1
35 #define BYTE_MODE 0
36
37 #define REG_PORT 0
38 #define RD_BITMAP_L 0x04
39 #define RD_BITMAP_U 0x05
40 #define WR_BITMAP_L 0x06
41 #define WR_BITMAP_U 0x07
42 #define RD_LEN_P0_L 0x08
43 #define RD_LEN_P0_U 0x09
44
45 #define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff
46
47 #define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
48
49 #define CTRL_PORT 0
50 #define CTRL_PORT_MASK 0x0001
51 #define DATA_PORT_MASK 0xfffe
52
53 #define MAX_MP_REGS 64
54 #define MAX_PORT 16
55
56 #define SDIO_MP_AGGR_DEF_PKT_LIMIT 8
57
58 #define SDIO_MP_TX_AGGR_DEF_BUF_SIZE (8192) /* 8K */
59
60 /* Multi port RX aggregation buffer size */
61 #define SDIO_MP_RX_AGGR_DEF_BUF_SIZE (16384) /* 16K */
62
63 /* Misc. Config Register : Auto Re-enable interrupts */
64 #define AUTO_RE_ENABLE_INT BIT(4)
65
66 /* Host Control Registers */
67 /* Host Control Registers : I/O port 0 */
68 #define IO_PORT_0_REG 0x78
69 /* Host Control Registers : I/O port 1 */
70 #define IO_PORT_1_REG 0x79
71 /* Host Control Registers : I/O port 2 */
72 #define IO_PORT_2_REG 0x7A
73
74 /* Host Control Registers : Configuration */
75 #define CONFIGURATION_REG 0x00
76 /* Host Control Registers : Host without Command 53 finish host*/
77 #define HOST_TO_CARD_EVENT (0x1U << 3)
78 /* Host Control Registers : Host without Command 53 finish host */
79 #define HOST_WO_CMD53_FINISH_HOST (0x1U << 2)
80 /* Host Control Registers : Host power up */
81 #define HOST_POWER_UP (0x1U << 1)
82 /* Host Control Registers : Host power down */
83 #define HOST_POWER_DOWN (0x1U << 0)
84
85 /* Host Control Registers : Host interrupt mask */
86 #define HOST_INT_MASK_REG 0x02
87 /* Host Control Registers : Upload host interrupt mask */
88 #define UP_LD_HOST_INT_MASK (0x1U)
89 /* Host Control Registers : Download host interrupt mask */
90 #define DN_LD_HOST_INT_MASK (0x2U)
91 /* Enable Host interrupt mask */
92 #define HOST_INT_ENABLE (UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK)
93 /* Disable Host interrupt mask */
94 #define HOST_INT_DISABLE 0xff
95
96 /* Host Control Registers : Host interrupt status */
97 #define HOST_INTSTATUS_REG 0x03
98 /* Host Control Registers : Upload host interrupt status */
99 #define UP_LD_HOST_INT_STATUS (0x1U)
100 /* Host Control Registers : Download host interrupt status */
101 #define DN_LD_HOST_INT_STATUS (0x2U)
102
103 /* Host Control Registers : Host interrupt RSR */
104 #define HOST_INT_RSR_REG 0x01
105 /* Host Control Registers : Upload host interrupt RSR */
106 #define UP_LD_HOST_INT_RSR (0x1U)
107 #define SDIO_INT_MASK 0x3F
108
109 /* Host Control Registers : Host interrupt status */
110 #define HOST_INT_STATUS_REG 0x28
111 /* Host Control Registers : Upload CRC error */
112 #define UP_LD_CRC_ERR (0x1U << 2)
113 /* Host Control Registers : Upload restart */
114 #define UP_LD_RESTART (0x1U << 1)
115 /* Host Control Registers : Download restart */
116 #define DN_LD_RESTART (0x1U << 0)
117
118 /* Card Control Registers : Card status register */
119 #define CARD_STATUS_REG 0x30
120 /* Card Control Registers : Card I/O ready */
121 #define CARD_IO_READY (0x1U << 3)
122 /* Card Control Registers : CIS card ready */
123 #define CIS_CARD_RDY (0x1U << 2)
124 /* Card Control Registers : Upload card ready */
125 #define UP_LD_CARD_RDY (0x1U << 1)
126 /* Card Control Registers : Download card ready */
127 #define DN_LD_CARD_RDY (0x1U << 0)
128
129 /* Card Control Registers : Host interrupt mask register */
130 #define HOST_INTERRUPT_MASK_REG 0x34
131 /* Card Control Registers : Host power interrupt mask */
132 #define HOST_POWER_INT_MASK (0x1U << 3)
133 /* Card Control Registers : Abort card interrupt mask */
134 #define ABORT_CARD_INT_MASK (0x1U << 2)
135 /* Card Control Registers : Upload card interrupt mask */
136 #define UP_LD_CARD_INT_MASK (0x1U << 1)
137 /* Card Control Registers : Download card interrupt mask */
138 #define DN_LD_CARD_INT_MASK (0x1U << 0)
139
140 /* Card Control Registers : Card interrupt status register */
141 #define CARD_INTERRUPT_STATUS_REG 0x38
142 /* Card Control Registers : Power up interrupt */
143 #define POWER_UP_INT (0x1U << 4)
144 /* Card Control Registers : Power down interrupt */
145 #define POWER_DOWN_INT (0x1U << 3)
146
147 /* Card Control Registers : Card interrupt RSR register */
148 #define CARD_INTERRUPT_RSR_REG 0x3c
149 /* Card Control Registers : Power up RSR */
150 #define POWER_UP_RSR (0x1U << 4)
151 /* Card Control Registers : Power down RSR */
152 #define POWER_DOWN_RSR (0x1U << 3)
153
154 /* Card Control Registers : Miscellaneous Configuration Register */
155 #define CARD_MISC_CFG_REG 0x6C
156
157 /* Host F1 read base 0 */
158 #define HOST_F1_RD_BASE_0 0x0040
159 /* Host F1 read base 1 */
160 #define HOST_F1_RD_BASE_1 0x0041
161 /* Host F1 card ready */
162 #define HOST_F1_CARD_RDY 0x0020
163
164 /* Firmware status 0 register */
165 #define CARD_FW_STATUS0_REG 0x60
166 /* Firmware status 1 register */
167 #define CARD_FW_STATUS1_REG 0x61
168 /* Rx length register */
169 #define CARD_RX_LEN_REG 0x62
170 /* Rx unit register */
171 #define CARD_RX_UNIT_REG 0x63
172
173 /* Max retry number of CMD53 write */
174 #define MAX_WRITE_IOMEM_RETRY 2
175
176 /* SDIO Tx aggregation in progress ? */
177 #define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
178
179 /* SDIO Tx aggregation buffer room for next packet ? */
180 #define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \
181 <= a->mpa_tx.buf_size)
182
183 /* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
184 #define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \
185 memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \
186 payload, pkt_len); \
187 a->mpa_tx.buf_len += pkt_len; \
188 if (!a->mpa_tx.pkt_cnt) \
189 a->mpa_tx.start_port = port; \
190 if (a->mpa_tx.start_port <= port) \
191 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \
192 else \
193 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+(MAX_PORT - \
194 a->mp_end_port))); \
195 a->mpa_tx.pkt_cnt++; \
196 } while (0);
197
198 /* SDIO Tx aggregation limit ? */
199 #define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
200 (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
201
202 /* SDIO Tx aggregation port limit ? */
203 #define MP_TX_AGGR_PORT_LIMIT_REACHED(a) ((a->curr_wr_port < \
204 a->mpa_tx.start_port) && (((MAX_PORT - \
205 a->mpa_tx.start_port) + a->curr_wr_port) >= \
206 SDIO_MP_AGGR_DEF_PKT_LIMIT))
207
208 /* Reset SDIO Tx aggregation buffer parameters */
209 #define MP_TX_AGGR_BUF_RESET(a) do { \
210 a->mpa_tx.pkt_cnt = 0; \
211 a->mpa_tx.buf_len = 0; \
212 a->mpa_tx.ports = 0; \
213 a->mpa_tx.start_port = 0; \
214 } while (0);
215
216 /* SDIO Rx aggregation limit ? */
217 #define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
218 (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
219
220 /* SDIO Tx aggregation port limit ? */
221 #define MP_RX_AGGR_PORT_LIMIT_REACHED(a) ((a->curr_rd_port < \
222 a->mpa_rx.start_port) && (((MAX_PORT - \
223 a->mpa_rx.start_port) + a->curr_rd_port) >= \
224 SDIO_MP_AGGR_DEF_PKT_LIMIT))
225
226 /* SDIO Rx aggregation in progress ? */
227 #define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
228
229 /* SDIO Rx aggregation buffer room for next packet ? */
230 #define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
231 ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
232
233 /* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
234 #define MP_RX_AGGR_SETUP(a, skb, port) do { \
235 a->mpa_rx.buf_len += skb->len; \
236 if (!a->mpa_rx.pkt_cnt) \
237 a->mpa_rx.start_port = port; \
238 if (a->mpa_rx.start_port <= port) \
239 a->mpa_rx.ports |= (1<<(a->mpa_rx.pkt_cnt)); \
240 else \
241 a->mpa_rx.ports |= (1<<(a->mpa_rx.pkt_cnt+1)); \
242 a->mpa_rx.skb_arr[a->mpa_rx.pkt_cnt] = skb; \
243 a->mpa_rx.len_arr[a->mpa_rx.pkt_cnt] = skb->len; \
244 a->mpa_rx.pkt_cnt++; \
245 } while (0);
246
247 /* Reset SDIO Rx aggregation buffer parameters */
248 #define MP_RX_AGGR_BUF_RESET(a) do { \
249 a->mpa_rx.pkt_cnt = 0; \
250 a->mpa_rx.buf_len = 0; \
251 a->mpa_rx.ports = 0; \
252 a->mpa_rx.start_port = 0; \
253 } while (0);
254
255
256 /* data structure for SDIO MPA TX */
257 struct mwifiex_sdio_mpa_tx {
258 /* multiport tx aggregation buffer pointer */
259 u8 *buf;
260 u32 buf_len;
261 u32 pkt_cnt;
262 u16 ports;
263 u16 start_port;
264 u8 enabled;
265 u32 buf_size;
266 u32 pkt_aggr_limit;
267 };
268
269 struct mwifiex_sdio_mpa_rx {
270 u8 *buf;
271 u32 buf_len;
272 u32 pkt_cnt;
273 u16 ports;
274 u16 start_port;
275
276 struct sk_buff *skb_arr[SDIO_MP_AGGR_DEF_PKT_LIMIT];
277 u32 len_arr[SDIO_MP_AGGR_DEF_PKT_LIMIT];
278
279 u8 enabled;
280 u32 buf_size;
281 u32 pkt_aggr_limit;
282 };
283
284 int mwifiex_bus_register(void);
285 void mwifiex_bus_unregister(void);
286
287 struct sdio_mmc_card {
288 struct sdio_func *func;
289 struct mwifiex_adapter *adapter;
290
291 u16 mp_rd_bitmap;
292 u16 mp_wr_bitmap;
293
294 u16 mp_end_port;
295 u16 mp_data_port_mask;
296
297 u8 curr_rd_port;
298 u8 curr_wr_port;
299
300 u8 *mp_regs;
301
302 struct mwifiex_sdio_mpa_tx mpa_tx;
303 struct mwifiex_sdio_mpa_rx mpa_rx;
304 };
305
306 /*
307 * .cmdrsp_complete handler
308 */
mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter * adapter,struct sk_buff * skb)309 static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
310 struct sk_buff *skb)
311 {
312 dev_kfree_skb_any(skb);
313 return 0;
314 }
315
316 /*
317 * .event_complete handler
318 */
mwifiex_sdio_event_complete(struct mwifiex_adapter * adapter,struct sk_buff * skb)319 static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
320 struct sk_buff *skb)
321 {
322 dev_kfree_skb_any(skb);
323 return 0;
324 }
325
326 #endif /* _MWIFIEX_SDIO_H */
327