1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef __AUDIOREACH_H__ 4 #define __AUDIOREACH_H__ 5 #include <linux/types.h> 6 #include <linux/soc/qcom/apr.h> 7 #include <uapi/sound/snd_ar_tokens.h> 8 #include <sound/soc.h> 9 struct q6apm; 10 struct q6apm_graph; 11 12 /* Module IDs */ 13 #define MODULE_ID_WR_SHARED_MEM_EP 0x07001000 14 #define MODULE_ID_RD_SHARED_MEM_EP 0x07001001 15 #define MODULE_ID_GAIN 0x07001002 16 #define MODULE_ID_PCM_CNV 0x07001003 17 #define MODULE_ID_PCM_ENC 0x07001004 18 #define MODULE_ID_PCM_DEC 0x07001005 19 #define MODULE_ID_PLACEHOLDER_ENCODER 0x07001008 20 #define MODULE_ID_PLACEHOLDER_DECODER 0x07001009 21 #define MODULE_ID_I2S_SINK 0x0700100A 22 #define MODULE_ID_I2S_SOURCE 0x0700100B 23 #define MODULE_ID_SAL 0x07001010 24 #define MODULE_ID_MFC 0x07001015 25 #define MODULE_ID_DATA_LOGGING 0x0700101A 26 #define MODULE_ID_AAC_DEC 0x0700101F 27 #define MODULE_ID_CODEC_DMA_SINK 0x07001023 28 #define MODULE_ID_CODEC_DMA_SOURCE 0x07001024 29 #define MODULE_ID_FLAC_DEC 0x0700102F 30 #define MODULE_ID_SMECNS_V2 0x07001031 31 #define MODULE_ID_MP3_DECODE 0x0700103B 32 #define MODULE_ID_GAPLESS 0x0700104D 33 #define MODULE_ID_DISPLAY_PORT_SINK 0x07001069 34 #define MODULE_ID_SPEAKER_PROTECTION 0x070010E2 35 #define MODULE_ID_SPEAKER_PROTECTION_VI 0x070010E3 36 #define MODULE_ID_OPUS_DEC 0x07001174 37 38 #define APM_CMD_GET_SPF_STATE 0x01001021 39 #define APM_CMD_RSP_GET_SPF_STATE 0x02001007 40 41 #define APM_MODULE_INSTANCE_ID 0x00000001 42 #define PRM_MODULE_INSTANCE_ID 0x00000002 43 #define AMDB_MODULE_INSTANCE_ID 0x00000003 44 #define VCPM_MODULE_INSTANCE_ID 0x00000004 45 #define AR_MODULE_INSTANCE_ID_START 0x00006000 46 #define AR_MODULE_INSTANCE_ID_END 0x00007000 47 #define AR_MODULE_DYNAMIC_INSTANCE_ID_START 0x00007000 48 #define AR_MODULE_DYNAMIC_INSTANCE_ID_END 0x00008000 49 #define AR_CONT_INSTANCE_ID_START 0x00005000 50 #define AR_CONT_INSTANCE_ID_END 0x00006000 51 #define AR_SG_INSTANCE_ID_START 0x00004000 52 53 #define APM_CMD_GRAPH_OPEN 0x01001000 54 #define APM_CMD_GRAPH_PREPARE 0x01001001 55 #define APM_CMD_GRAPH_START 0x01001002 56 #define APM_CMD_GRAPH_STOP 0x01001003 57 #define APM_CMD_GRAPH_CLOSE 0x01001004 58 #define APM_CMD_GRAPH_FLUSH 0x01001005 59 #define APM_CMD_SET_CFG 0x01001006 60 #define APM_CMD_GET_CFG 0x01001007 61 #define APM_CMD_SHARED_MEM_MAP_REGIONS 0x0100100C 62 #define APM_CMD_SHARED_MEM_UNMAP_REGIONS 0x0100100D 63 #define APM_CMD_RSP_SHARED_MEM_MAP_REGIONS 0x02001001 64 #define APM_CMD_RSP_GET_CFG 0x02001000 65 #define APM_CMD_CLOSE_ALL 0x01001013 66 #define APM_CMD_REGISTER_SHARED_CFG 0x0100100A 67 68 #define APM_MEMORY_MAP_SHMEM8_4K_POOL 3 69 70 struct apm_cmd_shared_mem_map_regions { 71 uint16_t mem_pool_id; 72 uint16_t num_regions; 73 uint32_t property_flag; 74 } __packed; 75 76 struct apm_shared_map_region_payload { 77 uint32_t shm_addr_lsw; 78 uint32_t shm_addr_msw; 79 uint32_t mem_size_bytes; 80 } __packed; 81 82 struct apm_cmd_shared_mem_unmap_regions { 83 uint32_t mem_map_handle; 84 } __packed; 85 86 struct apm_cmd_rsp_shared_mem_map_regions { 87 uint32_t mem_map_handle; 88 } __packed; 89 90 /* APM module */ 91 #define APM_PARAM_ID_SUB_GRAPH_LIST 0x08001005 92 93 #define APM_PARAM_ID_MODULE_LIST 0x08001002 94 95 struct apm_param_id_modules_list { 96 uint32_t num_modules_list; 97 } __packed; 98 99 #define APM_PARAM_ID_MODULE_PROP 0x08001003 100 101 struct apm_param_id_module_prop { 102 uint32_t num_modules_prop_cfg; 103 } __packed; 104 105 struct apm_module_prop_cfg { 106 uint32_t instance_id; 107 uint32_t num_props; 108 } __packed; 109 110 #define APM_PARAM_ID_MODULE_CONN 0x08001004 111 112 struct apm_param_id_module_conn { 113 uint32_t num_connections; 114 } __packed; 115 116 struct apm_module_conn_obj { 117 uint32_t src_mod_inst_id; 118 uint32_t src_mod_op_port_id; 119 uint32_t dst_mod_inst_id; 120 uint32_t dst_mod_ip_port_id; 121 } __packed; 122 123 #define APM_PARAM_ID_GAIN 0x08001006 124 125 struct param_id_gain_cfg { 126 uint16_t gain; 127 uint16_t reserved; 128 } __packed; 129 130 #define PARAM_ID_PCM_OUTPUT_FORMAT_CFG 0x08001008 131 132 struct param_id_pcm_output_format_cfg { 133 uint32_t data_format; 134 uint32_t fmt_id; 135 uint32_t payload_size; 136 } __packed; 137 138 struct payload_pcm_output_format_cfg { 139 uint16_t bit_width; 140 uint16_t alignment; 141 uint16_t bits_per_sample; 142 uint16_t q_factor; 143 uint16_t endianness; 144 uint16_t interleaved; 145 uint16_t reserved; 146 uint16_t num_channels; 147 uint8_t channel_mapping[]; 148 } __packed; 149 150 #define PARAM_ID_ENC_BITRATE 0x08001052 151 152 struct param_id_enc_bitrate_param { 153 uint32_t bitrate; 154 } __packed; 155 156 #define DATA_FORMAT_FIXED_POINT 1 157 #define DATA_FORMAT_GENERIC_COMPRESSED 5 158 #define DATA_FORMAT_RAW_COMPRESSED 6 159 #define PCM_LSB_ALIGNED 1 160 #define PCM_MSB_ALIGNED 2 161 #define PCM_LITTLE_ENDIAN 1 162 #define PCM_BIT_ENDIAN 2 163 164 #define MEDIA_FMT_ID_PCM 0x09001000 165 #define MEDIA_FMT_ID_MP3 0x09001009 166 #define SAMPLE_RATE_48K 48000 167 #define BIT_WIDTH_16 16 168 169 #define APM_PARAM_ID_PROP_PORT_INFO 0x08001015 170 171 struct apm_modules_prop_info { 172 uint32_t max_ip_port; 173 uint32_t max_op_port; 174 } __packed; 175 176 /* Shared memory module */ 177 #define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER 0x04001000 178 #define WR_SH_MEM_EP_TIMESTAMP_VALID_FLAG BIT(31) 179 #define WR_SH_MEM_EP_LAST_BUFFER_FLAG BIT(30) 180 #define WR_SH_MEM_EP_TS_CONTINUE_FLAG BIT(29) 181 #define WR_SH_MEM_EP_EOF_FLAG BIT(4) 182 183 struct apm_data_cmd_wr_sh_mem_ep_data_buffer { 184 uint32_t buf_addr_lsw; 185 uint32_t buf_addr_msw; 186 uint32_t mem_map_handle; 187 uint32_t buf_size; 188 uint32_t timestamp_lsw; 189 uint32_t timestamp_msw; 190 uint32_t flags; 191 } __packed; 192 193 #define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER_V2 0x0400100A 194 195 struct apm_data_cmd_wr_sh_mem_ep_data_buffer_v2 { 196 uint32_t buf_addr_lsw; 197 uint32_t buf_addr_msw; 198 uint32_t mem_map_handle; 199 uint32_t buf_size; 200 uint32_t timestamp_lsw; 201 uint32_t timestamp_msw; 202 uint32_t flags; 203 uint32_t md_addr_lsw; 204 uint32_t md_addr_msw; 205 uint32_t md_map_handle; 206 uint32_t md_buf_size; 207 } __packed; 208 209 #define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE 0x05001000 210 211 struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done { 212 uint32_t buf_addr_lsw; 213 uint32_t buf_addr_msw; 214 uint32_t mem_map_handle; 215 uint32_t status; 216 217 } __packed; 218 219 #define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE_V2 0x05001004 220 221 struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done_v2 { 222 uint32_t buf_addr_lsw; 223 uint32_t buf_addr_msw; 224 uint32_t mem_map_handle; 225 uint32_t status; 226 uint32_t md_buf_addr_lsw; 227 uint32_t md_buf_addr_msw; 228 uint32_t md_mem_map_handle; 229 uint32_t md_status; 230 } __packed; 231 232 #define PARAM_ID_MEDIA_FORMAT 0x0800100C 233 #define DATA_CMD_WR_SH_MEM_EP_MEDIA_FORMAT 0x04001001 234 235 struct apm_media_format { 236 uint32_t data_format; 237 uint32_t fmt_id; 238 uint32_t payload_size; 239 } __packed; 240 241 #define MEDIA_FMT_ID_FLAC 0x09001004 242 243 struct payload_media_fmt_flac_t { 244 uint16_t num_channels; 245 uint16_t sample_size; 246 uint16_t min_blk_size; 247 uint16_t max_blk_size; 248 uint32_t sample_rate; 249 uint32_t min_frame_size; 250 uint32_t max_frame_size; 251 } __packed; 252 253 #define MEDIA_FMT_ID_AAC 0x09001001 254 255 struct payload_media_fmt_aac_t { 256 uint16_t aac_fmt_flag; 257 uint16_t audio_obj_type; 258 uint16_t num_channels; 259 uint16_t total_size_of_PCE_bits; 260 uint32_t sample_rate; 261 } __packed; 262 263 #define MEDIA_FMT_ID_OPUS 0x09001039 264 struct payload_media_fmt_opus_t { 265 uint16_t bitstream_format; 266 uint16_t payload_type; 267 uint8_t version; 268 uint8_t num_channels; 269 uint16_t pre_skip; 270 uint32_t sample_rate; 271 uint16_t output_gain; 272 uint8_t mapping_family; 273 uint8_t stream_count; 274 uint8_t coupled_count; 275 uint8_t channel_mapping[8]; 276 uint8_t reserved[3]; 277 } __packed; 278 279 #define DATA_CMD_WR_SH_MEM_EP_EOS 0x04001002 280 #define WR_SH_MEM_EP_EOS_POLICY_LAST 1 281 #define WR_SH_MEM_EP_EOS_POLICY_EACH 2 282 283 struct data_cmd_wr_sh_mem_ep_eos { 284 uint32_t policy; 285 286 } __packed; 287 288 #define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER 0x04001003 289 290 struct data_cmd_rd_sh_mem_ep_data_buffer { 291 uint32_t buf_addr_lsw; 292 uint32_t buf_addr_msw; 293 uint32_t mem_map_handle; 294 uint32_t buf_size; 295 } __packed; 296 297 #define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER 0x05001002 298 299 struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done { 300 uint32_t status; 301 uint32_t buf_addr_lsw; 302 uint32_t buf_addr_msw; 303 uint32_t mem_map_handle; 304 uint32_t data_size; 305 uint32_t offset; 306 uint32_t timestamp_lsw; 307 uint32_t timestamp_msw; 308 uint32_t flags; 309 uint32_t num_frames; 310 } __packed; 311 312 #define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER_V2 0x0400100B 313 314 struct data_cmd_rd_sh_mem_ep_data_buffer_v2 { 315 uint32_t buf_addr_lsw; 316 uint32_t buf_addr_msw; 317 uint32_t mem_map_handle; 318 uint32_t buf_size; 319 uint32_t md_buf_addr_lsw; 320 uint32_t md_buf_addr_msw; 321 uint32_t md_mem_map_handle; 322 uint32_t md_buf_size; 323 } __packed; 324 325 #define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER_V2 0x05001005 326 327 struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done_v2 { 328 uint32_t status; 329 uint32_t buf_addr_lsw; 330 uint32_t buf_addr_msw; 331 uint32_t mem_map_handle; 332 uint32_t data_size; 333 uint32_t offset; 334 uint32_t timestamp_lsw; 335 uint32_t timestamp_msw; 336 uint32_t flags; 337 uint32_t num_frames; 338 uint32_t md_status; 339 uint32_t md_buf_addr_lsw; 340 uint32_t md_buf_addr_msw; 341 uint32_t md_mem_map_handle; 342 uint32_t md_size; 343 } __packed; 344 345 #define PARAM_ID_RD_SH_MEM_CFG 0x08001007 346 347 struct param_id_rd_sh_mem_cfg { 348 uint32_t num_frames_per_buffer; 349 uint32_t metadata_control_flags; 350 351 } __packed; 352 353 #define DATA_CMD_WR_SH_MEM_EP_EOS_RENDERED 0x05001001 354 355 struct data_cmd_wr_sh_mem_ep_eos_rendered { 356 uint32_t module_instance_id; 357 uint32_t render_status; 358 } __packed; 359 360 #define MODULE_ID_WR_SHARED_MEM_EP 0x07001000 361 362 struct apm_cmd_header { 363 uint32_t payload_address_lsw; 364 uint32_t payload_address_msw; 365 uint32_t mem_map_handle; 366 uint32_t payload_size; 367 } __packed; 368 369 #define APM_CMD_HDR_SIZE sizeof(struct apm_cmd_header) 370 371 struct apm_module_param_data { 372 uint32_t module_instance_id; 373 uint32_t param_id; 374 uint32_t param_size; 375 uint32_t error_code; 376 } __packed; 377 378 #define APM_MODULE_PARAM_DATA_SIZE sizeof(struct apm_module_param_data) 379 380 struct apm_module_param_shared_data { 381 uint32_t param_id; 382 uint32_t param_size; 383 } __packed; 384 385 struct apm_prop_data { 386 uint32_t prop_id; 387 uint32_t prop_size; 388 } __packed; 389 390 /* Sub-Graph Properties */ 391 #define APM_PARAM_ID_SUB_GRAPH_CONFIG 0x08001001 392 393 struct apm_param_id_sub_graph_cfg { 394 uint32_t num_sub_graphs; 395 } __packed; 396 397 struct apm_sub_graph_cfg { 398 uint32_t sub_graph_id; 399 uint32_t num_sub_graph_prop; 400 } __packed; 401 402 #define APM_SUB_GRAPH_PROP_ID_PERF_MODE 0x0800100E 403 404 struct apm_sg_prop_id_perf_mode { 405 uint32_t perf_mode; 406 } __packed; 407 408 #define APM_SG_PROP_ID_PERF_MODE_SIZE 4 409 410 #define APM_SUB_GRAPH_PROP_ID_DIRECTION 0x0800100F 411 412 struct apm_sg_prop_id_direction { 413 uint32_t direction; 414 } __packed; 415 416 #define APM_SG_PROP_ID_DIR_SIZE 4 417 418 #define APM_SUB_GRAPH_PROP_ID_SCENARIO_ID 0x08001010 419 #define APM_SUB_GRAPH_SID_AUDIO_PLAYBACK 0x1 420 #define APM_SUB_GRAPH_SID_AUDIO_RECORD 0x2 421 #define APM_SUB_GRAPH_SID_AUDIO_VOICE_CALL 0x3 422 423 struct apm_sg_prop_id_scenario_id { 424 uint32_t scenario_id; 425 } __packed; 426 427 #define APM_SG_PROP_ID_SID_SIZE 4 428 /* container api */ 429 #define APM_PARAM_ID_CONTAINER_CONFIG 0x08001000 430 431 struct apm_param_id_container_cfg { 432 uint32_t num_containers; 433 } __packed; 434 435 struct apm_container_cfg { 436 uint32_t container_id; 437 uint32_t num_prop; 438 } __packed; 439 440 struct apm_cont_capability { 441 uint32_t capability_id; 442 } __packed; 443 444 #define APM_CONTAINER_PROP_ID_CAPABILITY_LIST 0x08001011 445 #define APM_CONTAINER_PROP_ID_CAPABILITY_SIZE 8 446 447 #define APM_PROP_ID_INVALID 0x0 448 #define APM_CONTAINER_CAP_ID_PP 0x1 449 #define APM_CONTAINER_CAP_ID_PP 0x1 450 451 struct apm_cont_prop_id_cap_list { 452 uint32_t num_capability_id; 453 } __packed; 454 455 #define APM_CONTAINER_PROP_ID_GRAPH_POS 0x08001012 456 457 struct apm_cont_prop_id_graph_pos { 458 uint32_t graph_pos; 459 } __packed; 460 461 #define APM_CONTAINER_PROP_ID_STACK_SIZE 0x08001013 462 463 struct apm_cont_prop_id_stack_size { 464 uint32_t stack_size; 465 } __packed; 466 467 #define APM_CONTAINER_PROP_ID_PROC_DOMAIN 0x08001014 468 469 struct apm_cont_prop_id_domain { 470 uint32_t proc_domain; 471 } __packed; 472 473 #define CONFIG_I2S_WS_SRC_EXTERNAL 0x0 474 #define CONFIG_I2S_WS_SRC_INTERNAL 0x1 475 476 #define PARAM_ID_I2S_INTF_CFG 0x08001019 477 struct param_id_i2s_intf_cfg { 478 uint32_t lpaif_type; 479 uint32_t intf_idx; 480 uint16_t sd_line_idx; 481 uint16_t ws_src; 482 } __packed; 483 484 #define I2S_INTF_TYPE_PRIMARY 0 485 #define I2S_INTF_TYPE_SECONDARY 1 486 #define I2S_INTF_TYPE_TERTIARY 2 487 #define I2S_INTF_TYPE_QUATERNARY 3 488 #define I2S_INTF_TYPE_QUINARY 4 489 #define I2S_SD0 1 490 #define I2S_SD1 2 491 #define I2S_SD2 3 492 #define I2S_SD3 4 493 494 #define PORT_ID_I2S_INPUT 2 495 #define PORT_ID_I2S_OUPUT 1 496 #define I2S_STACK_SIZE 2048 497 498 #define PARAM_ID_DISPLAY_PORT_INTF_CFG 0x08001154 499 500 struct param_id_display_port_intf_cfg { 501 uint32_t channel_allocation; 502 /* Multi-Steam Transport index */ 503 uint32_t mst_idx; 504 uint32_t dptx_idx; 505 } __packed; 506 507 #define PARAM_ID_HW_EP_MF_CFG 0x08001017 508 struct param_id_hw_ep_mf { 509 uint32_t sample_rate; 510 uint16_t bit_width; 511 uint16_t num_channels; 512 uint32_t data_format; 513 } __packed; 514 515 #define PARAM_ID_HW_EP_FRAME_SIZE_FACTOR 0x08001018 516 517 struct param_id_fram_size_factor { 518 uint32_t frame_size_factor; 519 } __packed; 520 521 #define APM_CONTAINER_PROP_ID_PARENT_CONTAINER_ID 0x080010CB 522 523 struct apm_cont_prop_id_parent_container { 524 uint32_t parent_container_id; 525 } __packed; 526 527 #define APM_CONTAINER_PROP_ID_HEAP_ID 0x08001174 528 #define APM_CONT_HEAP_DEFAULT 0x1 529 #define APM_CONT_HEAP_LOW_POWER 0x2 530 531 struct apm_cont_prop_id_headp_id { 532 uint32_t heap_id; 533 } __packed; 534 535 struct apm_modules_list { 536 uint32_t sub_graph_id; 537 uint32_t container_id; 538 uint32_t num_modules; 539 } __packed; 540 541 struct apm_module_obj { 542 uint32_t module_id; 543 uint32_t instance_id; 544 } __packed; 545 546 #define APM_MODULE_PROP_ID_PORT_INFO 0x08001015 547 #define APM_MODULE_PROP_ID_PORT_INFO_SZ 8 548 struct apm_module_prop_id_port_info { 549 uint32_t max_ip_port; 550 uint32_t max_op_port; 551 } __packed; 552 553 #define DATA_LOGGING_MAX_INPUT_PORTS 0x1 554 #define DATA_LOGGING_MAX_OUTPUT_PORTS 0x1 555 #define DATA_LOGGING_STACK_SIZE 2048 556 #define PARAM_ID_DATA_LOGGING_CONFIG 0x08001031 557 558 struct data_logging_config { 559 uint32_t log_code; 560 uint32_t log_tap_point_id; 561 uint32_t mode; 562 } __packed; 563 564 /* Speaker Protection */ 565 #define PARAM_ID_SP_OP_MODE 0x080011e9 566 #define PARAM_ID_SP_OP_MODE_NORMAL 0 567 #define PARAM_ID_SP_OP_MODE_CALIBRATION 1 568 #define PARAM_ID_SP_OP_MODE_FACTORY_TEST 2 569 #define PARAM_ID_SP_OP_MODE_VALIDATION 3 570 571 struct param_id_sp_op_mode { 572 uint32_t operation_mode; 573 } __packed; 574 575 /* Speaker Protection VI */ 576 577 #define PARAM_ID_SP_VI_OP_MODE_CFG 0x080011f4 578 #define PARAM_ID_SP_VI_OP_MODE_NORMAL 0 579 #define PARAM_ID_SP_VI_OP_MODE_CALIBRATION 1 580 #define PARAM_ID_SP_VI_OP_MODE_FACTORY_TEST 2 581 #define PARAM_ID_SP_VI_OP_MODE_VALIDATION 3 582 struct param_id_sp_vi_op_mode_cfg { 583 uint32_t num_channels; 584 uint32_t operation_mode; 585 uint32_t quick_calibration; 586 uint32_t r0_t0_selection[]; 587 } __packed; 588 589 #define PARAM_ID_SP_VI_EX_MODE_CFG 0x080011ff 590 struct param_id_sp_vi_ex_mode_cfg { 591 uint32_t factory_mode; 592 } __packed; 593 594 #define PARAM_ID_SP_VI_CHANNEL_MAP_CFG 0x08001203 595 struct param_id_sp_vi_channel_map_cfg { 596 uint32_t num_channels; 597 /* [ Vsense of ch 1, Isense of ch 1, Vsense of ch 2, Isense of ch 2, ... ] */ 598 uint32_t channel_mapping[]; 599 } __packed; 600 601 #define PARAM_ID_SAL_OUTPUT_CFG 0x08001016 602 struct param_id_sal_output_config { 603 uint32_t bits_per_sample; 604 } __packed; 605 606 #define PARAM_ID_SAL_LIMITER_ENABLE 0x0800101E 607 struct param_id_sal_limiter_enable { 608 uint32_t enable_lim; 609 } __packed; 610 611 #define PARAM_ID_MFC_OUTPUT_MEDIA_FORMAT 0x08001024 612 #define PARAM_ID_EARLY_EOS_DELAY 0x0800114C 613 #define EARLY_EOS_DELAY_MS 150 614 615 struct param_id_mfc_media_format { 616 uint32_t sample_rate; 617 uint16_t bit_width; 618 uint16_t num_channels; 619 uint16_t channel_mapping[]; 620 } __packed; 621 622 struct param_id_gapless_early_eos_delay_t { 623 uint32_t early_eos_delay_ms; 624 } __packed; 625 626 struct media_format { 627 uint32_t data_format; 628 uint32_t fmt_id; 629 uint32_t payload_size; 630 } __packed; 631 632 struct payload_media_fmt_pcm { 633 uint32_t sample_rate; 634 uint16_t bit_width; 635 uint16_t alignment; 636 uint16_t bits_per_sample; 637 uint16_t q_factor; 638 uint16_t endianness; 639 uint16_t num_channels; 640 uint8_t channel_mapping[]; 641 } __packed; 642 643 #define PARAM_ID_MODULE_ENABLE 0x08001026 644 struct param_id_module_enable { 645 uint32_t enable; 646 } __packed; 647 648 #define PARAM_ID_CODEC_DMA_INTF_CFG 0x08001063 649 650 struct param_id_codec_dma_intf_cfg { 651 /* 1 - RXTX 652 * 2 - WSA 653 * 3 - VA 654 * 4 - AXI 655 */ 656 uint32_t lpaif_type; 657 /* 658 * RX0 | TX0 = 1 659 * RX1 | TX1 = 2 660 * RX2 | TX2 = 3... so on 661 */ 662 uint32_t intf_index; 663 uint32_t active_channels_mask; 664 } __packed; 665 666 struct audio_hw_clk_cfg { 667 uint32_t clock_id; 668 uint32_t clock_freq; 669 uint32_t clock_attri; 670 uint32_t clock_root; 671 } __packed; 672 673 struct audio_hw_clk_rel_cfg { 674 uint32_t clock_id; 675 } __packed; 676 677 #define PARAM_ID_HW_EP_POWER_MODE_CFG 0x8001176 678 #define AR_HW_EP_POWER_MODE_0 0 /* default */ 679 #define AR_HW_EP_POWER_MODE_1 1 /* XO Shutdown allowed */ 680 #define AR_HW_EP_POWER_MODE_2 2 /* XO Shutdown not allowed */ 681 682 struct param_id_hw_ep_power_mode_cfg { 683 uint32_t power_mode; 684 } __packed; 685 686 #define PARAM_ID_HW_EP_DMA_DATA_ALIGN 0x08001233 687 #define AR_HW_EP_DMA_DATA_ALIGN_MSB 0 688 #define AR_HW_EP_DMA_DATA_ALIGN_LSB 1 689 #define AR_PCM_MAX_NUM_CHANNEL 8 690 691 struct param_id_hw_ep_dma_data_align { 692 uint32_t dma_data_align; 693 } __packed; 694 695 #define PARAM_ID_VOL_CTRL_MASTER_GAIN 0x08001035 696 #define VOL_CTRL_DEFAULT_GAIN 0x2000 697 698 struct param_id_vol_ctrl_master_gain { 699 uint16_t master_gain; 700 uint16_t reserved; 701 } __packed; 702 703 704 #define PARAM_ID_REMOVE_INITIAL_SILENCE 0x0800114B 705 #define PARAM_ID_REMOVE_TRAILING_SILENCE 0x0800115D 706 707 #define PARAM_ID_REAL_MODULE_ID 0x0800100B 708 709 struct param_id_placeholder_real_module_id { 710 uint32_t real_module_id; 711 } __packed; 712 713 /* Graph */ 714 struct audioreach_connection { 715 /* Connections */ 716 uint32_t src_mod_inst_id; 717 uint32_t src_mod_op_port_id; 718 uint32_t dst_mod_inst_id; 719 uint32_t dst_mod_ip_port_id; 720 struct list_head node; 721 }; 722 723 struct audioreach_graph_info { 724 int id; 725 uint32_t num_sub_graphs; 726 struct list_head sg_list; 727 /* DPCM connection from FE Graph to BE graph */ 728 uint32_t src_mod_inst_id; 729 uint32_t src_mod_op_port_id; 730 uint32_t dst_mod_inst_id; 731 uint32_t dst_mod_ip_port_id; 732 }; 733 734 struct audioreach_sub_graph { 735 uint32_t sub_graph_id; 736 uint32_t perf_mode; 737 uint32_t direction; 738 uint32_t scenario_id; 739 struct list_head node; 740 741 struct audioreach_graph_info *info; 742 uint32_t num_containers; 743 struct list_head container_list; 744 }; 745 746 struct audioreach_container { 747 uint32_t container_id; 748 uint32_t capability_id; 749 uint32_t graph_pos; 750 uint32_t stack_size; 751 uint32_t proc_domain; 752 struct list_head node; 753 754 uint32_t num_modules; 755 struct list_head modules_list; 756 struct audioreach_sub_graph *sub_graph; 757 }; 758 759 #define AR_MAX_MOD_LINKS 8 760 761 struct audioreach_module { 762 uint32_t module_id; 763 uint32_t instance_id; 764 765 uint32_t max_ip_port; 766 uint32_t max_op_port; 767 768 uint32_t num_connections; 769 /* Connections */ 770 uint32_t src_mod_inst_id; 771 uint32_t src_mod_op_port_id[AR_MAX_MOD_LINKS]; 772 uint32_t dst_mod_inst_id[AR_MAX_MOD_LINKS]; 773 uint32_t dst_mod_ip_port_id[AR_MAX_MOD_LINKS]; 774 775 /* Format specifics */ 776 uint32_t ch_fmt; 777 uint32_t rate; 778 uint32_t bit_depth; 779 780 /* I2S module */ 781 uint32_t hw_interface_idx; 782 uint32_t sd_line_idx; 783 uint32_t ws_src; 784 uint32_t frame_size_factor; 785 uint32_t data_format; 786 uint32_t hw_interface_type; 787 788 /* PCM module specific */ 789 uint32_t interleave_type; 790 791 /* GAIN/Vol Control Module */ 792 uint16_t gain; 793 794 /* Logging */ 795 uint32_t log_code; 796 uint32_t log_tap_point_id; 797 uint32_t log_mode; 798 799 /* bookkeeping */ 800 struct list_head node; 801 struct audioreach_container *container; 802 struct snd_soc_dapm_widget *widget; 803 struct audioreach_module_priv_data *data; 804 }; 805 806 struct audioreach_module_config { 807 int direction; 808 u32 sample_rate; 809 u16 bit_width; 810 u16 bits_per_sample; 811 812 u16 data_format; 813 u16 num_channels; 814 u16 dp_idx; 815 u32 channel_allocation; 816 u32 sd_line_mask; 817 int fmt; 818 struct snd_codec codec; 819 u8 channel_map[AR_PCM_MAX_NUM_CHANNEL]; 820 }; 821 822 /* Packet Allocation routines */ 823 void *audioreach_alloc_apm_cmd_pkt(int pkt_size, uint32_t opcode, uint32_t 824 token); 825 void audioreach_set_default_channel_mapping(u8 *ch_map, int num_channels); 826 void *audioreach_alloc_cmd_pkt(int payload_size, uint32_t opcode, 827 uint32_t token, uint32_t src_port, 828 uint32_t dest_port); 829 void *audioreach_alloc_apm_pkt(int pkt_size, uint32_t opcode, uint32_t token, 830 uint32_t src_port); 831 void *audioreach_alloc_pkt(int payload_size, uint32_t opcode, 832 uint32_t token, uint32_t src_port, 833 uint32_t dest_port); 834 void *audioreach_alloc_graph_pkt(struct q6apm *apm, 835 const struct audioreach_graph_info *info); 836 /* Topology specific */ 837 int audioreach_tplg_init(struct snd_soc_component *component); 838 839 /* Module specific */ 840 void audioreach_graph_free_buf(struct q6apm_graph *graph); 841 int audioreach_map_memory_regions(struct q6apm_graph *graph, 842 unsigned int dir, size_t period_sz, 843 unsigned int periods, 844 bool is_contiguous); 845 int audioreach_send_cmd_sync(struct device *dev, gpr_device_t *gdev, struct gpr_ibasic_rsp_result_t *result, 846 struct mutex *cmd_lock, gpr_port_t *port, wait_queue_head_t *cmd_wait, 847 struct gpr_pkt *pkt, uint32_t rsp_opcode); 848 int audioreach_graph_send_cmd_sync(struct q6apm_graph *graph, struct gpr_pkt *pkt, 849 uint32_t rsp_opcode); 850 int audioreach_set_media_format(struct q6apm_graph *graph, 851 const struct audioreach_module *module, 852 const struct audioreach_module_config *cfg); 853 int audioreach_shared_memory_send_eos(struct q6apm_graph *graph); 854 int audioreach_gain_set_vol_ctrl(struct q6apm *apm, 855 const struct audioreach_module *module, int vol); 856 int audioreach_send_u32_param(struct q6apm_graph *graph, 857 const struct audioreach_module *module, 858 uint32_t param_id, uint32_t param_val); 859 int audioreach_compr_set_param(struct q6apm_graph *graph, 860 const struct audioreach_module_config *mcfg); 861 862 #endif /* __AUDIOREACH_H__ */ 863