1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2025, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 35 #ifndef _IXGBE_TYPE_E610_H_ 36 #define _IXGBE_TYPE_E610_H_ 37 38 39 /* Generic defines */ 40 #ifndef BIT 41 #define BIT(a) (1UL << (a)) 42 #endif /* !BIT */ 43 #ifndef BIT_ULL 44 #define BIT_ULL(a) (1ULL << (a)) 45 #endif /* !BIT_ULL */ 46 #ifndef BITS_PER_BYTE 47 #define BITS_PER_BYTE 8 48 #endif /* !BITS_PER_BYTE */ 49 #ifndef DIVIDE_AND_ROUND_UP 50 #define DIVIDE_AND_ROUND_UP(a, b) (((a) + (b) - 1) / (b)) 51 #endif /* !DIVIDE_AND_ROUND_UP */ 52 53 #ifndef ROUND_UP 54 /** 55 * ROUND_UP - round up to next arbitrary multiple (not a power of 2) 56 * @a: value to round up 57 * @b: arbitrary multiple 58 * 59 * Round up to the next multiple of the arbitrary b. 60 */ 61 #define ROUND_UP(a, b) ((b) * DIVIDE_AND_ROUND_UP((a), (b))) 62 #endif /* !ROUND_UP */ 63 64 #define MAKEMASK(mask, shift) (mask << shift) 65 66 #define BYTES_PER_WORD 2 67 #define BYTES_PER_DWORD 4 68 69 #ifndef BITS_PER_LONG 70 #define BITS_PER_LONG 64 71 #endif /* !BITS_PER_LONG */ 72 #ifndef BITS_PER_LONG_LONG 73 #define BITS_PER_LONG_LONG 64 74 #endif /* !BITS_PER_LONG_LONG */ 75 #undef GENMASK 76 #define GENMASK(h, l) \ 77 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) 78 #undef GENMASK_ULL 79 #define GENMASK_ULL(h, l) \ 80 (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) 81 82 /* Data type manipulation macros. */ 83 #define HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) 84 #define LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) 85 #define HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) 86 #define LO_WORD(x) ((u16)((x) & 0xFFFF)) 87 #define HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF)) 88 #define LO_BYTE(x) ((u8)((x) & 0xFF)) 89 90 #ifndef MIN_T 91 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b)) 92 #endif 93 94 #define IS_ASCII(_ch) ((_ch) < 0x80) 95 96 /** 97 * ixgbe_struct_size - size of struct with C99 flexible array member 98 * @ptr: pointer to structure 99 * @field: flexible array member (last member of the structure) 100 * @num: number of elements of that flexible array member 101 */ 102 #define ixgbe_struct_size(ptr, field, num) \ 103 (sizeof(*(ptr)) + sizeof(*(ptr)->field) * (num)) 104 105 /* General E610 defines */ 106 #define IXGBE_MAX_VSI 768 107 108 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ 109 #define E610_SR_VPD_SIZE_WORDS 512 110 #define E610_SR_PCIE_ALT_SIZE_WORDS 512 111 112 /* Checksum and Shadow RAM pointers */ 113 #define E610_SR_NVM_DEV_STARTER_VER 0x18 114 #define E610_NVM_VER_LO_SHIFT 0 115 #define E610_NVM_VER_LO_MASK (0xff << E610_NVM_VER_LO_SHIFT) 116 #define E610_NVM_VER_HI_SHIFT 12 117 #define E610_NVM_VER_HI_MASK (0xf << E610_NVM_VER_HI_SHIFT) 118 #define E610_SR_NVM_MAP_VER 0x29 119 #define E610_SR_NVM_EETRACK_LO 0x2D 120 #define E610_SR_NVM_EETRACK_HI 0x2E 121 #define E610_SR_VPD_PTR 0x2F 122 #define E610_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E 123 #define E610_SR_SW_CHECKSUM_WORD 0x3F 124 #define E610_SR_PFA_PTR 0x40 125 #define E610_SR_1ST_NVM_BANK_PTR 0x42 126 #define E610_SR_NVM_BANK_SIZE 0x43 127 #define E610_SR_1ST_OROM_BANK_PTR 0x44 128 #define E610_SR_OROM_BANK_SIZE 0x45 129 #define E610_SR_NETLIST_BANK_PTR 0x46 130 #define E610_SR_NETLIST_BANK_SIZE 0x47 131 #define E610_SR_POINTER_TYPE_BIT BIT(15) 132 #define E610_SR_POINTER_MASK 0x7fff 133 #define E610_SR_HALF_4KB_SECTOR_UNITS 2048 134 #define E610_GET_PFA_POINTER_IN_WORDS(offset) \ 135 ((offset & E610_SR_POINTER_TYPE_BIT) == E610_SR_POINTER_TYPE_BIT) ? \ 136 ((offset & E610_SR_POINTER_MASK) * E610_SR_HALF_4KB_SECTOR_UNITS) : \ 137 (offset & E610_SR_POINTER_MASK) 138 139 /* Checksum and Shadow RAM pointers */ 140 #define E610_SR_NVM_CTRL_WORD 0x00 141 #define E610_SR_PBA_BLOCK_PTR 0x16 142 143 /* The Orom version topology */ 144 #define IXGBE_OROM_VER_PATCH_SHIFT 0 145 #define IXGBE_OROM_VER_PATCH_MASK (0xff << IXGBE_OROM_VER_PATCH_SHIFT) 146 #define IXGBE_OROM_VER_BUILD_SHIFT 8 147 #define IXGBE_OROM_VER_BUILD_MASK (0xffff << IXGBE_OROM_VER_BUILD_SHIFT) 148 #define IXGBE_OROM_VER_SHIFT 24 149 #define IXGBE_OROM_VER_MASK (0xff << IXGBE_OROM_VER_SHIFT) 150 151 /* CSS Header words */ 152 #define IXGBE_NVM_CSS_HDR_LEN_L 0x02 153 #define IXGBE_NVM_CSS_HDR_LEN_H 0x03 154 #define IXGBE_NVM_CSS_SREV_L 0x14 155 #define IXGBE_NVM_CSS_SREV_H 0x15 156 157 /* Length of Authentication header section in words */ 158 #define IXGBE_NVM_AUTH_HEADER_LEN 0x08 159 160 /* The Netlist ID Block is located after all of the Link Topology nodes. */ 161 #define IXGBE_NETLIST_ID_BLK_SIZE 0x30 162 #define IXGBE_NETLIST_ID_BLK_OFFSET(n) IXGBE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n)) 163 164 /* netlist ID block field offsets (word offsets) */ 165 #define IXGBE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02 166 #define IXGBE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03 167 #define IXGBE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04 168 #define IXGBE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05 169 #define IXGBE_NETLIST_ID_BLK_TYPE_LOW 0x06 170 #define IXGBE_NETLIST_ID_BLK_TYPE_HIGH 0x07 171 #define IXGBE_NETLIST_ID_BLK_REV_LOW 0x08 172 #define IXGBE_NETLIST_ID_BLK_REV_HIGH 0x09 173 #define IXGBE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n)) 174 #define IXGBE_NETLIST_ID_BLK_CUST_VER 0x2F 175 176 /* The Link Topology Netlist section is stored as a series of words. It is 177 * stored in the NVM as a TLV, with the first two words containing the type 178 * and length. 179 */ 180 #define IXGBE_NETLIST_LINK_TOPO_MOD_ID 0x011B 181 #define IXGBE_NETLIST_TYPE_OFFSET 0x0000 182 #define IXGBE_NETLIST_LEN_OFFSET 0x0001 183 184 /* The Link Topology section follows the TLV header. When reading the netlist 185 * using ixgbe_read_netlist_module, we need to account for the 2-word TLV 186 * header. 187 */ 188 #define IXGBE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2) 189 #define IXGBE_LINK_TOPO_MODULE_LEN IXGBE_NETLIST_LINK_TOPO_OFFSET(0x0000) 190 #define IXGBE_LINK_TOPO_NODE_COUNT IXGBE_NETLIST_LINK_TOPO_OFFSET(0x0001) 191 #define IXGBE_LINK_TOPO_NODE_COUNT_M MAKEMASK(0x3FF, 0) 192 193 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ 194 #define IXGBE_SR_CTRL_WORD_1_S 0x06 195 #define IXGBE_SR_CTRL_WORD_1_M (0x03 << IXGBE_SR_CTRL_WORD_1_S) 196 #define IXGBE_SR_CTRL_WORD_VALID 0x1 197 #define IXGBE_SR_CTRL_WORD_OROM_BANK BIT(3) 198 #define IXGBE_SR_CTRL_WORD_NETLIST_BANK BIT(4) 199 #define IXGBE_SR_CTRL_WORD_NVM_BANK BIT(5) 200 #define IXGBE_SR_NVM_PTR_4KB_UNITS BIT(15) 201 202 /* These macros strip from NVM Image Revision the particular part of NVM ver: 203 major ver, minor ver and image id */ 204 #define E610_NVM_MAJOR_VER(x) ((x & 0xF000) >> 12) 205 #define E610_NVM_MINOR_VER(x) (x & 0x00FF) 206 207 /* Shadow RAM related */ 208 #define IXGBE_SR_SECTOR_SIZE_IN_WORDS 0x800 209 #define IXGBE_SR_WORDS_IN_1KB 512 210 /* Checksum should be calculated such that after adding all the words, 211 * including the checksum word itself, the sum should be 0xBABA. 212 */ 213 #define IXGBE_SR_SW_CHECKSUM_BASE 0xBABA 214 215 /* Netlist */ 216 #define IXGBE_MAX_NETLIST_SIZE 10 217 218 /* General registers */ 219 220 /* Firmware Status Register (GL_FWSTS) */ 221 #define GL_FWSTS 0x00083048 /* Reset Source: POR */ 222 #define GL_FWSTS_FWS0B_S 0 223 #define GL_FWSTS_FWS0B_M MAKEMASK(0xFF, 0) 224 #define GL_FWSTS_FWROWD_S 8 225 #define GL_FWSTS_FWROWD_M BIT(8) 226 #define GL_FWSTS_FWRI_S 9 227 #define GL_FWSTS_FWRI_M BIT(9) 228 #define GL_FWSTS_FWS1B_S 16 229 #define GL_FWSTS_FWS1B_M MAKEMASK(0xFF, 16) 230 #define GL_FWSTS_EP_PF0 BIT(24) 231 #define GL_FWSTS_EP_PF1 BIT(25) 232 233 /* Recovery mode values of Firmware Status 1 Byte (FWS1B) bitfield */ 234 #define GL_FWSTS_FWS1B_RECOVERY_MODE_CORER_LEGACY 0x0B 235 #define GL_FWSTS_FWS1B_RECOVERY_MODE_GLOBR_LEGACY 0x0C 236 #define GL_FWSTS_FWS1B_RECOVERY_MODE_CORER 0x30 237 #define GL_FWSTS_FWS1B_RECOVERY_MODE_GLOBR 0x31 238 #define GL_FWSTS_FWS1B_RECOVERY_MODE_TRANSITION 0x32 239 #define GL_FWSTS_FWS1B_RECOVERY_MODE_NVM 0x33 240 241 /* Firmware Status (GL_MNG_FWSM) */ 242 #define GL_MNG_FWSM 0x000B6134 /* Reset Source: POR */ 243 #define GL_MNG_FWSM_FW_MODES_S 0 244 #define GL_MNG_FWSM_FW_MODES_M MAKEMASK(0x7, 0) 245 #define GL_MNG_FWSM_RSV0_S 2 246 #define GL_MNG_FWSM_RSV0_M MAKEMASK(0xFF, 2) 247 #define GL_MNG_FWSM_EEP_RELOAD_IND_S 10 248 #define GL_MNG_FWSM_EEP_RELOAD_IND_M BIT(10) 249 #define GL_MNG_FWSM_RSV1_S 11 250 #define GL_MNG_FWSM_RSV1_M MAKEMASK(0xF, 11) 251 #define GL_MNG_FWSM_RSV2_S 15 252 #define GL_MNG_FWSM_RSV2_M BIT(15) 253 #define GL_MNG_FWSM_PCIR_AL_FAILURE_S 16 254 #define GL_MNG_FWSM_PCIR_AL_FAILURE_M BIT(16) 255 #define GL_MNG_FWSM_POR_AL_FAILURE_S 17 256 #define GL_MNG_FWSM_POR_AL_FAILURE_M BIT(17) 257 #define GL_MNG_FWSM_RSV3_S 18 258 #define GL_MNG_FWSM_RSV3_M BIT(18) 259 #define GL_MNG_FWSM_EXT_ERR_IND_S 19 260 #define GL_MNG_FWSM_EXT_ERR_IND_M MAKEMASK(0x3F, 19) 261 #define GL_MNG_FWSM_RSV4_S 25 262 #define GL_MNG_FWSM_RSV4_M BIT(25) 263 #define GL_MNG_FWSM_RESERVED_11_S 26 264 #define GL_MNG_FWSM_RESERVED_11_M MAKEMASK(0xF, 26) 265 #define GL_MNG_FWSM_RSV5_S 30 266 #define GL_MNG_FWSM_RSV5_M MAKEMASK(0x3, 30) 267 268 /* FW mode indications */ 269 #define GL_MNG_FWSM_FW_MODES_DEBUG_M BIT(0) 270 #define GL_MNG_FWSM_FW_MODES_RECOVERY_M BIT(1) 271 #define GL_MNG_FWSM_FW_MODES_ROLLBACK_M BIT(2) 272 273 /* Global NVM General Status Register */ 274 #define GLNVM_GENS 0x000B6100 /* Reset Source: POR */ 275 #define GLNVM_GENS_NVM_PRES_S 0 276 #define GLNVM_GENS_NVM_PRES_M BIT(0) 277 #define GLNVM_GENS_SR_SIZE_S 5 278 #define GLNVM_GENS_SR_SIZE_M MAKEMASK(0x7, 5) 279 #define GLNVM_GENS_BANK1VAL_S 8 280 #define GLNVM_GENS_BANK1VAL_M BIT(8) 281 #define GLNVM_GENS_ALT_PRST_S 23 282 #define GLNVM_GENS_ALT_PRST_M BIT(23) 283 #define GLNVM_GENS_FL_AUTO_RD_S 25 284 #define GLNVM_GENS_FL_AUTO_RD_M BIT(25) 285 286 /* Flash Access Register */ 287 #define GLNVM_FLA 0x000B6108 /* Reset Source: POR */ 288 #define GLNVM_FLA_LOCKED_S 6 289 #define GLNVM_FLA_LOCKED_M BIT(6) 290 291 /* Bit Bang registers */ 292 #define RDASB_MSGCTL 0x000B6820 293 #define RDASB_MSGCTL_HDR_DWS_S 0 294 #define RDASB_MSGCTL_EXP_RDW_S 8 295 #define RDASB_MSGCTL_CMDV_M BIT(31) 296 #define RDASB_RSPCTL 0x000B6824 297 #define RDASB_RSPCTL_BAD_LENGTH_M BIT(30) 298 #define RDASB_RSPCTL_NOT_SUCCESS_M BIT(31) 299 #define RDASB_WHDR0 0x000B68F4 300 #define RDASB_WHDR1 0x000B68F8 301 #define RDASB_WHDR2 0x000B68FC 302 #define RDASB_WHDR3 0x000B6900 303 #define RDASB_WHDR4 0x000B6904 304 #define RDASB_RHDR0 0x000B6AFC 305 #define RDASB_RHDR0_RESPONSE_S 27 306 #define RDASB_RHDR0_RESPONSE_M MAKEMASK(0x7, 27) 307 #define RDASB_RDATA0 0x000B6B00 308 #define RDASB_RDATA1 0x000B6B04 309 310 /* SPI Registers */ 311 #define SPISB_MSGCTL 0x000B7020 312 #define SPISB_MSGCTL_HDR_DWS_S 0 313 #define SPISB_MSGCTL_EXP_RDW_S 8 314 #define SPISB_MSGCTL_MSG_MODE_S 26 315 #define SPISB_MSGCTL_TOKEN_MODE_S 28 316 #define SPISB_MSGCTL_BARCLR_S 30 317 #define SPISB_MSGCTL_CMDV_S 31 318 #define SPISB_MSGCTL_CMDV_M BIT(31) 319 #define SPISB_RSPCTL 0x000B7024 320 #define SPISB_RSPCTL_BAD_LENGTH_M BIT(30) 321 #define SPISB_RSPCTL_NOT_SUCCESS_M BIT(31) 322 #define SPISB_WHDR0 0x000B70F4 323 #define SPISB_WHDR0_DEST_SEL_S 12 324 #define SPISB_WHDR0_OPCODE_SEL_S 16 325 #define SPISB_WHDR0_TAG_S 24 326 #define SPISB_WHDR1 0x000B70F8 327 #define SPISB_WHDR2 0x000B70FC 328 #define SPISB_RDATA 0x000B7300 329 #define SPISB_WDATA 0x000B7100 330 331 /* Firmware Reset Count register */ 332 #define GL_FWRESETCNT 0x00083100 /* Reset Source: POR */ 333 #define GL_FWRESETCNT_FWRESETCNT_S 0 334 #define GL_FWRESETCNT_FWRESETCNT_M MAKEMASK(0xFFFFFFFF, 0) 335 336 /* Admin Command Interface (ACI) registers */ 337 #define PF_HIDA(_i) (0x00085000 + ((_i) * 4)) 338 #define PF_HIDA_2(_i) (0x00085020 + ((_i) * 4)) 339 #define PF_HIBA(_i) (0x00084000 + ((_i) * 4)) 340 #define PF_HICR 0x00082048 341 342 #define PF_HIDA_MAX_INDEX 15 343 #define PF_HIBA_MAX_INDEX 1023 344 345 #define PF_HICR_EN BIT(0) 346 #define PF_HICR_C BIT(1) 347 #define PF_HICR_SV BIT(2) 348 #define PF_HICR_EV BIT(3) 349 350 #define GL_HIDA(_i) (0x00082000 + ((_i) * 4)) 351 #define GL_HIDA_2(_i) (0x00082020 + ((_i) * 4)) 352 #define GL_HIBA(_i) (0x00081000 + ((_i) * 4)) 353 #define GL_HICR 0x00082040 354 355 #define GL_HIDA_MAX_INDEX 15 356 #define GL_HIBA_MAX_INDEX 1023 357 358 #define GL_HICR_C BIT(1) 359 #define GL_HICR_SV BIT(2) 360 #define GL_HICR_EV BIT(3) 361 362 #define GL_HICR_EN 0x00082044 363 364 #define GL_HICR_EN_CHECK BIT(0) 365 366 /* Admin Command Interface (ACI) defines */ 367 /* Defines that help manage the driver vs FW API checks. 368 */ 369 #define IXGBE_FW_API_VER_BRANCH 0x00 370 #define IXGBE_FW_API_VER_MAJOR 0x01 371 #define IXGBE_FW_API_VER_MINOR 0x07 372 #define IXGBE_FW_API_VER_DIFF_ALLOWED 0x02 373 374 #define IXGBE_ACI_DESC_SIZE 32 375 #define IXGBE_ACI_DESC_SIZE_IN_DWORDS IXGBE_ACI_DESC_SIZE / BYTES_PER_DWORD 376 377 #define IXGBE_ACI_MAX_BUFFER_SIZE 4096 /* Size in bytes */ 378 #define IXGBE_ACI_DESC_COOKIE_L_DWORD_OFFSET 3 379 #define IXGBE_ACI_SEND_DELAY_TIME_MS 10 380 #define IXGBE_ACI_SEND_MAX_EXECUTE 3 381 /* [ms] timeout of waiting for sync response */ 382 #define IXGBE_ACI_SYNC_RESPONSE_TIMEOUT 100000 383 /* [ms] timeout of waiting for async response */ 384 #define IXGBE_ACI_ASYNC_RESPONSE_TIMEOUT 150000 385 /* [ms] timeout of waiting for resource release */ 386 #define IXGBE_ACI_RELEASE_RES_TIMEOUT 10000 387 388 /* Timestamp spacing for Tools ACI: queue is active if spacing is within the range [LO..HI] */ 389 #define IXGBE_TOOLS_ACI_ACTIVE_STAMP_SPACING_LO 0 390 #define IXGBE_TOOLS_ACI_ACTIVE_STAMP_SPACING_HI 200 391 392 /* Timestamp spacing for Tools ACI: queue is expired if spacing is outside the range [LO..HI] */ 393 #define IXGBE_TOOLS_ACI_EXPIRED_STAMP_SPACING_LO -5 394 #define IXGBE_TOOLS_ACI_EXPIRED_STAMP_SPACING_HI 205 395 396 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 397 #define IXGBE_ACI_LG_BUF 512 398 399 /* Flags sub-structure 400 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 401 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 402 */ 403 404 /* command flags and offsets */ 405 #define IXGBE_ACI_FLAG_DD_S 0 406 #define IXGBE_ACI_FLAG_CMP_S 1 407 #define IXGBE_ACI_FLAG_ERR_S 2 408 #define IXGBE_ACI_FLAG_VFE_S 3 409 #define IXGBE_ACI_FLAG_LB_S 9 410 #define IXGBE_ACI_FLAG_RD_S 10 411 #define IXGBE_ACI_FLAG_VFC_S 11 412 #define IXGBE_ACI_FLAG_BUF_S 12 413 #define IXGBE_ACI_FLAG_SI_S 13 414 #define IXGBE_ACI_FLAG_EI_S 14 415 #define IXGBE_ACI_FLAG_FE_S 15 416 417 #define IXGBE_ACI_FLAG_DD BIT(IXGBE_ACI_FLAG_DD_S) /* 0x1 */ 418 #define IXGBE_ACI_FLAG_CMP BIT(IXGBE_ACI_FLAG_CMP_S) /* 0x2 */ 419 #define IXGBE_ACI_FLAG_ERR BIT(IXGBE_ACI_FLAG_ERR_S) /* 0x4 */ 420 #define IXGBE_ACI_FLAG_VFE BIT(IXGBE_ACI_FLAG_VFE_S) /* 0x8 */ 421 #define IXGBE_ACI_FLAG_LB BIT(IXGBE_ACI_FLAG_LB_S) /* 0x200 */ 422 #define IXGBE_ACI_FLAG_RD BIT(IXGBE_ACI_FLAG_RD_S) /* 0x400 */ 423 #define IXGBE_ACI_FLAG_VFC BIT(IXGBE_ACI_FLAG_VFC_S) /* 0x800 */ 424 #define IXGBE_ACI_FLAG_BUF BIT(IXGBE_ACI_FLAG_BUF_S) /* 0x1000 */ 425 #define IXGBE_ACI_FLAG_SI BIT(IXGBE_ACI_FLAG_SI_S) /* 0x2000 */ 426 #define IXGBE_ACI_FLAG_EI BIT(IXGBE_ACI_FLAG_EI_S) /* 0x4000 */ 427 #define IXGBE_ACI_FLAG_FE BIT(IXGBE_ACI_FLAG_FE_S) /* 0x8000 */ 428 429 /* Admin Command Interface (ACI) error codes */ 430 enum ixgbe_aci_err { 431 IXGBE_ACI_RC_OK = 0, /* Success */ 432 IXGBE_ACI_RC_EPERM = 1, /* Operation not permitted */ 433 IXGBE_ACI_RC_ENOENT = 2, /* No such element */ 434 IXGBE_ACI_RC_ESRCH = 3, /* Bad opcode */ 435 IXGBE_ACI_RC_EINTR = 4, /* Operation interrupted */ 436 IXGBE_ACI_RC_EIO = 5, /* I/O error */ 437 IXGBE_ACI_RC_ENXIO = 6, /* No such resource */ 438 IXGBE_ACI_RC_E2BIG = 7, /* Arg too long */ 439 IXGBE_ACI_RC_EAGAIN = 8, /* Try again */ 440 IXGBE_ACI_RC_ENOMEM = 9, /* Out of memory */ 441 IXGBE_ACI_RC_EACCES = 10, /* Permission denied */ 442 IXGBE_ACI_RC_EFAULT = 11, /* Bad address */ 443 IXGBE_ACI_RC_EBUSY = 12, /* Device or resource busy */ 444 IXGBE_ACI_RC_EEXIST = 13, /* Object already exists */ 445 IXGBE_ACI_RC_EINVAL = 14, /* Invalid argument */ 446 IXGBE_ACI_RC_ENOTTY = 15, /* Not a typewriter */ 447 IXGBE_ACI_RC_ENOSPC = 16, /* No space left or allocation failure */ 448 IXGBE_ACI_RC_ENOSYS = 17, /* Function not implemented */ 449 IXGBE_ACI_RC_ERANGE = 18, /* Parameter out of range */ 450 IXGBE_ACI_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 451 IXGBE_ACI_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 452 IXGBE_ACI_RC_EMODE = 21, /* Op not allowed in current dev mode */ 453 IXGBE_ACI_RC_EFBIG = 22, /* File too big */ 454 IXGBE_ACI_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */ 455 IXGBE_ACI_RC_ENOSEC = 24, /* Missing security manifest */ 456 IXGBE_ACI_RC_EBADSIG = 25, /* Bad RSA signature */ 457 IXGBE_ACI_RC_ESVN = 26, /* SVN number prohibits this package */ 458 IXGBE_ACI_RC_EBADMAN = 27, /* Manifest hash mismatch */ 459 IXGBE_ACI_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 460 IXGBE_ACI_RC_EACCES_BMCU = 29, /* BMC Update in progress */ 461 }; 462 463 /* Admin Command Interface (ACI) opcodes */ 464 enum ixgbe_aci_opc { 465 ixgbe_aci_opc_get_ver = 0x0001, 466 ixgbe_aci_opc_driver_ver = 0x0002, 467 ixgbe_aci_opc_get_exp_err = 0x0005, 468 469 /* resource ownership */ 470 ixgbe_aci_opc_req_res = 0x0008, 471 ixgbe_aci_opc_release_res = 0x0009, 472 473 /* device/function capabilities */ 474 ixgbe_aci_opc_list_func_caps = 0x000A, 475 ixgbe_aci_opc_list_dev_caps = 0x000B, 476 477 /* safe disable of RXEN */ 478 ixgbe_aci_opc_disable_rxen = 0x000C, 479 480 /* FW events */ 481 ixgbe_aci_opc_get_fw_event = 0x0014, 482 483 /* PHY commands */ 484 ixgbe_aci_opc_get_phy_caps = 0x0600, 485 ixgbe_aci_opc_set_phy_cfg = 0x0601, 486 ixgbe_aci_opc_restart_an = 0x0605, 487 ixgbe_aci_opc_get_link_status = 0x0607, 488 ixgbe_aci_opc_set_event_mask = 0x0613, 489 ixgbe_aci_opc_get_link_topo = 0x06E0, 490 ixgbe_aci_opc_read_i2c = 0x06E2, 491 ixgbe_aci_opc_write_i2c = 0x06E3, 492 ixgbe_aci_opc_read_mdio = 0x06E4, 493 ixgbe_aci_opc_write_mdio = 0x06E5, 494 ixgbe_aci_opc_set_gpio_by_func = 0x06E6, 495 ixgbe_aci_opc_get_gpio_by_func = 0x06E7, 496 ixgbe_aci_opc_set_port_id_led = 0x06E9, 497 ixgbe_aci_opc_set_gpio = 0x06EC, 498 ixgbe_aci_opc_get_gpio = 0x06ED, 499 ixgbe_aci_opc_sff_eeprom = 0x06EE, 500 ixgbe_aci_opc_prog_topo_dev_nvm = 0x06F2, 501 ixgbe_aci_opc_read_topo_dev_nvm = 0x06F3, 502 503 /* NVM commands */ 504 ixgbe_aci_opc_nvm_read = 0x0701, 505 ixgbe_aci_opc_nvm_erase = 0x0702, 506 ixgbe_aci_opc_nvm_write = 0x0703, 507 ixgbe_aci_opc_nvm_cfg_read = 0x0704, 508 ixgbe_aci_opc_nvm_cfg_write = 0x0705, 509 ixgbe_aci_opc_nvm_checksum = 0x0706, 510 ixgbe_aci_opc_nvm_write_activate = 0x0707, 511 ixgbe_aci_opc_nvm_sr_dump = 0x0707, 512 ixgbe_aci_opc_nvm_save_factory_settings = 0x0708, 513 ixgbe_aci_opc_nvm_update_empr = 0x0709, 514 ixgbe_aci_opc_nvm_pkg_data = 0x070A, 515 ixgbe_aci_opc_nvm_pass_component_tbl = 0x070B, 516 ixgbe_aci_opc_nvm_sanitization = 0x070C, 517 518 /* Alternate Structure Commands */ 519 ixgbe_aci_opc_write_alt_direct = 0x0900, 520 ixgbe_aci_opc_write_alt_indirect = 0x0901, 521 ixgbe_aci_opc_read_alt_direct = 0x0902, 522 ixgbe_aci_opc_read_alt_indirect = 0x0903, 523 ixgbe_aci_opc_done_alt_write = 0x0904, 524 ixgbe_aci_opc_clear_port_alt_write = 0x0906, 525 526 ixgbe_aci_opc_temp_tca_event = 0x0C94, 527 528 /* debug commands */ 529 ixgbe_aci_opc_debug_dump_internals = 0xFF08, 530 531 /* SystemDiagnostic commands */ 532 ixgbe_aci_opc_set_health_status_config = 0xFF20, 533 ixgbe_aci_opc_get_supported_health_status_codes = 0xFF21, 534 ixgbe_aci_opc_get_health_status = 0xFF22, 535 ixgbe_aci_opc_clear_health_status = 0xFF23, 536 537 /* FW Logging Commands */ 538 ixgbe_aci_opc_fw_logs_config = 0xFF30, 539 ixgbe_aci_opc_fw_logs_register = 0xFF31, 540 ixgbe_aci_opc_fw_logs_query = 0xFF32, 541 ixgbe_aci_opc_fw_logs_event = 0xFF33, 542 ixgbe_aci_opc_fw_logs_get = 0xFF34, 543 ixgbe_aci_opc_fw_logs_clear = 0xFF35 544 }; 545 546 /* This macro is used to generate a compilation error if a structure 547 * is not exactly the correct length. It gives a divide by zero error if the 548 * structure is not of the correct size, otherwise it creates an enum that is 549 * never used. 550 */ 551 #define IXGBE_CHECK_STRUCT_LEN(n, X) enum ixgbe_static_assert_enum_##X \ 552 { ixgbe_static_assert_##X = (n) / ((sizeof(struct X) == (n)) ? 1 : 0) } 553 554 /* This macro is used to generate a compilation error if a variable-length 555 * structure is not exactly the correct length assuming a single element of 556 * the variable-length object as the last element of the structure. It gives 557 * a divide by zero error if the structure is not of the correct size, 558 * otherwise it creates an enum that is never used. 559 */ 560 #define IXGBE_CHECK_VAR_LEN_STRUCT_LEN(n, X, T) enum ixgbe_static_assert_enum_##X \ 561 { ixgbe_static_assert_##X = (n) / \ 562 (((sizeof(struct X) + sizeof(T)) == (n)) ? 1 : 0) } 563 564 /* This macro is used to ensure that parameter structures (i.e. structures 565 * in the params union member of struct ixgbe_aci_desc) are 16 bytes in length. 566 * 567 * NOT intended to be used to check the size of an indirect command/response 568 * additional data buffer (e.g. struct foo) which should just happen to be 16 569 * bytes (instead, use IXGBE_CHECK_STRUCT_LEN(16, foo) for that). 570 */ 571 #define IXGBE_CHECK_PARAM_LEN(X) IXGBE_CHECK_STRUCT_LEN(16, X) 572 573 struct ixgbe_aci_cmd_generic { 574 __le32 param0; 575 __le32 param1; 576 __le32 addr_high; 577 __le32 addr_low; 578 }; 579 580 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_generic); 581 582 /* Get version (direct 0x0001) */ 583 struct ixgbe_aci_cmd_get_ver { 584 __le32 rom_ver; 585 __le32 fw_build; 586 u8 fw_branch; 587 u8 fw_major; 588 u8 fw_minor; 589 u8 fw_patch; 590 u8 api_branch; 591 u8 api_major; 592 u8 api_minor; 593 u8 api_patch; 594 }; 595 596 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_ver); 597 598 #define IXGBE_DRV_VER_STR_LEN_E610 32 599 600 struct ixgbe_driver_ver { 601 u8 major_ver; 602 u8 minor_ver; 603 u8 build_ver; 604 u8 subbuild_ver; 605 u8 driver_string[IXGBE_DRV_VER_STR_LEN_E610]; 606 }; 607 608 /* Send driver version (indirect 0x0002) */ 609 struct ixgbe_aci_cmd_driver_ver { 610 u8 major_ver; 611 u8 minor_ver; 612 u8 build_ver; 613 u8 subbuild_ver; 614 u8 reserved[4]; 615 __le32 addr_high; 616 __le32 addr_low; 617 }; 618 619 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_driver_ver); 620 621 /* Get Expanded Error Code (0x0005, direct) */ 622 struct ixgbe_aci_cmd_get_exp_err { 623 __le32 reason; 624 #define IXGBE_ACI_EXPANDED_ERROR_NOT_PROVIDED 0xFFFFFFFF 625 __le32 identifier; 626 u8 rsvd[8]; 627 }; 628 629 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_exp_err); 630 631 /* FW update timeout definitions are in milliseconds */ 632 #define IXGBE_NVM_TIMEOUT 180000 633 #define IXGBE_CHANGE_LOCK_TIMEOUT 1000 634 #define IXGBE_GLOBAL_CFG_LOCK_TIMEOUT 3000 635 636 enum ixgbe_aci_res_access_type { 637 IXGBE_RES_READ = 1, 638 IXGBE_RES_WRITE 639 }; 640 641 enum ixgbe_aci_res_ids { 642 IXGBE_NVM_RES_ID = 1, 643 IXGBE_SPD_RES_ID, 644 IXGBE_CHANGE_LOCK_RES_ID, 645 IXGBE_GLOBAL_CFG_LOCK_RES_ID 646 }; 647 648 /* Request resource ownership (direct 0x0008) 649 * Release resource ownership (direct 0x0009) 650 */ 651 struct ixgbe_aci_cmd_req_res { 652 __le16 res_id; 653 #define IXGBE_ACI_RES_ID_NVM 1 654 #define IXGBE_ACI_RES_ID_SDP 2 655 #define IXGBE_ACI_RES_ID_CHNG_LOCK 3 656 #define IXGBE_ACI_RES_ID_GLBL_LOCK 4 657 __le16 access_type; 658 #define IXGBE_ACI_RES_ACCESS_READ 1 659 #define IXGBE_ACI_RES_ACCESS_WRITE 2 660 661 /* Upon successful completion, FW writes this value and driver is 662 * expected to release resource before timeout. This value is provided 663 * in milliseconds. 664 */ 665 __le32 timeout; 666 #define IXGBE_ACI_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 667 #define IXGBE_ACI_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 668 #define IXGBE_ACI_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 669 #define IXGBE_ACI_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 670 /* For SDP: pin ID of the SDP */ 671 __le32 res_number; 672 /* Status is only used for IXGBE_ACI_RES_ID_GLBL_LOCK */ 673 __le16 status; 674 #define IXGBE_ACI_RES_GLBL_SUCCESS 0 675 #define IXGBE_ACI_RES_GLBL_IN_PROG 1 676 #define IXGBE_ACI_RES_GLBL_DONE 2 677 u8 reserved[2]; 678 }; 679 680 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_req_res); 681 682 /* Get function capabilities (indirect 0x000A) 683 * Get device capabilities (indirect 0x000B) 684 */ 685 struct ixgbe_aci_cmd_list_caps { 686 u8 cmd_flags; 687 u8 pf_index; 688 u8 reserved[2]; 689 __le32 count; 690 __le32 addr_high; 691 __le32 addr_low; 692 }; 693 694 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_list_caps); 695 696 /* Device/Function buffer entry, repeated per reported capability */ 697 struct ixgbe_aci_cmd_list_caps_elem { 698 __le16 cap; 699 #define IXGBE_ACI_CAPS_VALID_FUNCTIONS 0x0005 700 #define IXGBE_ACI_MAX_VALID_FUNCTIONS 0x8 701 #define IXGBE_ACI_CAPS_SRIOV 0x0012 702 #define IXGBE_ACI_CAPS_VF 0x0013 703 #define IXGBE_ACI_CAPS_VMDQ 0x0014 704 #define IXGBE_ACI_CAPS_VSI 0x0017 705 #define IXGBE_ACI_CAPS_DCB 0x0018 706 #define IXGBE_ACI_CAPS_RSS 0x0040 707 #define IXGBE_ACI_CAPS_RXQS 0x0041 708 #define IXGBE_ACI_CAPS_TXQS 0x0042 709 #define IXGBE_ACI_CAPS_MSIX 0x0043 710 #define IXGBE_ACI_CAPS_FD 0x0045 711 #define IXGBE_ACI_CAPS_MAX_MTU 0x0047 712 #define IXGBE_ACI_CAPS_NVM_VER 0x0048 713 #define IXGBE_ACI_CAPS_INLINE_IPSEC 0x0070 714 #define IXGBE_ACI_CAPS_NUM_ENABLED_PORTS 0x0072 715 #define IXGBE_ACI_CAPS_PCIE_RESET_AVOIDANCE 0x0076 716 #define IXGBE_ACI_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 717 #define IXGBE_ACI_CAPS_NVM_MGMT 0x0080 718 #define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG0 0x0081 719 #define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG1 0x0082 720 #define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG2 0x0083 721 #define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG3 0x0084 722 #define IXGBE_ACI_CAPS_OROM_RECOVERY_UPDATE 0x0090 723 #define IXGBE_ACI_CAPS_NEXT_CLUSTER_ID 0x0096 724 #define IXGBE_ACI_CAPS_EEE 0x009B 725 u8 major_ver; 726 u8 minor_ver; 727 /* Number of resources described by this capability */ 728 __le32 number; 729 /* Only meaningful for some types of resources */ 730 __le32 logical_id; 731 /* Only meaningful for some types of resources */ 732 __le32 phys_id; 733 __le64 rsvd1; 734 __le64 rsvd2; 735 }; 736 737 IXGBE_CHECK_STRUCT_LEN(32, ixgbe_aci_cmd_list_caps_elem); 738 739 /* Disable RXEN (direct 0x000C) */ 740 struct ixgbe_aci_cmd_disable_rxen { 741 u8 lport_num; 742 u8 reserved[15]; 743 }; 744 745 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_disable_rxen); 746 747 /* Get FW Event (indirect 0x0014) */ 748 struct ixgbe_aci_cmd_get_fw_event { 749 __le16 fw_buf_status; 750 #define IXGBE_ACI_GET_FW_EVENT_STATUS_OBTAINED BIT(0) 751 #define IXGBE_ACI_GET_FW_EVENT_STATUS_PENDING BIT(1) 752 u8 rsvd[14]; 753 }; 754 755 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_fw_event); 756 757 /* Get PHY capabilities (indirect 0x0600) */ 758 struct ixgbe_aci_cmd_get_phy_caps { 759 u8 lport_num; 760 u8 reserved; 761 __le16 param0; 762 /* 18.0 - Report qualified modules */ 763 #define IXGBE_ACI_GET_PHY_RQM BIT(0) 764 /* 18.1 - 18.3 : Report mode 765 * 000b - Report topology capabilities, without media 766 * 001b - Report topology capabilities, with media 767 * 010b - Report Active configuration 768 * 011b - Report PHY Type and FEC mode capabilities 769 * 100b - Report Default capabilities 770 */ 771 #define IXGBE_ACI_REPORT_MODE_S 1 772 #define IXGBE_ACI_REPORT_MODE_M (7 << IXGBE_ACI_REPORT_MODE_S) 773 #define IXGBE_ACI_REPORT_TOPO_CAP_NO_MEDIA 0 774 #define IXGBE_ACI_REPORT_TOPO_CAP_MEDIA BIT(1) 775 #define IXGBE_ACI_REPORT_ACTIVE_CFG BIT(2) 776 #define IXGBE_ACI_REPORT_DFLT_CFG BIT(3) 777 __le32 reserved1; 778 __le32 addr_high; 779 __le32 addr_low; 780 }; 781 782 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_phy_caps); 783 784 /* This is #define of PHY type (Extended): 785 * The first set of defines is for phy_type_low. 786 */ 787 #define IXGBE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 788 #define IXGBE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 789 #define IXGBE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 790 #define IXGBE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 791 #define IXGBE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 792 #define IXGBE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 793 #define IXGBE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 794 #define IXGBE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 795 #define IXGBE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 796 #define IXGBE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 797 #define IXGBE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 798 #define IXGBE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 799 #define IXGBE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 800 #define IXGBE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 801 #define IXGBE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 802 #define IXGBE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 803 #define IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 804 #define IXGBE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 805 #define IXGBE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 806 #define IXGBE_PHY_TYPE_LOW_MAX_INDEX 18 807 /* The second set of defines is for phy_type_high. */ 808 #define IXGBE_PHY_TYPE_HIGH_10BASE_T BIT_ULL(1) 809 #define IXGBE_PHY_TYPE_HIGH_10M_SGMII BIT_ULL(2) 810 #define IXGBE_PHY_TYPE_HIGH_2500M_SGMII BIT_ULL(56) 811 #define IXGBE_PHY_TYPE_HIGH_100M_USXGMII BIT_ULL(57) 812 #define IXGBE_PHY_TYPE_HIGH_1G_USXGMII BIT_ULL(58) 813 #define IXGBE_PHY_TYPE_HIGH_2500M_USXGMII BIT_ULL(59) 814 #define IXGBE_PHY_TYPE_HIGH_5G_USXGMII BIT_ULL(60) 815 #define IXGBE_PHY_TYPE_HIGH_10G_USXGMII BIT_ULL(61) 816 #define IXGBE_PHY_TYPE_HIGH_MAX_INDEX 61 817 818 struct ixgbe_aci_cmd_get_phy_caps_data { 819 __le64 phy_type_low; /* Use values from IXGBE_PHY_TYPE_LOW_* */ 820 __le64 phy_type_high; /* Use values from IXGBE_PHY_TYPE_HIGH_* */ 821 u8 caps; 822 #define IXGBE_ACI_PHY_EN_TX_LINK_PAUSE BIT(0) 823 #define IXGBE_ACI_PHY_EN_RX_LINK_PAUSE BIT(1) 824 #define IXGBE_ACI_PHY_LOW_POWER_MODE BIT(2) 825 #define IXGBE_ACI_PHY_EN_LINK BIT(3) 826 #define IXGBE_ACI_PHY_AN_MODE BIT(4) 827 #define IXGBE_ACI_PHY_EN_MOD_QUAL BIT(5) 828 #define IXGBE_ACI_PHY_EN_LESM BIT(6) 829 #define IXGBE_ACI_PHY_EN_AUTO_FEC BIT(7) 830 #define IXGBE_ACI_PHY_CAPS_MASK MAKEMASK(0xff, 0) 831 u8 low_power_ctrl_an; 832 #define IXGBE_ACI_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 833 #define IXGBE_ACI_PHY_AN_EN_CLAUSE28 BIT(1) 834 #define IXGBE_ACI_PHY_AN_EN_CLAUSE73 BIT(2) 835 #define IXGBE_ACI_PHY_AN_EN_CLAUSE37 BIT(3) 836 __le16 eee_cap; 837 #define IXGBE_ACI_PHY_EEE_EN_100BASE_TX BIT(0) 838 #define IXGBE_ACI_PHY_EEE_EN_1000BASE_T BIT(1) 839 #define IXGBE_ACI_PHY_EEE_EN_10GBASE_T BIT(2) 840 #define IXGBE_ACI_PHY_EEE_EN_5GBASE_T BIT(11) 841 #define IXGBE_ACI_PHY_EEE_EN_2_5GBASE_T BIT(12) 842 __le16 eeer_value; 843 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 844 u8 phy_fw_ver[8]; 845 u8 link_fec_options; 846 #define IXGBE_ACI_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 847 #define IXGBE_ACI_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 848 #define IXGBE_ACI_PHY_FEC_25G_RS_528_REQ BIT(2) 849 #define IXGBE_ACI_PHY_FEC_25G_KR_REQ BIT(3) 850 #define IXGBE_ACI_PHY_FEC_25G_RS_544_REQ BIT(4) 851 #define IXGBE_ACI_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 852 #define IXGBE_ACI_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 853 #define IXGBE_ACI_PHY_FEC_MASK MAKEMASK(0xdf, 0) 854 u8 module_compliance_enforcement; 855 #define IXGBE_ACI_MOD_ENFORCE_STRICT_MODE BIT(0) 856 u8 extended_compliance_code; 857 #define IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE 3 858 u8 module_type[IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE]; 859 #define IXGBE_ACI_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 860 #define IXGBE_ACI_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 861 #define IXGBE_ACI_MOD_TYPE_IDENT 1 862 #define IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 863 #define IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 864 #define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 865 #define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 866 #define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 867 #define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 868 #define IXGBE_ACI_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 869 #define IXGBE_ACI_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 870 u8 qualified_module_count; 871 u8 rsvd2; 872 __le16 eee_entry_delay; 873 u8 rsvd3[4]; 874 #define IXGBE_ACI_QUAL_MOD_COUNT_MAX 16 875 struct { 876 u8 v_oui[3]; 877 u8 rsvd3; 878 u8 v_part[16]; 879 __le32 v_rev; 880 __le64 rsvd4; 881 } qual_modules[IXGBE_ACI_QUAL_MOD_COUNT_MAX]; 882 }; 883 884 IXGBE_CHECK_STRUCT_LEN(560, ixgbe_aci_cmd_get_phy_caps_data); 885 886 /* Set PHY capabilities (direct 0x0601) 887 * NOTE: This command must be followed by setup link and restart auto-neg 888 */ 889 struct ixgbe_aci_cmd_set_phy_cfg { 890 u8 reserved[8]; 891 __le32 addr_high; 892 __le32 addr_low; 893 }; 894 895 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_phy_cfg); 896 897 /* Set PHY config obsolete command data structure (<FW 1.40) */ 898 struct ixgbe_aci_cmd_set_phy_cfg_data_pre_1_40 { 899 __le64 phy_type_low; /* Use values from IXGBE_PHY_TYPE_LOW_* */ 900 __le64 phy_type_high; /* Use values from IXGBE_PHY_TYPE_HIGH_* */ 901 u8 caps; 902 u8 low_power_ctrl_an; 903 __le16 eee_cap; /* Value from ixgbe_aci_get_phy_caps */ 904 __le16 eeer_value; /* Use defines from ixgbe_aci_get_phy_caps */ 905 u8 link_fec_opt; /* Use defines from ixgbe_aci_get_phy_caps */ 906 u8 module_compliance_enforcement; 907 }; 908 909 IXGBE_CHECK_STRUCT_LEN(24, ixgbe_aci_cmd_set_phy_cfg_data_pre_1_40); 910 911 #pragma pack(1) 912 /* Set PHY config command data structure */ 913 struct ixgbe_aci_cmd_set_phy_cfg_data { 914 __le64 phy_type_low; /* Use values from IXGBE_PHY_TYPE_LOW_* */ 915 __le64 phy_type_high; /* Use values from IXGBE_PHY_TYPE_HIGH_* */ 916 u8 caps; 917 u8 low_power_ctrl_an; 918 __le16 eee_cap; /* Value from ixgbe_aci_get_phy_caps */ 919 __le16 eeer_value; /* Use defines from ixgbe_aci_get_phy_caps */ 920 u8 link_fec_opt; /* Use defines from ixgbe_aci_get_phy_caps */ 921 u8 module_compliance_enforcement; 922 __le16 eee_entry_delay; 923 }; 924 925 IXGBE_CHECK_STRUCT_LEN(26, ixgbe_aci_cmd_set_phy_cfg_data); 926 #pragma pack() 927 928 /* Set PHY config capabilities (@caps) defines */ 929 #define IXGBE_ACI_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0) 930 #define IXGBE_ACI_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 931 #define IXGBE_ACI_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 932 #define IXGBE_ACI_PHY_ENA_LOW_POWER BIT(2) 933 #define IXGBE_ACI_PHY_ENA_LINK BIT(3) 934 #define IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT BIT(5) 935 #define IXGBE_ACI_PHY_ENA_LESM BIT(6) 936 #define IXGBE_ACI_PHY_ENA_AUTO_FEC BIT(7) 937 938 939 /* Restart AN command data structure (direct 0x0605) 940 * Also used for response, with only the lport_num field present. 941 */ 942 struct ixgbe_aci_cmd_restart_an { 943 u8 reserved[2]; 944 u8 cmd_flags; 945 #define IXGBE_ACI_RESTART_AN_LINK_RESTART BIT(1) 946 #define IXGBE_ACI_RESTART_AN_LINK_ENABLE BIT(2) 947 u8 reserved2[13]; 948 }; 949 950 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_restart_an); 951 952 #pragma pack(1) 953 /* Get link status (indirect 0x0607), also used for Link Status Event */ 954 struct ixgbe_aci_cmd_get_link_status { 955 u8 reserved[2]; 956 u8 cmd_flags; 957 #define IXGBE_ACI_LSE_M 0x3 958 #define IXGBE_ACI_LSE_NOP 0x0 959 #define IXGBE_ACI_LSE_DIS 0x2 960 #define IXGBE_ACI_LSE_ENA 0x3 961 /* only response uses this flag */ 962 #define IXGBE_ACI_LSE_IS_ENABLED 0x1 963 u8 reserved2[5]; 964 __le32 addr_high; 965 __le32 addr_low; 966 }; 967 968 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_link_status); 969 970 /* Get link status response data structure, also used for Link Status Event */ 971 struct ixgbe_aci_cmd_get_link_status_data { 972 u8 topo_media_conflict; 973 #define IXGBE_ACI_LINK_TOPO_CONFLICT BIT(0) 974 #define IXGBE_ACI_LINK_MEDIA_CONFLICT BIT(1) 975 #define IXGBE_ACI_LINK_TOPO_CORRUPT BIT(2) 976 #define IXGBE_ACI_LINK_TOPO_UNREACH_PRT BIT(4) 977 #define IXGBE_ACI_LINK_TOPO_UNDRUTIL_PRT BIT(5) 978 #define IXGBE_ACI_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 979 #define IXGBE_ACI_LINK_TOPO_UNSUPP_MEDIA BIT(7) 980 u8 link_cfg_err; 981 #define IXGBE_ACI_LINK_CFG_ERR BIT(0) 982 #define IXGBE_ACI_LINK_CFG_COMPLETED BIT(1) 983 #define IXGBE_ACI_LINK_ACT_PORT_OPT_INVAL BIT(2) 984 #define IXGBE_ACI_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3) 985 #define IXGBE_ACI_LINK_TOPO_CRITICAL_SDP_ERR BIT(4) 986 #define IXGBE_ACI_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 987 #define IXGBE_ACI_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6) 988 #define IXGBE_ACI_LINK_INVAL_MAX_POWER_LIMIT BIT(7) 989 u8 link_info; 990 #define IXGBE_ACI_LINK_UP BIT(0) /* Link Status */ 991 #define IXGBE_ACI_LINK_FAULT BIT(1) 992 #define IXGBE_ACI_LINK_FAULT_TX BIT(2) 993 #define IXGBE_ACI_LINK_FAULT_RX BIT(3) 994 #define IXGBE_ACI_LINK_FAULT_REMOTE BIT(4) 995 #define IXGBE_ACI_LINK_UP_PORT BIT(5) /* External Port Link Status */ 996 #define IXGBE_ACI_MEDIA_AVAILABLE BIT(6) 997 #define IXGBE_ACI_SIGNAL_DETECT BIT(7) 998 u8 an_info; 999 #define IXGBE_ACI_AN_COMPLETED BIT(0) 1000 #define IXGBE_ACI_LP_AN_ABILITY BIT(1) 1001 #define IXGBE_ACI_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1002 #define IXGBE_ACI_FEC_EN BIT(3) 1003 #define IXGBE_ACI_PHY_LOW_POWER BIT(4) /* Low Power State */ 1004 #define IXGBE_ACI_LINK_PAUSE_TX BIT(5) 1005 #define IXGBE_ACI_LINK_PAUSE_RX BIT(6) 1006 #define IXGBE_ACI_QUALIFIED_MODULE BIT(7) 1007 u8 ext_info; 1008 #define IXGBE_ACI_LINK_PHY_TEMP_ALARM BIT(0) 1009 #define IXGBE_ACI_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1010 /* Port Tx Suspended */ 1011 #define IXGBE_ACI_LINK_TX_S 2 1012 #define IXGBE_ACI_LINK_TX_M (0x03 << IXGBE_ACI_LINK_TX_S) 1013 #define IXGBE_ACI_LINK_TX_ACTIVE 0 1014 #define IXGBE_ACI_LINK_TX_DRAINED 1 1015 #define IXGBE_ACI_LINK_TX_FLUSHED 3 1016 u8 lb_status; 1017 #define IXGBE_ACI_LINK_LB_PHY_LCL BIT(0) 1018 #define IXGBE_ACI_LINK_LB_PHY_RMT BIT(1) 1019 #define IXGBE_ACI_LINK_LB_MAC_LCL BIT(2) 1020 #define IXGBE_ACI_LINK_LB_PHY_IDX_S 3 1021 #define IXGBE_ACI_LINK_LB_PHY_IDX_M (0x7 << IXGBE_ACI_LB_PHY_IDX_S) 1022 __le16 max_frame_size; 1023 u8 cfg; 1024 #define IXGBE_ACI_LINK_25G_KR_FEC_EN BIT(0) 1025 #define IXGBE_ACI_LINK_25G_RS_528_FEC_EN BIT(1) 1026 #define IXGBE_ACI_LINK_25G_RS_544_FEC_EN BIT(2) 1027 #define IXGBE_ACI_FEC_MASK MAKEMASK(0x7, 0) 1028 /* Pacing Config */ 1029 #define IXGBE_ACI_CFG_PACING_S 3 1030 #define IXGBE_ACI_CFG_PACING_M (0xF << IXGBE_ACI_CFG_PACING_S) 1031 #define IXGBE_ACI_CFG_PACING_TYPE_M BIT(7) 1032 #define IXGBE_ACI_CFG_PACING_TYPE_AVG 0 1033 #define IXGBE_ACI_CFG_PACING_TYPE_FIXED IXGBE_ACI_CFG_PACING_TYPE_M 1034 /* External Device Power Ability */ 1035 u8 power_desc; 1036 #define IXGBE_ACI_PWR_CLASS_M 0x3F 1037 #define IXGBE_ACI_LINK_PWR_BASET_LOW_HIGH 0 1038 #define IXGBE_ACI_LINK_PWR_BASET_HIGH 1 1039 #define IXGBE_ACI_LINK_PWR_QSFP_CLASS_1 0 1040 #define IXGBE_ACI_LINK_PWR_QSFP_CLASS_2 1 1041 #define IXGBE_ACI_LINK_PWR_QSFP_CLASS_3 2 1042 #define IXGBE_ACI_LINK_PWR_QSFP_CLASS_4 3 1043 __le16 link_speed; 1044 #define IXGBE_ACI_LINK_SPEED_M 0x7FF 1045 #define IXGBE_ACI_LINK_SPEED_10MB BIT(0) 1046 #define IXGBE_ACI_LINK_SPEED_100MB BIT(1) 1047 #define IXGBE_ACI_LINK_SPEED_1000MB BIT(2) 1048 #define IXGBE_ACI_LINK_SPEED_2500MB BIT(3) 1049 #define IXGBE_ACI_LINK_SPEED_5GB BIT(4) 1050 #define IXGBE_ACI_LINK_SPEED_10GB BIT(5) 1051 #define IXGBE_ACI_LINK_SPEED_20GB BIT(6) 1052 #define IXGBE_ACI_LINK_SPEED_25GB BIT(7) 1053 #define IXGBE_ACI_LINK_SPEED_40GB BIT(8) 1054 #define IXGBE_ACI_LINK_SPEED_50GB BIT(9) 1055 #define IXGBE_ACI_LINK_SPEED_100GB BIT(10) 1056 #define IXGBE_ACI_LINK_SPEED_200GB BIT(11) 1057 #define IXGBE_ACI_LINK_SPEED_UNKNOWN BIT(15) 1058 __le16 reserved3; /* Aligns next field to 8-byte boundary */ 1059 u8 eee_status; 1060 #define IXGBE_ACI_LINK_EEE_ENABLED BIT(2) 1061 #define IXGBE_ACI_LINK_EEE_ACTIVE BIT(3) 1062 u8 reserved4; 1063 __le64 phy_type_low; /* Use values from IXGBE_PHY_TYPE_LOW_* */ 1064 __le64 phy_type_high; /* Use values from IXGBE_PHY_TYPE_HIGH_* */ 1065 /* Get link status version 2 link partner data */ 1066 __le64 lp_phy_type_low; /* Use values from IXGBE_PHY_TYPE_LOW_* */ 1067 __le64 lp_phy_type_high; /* Use values from IXGBE_PHY_TYPE_HIGH_* */ 1068 u8 lp_fec_adv; 1069 #define IXGBE_ACI_LINK_LP_10G_KR_FEC_CAP BIT(0) 1070 #define IXGBE_ACI_LINK_LP_25G_KR_FEC_CAP BIT(1) 1071 #define IXGBE_ACI_LINK_LP_RS_528_FEC_CAP BIT(2) 1072 #define IXGBE_ACI_LINK_LP_50G_KR_272_FEC_CAP BIT(3) 1073 #define IXGBE_ACI_LINK_LP_100G_KR_272_FEC_CAP BIT(4) 1074 #define IXGBE_ACI_LINK_LP_200G_KR_272_FEC_CAP BIT(5) 1075 u8 lp_fec_req; 1076 #define IXGBE_ACI_LINK_LP_10G_KR_FEC_REQ BIT(0) 1077 #define IXGBE_ACI_LINK_LP_25G_KR_FEC_REQ BIT(1) 1078 #define IXGBE_ACI_LINK_LP_RS_528_FEC_REQ BIT(2) 1079 #define IXGBE_ACI_LINK_LP_KR_272_FEC_REQ BIT(3) 1080 u8 lp_flowcontrol; 1081 #define IXGBE_ACI_LINK_LP_PAUSE_ADV BIT(0) 1082 #define IXGBE_ACI_LINK_LP_ASM_DIR_ADV BIT(1) 1083 u8 reserved5[5]; 1084 }; 1085 #pragma pack() 1086 1087 IXGBE_CHECK_STRUCT_LEN(56, ixgbe_aci_cmd_get_link_status_data); 1088 1089 /* Set event mask command (direct 0x0613) */ 1090 struct ixgbe_aci_cmd_set_event_mask { 1091 u8 reserved[8]; 1092 __le16 event_mask; 1093 #define IXGBE_ACI_LINK_EVENT_UPDOWN BIT(1) 1094 #define IXGBE_ACI_LINK_EVENT_MEDIA_NA BIT(2) 1095 #define IXGBE_ACI_LINK_EVENT_LINK_FAULT BIT(3) 1096 #define IXGBE_ACI_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1097 #define IXGBE_ACI_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1098 #define IXGBE_ACI_LINK_EVENT_SIGNAL_DETECT BIT(6) 1099 #define IXGBE_ACI_LINK_EVENT_AN_COMPLETED BIT(7) 1100 #define IXGBE_ACI_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1101 #define IXGBE_ACI_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1102 #define IXGBE_ACI_LINK_EVENT_TOPO_CONFLICT BIT(10) 1103 #define IXGBE_ACI_LINK_EVENT_MEDIA_CONFLICT BIT(11) 1104 #define IXGBE_ACI_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12) 1105 u8 reserved1[6]; 1106 }; 1107 1108 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_event_mask); 1109 1110 struct ixgbe_aci_cmd_link_topo_params { 1111 u8 lport_num; 1112 u8 lport_num_valid; 1113 #define IXGBE_ACI_LINK_TOPO_PORT_NUM_VALID BIT(0) 1114 u8 node_type_ctx; 1115 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_S 0 1116 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_M (0xF << IXGBE_ACI_LINK_TOPO_NODE_TYPE_S) 1117 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_PHY 0 1118 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1119 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1120 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1121 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_LED 4 1122 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_THERMAL 5 1123 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_CAGE 6 1124 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_MEZZ 7 1125 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1126 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_GPS 11 1127 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_S 4 1128 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_M \ 1129 (0xF << IXGBE_ACI_LINK_TOPO_NODE_CTX_S) 1130 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_GLOBAL 0 1131 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_BOARD 1 1132 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_PORT 2 1133 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_NODE 3 1134 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_NODE_HANDLE 4 1135 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_DIRECT_BUS_ACCESS 5 1136 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_NODE_HANDLE_BUS_ADDRESS 6 1137 u8 index; 1138 }; 1139 1140 IXGBE_CHECK_STRUCT_LEN(4, ixgbe_aci_cmd_link_topo_params); 1141 1142 struct ixgbe_aci_cmd_link_topo_addr { 1143 struct ixgbe_aci_cmd_link_topo_params topo_params; 1144 __le16 handle; 1145 #define IXGBE_ACI_LINK_TOPO_HANDLE_S 0 1146 #define IXGBE_ACI_LINK_TOPO_HANDLE_M (0x3FF << IXGBE_ACI_LINK_TOPO_HANDLE_S) 1147 /* Used to decode the handle field */ 1148 #define IXGBE_ACI_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1149 #define IXGBE_ACI_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1150 #define IXGBE_ACI_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1151 #define IXGBE_ACI_LINK_TOPO_HANDLE_NODE_S 0 1152 /* In case of a Mezzanine type */ 1153 #define IXGBE_ACI_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1154 (0x3F << IXGBE_ACI_LINK_TOPO_HANDLE_NODE_S) 1155 #define IXGBE_ACI_LINK_TOPO_HANDLE_MEZZ_S 6 1156 #define IXGBE_ACI_LINK_TOPO_HANDLE_MEZZ_M \ 1157 (0x7 << IXGBE_ACI_LINK_TOPO_HANDLE_MEZZ_S) 1158 /* In case of a LOM type */ 1159 #define IXGBE_ACI_LINK_TOPO_HANDLE_LOM_NODE_M \ 1160 (0x1FF << IXGBE_ACI_LINK_TOPO_HANDLE_NODE_S) 1161 }; 1162 1163 IXGBE_CHECK_STRUCT_LEN(6, ixgbe_aci_cmd_link_topo_addr); 1164 1165 /* Get Link Topology Handle (direct, 0x06E0) */ 1166 struct ixgbe_aci_cmd_get_link_topo { 1167 struct ixgbe_aci_cmd_link_topo_addr addr; 1168 u8 node_part_num; 1169 #define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 1170 #define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_GEN_GPS 0x48 1171 #define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_E610_PTC 0x49 1172 u8 rsvd[9]; 1173 }; 1174 1175 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_link_topo); 1176 1177 /* Read/Write I2C (direct, 0x06E2/0x06E3) */ 1178 struct ixgbe_aci_cmd_i2c { 1179 struct ixgbe_aci_cmd_link_topo_addr topo_addr; 1180 __le16 i2c_addr; 1181 u8 i2c_params; 1182 #define IXGBE_ACI_I2C_DATA_SIZE_S 0 1183 #define IXGBE_ACI_I2C_DATA_SIZE_M (0xF << IXGBE_ACI_I2C_DATA_SIZE_S) 1184 #define IXGBE_ACI_I2C_ADDR_TYPE_M BIT(4) 1185 #define IXGBE_ACI_I2C_ADDR_TYPE_7BIT 0 1186 #define IXGBE_ACI_I2C_ADDR_TYPE_10BIT IXGBE_ACI_I2C_ADDR_TYPE_M 1187 #define IXGBE_ACI_I2C_DATA_OFFSET_S 5 1188 #define IXGBE_ACI_I2C_DATA_OFFSET_M (0x3 << IXGBE_ACI_I2C_DATA_OFFSET_S) 1189 #define IXGBE_ACI_I2C_USE_REPEATED_START BIT(7) 1190 u8 rsvd; 1191 __le16 i2c_bus_addr; 1192 #define IXGBE_ACI_I2C_ADDR_7BIT_MASK 0x7F 1193 #define IXGBE_ACI_I2C_ADDR_10BIT_MASK 0x3FF 1194 u8 i2c_data[4]; /* Used only by write command, reserved in read. */ 1195 }; 1196 1197 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_i2c); 1198 1199 /* Read I2C Response (direct, 0x06E2) */ 1200 struct ixgbe_aci_cmd_read_i2c_resp { 1201 u8 i2c_data[16]; 1202 }; 1203 1204 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_read_i2c_resp); 1205 1206 /* Read/Write MDIO (direct, 0x06E4/0x06E5) */ 1207 struct ixgbe_aci_cmd_mdio { 1208 struct ixgbe_aci_cmd_link_topo_addr topo_addr; 1209 u8 mdio_device_addr; 1210 #define IXGBE_ACI_MDIO_DEV_S 0 1211 #define IXGBE_ACI_MDIO_DEV_M (0x1F << IXGBE_ACI_MDIO_DEV_S) 1212 #define IXGBE_ACI_MDIO_CLAUSE_22 BIT(5) 1213 #define IXGBE_ACI_MDIO_CLAUSE_45 BIT(6) 1214 u8 mdio_bus_address; 1215 #define IXGBE_ACI_MDIO_BUS_ADDR_S 0 1216 #define IXGBE_ACI_MDIO_BUS_ADDR_M (0x1F << IXGBE_ACI_MDIO_BUS_ADDR_S) 1217 __le16 offset; 1218 __le16 data; /* Input in write cmd, output in read cmd. */ 1219 u8 rsvd1[4]; 1220 }; 1221 1222 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_mdio); 1223 1224 /* Set/Get GPIO By Function (direct, 0x06E6/0x06E7) */ 1225 struct ixgbe_aci_cmd_gpio_by_func { 1226 struct ixgbe_aci_cmd_link_topo_addr topo_addr; 1227 u8 io_func_num; 1228 #define IXGBE_ACI_GPIO_FUNC_S 0 1229 #define IXGBE_ACI_GPIO_FUNC_M (0x1F << IXGBE_ACI_GPIO_IO_FUNC_NUM_S) 1230 u8 io_value; /* Input in write cmd, output in read cmd. */ 1231 #define IXGBE_ACI_GPIO_ON BIT(0) 1232 #define IXGBE_ACI_GPIO_OFF 0 1233 u8 rsvd[8]; 1234 }; 1235 1236 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_gpio_by_func); 1237 1238 /* Set Port Identification LED (direct, 0x06E9) */ 1239 struct ixgbe_aci_cmd_set_port_id_led { 1240 u8 lport_num; 1241 u8 lport_num_valid; 1242 #define IXGBE_ACI_PORT_ID_PORT_NUM_VALID BIT(0) 1243 u8 ident_mode; 1244 #define IXGBE_ACI_PORT_IDENT_LED_BLINK BIT(0) 1245 #define IXGBE_ACI_PORT_IDENT_LED_ORIG 0 1246 u8 rsvd[13]; 1247 }; 1248 1249 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_port_id_led); 1250 1251 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */ 1252 struct ixgbe_aci_cmd_gpio { 1253 __le16 gpio_ctrl_handle; 1254 #define IXGBE_ACI_GPIO_HANDLE_S 0 1255 #define IXGBE_ACI_GPIO_HANDLE_M (0x3FF << IXGBE_ACI_GPIO_HANDLE_S) 1256 u8 gpio_num; 1257 u8 gpio_val; 1258 u8 rsvd[12]; 1259 }; 1260 1261 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_gpio); 1262 1263 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1264 struct ixgbe_aci_cmd_sff_eeprom { 1265 u8 lport_num; 1266 u8 lport_num_valid; 1267 #define IXGBE_ACI_SFF_PORT_NUM_VALID BIT(0) 1268 __le16 i2c_bus_addr; 1269 #define IXGBE_ACI_SFF_I2CBUS_7BIT_M 0x7F 1270 #define IXGBE_ACI_SFF_I2CBUS_10BIT_M 0x3FF 1271 #define IXGBE_ACI_SFF_I2CBUS_TYPE_M BIT(10) 1272 #define IXGBE_ACI_SFF_I2CBUS_TYPE_7BIT 0 1273 #define IXGBE_ACI_SFF_I2CBUS_TYPE_10BIT IXGBE_ACI_SFF_I2CBUS_TYPE_M 1274 #define IXGBE_ACI_SFF_PAGE_BANK_CTRL_S 11 1275 #define IXGBE_ACI_SFF_PAGE_BANK_CTRL_M (0x3 << IXGBE_ACI_SFF_PAGE_BANK_CTRL_S) 1276 #define IXGBE_ACI_SFF_NO_PAGE_BANK_UPDATE 0 1277 #define IXGBE_ACI_SFF_UPDATE_PAGE 1 1278 #define IXGBE_ACI_SFF_UPDATE_BANK 2 1279 #define IXGBE_ACI_SFF_UPDATE_PAGE_BANK 3 1280 #define IXGBE_ACI_SFF_IS_WRITE BIT(15) 1281 __le16 i2c_offset; 1282 u8 module_bank; 1283 u8 module_page; 1284 __le32 addr_high; 1285 __le32 addr_low; 1286 }; 1287 1288 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_sff_eeprom); 1289 1290 /* Program Topology Device NVM (direct, 0x06F2) */ 1291 struct ixgbe_aci_cmd_prog_topo_dev_nvm { 1292 struct ixgbe_aci_cmd_link_topo_params topo_params; 1293 u8 rsvd[12]; 1294 }; 1295 1296 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_prog_topo_dev_nvm); 1297 1298 /* Read Topology Device NVM (direct, 0x06F3) */ 1299 struct ixgbe_aci_cmd_read_topo_dev_nvm { 1300 struct ixgbe_aci_cmd_link_topo_params topo_params; 1301 __le32 start_address; 1302 #define IXGBE_ACI_READ_TOPO_DEV_NVM_DATA_READ_SIZE 8 1303 u8 data_read[IXGBE_ACI_READ_TOPO_DEV_NVM_DATA_READ_SIZE]; 1304 }; 1305 1306 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_read_topo_dev_nvm); 1307 1308 /* NVM Read command (indirect 0x0701) 1309 * NVM Erase commands (direct 0x0702) 1310 * NVM Write commands (indirect 0x0703) 1311 * NVM Write Activate commands (direct 0x0707) 1312 * NVM Shadow RAM Dump commands (direct 0x0707) 1313 */ 1314 struct ixgbe_aci_cmd_nvm { 1315 #define IXGBE_ACI_NVM_MAX_OFFSET 0xFFFFFF 1316 __le16 offset_low; 1317 u8 offset_high; /* For Write Activate offset_high is used as flags2 */ 1318 u8 cmd_flags; 1319 #define IXGBE_ACI_NVM_LAST_CMD BIT(0) 1320 #define IXGBE_ACI_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */ 1321 #define IXGBE_ACI_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */ 1322 #define IXGBE_ACI_NVM_PRESERVATION_M (3 << IXGBE_ACI_NVM_PRESERVATION_S) 1323 #define IXGBE_ACI_NVM_NO_PRESERVATION (0 << IXGBE_ACI_NVM_PRESERVATION_S) 1324 #define IXGBE_ACI_NVM_PRESERVE_ALL BIT(1) 1325 #define IXGBE_ACI_NVM_FACTORY_DEFAULT (2 << IXGBE_ACI_NVM_PRESERVATION_S) 1326 #define IXGBE_ACI_NVM_PRESERVE_SELECTED (3 << IXGBE_ACI_NVM_PRESERVATION_S) 1327 #define IXGBE_ACI_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 1328 #define IXGBE_ACI_NVM_ACTIV_SEL_OROM BIT(4) 1329 #define IXGBE_ACI_NVM_ACTIV_SEL_NETLIST BIT(5) 1330 #define IXGBE_ACI_NVM_SPECIAL_UPDATE BIT(6) 1331 #define IXGBE_ACI_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 1332 #define IXGBE_ACI_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3) 1333 #define IXGBE_ACI_NVM_FLASH_ONLY BIT(7) 1334 #define IXGBE_ACI_NVM_RESET_LVL_M MAKEMASK(0x3, 0) /* Write reply only */ 1335 #define IXGBE_ACI_NVM_POR_FLAG 0 1336 #define IXGBE_ACI_NVM_PERST_FLAG 1 1337 #define IXGBE_ACI_NVM_EMPR_FLAG 2 1338 #define IXGBE_ACI_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */ 1339 /* For Write Activate, several flags are sent as part of a separate 1340 * flags2 field using a separate byte. For simplicity of the software 1341 * interface, we pass the flags as a 16 bit value so these flags are 1342 * all offset by 8 bits 1343 */ 1344 #define IXGBE_ACI_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */ 1345 __le16 module_typeid; 1346 __le16 length; 1347 #define IXGBE_ACI_NVM_ERASE_LEN 0xFFFF 1348 __le32 addr_high; 1349 __le32 addr_low; 1350 }; 1351 1352 /* NVM Module_Type ID, needed offset and read_len for struct ixgbe_aci_cmd_nvm. */ 1353 #define IXGBE_ACI_NVM_SECTOR_UNIT 4096 /* In Bytes */ 1354 #define IXGBE_ACI_NVM_WORD_UNIT 2 /* In Bytes */ 1355 1356 #define IXGBE_ACI_NVM_START_POINT 0 1357 #define IXGBE_ACI_NVM_EMP_SR_PTR_OFFSET 0x90 1358 #define IXGBE_ACI_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */ 1359 #define IXGBE_ACI_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0) 1360 #define IXGBE_ACI_NVM_EMP_SR_PTR_TYPE_S 15 1361 #define IXGBE_ACI_NVM_EMP_SR_PTR_TYPE_M BIT(15) 1362 #define IXGBE_ACI_NVM_EMP_SR_PTR_TYPE_SECTOR 1 1363 1364 #define IXGBE_ACI_NVM_LLDP_CFG_PTR_OFFSET 0x46 1365 #define IXGBE_ACI_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */ 1366 #define IXGBE_ACI_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */ 1367 1368 #define IXGBE_ACI_NVM_LLDP_PRESERVED_MOD_ID 0x129 1369 #define IXGBE_ACI_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */ 1370 #define IXGBE_ACI_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0) 1371 #define IXGBE_ACI_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */ 1372 #define IXGBE_ACI_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */ 1373 1374 #define IXGBE_ACI_NVM_MINSREV_MOD_ID 0x130 1375 1376 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_nvm); 1377 1378 /* Used for reading and writing MinSRev using 0x0701 and 0x0703. Note that the 1379 * type field is excluded from the section when reading and writing from 1380 * a module using the module_typeid field with these AQ commands. 1381 */ 1382 struct ixgbe_aci_cmd_nvm_minsrev { 1383 __le16 length; 1384 __le16 validity; 1385 #define IXGBE_ACI_NVM_MINSREV_NVM_VALID BIT(0) 1386 #define IXGBE_ACI_NVM_MINSREV_OROM_VALID BIT(1) 1387 __le16 nvm_minsrev_l; 1388 __le16 nvm_minsrev_h; 1389 __le16 orom_minsrev_l; 1390 __le16 orom_minsrev_h; 1391 }; 1392 1393 IXGBE_CHECK_STRUCT_LEN(12, ixgbe_aci_cmd_nvm_minsrev); 1394 1395 /* Used for 0x0704 as well as for 0x0705 commands */ 1396 struct ixgbe_aci_cmd_nvm_cfg { 1397 u8 cmd_flags; 1398 #define IXGBE_ACI_ANVM_MULTIPLE_ELEMS BIT(0) 1399 #define IXGBE_ACI_ANVM_IMMEDIATE_FIELD BIT(1) 1400 #define IXGBE_ACI_ANVM_NEW_CFG BIT(2) 1401 u8 reserved; 1402 __le16 count; 1403 __le16 id; 1404 u8 reserved1[2]; 1405 __le32 addr_high; 1406 __le32 addr_low; 1407 }; 1408 1409 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_nvm_cfg); 1410 1411 struct ixgbe_aci_cmd_nvm_cfg_data { 1412 __le16 field_id; 1413 __le16 field_options; 1414 __le16 field_value; 1415 }; 1416 1417 IXGBE_CHECK_STRUCT_LEN(6, ixgbe_aci_cmd_nvm_cfg_data); 1418 1419 /* NVM Checksum Command (direct, 0x0706) */ 1420 struct ixgbe_aci_cmd_nvm_checksum { 1421 u8 flags; 1422 #define IXGBE_ACI_NVM_CHECKSUM_VERIFY BIT(0) 1423 #define IXGBE_ACI_NVM_CHECKSUM_RECALC BIT(1) 1424 u8 rsvd; 1425 __le16 checksum; /* Used only by response */ 1426 #define IXGBE_ACI_NVM_CHECKSUM_CORRECT 0xBABA 1427 u8 rsvd2[12]; 1428 }; 1429 1430 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_nvm_checksum); 1431 1432 /* Used for NVM Sanitization command - 0x070C */ 1433 struct ixgbe_aci_cmd_nvm_sanitization { 1434 u8 cmd_flags; 1435 #define IXGBE_ACI_SANITIZE_REQ_READ 0 1436 #define IXGBE_ACI_SANITIZE_REQ_OPERATE BIT(0) 1437 1438 #define IXGBE_ACI_SANITIZE_READ_SUBJECT_NVM_BITS 0 1439 #define IXGBE_ACI_SANITIZE_READ_SUBJECT_NVM_STATE BIT(1) 1440 #define IXGBE_ACI_SANITIZE_OPERATE_SUBJECT_CLEAR 0 1441 u8 values; 1442 #define IXGBE_ACI_SANITIZE_NVM_BITS_HOST_CLEAN_SUPPORT BIT(0) 1443 #define IXGBE_ACI_SANITIZE_NVM_BITS_BMC_CLEAN_SUPPORT BIT(2) 1444 #define IXGBE_ACI_SANITIZE_NVM_STATE_HOST_CLEAN_DONE BIT(0) 1445 #define IXGBE_ACI_SANITIZE_NVM_STATE_HOST_CLEAN_SUCCESS BIT(1) 1446 #define IXGBE_ACI_SANITIZE_NVM_STATE_BMC_CLEAN_DONE BIT(2) 1447 #define IXGBE_ACI_SANITIZE_NVM_STATE_BMC_CLEAN_SUCCESS BIT(3) 1448 #define IXGBE_ACI_SANITIZE_OPERATE_HOST_CLEAN_DONE BIT(0) 1449 #define IXGBE_ACI_SANITIZE_OPERATE_HOST_CLEAN_SUCCESS BIT(1) 1450 #define IXGBE_ACI_SANITIZE_OPERATE_BMC_CLEAN_DONE BIT(2) 1451 #define IXGBE_ACI_SANITIZE_OPERATE_BMC_CLEAN_SUCCESS BIT(3) 1452 u8 reserved[14]; 1453 }; 1454 1455 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_nvm_sanitization); 1456 1457 /* Write/Read Alternate - Direct (direct 0x0900/0x0902) */ 1458 struct ixgbe_aci_cmd_read_write_alt_direct { 1459 __le32 dword0_addr; 1460 __le32 dword0_value; 1461 __le32 dword1_addr; 1462 __le32 dword1_value; 1463 }; 1464 1465 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_read_write_alt_direct); 1466 1467 /* Write/Read Alternate - Indirect (indirect 0x0901/0x0903) */ 1468 struct ixgbe_aci_cmd_read_write_alt_indirect { 1469 __le32 base_dword_addr; 1470 __le32 num_dwords; 1471 __le32 addr_high; 1472 __le32 addr_low; 1473 }; 1474 1475 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_read_write_alt_indirect); 1476 1477 /* Done Alternate Write (direct 0x0904) */ 1478 struct ixgbe_aci_cmd_done_alt_write { 1479 u8 flags; 1480 #define IXGBE_ACI_CMD_UEFI_BIOS_MODE BIT(0) 1481 #define IXGBE_ACI_RESP_RESET_NEEDED BIT(1) 1482 u8 reserved[15]; 1483 }; 1484 1485 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_done_alt_write); 1486 1487 /* Clear Port Alternate Write (direct 0x0906) */ 1488 struct ixgbe_aci_cmd_clear_port_alt_write { 1489 u8 reserved[16]; 1490 }; 1491 1492 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_clear_port_alt_write); 1493 1494 /* Get CGU abilities command response data structure (indirect 0x0C61) */ 1495 struct ixgbe_aci_cmd_get_cgu_abilities { 1496 u8 num_inputs; 1497 u8 num_outputs; 1498 u8 pps_dpll_idx; 1499 u8 synce_dpll_idx; 1500 __le32 max_in_freq; 1501 __le32 max_in_phase_adj; 1502 __le32 max_out_freq; 1503 __le32 max_out_phase_adj; 1504 u8 cgu_part_num; 1505 u8 rsvd[3]; 1506 }; 1507 1508 IXGBE_CHECK_STRUCT_LEN(24, ixgbe_aci_cmd_get_cgu_abilities); 1509 1510 #define IXGBE_ACI_NODE_HANDLE_VALID BIT(10) 1511 #define IXGBE_ACI_NODE_HANDLE MAKEMASK(0x3FF, 0) 1512 #define IXGBE_ACI_DRIVING_CLK_NUM_SHIFT 10 1513 #define IXGBE_ACI_DRIVING_CLK_NUM MAKEMASK(0x3F, IXGBE_ACI_DRIVING_CLK_NUM_SHIFT) 1514 1515 /* Set CGU input config (direct 0x0C62) */ 1516 struct ixgbe_aci_cmd_set_cgu_input_config { 1517 u8 input_idx; 1518 u8 flags1; 1519 #define IXGBE_ACI_SET_CGU_IN_CFG_FLG1_UPDATE_FREQ BIT(6) 1520 #define IXGBE_ACI_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY BIT(7) 1521 u8 flags2; 1522 #define IXGBE_ACI_SET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5) 1523 #define IXGBE_ACI_SET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6) 1524 u8 rsvd; 1525 __le32 freq; 1526 __le32 phase_delay; 1527 u8 rsvd2[2]; 1528 __le16 node_handle; 1529 }; 1530 1531 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_cgu_input_config); 1532 1533 /* Get CGU input config response descriptor structure (direct 0x0C63) */ 1534 struct ixgbe_aci_cmd_get_cgu_input_config { 1535 u8 input_idx; 1536 u8 status; 1537 #define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_LOS BIT(0) 1538 #define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_SCM_FAIL BIT(1) 1539 #define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_CFM_FAIL BIT(2) 1540 #define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_GST_FAIL BIT(3) 1541 #define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_PFM_FAIL BIT(4) 1542 #define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_ESYNC_FAIL BIT(6) 1543 #define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_ESYNC_CAP BIT(7) 1544 u8 type; 1545 #define IXGBE_ACI_GET_CGU_IN_CFG_TYPE_READ_ONLY BIT(0) 1546 #define IXGBE_ACI_GET_CGU_IN_CFG_TYPE_GPS BIT(4) 1547 #define IXGBE_ACI_GET_CGU_IN_CFG_TYPE_EXTERNAL BIT(5) 1548 #define IXGBE_ACI_GET_CGU_IN_CFG_TYPE_PHY BIT(6) 1549 u8 flags1; 1550 #define IXGBE_ACI_GET_CGU_IN_CFG_FLG1_PHASE_DELAY_SUPP BIT(0) 1551 #define IXGBE_ACI_GET_CGU_IN_CFG_FLG1_1PPS_SUPP BIT(2) 1552 #define IXGBE_ACI_GET_CGU_IN_CFG_FLG1_10MHZ_SUPP BIT(3) 1553 #define IXGBE_ACI_GET_CGU_IN_CFG_FLG1_ANYFREQ BIT(7) 1554 __le32 freq; 1555 __le32 phase_delay; 1556 u8 flags2; 1557 #define IXGBE_ACI_GET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5) 1558 #define IXGBE_ACI_GET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6) 1559 u8 rsvd[1]; 1560 __le16 node_handle; 1561 }; 1562 1563 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_cgu_input_config); 1564 1565 /* Set CGU output config (direct 0x0C64) */ 1566 struct ixgbe_aci_cmd_set_cgu_output_config { 1567 u8 output_idx; 1568 u8 flags; 1569 #define IXGBE_ACI_SET_CGU_OUT_CFG_OUT_EN BIT(0) 1570 #define IXGBE_ACI_SET_CGU_OUT_CFG_ESYNC_EN BIT(1) 1571 #define IXGBE_ACI_SET_CGU_OUT_CFG_UPDATE_FREQ BIT(2) 1572 #define IXGBE_ACI_SET_CGU_OUT_CFG_UPDATE_PHASE BIT(3) 1573 #define IXGBE_ACI_SET_CGU_OUT_CFG_UPDATE_SRC_SEL BIT(4) 1574 u8 src_sel; 1575 #define IXGBE_ACI_SET_CGU_OUT_CFG_DPLL_SRC_SEL MAKEMASK(0x1F, 0) 1576 u8 rsvd; 1577 __le32 freq; 1578 __le32 phase_delay; 1579 u8 rsvd2[2]; 1580 __le16 node_handle; 1581 }; 1582 1583 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_cgu_output_config); 1584 1585 /* Get CGU output config (direct 0x0C65) */ 1586 struct ixgbe_aci_cmd_get_cgu_output_config { 1587 u8 output_idx; 1588 u8 flags; 1589 #define IXGBE_ACI_GET_CGU_OUT_CFG_OUT_EN BIT(0) 1590 #define IXGBE_ACI_GET_CGU_OUT_CFG_ESYNC_EN BIT(1) 1591 #define IXGBE_ACI_GET_CGU_OUT_CFG_ESYNC_ABILITY BIT(2) 1592 u8 src_sel; 1593 #define IXGBE_ACI_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT 0 1594 #define IXGBE_ACI_GET_CGU_OUT_CFG_DPLL_SRC_SEL \ 1595 MAKEMASK(0x1F, IXGBE_ACI_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT) 1596 #define IXGBE_ACI_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT 5 1597 #define IXGBE_ACI_GET_CGU_OUT_CFG_DPLL_MODE \ 1598 MAKEMASK(0x7, IXGBE_ACI_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT) 1599 u8 rsvd; 1600 __le32 freq; 1601 __le32 src_freq; 1602 u8 rsvd2[2]; 1603 __le16 node_handle; 1604 }; 1605 1606 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_cgu_output_config); 1607 1608 /* Get CGU DPLL status (direct 0x0C66) */ 1609 struct ixgbe_aci_cmd_get_cgu_dpll_status { 1610 u8 dpll_num; 1611 u8 ref_state; 1612 #define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_LOS BIT(0) 1613 #define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_SCM BIT(1) 1614 #define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_CFM BIT(2) 1615 #define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_GST BIT(3) 1616 #define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_PFM BIT(4) 1617 #define IXGBE_ACI_GET_CGU_DPLL_STATUS_FAST_LOCK_EN BIT(5) 1618 #define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_ESYNC BIT(6) 1619 __le16 dpll_state; 1620 #define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_LOCK BIT(0) 1621 #define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_HO BIT(1) 1622 #define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_HO_READY BIT(2) 1623 #define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_FLHIT BIT(5) 1624 #define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_PSLHIT BIT(7) 1625 #define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_CLK_REF_SHIFT 8 1626 #define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_CLK_REF_SEL \ 1627 MAKEMASK(0x1F, IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_CLK_REF_SHIFT) 1628 #define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_MODE_SHIFT 13 1629 #define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_MODE \ 1630 MAKEMASK(0x7, IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_MODE_SHIFT) 1631 __le32 phase_offset_h; 1632 __le32 phase_offset_l; 1633 u8 eec_mode; 1634 #define IXGBE_ACI_GET_CGU_DPLL_STATUS_EEC_MODE_1 0xA 1635 #define IXGBE_ACI_GET_CGU_DPLL_STATUS_EEC_MODE_2 0xB 1636 #define IXGBE_ACI_GET_CGU_DPLL_STATUS_EEC_MODE_UNKNOWN 0xF 1637 u8 rsvd[1]; 1638 __le16 node_handle; 1639 }; 1640 1641 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_cgu_dpll_status); 1642 1643 /* Set CGU DPLL config (direct 0x0C67) */ 1644 struct ixgbe_aci_cmd_set_cgu_dpll_config { 1645 u8 dpll_num; 1646 u8 ref_state; 1647 #define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_LOS BIT(0) 1648 #define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_SCM BIT(1) 1649 #define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_CFM BIT(2) 1650 #define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_GST BIT(3) 1651 #define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_PFM BIT(4) 1652 #define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_FLOCK_EN BIT(5) 1653 #define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_ESYNC BIT(6) 1654 u8 rsvd; 1655 u8 config; 1656 #define IXGBE_ACI_SET_CGU_DPLL_CONFIG_CLK_REF_SEL MAKEMASK(0x1F, 0) 1657 #define IXGBE_ACI_SET_CGU_DPLL_CONFIG_MODE MAKEMASK(0x7, 5) 1658 u8 rsvd2[8]; 1659 u8 eec_mode; 1660 u8 rsvd3[1]; 1661 __le16 node_handle; 1662 }; 1663 1664 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_cgu_dpll_config); 1665 1666 /* Set CGU reference priority (direct 0x0C68) */ 1667 struct ixgbe_aci_cmd_set_cgu_ref_prio { 1668 u8 dpll_num; 1669 u8 ref_idx; 1670 u8 ref_priority; 1671 u8 rsvd[11]; 1672 __le16 node_handle; 1673 }; 1674 1675 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_cgu_ref_prio); 1676 1677 /* Get CGU reference priority (direct 0x0C69) */ 1678 struct ixgbe_aci_cmd_get_cgu_ref_prio { 1679 u8 dpll_num; 1680 u8 ref_idx; 1681 u8 ref_priority; /* Valid only in response */ 1682 u8 rsvd[13]; 1683 }; 1684 1685 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_cgu_ref_prio); 1686 1687 /* Get CGU info (direct 0x0C6A) */ 1688 struct ixgbe_aci_cmd_get_cgu_info { 1689 __le32 cgu_id; 1690 __le32 cgu_cfg_ver; 1691 __le32 cgu_fw_ver; 1692 u8 node_part_num; 1693 u8 dev_rev; 1694 __le16 node_handle; 1695 }; 1696 1697 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_cgu_info); 1698 1699 struct ixgbe_aci_cmd_temp_tca_event { 1700 u8 event_desc; 1701 #define IXGBE_TEMP_TCA_EVENT_DESC_SUBJ_SHIFT 0 1702 #define IXGBE_TEMP_TCA_EVENT_DESC_SUBJ_NVM 0 1703 #define IXGBE_TEMP_TCA_EVENT_DESC_SUBJ_EVENT_STATE 1 1704 #define IXGBE_TEMP_TCA_EVENT_DESC_SUBJ_ALL 2 1705 1706 #define IXGBE_TEMP_TCA_EVENT_DESC_ALARM_SHIFT 2 1707 #define IXGBE_TEMP_TCA_EVENT_DESC_WARNING_CLEARED 0 1708 #define IXGBE_TEMP_TCA_EVENT_DESC_ALARM_CLEARED 1 1709 #define IXGBE_TEMP_TCA_EVENT_DESC_WARNING_RAISED 2 1710 #define IXGBE_TEMP_TCA_EVENT_DESC_ALARM_RAISED 3 1711 1712 u8 reserved; 1713 __le16 temperature; 1714 __le16 thermal_sensor_max_value; 1715 __le16 thermal_sensor_min_value; 1716 __le32 addr_high; 1717 __le32 addr_low; 1718 }; 1719 1720 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_temp_tca_event); 1721 1722 /* Debug Dump Internal Data (indirect 0xFF08) */ 1723 struct ixgbe_aci_cmd_debug_dump_internals { 1724 __le16 cluster_id; /* Expresses next cluster ID in response */ 1725 #define IXGBE_ACI_DBG_DUMP_CLUSTER_ID_LINK 0 1726 #define IXGBE_ACI_DBG_DUMP_CLUSTER_ID_FULL_CSR_SPACE 1 1727 __le16 table_id; /* Used only for non-memory clusters */ 1728 __le32 idx; /* In table entries for tables, in bytes for memory */ 1729 __le32 addr_high; 1730 __le32 addr_low; 1731 }; 1732 1733 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_debug_dump_internals); 1734 1735 /* Set Health Status (direct 0xFF20) */ 1736 struct ixgbe_aci_cmd_set_health_status_config { 1737 u8 event_source; 1738 #define IXGBE_ACI_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0) 1739 #define IXGBE_ACI_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1) 1740 #define IXGBE_ACI_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2) 1741 u8 reserved[15]; 1742 }; 1743 1744 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_health_status_config); 1745 1746 #define IXGBE_ACI_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT 0x101 1747 #define IXGBE_ACI_HEALTH_STATUS_ERR_MOD_TYPE 0x102 1748 #define IXGBE_ACI_HEALTH_STATUS_ERR_MOD_QUAL 0x103 1749 #define IXGBE_ACI_HEALTH_STATUS_ERR_MOD_COMM 0x104 1750 #define IXGBE_ACI_HEALTH_STATUS_ERR_MOD_CONFLICT 0x105 1751 #define IXGBE_ACI_HEALTH_STATUS_ERR_MOD_NOT_PRESENT 0x106 1752 #define IXGBE_ACI_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED 0x107 1753 #define IXGBE_ACI_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT 0x108 1754 #define IXGBE_ACI_HEALTH_STATUS_ERR_MOD_DIAGNOSTIC_FEATURE 0x109 1755 #define IXGBE_ACI_HEALTH_STATUS_ERR_INVALID_LINK_CFG 0x10B 1756 #define IXGBE_ACI_HEALTH_STATUS_ERR_PORT_ACCESS 0x10C 1757 #define IXGBE_ACI_HEALTH_STATUS_ERR_PORT_UNREACHABLE 0x10D 1758 #define IXGBE_ACI_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED 0x10F 1759 #define IXGBE_ACI_HEALTH_STATUS_ERR_PARALLEL_FAULT 0x110 1760 #define IXGBE_ACI_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED 0x111 1761 #define IXGBE_ACI_HEALTH_STATUS_ERR_NETLIST_TOPO 0x112 1762 #define IXGBE_ACI_HEALTH_STATUS_ERR_NETLIST 0x113 1763 #define IXGBE_ACI_HEALTH_STATUS_ERR_TOPO_CONFLICT 0x114 1764 #define IXGBE_ACI_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115 1765 #define IXGBE_ACI_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116 1766 #define IXGBE_ACI_HEALTH_STATUS_ERR_DNL_INIT 0x117 1767 #define IXGBE_ACI_HEALTH_STATUS_ERR_PHY_NVM_PROG 0x120 1768 #define IXGBE_ACI_HEALTH_STATUS_ERR_PHY_FW_LOAD 0x121 1769 #define IXGBE_ACI_HEALTH_STATUS_INFO_RECOVERY 0x500 1770 #define IXGBE_ACI_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501 1771 #define IXGBE_ACI_HEALTH_STATUS_ERR_NVM_AUTH 0x502 1772 #define IXGBE_ACI_HEALTH_STATUS_ERR_OROM_AUTH 0x503 1773 #define IXGBE_ACI_HEALTH_STATUS_ERR_DDP_AUTH 0x504 1774 #define IXGBE_ACI_HEALTH_STATUS_ERR_NVM_COMPAT 0x505 1775 #define IXGBE_ACI_HEALTH_STATUS_ERR_OROM_COMPAT 0x506 1776 #define IXGBE_ACI_HEALTH_STATUS_ERR_NVM_SEC_VIOLATION 0x507 1777 #define IXGBE_ACI_HEALTH_STATUS_ERR_OROM_SEC_VIOLATION 0x508 1778 #define IXGBE_ACI_HEALTH_STATUS_ERR_DCB_MIB 0x509 1779 #define IXGBE_ACI_HEALTH_STATUS_ERR_MNG_TIMEOUT 0x50A 1780 #define IXGBE_ACI_HEALTH_STATUS_ERR_BMC_RESET 0x50B 1781 #define IXGBE_ACI_HEALTH_STATUS_ERR_LAST_MNG_FAIL 0x50C 1782 #define IXGBE_ACI_HEALTH_STATUS_ERR_RESOURCE_ALLOC_FAIL 0x50D 1783 #define IXGBE_ACI_HEALTH_STATUS_ERR_FW_LOOP 0x1000 1784 #define IXGBE_ACI_HEALTH_STATUS_ERR_FW_PFR_FAIL 0x1001 1785 #define IXGBE_ACI_HEALTH_STATUS_ERR_LAST_FAIL_AQ 0x1002 1786 1787 /* Get Health Status codes (indirect 0xFF21) */ 1788 struct ixgbe_aci_cmd_get_supported_health_status_codes { 1789 __le16 health_code_count; 1790 u8 reserved[6]; 1791 __le32 addr_high; 1792 __le32 addr_low; 1793 }; 1794 1795 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_supported_health_status_codes); 1796 1797 /* Get Health Status (indirect 0xFF22) */ 1798 struct ixgbe_aci_cmd_get_health_status { 1799 __le16 health_status_count; 1800 u8 reserved[6]; 1801 __le32 addr_high; 1802 __le32 addr_low; 1803 }; 1804 1805 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_health_status); 1806 1807 /* Get Health Status event buffer entry, (0xFF22) 1808 * repeated per reported health status 1809 */ 1810 struct ixgbe_aci_cmd_health_status_elem { 1811 __le16 health_status_code; 1812 __le16 event_source; 1813 #define IXGBE_ACI_HEALTH_STATUS_PF (0x1) 1814 #define IXGBE_ACI_HEALTH_STATUS_PORT (0x2) 1815 #define IXGBE_ACI_HEALTH_STATUS_GLOBAL (0x3) 1816 __le32 internal_data1; 1817 #define IXGBE_ACI_HEALTH_STATUS_UNDEFINED_DATA (0xDEADBEEF) 1818 __le32 internal_data2; 1819 }; 1820 1821 IXGBE_CHECK_STRUCT_LEN(12, ixgbe_aci_cmd_health_status_elem); 1822 1823 /* Clear Health Status (direct 0xFF23) */ 1824 struct ixgbe_aci_cmd_clear_health_status { 1825 __le32 reserved[4]; 1826 }; 1827 1828 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_clear_health_status); 1829 1830 enum ixgbe_aci_fw_logging_mod { 1831 IXGBE_ACI_FW_LOG_ID_GENERAL = 0, 1832 IXGBE_ACI_FW_LOG_ID_CTRL = 1, 1833 IXGBE_ACI_FW_LOG_ID_LINK = 2, 1834 IXGBE_ACI_FW_LOG_ID_LINK_TOPO = 3, 1835 IXGBE_ACI_FW_LOG_ID_DNL = 4, 1836 IXGBE_ACI_FW_LOG_ID_I2C = 5, 1837 IXGBE_ACI_FW_LOG_ID_SDP = 6, 1838 IXGBE_ACI_FW_LOG_ID_MDIO = 7, 1839 IXGBE_ACI_FW_LOG_ID_ADMINQ = 8, 1840 IXGBE_ACI_FW_LOG_ID_HDMA = 9, 1841 IXGBE_ACI_FW_LOG_ID_LLDP = 10, 1842 IXGBE_ACI_FW_LOG_ID_DCBX = 11, 1843 IXGBE_ACI_FW_LOG_ID_DCB = 12, 1844 IXGBE_ACI_FW_LOG_ID_XLR = 13, 1845 IXGBE_ACI_FW_LOG_ID_NVM = 14, 1846 IXGBE_ACI_FW_LOG_ID_AUTH = 15, 1847 IXGBE_ACI_FW_LOG_ID_VPD = 16, 1848 IXGBE_ACI_FW_LOG_ID_IOSF = 17, 1849 IXGBE_ACI_FW_LOG_ID_PARSER = 18, 1850 IXGBE_ACI_FW_LOG_ID_SW = 19, 1851 IXGBE_ACI_FW_LOG_ID_SCHEDULER = 20, 1852 IXGBE_ACI_FW_LOG_ID_TXQ = 21, 1853 IXGBE_ACI_FW_LOG_ID_ACL = 22, 1854 IXGBE_ACI_FW_LOG_ID_POST = 23, 1855 IXGBE_ACI_FW_LOG_ID_WATCHDOG = 24, 1856 IXGBE_ACI_FW_LOG_ID_TASK_DISPATCH = 25, 1857 IXGBE_ACI_FW_LOG_ID_MNG = 26, 1858 IXGBE_ACI_FW_LOG_ID_SYNCE = 27, 1859 IXGBE_ACI_FW_LOG_ID_HEALTH = 28, 1860 IXGBE_ACI_FW_LOG_ID_TSDRV = 29, 1861 IXGBE_ACI_FW_LOG_ID_PFREG = 30, 1862 IXGBE_ACI_FW_LOG_ID_MDLVER = 31, 1863 IXGBE_ACI_FW_LOG_ID_MAX = 32, 1864 }; 1865 1866 /* Only a single log level should be set and all log levels under the set value 1867 * are enabled, e.g. if log level is set to IXGBE_FWLOG_LEVEL_VERBOSE, then all 1868 * other log levels are included (except IXGBE_FWLOG_LEVEL_NONE) 1869 */ 1870 enum ixgbe_fwlog_level { 1871 IXGBE_FWLOG_LEVEL_NONE = 0, 1872 IXGBE_FWLOG_LEVEL_ERROR = 1, 1873 IXGBE_FWLOG_LEVEL_WARNING = 2, 1874 IXGBE_FWLOG_LEVEL_NORMAL = 3, 1875 IXGBE_FWLOG_LEVEL_VERBOSE = 4, 1876 IXGBE_FWLOG_LEVEL_INVALID, /* all values >= this entry are invalid */ 1877 }; 1878 1879 struct ixgbe_fwlog_module_entry { 1880 /* module ID for the corresponding firmware logging event */ 1881 u16 module_id; 1882 /* verbosity level for the module_id */ 1883 u8 log_level; 1884 }; 1885 1886 struct ixgbe_fwlog_cfg { 1887 /* list of modules for configuring log level */ 1888 struct ixgbe_fwlog_module_entry module_entries[IXGBE_ACI_FW_LOG_ID_MAX]; 1889 #define IXGBE_FWLOG_OPTION_ARQ_ENA BIT(0) 1890 #define IXGBE_FWLOG_OPTION_UART_ENA BIT(1) 1891 /* set before calling ixgbe_fwlog_init() so the PF registers for firmware 1892 * logging on initialization 1893 */ 1894 #define IXGBE_FWLOG_OPTION_REGISTER_ON_INIT BIT(2) 1895 /* set in the ixgbe_fwlog_get() response if the PF is registered for FW 1896 * logging events over ARQ 1897 */ 1898 #define IXGBE_FWLOG_OPTION_IS_REGISTERED BIT(3) 1899 /* options used to configure firmware logging */ 1900 u16 options; 1901 /* minimum number of log events sent per Admin Receive Queue event */ 1902 u8 log_resolution; 1903 }; 1904 1905 struct ixgbe_fwlog_data { 1906 u16 data_size; 1907 u8 *data; 1908 }; 1909 1910 struct ixgbe_fwlog_ring { 1911 struct ixgbe_fwlog_data *rings; 1912 u16 size; 1913 u16 head; 1914 u16 tail; 1915 }; 1916 1917 #define IXGBE_FWLOG_RING_SIZE_DFLT 256 1918 #define IXGBE_FWLOG_RING_SIZE_MAX 512 1919 1920 /* Set FW Logging configuration (indirect 0xFF30) 1921 * Register for FW Logging (indirect 0xFF31) 1922 * Query FW Logging (indirect 0xFF32) 1923 * FW Log Event (indirect 0xFF33) 1924 * Get FW Log (indirect 0xFF34) 1925 * Clear FW Log (indirect 0xFF35) 1926 */ 1927 struct ixgbe_aci_cmd_fw_log { 1928 u8 cmd_flags; 1929 #define IXGBE_ACI_FW_LOG_CONF_UART_EN BIT(0) 1930 #define IXGBE_ACI_FW_LOG_CONF_AQ_EN BIT(1) 1931 #define IXGBE_ACI_FW_LOG_QUERY_REGISTERED BIT(2) 1932 #define IXGBE_ACI_FW_LOG_CONF_SET_VALID BIT(3) 1933 #define IXGBE_ACI_FW_LOG_AQ_REGISTER BIT(0) 1934 #define IXGBE_ACI_FW_LOG_AQ_QUERY BIT(2) 1935 #define IXGBE_ACI_FW_LOG_PERSISTENT BIT(0) 1936 u8 rsp_flag; 1937 #define IXGBE_ACI_FW_LOG_MORE_DATA BIT(1) 1938 __le16 fw_rt_msb; 1939 union { 1940 struct { 1941 __le32 fw_rt_lsb; 1942 } sync; 1943 struct { 1944 __le16 log_resolution; 1945 #define IXGBE_ACI_FW_LOG_MIN_RESOLUTION (1) 1946 #define IXGBE_ACI_FW_LOG_MAX_RESOLUTION (128) 1947 __le16 mdl_cnt; 1948 } cfg; 1949 } ops; 1950 __le32 addr_high; 1951 __le32 addr_low; 1952 }; 1953 1954 IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_fw_log); 1955 1956 /* Response Buffer for: 1957 * Set Firmware Logging Configuration (0xFF30) 1958 * Query FW Logging (0xFF32) 1959 */ 1960 struct ixgbe_aci_cmd_fw_log_cfg_resp { 1961 __le16 module_identifier; 1962 u8 log_level; 1963 u8 rsvd0; 1964 }; 1965 1966 IXGBE_CHECK_STRUCT_LEN(4, ixgbe_aci_cmd_fw_log_cfg_resp); 1967 1968 /** 1969 * struct ixgbe_aq_desc - Admin Command (AC) descriptor 1970 * @flags: IXGBE_ACI_FLAG_* flags 1971 * @opcode: Admin command opcode 1972 * @datalen: length in bytes of indirect/external data buffer 1973 * @retval: return value from firmware 1974 * @cookie_high: opaque data high-half 1975 * @cookie_low: opaque data low-half 1976 * @params: command-specific parameters 1977 * 1978 * Descriptor format for commands the driver posts via the Admin Command Interface 1979 * (ACI). The firmware writes back onto the command descriptor and returns 1980 * the result of the command. Asynchronous events that are not an immediate 1981 * result of the command are written to the Admin Command Interface (ACI) using 1982 * the same descriptor format. Descriptors are in little-endian notation with 1983 * 32-bit words. 1984 */ 1985 struct ixgbe_aci_desc { 1986 __le16 flags; 1987 __le16 opcode; 1988 __le16 datalen; 1989 __le16 retval; 1990 __le32 cookie_high; 1991 __le32 cookie_low; 1992 union { 1993 u8 raw[16]; 1994 struct ixgbe_aci_cmd_generic generic; 1995 struct ixgbe_aci_cmd_get_ver get_ver; 1996 struct ixgbe_aci_cmd_driver_ver driver_ver; 1997 struct ixgbe_aci_cmd_get_exp_err exp_err; 1998 struct ixgbe_aci_cmd_req_res res_owner; 1999 struct ixgbe_aci_cmd_list_caps get_cap; 2000 struct ixgbe_aci_cmd_disable_rxen disable_rxen; 2001 struct ixgbe_aci_cmd_get_fw_event get_fw_event; 2002 struct ixgbe_aci_cmd_get_phy_caps get_phy; 2003 struct ixgbe_aci_cmd_set_phy_cfg set_phy; 2004 struct ixgbe_aci_cmd_restart_an restart_an; 2005 struct ixgbe_aci_cmd_get_link_status get_link_status; 2006 struct ixgbe_aci_cmd_set_event_mask set_event_mask; 2007 struct ixgbe_aci_cmd_get_link_topo get_link_topo; 2008 struct ixgbe_aci_cmd_i2c read_write_i2c; 2009 struct ixgbe_aci_cmd_read_i2c_resp read_i2c_resp; 2010 struct ixgbe_aci_cmd_mdio read_write_mdio; 2011 struct ixgbe_aci_cmd_mdio read_mdio; 2012 struct ixgbe_aci_cmd_mdio write_mdio; 2013 struct ixgbe_aci_cmd_set_port_id_led set_port_id_led; 2014 struct ixgbe_aci_cmd_gpio_by_func read_write_gpio_by_func; 2015 struct ixgbe_aci_cmd_gpio read_write_gpio; 2016 struct ixgbe_aci_cmd_sff_eeprom read_write_sff_param; 2017 struct ixgbe_aci_cmd_prog_topo_dev_nvm prog_topo_dev_nvm; 2018 struct ixgbe_aci_cmd_read_topo_dev_nvm read_topo_dev_nvm; 2019 struct ixgbe_aci_cmd_nvm nvm; 2020 struct ixgbe_aci_cmd_nvm_cfg nvm_cfg; 2021 struct ixgbe_aci_cmd_nvm_checksum nvm_checksum; 2022 struct ixgbe_aci_cmd_read_write_alt_direct read_write_alt_direct; 2023 struct ixgbe_aci_cmd_read_write_alt_indirect read_write_alt_indirect; 2024 struct ixgbe_aci_cmd_done_alt_write done_alt_write; 2025 struct ixgbe_aci_cmd_clear_port_alt_write clear_port_alt_write; 2026 struct ixgbe_aci_cmd_debug_dump_internals debug_dump; 2027 struct ixgbe_aci_cmd_set_health_status_config 2028 set_health_status_config; 2029 struct ixgbe_aci_cmd_get_supported_health_status_codes 2030 get_supported_health_status_codes; 2031 struct ixgbe_aci_cmd_get_health_status get_health_status; 2032 struct ixgbe_aci_cmd_clear_health_status clear_health_status; 2033 struct ixgbe_aci_cmd_fw_log fw_log; 2034 struct ixgbe_aci_cmd_nvm_sanitization nvm_sanitization; 2035 } params; 2036 }; 2037 2038 /* E610-specific adapter context structures */ 2039 2040 struct ixgbe_link_status { 2041 /* Refer to ixgbe_aci_phy_type for bits definition */ 2042 u64 phy_type_low; 2043 u64 phy_type_high; 2044 u8 topo_media_conflict; 2045 u16 max_frame_size; 2046 u16 link_speed; 2047 u16 req_speeds; 2048 u8 link_cfg_err; 2049 u8 lse_ena; /* Link Status Event notification */ 2050 u8 link_info; 2051 u8 an_info; 2052 u8 ext_info; 2053 u8 fec_info; 2054 u8 pacing; 2055 /* Refer to #define from module_type[IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE] of 2056 * ixgbe_aci_get_phy_caps structure 2057 */ 2058 u8 module_type[IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE]; 2059 u8 eee_status; 2060 }; 2061 2062 /* Common HW capabilities for SW use */ 2063 struct ixgbe_hw_common_caps { 2064 /* Write CSR protection */ 2065 u64 wr_csr_prot; 2066 u32 switching_mode; 2067 /* switching mode supported - EVB switching (including cloud) */ 2068 #define IXGBE_NVM_IMAGE_TYPE_EVB 0x0 2069 2070 /* Manageability mode & supported protocols over MCTP */ 2071 u32 mgmt_mode; 2072 #define IXGBE_MGMT_MODE_PASS_THRU_MODE_M 0xF 2073 #define IXGBE_MGMT_MODE_CTL_INTERFACE_M 0xF0 2074 #define IXGBE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00 2075 2076 u32 mgmt_protocols_mctp; 2077 #define IXGBE_MGMT_MODE_PROTO_RSVD BIT(0) 2078 #define IXGBE_MGMT_MODE_PROTO_PLDM BIT(1) 2079 #define IXGBE_MGMT_MODE_PROTO_OEM BIT(2) 2080 #define IXGBE_MGMT_MODE_PROTO_NC_SI BIT(3) 2081 2082 u32 os2bmc; 2083 u32 valid_functions; 2084 /* DCB capabilities */ 2085 u32 active_tc_bitmap; 2086 u32 maxtc; 2087 2088 /* RSS related capabilities */ 2089 u32 rss_table_size; /* 512 for PFs and 64 for VFs */ 2090 u32 rss_table_entry_width; /* RSS Entry width in bits */ 2091 2092 /* Tx/Rx queues */ 2093 u32 num_rxq; /* Number/Total Rx queues */ 2094 u32 rxq_first_id; /* First queue ID for Rx queues */ 2095 u32 num_txq; /* Number/Total Tx queues */ 2096 u32 txq_first_id; /* First queue ID for Tx queues */ 2097 2098 /* MSI-X vectors */ 2099 u32 num_msix_vectors; 2100 u32 msix_vector_first_id; 2101 2102 /* Max MTU for function or device */ 2103 u32 max_mtu; 2104 2105 /* WOL related */ 2106 u32 num_wol_proxy_fltr; 2107 u32 wol_proxy_vsi_seid; 2108 2109 /* LED/SDP pin count */ 2110 u32 led_pin_num; 2111 u32 sdp_pin_num; 2112 2113 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */ 2114 #define IXGBE_MAX_SUPPORTED_GPIO_LED 12 2115 #define IXGBE_MAX_SUPPORTED_GPIO_SDP 8 2116 u8 led[IXGBE_MAX_SUPPORTED_GPIO_LED]; 2117 u8 sdp[IXGBE_MAX_SUPPORTED_GPIO_SDP]; 2118 /* SR-IOV virtualization */ 2119 u8 sr_iov_1_1; /* SR-IOV enabled */ 2120 /* VMDQ */ 2121 u8 vmdq; /* VMDQ supported */ 2122 2123 /* EVB capabilities */ 2124 u8 evb_802_1_qbg; /* Edge Virtual Bridging */ 2125 u8 evb_802_1_qbh; /* Bridge Port Extension */ 2126 2127 u8 dcb; 2128 u8 iscsi; 2129 u8 mgmt_cem; 2130 2131 /* WoL and APM support */ 2132 #define IXGBE_WOL_SUPPORT_M BIT(0) 2133 #define IXGBE_ACPI_PROG_MTHD_M BIT(1) 2134 #define IXGBE_PROXY_SUPPORT_M BIT(2) 2135 u8 apm_wol_support; 2136 u8 acpi_prog_mthd; 2137 u8 proxy_support; 2138 u8 eee_support; 2139 #define IXGBE_EEE_SUPPORT_100BASE_TX BIT(0) 2140 #define IXGBE_EEE_SUPPORT_1000BASE_T BIT(1) 2141 #define IXGBE_EEE_SUPPORT_10GBASE_T BIT(2) 2142 #define IXGBE_EEE_SUPPORT_5GBASE_T BIT(3) 2143 #define IXGBE_EEE_SUPPORT_2_5GBASE_T BIT(4) 2144 bool sec_rev_disabled; 2145 bool update_disabled; 2146 bool nvm_unified_update; 2147 bool netlist_auth; 2148 #define IXGBE_NVM_MGMT_SEC_REV_DISABLED BIT(0) 2149 #define IXGBE_NVM_MGMT_UPDATE_DISABLED BIT(1) 2150 #define IXGBE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) 2151 #define IXGBE_NVM_MGMT_NETLIST_AUTH_SUPPORT BIT(5) 2152 bool no_drop_policy_support; 2153 /* PCIe reset avoidance */ 2154 bool pcie_reset_avoidance; /* false: not supported, true: supported */ 2155 /* Post update reset restriction */ 2156 bool reset_restrict_support; /* false: not supported, true: supported */ 2157 2158 /* External topology device images within the NVM */ 2159 #define IXGBE_EXT_TOPO_DEV_IMG_COUNT 4 2160 u32 ext_topo_dev_img_ver_high[IXGBE_EXT_TOPO_DEV_IMG_COUNT]; 2161 u32 ext_topo_dev_img_ver_low[IXGBE_EXT_TOPO_DEV_IMG_COUNT]; 2162 u8 ext_topo_dev_img_part_num[IXGBE_EXT_TOPO_DEV_IMG_COUNT]; 2163 #define IXGBE_EXT_TOPO_DEV_IMG_PART_NUM_S 8 2164 #define IXGBE_EXT_TOPO_DEV_IMG_PART_NUM_M \ 2165 MAKEMASK(0xFF, IXGBE_EXT_TOPO_DEV_IMG_PART_NUM_S) 2166 bool ext_topo_dev_img_load_en[IXGBE_EXT_TOPO_DEV_IMG_COUNT]; 2167 #define IXGBE_EXT_TOPO_DEV_IMG_LOAD_EN BIT(0) 2168 bool ext_topo_dev_img_prog_en[IXGBE_EXT_TOPO_DEV_IMG_COUNT]; 2169 #define IXGBE_EXT_TOPO_DEV_IMG_PROG_EN BIT(1) 2170 /* Support for OROM update in Recovery Mode. */ 2171 bool orom_recovery_update; 2172 bool next_cluster_id_support; 2173 }; 2174 2175 #pragma pack(1) 2176 struct ixgbe_orom_civd_info { 2177 u8 signature[4]; /* Must match ASCII '$CIV' characters */ 2178 u8 checksum; /* Simple modulo 256 sum of all structure bytes must equal 0 */ 2179 __le32 combo_ver; /* Combo Image Version number */ 2180 u8 combo_name_len; /* Length of the unicode combo image version string, max of 32 */ 2181 __le16 combo_name[32]; /* Unicode string representing the Combo Image version */ 2182 }; 2183 #pragma pack() 2184 2185 /* Function specific capabilities */ 2186 struct ixgbe_hw_func_caps { 2187 struct ixgbe_hw_common_caps common_cap; 2188 u32 num_allocd_vfs; /* Number of allocated VFs */ 2189 u32 vf_base_id; /* Logical ID of the first VF */ 2190 u32 guar_num_vsi; 2191 bool no_drop_policy_ena; 2192 }; 2193 2194 /* Device wide capabilities */ 2195 struct ixgbe_hw_dev_caps { 2196 struct ixgbe_hw_common_caps common_cap; 2197 u32 num_vfs_exposed; /* Total number of VFs exposed */ 2198 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 2199 u32 num_flow_director_fltr; /* Number of FD filters available */ 2200 u32 num_funcs; 2201 }; 2202 2203 /* ACI event information */ 2204 struct ixgbe_aci_event { 2205 struct ixgbe_aci_desc desc; 2206 u16 msg_len; 2207 u16 buf_len; 2208 u8 *msg_buf; 2209 }; 2210 2211 struct ixgbe_aci_info { 2212 enum ixgbe_aci_err last_status; /* last status of sent admin command */ 2213 struct ixgbe_lock lock; /* admin command interface lock */ 2214 }; 2215 2216 /* Minimum Security Revision information */ 2217 struct ixgbe_minsrev_info { 2218 u32 nvm; 2219 u32 orom; 2220 u8 nvm_valid : 1; 2221 u8 orom_valid : 1; 2222 }; 2223 2224 /* Enumeration of which flash bank is desired to read from, either the active 2225 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from 2226 * code which just wants to read the active or inactive flash bank. 2227 */ 2228 enum ixgbe_bank_select { 2229 IXGBE_ACTIVE_FLASH_BANK, 2230 IXGBE_INACTIVE_FLASH_BANK, 2231 }; 2232 2233 /* Option ROM version information */ 2234 struct ixgbe_orom_info { 2235 u8 major; /* Major version of OROM */ 2236 u8 patch; /* Patch version of OROM */ 2237 u16 build; /* Build version of OROM */ 2238 u32 srev; /* Security revision */ 2239 }; 2240 2241 /* NVM version information */ 2242 struct ixgbe_nvm_info { 2243 u32 eetrack; 2244 u32 srev; 2245 u8 major; 2246 u8 minor; 2247 }; 2248 2249 /* netlist version information */ 2250 struct ixgbe_netlist_info { 2251 u32 major; /* major high/low */ 2252 u32 minor; /* minor high/low */ 2253 u32 type; /* type high/low */ 2254 u32 rev; /* revision high/low */ 2255 u32 hash; /* SHA-1 hash word */ 2256 u16 cust_ver; /* customer version */ 2257 }; 2258 2259 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules 2260 * of the flash image. 2261 */ 2262 enum ixgbe_flash_bank { 2263 IXGBE_INVALID_FLASH_BANK, 2264 IXGBE_1ST_FLASH_BANK, 2265 IXGBE_2ND_FLASH_BANK, 2266 }; 2267 2268 /* information for accessing NVM, OROM, and Netlist flash banks */ 2269 struct ixgbe_bank_info { 2270 u32 nvm_ptr; /* Pointer to 1st NVM bank */ 2271 u32 nvm_size; /* Size of NVM bank */ 2272 u32 orom_ptr; /* Pointer to 1st OROM bank */ 2273 u32 orom_size; /* Size of OROM bank */ 2274 u32 netlist_ptr; /* Pointer to 1st Netlist bank */ 2275 u32 netlist_size; /* Size of Netlist bank */ 2276 enum ixgbe_flash_bank nvm_bank; /* Active NVM bank */ 2277 enum ixgbe_flash_bank orom_bank; /* Active OROM bank */ 2278 enum ixgbe_flash_bank netlist_bank; /* Active Netlist bank */ 2279 }; 2280 2281 /* Flash Chip Information */ 2282 struct ixgbe_flash_info { 2283 struct ixgbe_orom_info orom; /* Option ROM version info */ 2284 struct ixgbe_nvm_info nvm; /* NVM version information */ 2285 struct ixgbe_netlist_info netlist; /* Netlist version info */ 2286 struct ixgbe_bank_info banks; /* Flash Bank information */ 2287 u16 sr_words; /* Shadow RAM size in words */ 2288 u32 flash_size; /* Size of available flash in bytes */ 2289 u8 blank_nvm_mode; /* is NVM empty (no FW present) */ 2290 }; 2291 2292 #define IXGBE_NVM_CMD_READ 0x0000000B 2293 #define IXGBE_NVM_CMD_WRITE 0x0000000C 2294 2295 /* NVM Access command */ 2296 struct ixgbe_nvm_access_cmd { 2297 u32 command; /* NVM command: READ or WRITE */ 2298 u32 offset; /* Offset to read/write, in bytes */ 2299 u32 data_size; /* Size of data field, in bytes */ 2300 }; 2301 2302 /* NVM Access data */ 2303 struct ixgbe_nvm_access_data { 2304 u32 regval; /* Storage for register value */ 2305 }; 2306 2307 #endif /* _IXGBE_TYPE_E610_H_ */ 2308