1 /*
2 * Copyright 2016-2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "dc.h"
28 #include "mod_freesync.h"
29 #include "core_types.h"
30
31 #define MOD_FREESYNC_MAX_CONCURRENT_STREAMS 32
32
33 #define MIN_REFRESH_RANGE 10
34 /* Refresh rate ramp at a fixed rate of 65 Hz/second */
35 #define STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME ((1000 / 60) * 65)
36 /* Number of elements in the render times cache array */
37 #define RENDER_TIMES_MAX_COUNT 10
38 /* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */
39 #define BTR_MAX_MARGIN 2500
40 /* Threshold to change BTR multiplier (to avoid frequent changes) */
41 #define BTR_DRIFT_MARGIN 2000
42 /* Threshold to exit fixed refresh rate */
43 #define FIXED_REFRESH_EXIT_MARGIN_IN_HZ 1
44 /* Number of consecutive frames to check before entering/exiting fixed refresh */
45 #define FIXED_REFRESH_ENTER_FRAME_COUNT 5
46 #define FIXED_REFRESH_EXIT_FRAME_COUNT 10
47 /* Flip interval workaround constants */
48 #define VSYNCS_BETWEEN_FLIP_THRESHOLD 2
49 #define FREESYNC_CONSEC_FLIP_AFTER_VSYNC 5
50 #define FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US 500
51 #define MICRO_HZ_TO_HZ(x) (x / 1000000)
52
53 struct core_freesync {
54 struct mod_freesync public;
55 struct dc *dc;
56 };
57
58 #define MOD_FREESYNC_TO_CORE(mod_freesync)\
59 container_of(mod_freesync, struct core_freesync, public)
60
mod_freesync_create(struct dc * dc)61 struct mod_freesync *mod_freesync_create(struct dc *dc)
62 {
63 struct core_freesync *core_freesync =
64 kzalloc(sizeof(struct core_freesync), GFP_KERNEL);
65
66 if (core_freesync == NULL)
67 goto fail_alloc_context;
68
69 if (dc == NULL)
70 goto fail_construct;
71
72 core_freesync->dc = dc;
73 return &core_freesync->public;
74
75 fail_construct:
76 kfree(core_freesync);
77
78 fail_alloc_context:
79 return NULL;
80 }
81
mod_freesync_destroy(struct mod_freesync * mod_freesync)82 void mod_freesync_destroy(struct mod_freesync *mod_freesync)
83 {
84 struct core_freesync *core_freesync = NULL;
85
86 if (mod_freesync == NULL)
87 return;
88 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
89 kfree(core_freesync);
90 }
91
92 #if 0 /* Unused currently */
93 static unsigned int calc_refresh_in_uhz_from_duration(
94 unsigned int duration_in_ns)
95 {
96 unsigned int refresh_in_uhz =
97 ((unsigned int)(div64_u64((1000000000ULL * 1000000),
98 duration_in_ns)));
99 return refresh_in_uhz;
100 }
101 #endif
102
calc_duration_in_us_from_refresh_in_uhz(unsigned int refresh_in_uhz)103 static unsigned int calc_duration_in_us_from_refresh_in_uhz(
104 unsigned int refresh_in_uhz)
105 {
106 unsigned int duration_in_us =
107 ((unsigned int)(div64_u64((1000000000ULL * 1000),
108 refresh_in_uhz)));
109 return duration_in_us;
110 }
111
calc_duration_in_us_from_v_total(const struct dc_stream_state * stream,const struct mod_vrr_params * in_vrr,unsigned int v_total)112 static unsigned int calc_duration_in_us_from_v_total(
113 const struct dc_stream_state *stream,
114 const struct mod_vrr_params *in_vrr,
115 unsigned int v_total)
116 {
117 unsigned int duration_in_us =
118 (unsigned int)(div64_u64(((unsigned long long)(v_total)
119 * 10000) * stream->timing.h_total,
120 stream->timing.pix_clk_100hz));
121
122 return duration_in_us;
123 }
124
calc_max_hardware_v_total(const struct dc_stream_state * stream)125 static unsigned int calc_max_hardware_v_total(const struct dc_stream_state *stream)
126 {
127 unsigned int max_hw_v_total = stream->ctx->dc->caps.max_v_total;
128
129 if (stream->ctx->dc->caps.vtotal_limited_by_fp2) {
130 max_hw_v_total -= stream->timing.v_front_porch + 1;
131 }
132
133 return max_hw_v_total;
134 }
135
mod_freesync_calc_v_total_from_refresh(const struct dc_stream_state * stream,unsigned int refresh_in_uhz)136 unsigned int mod_freesync_calc_v_total_from_refresh(
137 const struct dc_stream_state *stream,
138 unsigned int refresh_in_uhz)
139 {
140 unsigned int v_total;
141 unsigned int frame_duration_in_ns;
142
143 if (refresh_in_uhz == 0)
144 return stream->timing.v_total;
145
146 frame_duration_in_ns =
147 ((unsigned int)(div64_u64((1000000000ULL * 1000000),
148 refresh_in_uhz)));
149
150 if (MICRO_HZ_TO_HZ(refresh_in_uhz) <= stream->timing.min_refresh_in_uhz) {
151 /* When the target refresh rate is the minimum panel refresh rate,
152 * round down the vtotal value to avoid stretching vblank over
153 * panel's vtotal boundary.
154 */
155 v_total = div64_u64(div64_u64(((unsigned long long)(
156 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),
157 stream->timing.h_total), 1000000);
158 } else {
159 v_total = div64_u64(div64_u64(((unsigned long long)(
160 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),
161 stream->timing.h_total) + 500000, 1000000);
162 }
163
164 /* v_total cannot be less than nominal */
165 if (v_total < stream->timing.v_total) {
166 ASSERT(v_total < stream->timing.v_total);
167 v_total = stream->timing.v_total;
168 }
169
170 return v_total;
171 }
172
calc_v_total_from_duration(const struct dc_stream_state * stream,const struct mod_vrr_params * vrr,unsigned int duration_in_us)173 static unsigned int calc_v_total_from_duration(
174 const struct dc_stream_state *stream,
175 const struct mod_vrr_params *vrr,
176 unsigned int duration_in_us)
177 {
178 unsigned int v_total = 0;
179
180 if (duration_in_us < vrr->min_duration_in_us)
181 duration_in_us = vrr->min_duration_in_us;
182
183 if (duration_in_us > vrr->max_duration_in_us)
184 duration_in_us = vrr->max_duration_in_us;
185
186 if (dc_is_hdmi_signal(stream->signal)) { // change for HDMI to comply with spec
187 uint32_t h_total_up_scaled;
188
189 h_total_up_scaled = stream->timing.h_total * 10000;
190 v_total = div_u64((unsigned long long)duration_in_us
191 * stream->timing.pix_clk_100hz + (h_total_up_scaled - 1),
192 h_total_up_scaled); //ceiling for MMax and MMin for MVRR
193 } else {
194 v_total = div64_u64(div64_u64(((unsigned long long)(
195 duration_in_us) * (stream->timing.pix_clk_100hz / 10)),
196 stream->timing.h_total), 1000);
197 }
198
199 /* v_total cannot be less than nominal */
200 if (v_total < stream->timing.v_total) {
201 ASSERT(v_total < stream->timing.v_total);
202 v_total = stream->timing.v_total;
203 }
204
205 return v_total;
206 }
207
update_v_total_for_static_ramp(struct core_freesync * core_freesync,const struct dc_stream_state * stream,struct mod_vrr_params * in_out_vrr)208 static void update_v_total_for_static_ramp(
209 struct core_freesync *core_freesync,
210 const struct dc_stream_state *stream,
211 struct mod_vrr_params *in_out_vrr)
212 {
213 unsigned int v_total = 0;
214 unsigned int current_duration_in_us =
215 calc_duration_in_us_from_v_total(
216 stream, in_out_vrr,
217 in_out_vrr->adjust.v_total_max);
218 unsigned int target_duration_in_us =
219 calc_duration_in_us_from_refresh_in_uhz(
220 in_out_vrr->fixed.target_refresh_in_uhz);
221 bool ramp_direction_is_up = (current_duration_in_us >
222 target_duration_in_us) ? true : false;
223
224 /* Calculate ratio between new and current frame duration with 3 digit */
225 unsigned int frame_duration_ratio = div64_u64(1000000,
226 (1000 + div64_u64(((unsigned long long)(
227 STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME) *
228 current_duration_in_us),
229 1000000)));
230
231 /* Calculate delta between new and current frame duration in us */
232 unsigned int frame_duration_delta = div64_u64(((unsigned long long)(
233 current_duration_in_us) *
234 (1000 - frame_duration_ratio)), 1000);
235
236 /* Adjust frame duration delta based on ratio between current and
237 * standard frame duration (frame duration at 60 Hz refresh rate).
238 */
239 unsigned int ramp_rate_interpolated = div64_u64(((unsigned long long)(
240 frame_duration_delta) * current_duration_in_us), 16666);
241
242 /* Going to a higher refresh rate (lower frame duration) */
243 if (ramp_direction_is_up) {
244 /* Reduce frame duration */
245 current_duration_in_us -= ramp_rate_interpolated;
246
247 /* Adjust for frame duration below min */
248 if (current_duration_in_us <= target_duration_in_us) {
249 in_out_vrr->fixed.ramping_active = false;
250 in_out_vrr->fixed.ramping_done = true;
251 current_duration_in_us =
252 calc_duration_in_us_from_refresh_in_uhz(
253 in_out_vrr->fixed.target_refresh_in_uhz);
254 }
255 /* Going to a lower refresh rate (larger frame duration) */
256 } else {
257 /* Increase frame duration */
258 current_duration_in_us += ramp_rate_interpolated;
259
260 /* Adjust for frame duration above max */
261 if (current_duration_in_us >= target_duration_in_us) {
262 in_out_vrr->fixed.ramping_active = false;
263 in_out_vrr->fixed.ramping_done = true;
264 current_duration_in_us =
265 calc_duration_in_us_from_refresh_in_uhz(
266 in_out_vrr->fixed.target_refresh_in_uhz);
267 }
268 }
269
270 v_total = div64_u64(div64_u64(((unsigned long long)(
271 current_duration_in_us) * (stream->timing.pix_clk_100hz / 10)),
272 stream->timing.h_total), 1000);
273
274 /* v_total cannot be less than nominal */
275 if (v_total < stream->timing.v_total)
276 v_total = stream->timing.v_total;
277
278 in_out_vrr->adjust.v_total_min = v_total;
279 in_out_vrr->adjust.v_total_max = v_total;
280 }
281
apply_below_the_range(struct core_freesync * core_freesync,const struct dc_stream_state * stream,unsigned int last_render_time_in_us,struct mod_vrr_params * in_out_vrr)282 static void apply_below_the_range(struct core_freesync *core_freesync,
283 const struct dc_stream_state *stream,
284 unsigned int last_render_time_in_us,
285 struct mod_vrr_params *in_out_vrr)
286 {
287 unsigned int inserted_frame_duration_in_us = 0;
288 unsigned int mid_point_frames_ceil = 0;
289 unsigned int mid_point_frames_floor = 0;
290 unsigned int frame_time_in_us = 0;
291 unsigned int delta_from_mid_point_in_us_1 = 0xFFFFFFFF;
292 unsigned int delta_from_mid_point_in_us_2 = 0xFFFFFFFF;
293 unsigned int frames_to_insert = 0;
294 unsigned int delta_from_mid_point_delta_in_us;
295 unsigned int max_render_time_in_us =
296 in_out_vrr->max_duration_in_us - in_out_vrr->btr.margin_in_us;
297
298 /* Program BTR */
299 if ((last_render_time_in_us + in_out_vrr->btr.margin_in_us / 2) < max_render_time_in_us) {
300 /* Exit Below the Range */
301 if (in_out_vrr->btr.btr_active) {
302 in_out_vrr->btr.frame_counter = 0;
303 in_out_vrr->btr.btr_active = false;
304 }
305 } else if (last_render_time_in_us > (max_render_time_in_us + in_out_vrr->btr.margin_in_us / 2)) {
306 /* Enter Below the Range */
307 if (!in_out_vrr->btr.btr_active)
308 in_out_vrr->btr.btr_active = true;
309 }
310
311 /* BTR set to "not active" so disengage */
312 if (!in_out_vrr->btr.btr_active) {
313 in_out_vrr->btr.inserted_duration_in_us = 0;
314 in_out_vrr->btr.frames_to_insert = 0;
315 in_out_vrr->btr.frame_counter = 0;
316
317 /* Restore FreeSync */
318 in_out_vrr->adjust.v_total_min =
319 mod_freesync_calc_v_total_from_refresh(stream,
320 in_out_vrr->max_refresh_in_uhz);
321 in_out_vrr->adjust.v_total_max =
322 mod_freesync_calc_v_total_from_refresh(stream,
323 in_out_vrr->min_refresh_in_uhz);
324 /* BTR set to "active" so engage */
325 } else {
326
327 /* Calculate number of midPoint frames that could fit within
328 * the render time interval - take ceil of this value
329 */
330 mid_point_frames_ceil = (last_render_time_in_us +
331 in_out_vrr->btr.mid_point_in_us - 1) /
332 in_out_vrr->btr.mid_point_in_us;
333
334 if (mid_point_frames_ceil > 0) {
335 frame_time_in_us = last_render_time_in_us /
336 mid_point_frames_ceil;
337 delta_from_mid_point_in_us_1 =
338 (in_out_vrr->btr.mid_point_in_us >
339 frame_time_in_us) ?
340 (in_out_vrr->btr.mid_point_in_us - frame_time_in_us) :
341 (frame_time_in_us - in_out_vrr->btr.mid_point_in_us);
342 }
343
344 /* Calculate number of midPoint frames that could fit within
345 * the render time interval - take floor of this value
346 */
347 mid_point_frames_floor = last_render_time_in_us /
348 in_out_vrr->btr.mid_point_in_us;
349
350 if (mid_point_frames_floor > 0) {
351
352 frame_time_in_us = last_render_time_in_us /
353 mid_point_frames_floor;
354 delta_from_mid_point_in_us_2 =
355 (in_out_vrr->btr.mid_point_in_us >
356 frame_time_in_us) ?
357 (in_out_vrr->btr.mid_point_in_us - frame_time_in_us) :
358 (frame_time_in_us - in_out_vrr->btr.mid_point_in_us);
359 }
360
361 /* Choose number of frames to insert based on how close it
362 * can get to the mid point of the variable range.
363 * - Delta for CEIL: delta_from_mid_point_in_us_1
364 * - Delta for FLOOR: delta_from_mid_point_in_us_2
365 */
366 if (mid_point_frames_ceil &&
367 (last_render_time_in_us / mid_point_frames_ceil) <
368 in_out_vrr->min_duration_in_us) {
369 /* Check for out of range.
370 * If using CEIL produces a value that is out of range,
371 * then we are forced to use FLOOR.
372 */
373 frames_to_insert = mid_point_frames_floor;
374 } else if (mid_point_frames_floor < 2) {
375 /* Check if FLOOR would result in non-LFC. In this case
376 * choose to use CEIL
377 */
378 frames_to_insert = mid_point_frames_ceil;
379 } else if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) {
380 /* If choosing CEIL results in a frame duration that is
381 * closer to the mid point of the range.
382 * Choose CEIL
383 */
384 frames_to_insert = mid_point_frames_ceil;
385 } else {
386 /* If choosing FLOOR results in a frame duration that is
387 * closer to the mid point of the range.
388 * Choose FLOOR
389 */
390 frames_to_insert = mid_point_frames_floor;
391 }
392
393 /* Prefer current frame multiplier when BTR is enabled unless it drifts
394 * too far from the midpoint
395 */
396 if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) {
397 delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_2 -
398 delta_from_mid_point_in_us_1;
399 } else {
400 delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_1 -
401 delta_from_mid_point_in_us_2;
402 }
403 if (in_out_vrr->btr.frames_to_insert != 0 &&
404 delta_from_mid_point_delta_in_us < BTR_DRIFT_MARGIN) {
405 if (((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) <
406 max_render_time_in_us) &&
407 ((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) >
408 in_out_vrr->min_duration_in_us))
409 frames_to_insert = in_out_vrr->btr.frames_to_insert;
410 }
411
412 /* Either we've calculated the number of frames to insert,
413 * or we need to insert min duration frames
414 */
415 if (frames_to_insert &&
416 (last_render_time_in_us / frames_to_insert) <
417 in_out_vrr->min_duration_in_us){
418 frames_to_insert -= (frames_to_insert > 1) ?
419 1 : 0;
420 }
421
422 if (frames_to_insert > 0)
423 inserted_frame_duration_in_us = last_render_time_in_us /
424 frames_to_insert;
425
426 if (inserted_frame_duration_in_us < in_out_vrr->min_duration_in_us)
427 inserted_frame_duration_in_us = in_out_vrr->min_duration_in_us;
428
429 /* Cache the calculated variables */
430 in_out_vrr->btr.inserted_duration_in_us =
431 inserted_frame_duration_in_us;
432 in_out_vrr->btr.frames_to_insert = frames_to_insert;
433 in_out_vrr->btr.frame_counter = frames_to_insert;
434 }
435 }
436
apply_fixed_refresh(struct core_freesync * core_freesync,const struct dc_stream_state * stream,unsigned int last_render_time_in_us,struct mod_vrr_params * in_out_vrr)437 static void apply_fixed_refresh(struct core_freesync *core_freesync,
438 const struct dc_stream_state *stream,
439 unsigned int last_render_time_in_us,
440 struct mod_vrr_params *in_out_vrr)
441 {
442 bool update = false;
443 unsigned int max_render_time_in_us = in_out_vrr->max_duration_in_us;
444
445 /* Compute the exit refresh rate and exit frame duration */
446 unsigned int exit_refresh_rate_in_milli_hz = ((1000000000/max_render_time_in_us)
447 + (1000*FIXED_REFRESH_EXIT_MARGIN_IN_HZ));
448 unsigned int exit_frame_duration_in_us = 1000000000/exit_refresh_rate_in_milli_hz;
449
450 if (last_render_time_in_us < exit_frame_duration_in_us) {
451 /* Exit Fixed Refresh mode */
452 if (in_out_vrr->fixed.fixed_active) {
453 in_out_vrr->fixed.frame_counter++;
454
455 if (in_out_vrr->fixed.frame_counter >
456 FIXED_REFRESH_EXIT_FRAME_COUNT) {
457 in_out_vrr->fixed.frame_counter = 0;
458 in_out_vrr->fixed.fixed_active = false;
459 in_out_vrr->fixed.target_refresh_in_uhz = 0;
460 update = true;
461 }
462 } else
463 in_out_vrr->fixed.frame_counter = 0;
464 } else if (last_render_time_in_us > max_render_time_in_us) {
465 /* Enter Fixed Refresh mode */
466 if (!in_out_vrr->fixed.fixed_active) {
467 in_out_vrr->fixed.frame_counter++;
468
469 if (in_out_vrr->fixed.frame_counter >
470 FIXED_REFRESH_ENTER_FRAME_COUNT) {
471 in_out_vrr->fixed.frame_counter = 0;
472 in_out_vrr->fixed.fixed_active = true;
473 in_out_vrr->fixed.target_refresh_in_uhz =
474 in_out_vrr->max_refresh_in_uhz;
475 update = true;
476 }
477 } else
478 in_out_vrr->fixed.frame_counter = 0;
479 }
480
481 if (update) {
482 if (in_out_vrr->fixed.fixed_active) {
483 in_out_vrr->adjust.v_total_min =
484 mod_freesync_calc_v_total_from_refresh(
485 stream, in_out_vrr->max_refresh_in_uhz);
486 in_out_vrr->adjust.v_total_max =
487 in_out_vrr->adjust.v_total_min;
488 } else {
489 in_out_vrr->adjust.v_total_min =
490 mod_freesync_calc_v_total_from_refresh(stream,
491 in_out_vrr->max_refresh_in_uhz);
492 in_out_vrr->adjust.v_total_max =
493 mod_freesync_calc_v_total_from_refresh(stream,
494 in_out_vrr->min_refresh_in_uhz);
495 }
496 }
497 }
498
determine_flip_interval_workaround_req(struct mod_vrr_params * in_vrr,unsigned int curr_time_stamp_in_us)499 static void determine_flip_interval_workaround_req(struct mod_vrr_params *in_vrr,
500 unsigned int curr_time_stamp_in_us)
501 {
502 in_vrr->flip_interval.vsync_to_flip_in_us = curr_time_stamp_in_us -
503 in_vrr->flip_interval.v_update_timestamp_in_us;
504
505 /* Determine conditions for stopping workaround */
506 if (in_vrr->flip_interval.flip_interval_workaround_active &&
507 in_vrr->flip_interval.vsyncs_between_flip < VSYNCS_BETWEEN_FLIP_THRESHOLD &&
508 in_vrr->flip_interval.vsync_to_flip_in_us > FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US) {
509 in_vrr->flip_interval.flip_interval_detect_counter = 0;
510 in_vrr->flip_interval.program_flip_interval_workaround = true;
511 in_vrr->flip_interval.flip_interval_workaround_active = false;
512 } else {
513 /* Determine conditions for starting workaround */
514 if (in_vrr->flip_interval.vsyncs_between_flip >= VSYNCS_BETWEEN_FLIP_THRESHOLD &&
515 in_vrr->flip_interval.vsync_to_flip_in_us < FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US) {
516 /* Increase flip interval counter we have 2 vsyncs between flips and
517 * vsync to flip interval is less than 500us
518 */
519 in_vrr->flip_interval.flip_interval_detect_counter++;
520 if (in_vrr->flip_interval.flip_interval_detect_counter > FREESYNC_CONSEC_FLIP_AFTER_VSYNC) {
521 /* Start workaround if we detect 5 consecutive instances of the above case */
522 in_vrr->flip_interval.program_flip_interval_workaround = true;
523 in_vrr->flip_interval.flip_interval_workaround_active = true;
524 }
525 } else {
526 /* Reset the flip interval counter if we condition is no longer met */
527 in_vrr->flip_interval.flip_interval_detect_counter = 0;
528 }
529 }
530
531 in_vrr->flip_interval.vsyncs_between_flip = 0;
532 }
533
vrr_settings_require_update(struct core_freesync * core_freesync,struct mod_freesync_config * in_config,unsigned int min_refresh_in_uhz,unsigned int max_refresh_in_uhz,struct mod_vrr_params * in_vrr)534 static bool vrr_settings_require_update(struct core_freesync *core_freesync,
535 struct mod_freesync_config *in_config,
536 unsigned int min_refresh_in_uhz,
537 unsigned int max_refresh_in_uhz,
538 struct mod_vrr_params *in_vrr)
539 {
540 if (in_vrr->state != in_config->state) {
541 return true;
542 } else if (in_vrr->state == VRR_STATE_ACTIVE_FIXED &&
543 in_vrr->fixed.target_refresh_in_uhz !=
544 in_config->fixed_refresh_in_uhz) {
545 return true;
546 } else if (in_vrr->min_refresh_in_uhz != min_refresh_in_uhz) {
547 return true;
548 } else if (in_vrr->max_refresh_in_uhz != max_refresh_in_uhz) {
549 return true;
550 }
551
552 return false;
553 }
554
build_vrr_infopacket_data_v1(const struct mod_vrr_params * vrr,struct dc_info_packet * infopacket,bool freesync_on_desktop)555 static void build_vrr_infopacket_data_v1(const struct mod_vrr_params *vrr,
556 struct dc_info_packet *infopacket,
557 bool freesync_on_desktop)
558 {
559 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
560 infopacket->sb[1] = 0x1A;
561
562 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
563 infopacket->sb[2] = 0x00;
564
565 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
566 infopacket->sb[3] = 0x00;
567
568 /* PB4 = Reserved */
569
570 /* PB5 = Reserved */
571
572 /* PB6 = [Bits 7:3 = Reserved] */
573
574 /* PB6 = [Bit 0 = FreeSync Supported] */
575 if (vrr->state != VRR_STATE_UNSUPPORTED)
576 infopacket->sb[6] |= 0x01;
577
578 /* PB6 = [Bit 1 = FreeSync Enabled] */
579 if (vrr->state != VRR_STATE_DISABLED &&
580 vrr->state != VRR_STATE_UNSUPPORTED)
581 infopacket->sb[6] |= 0x02;
582
583 if (freesync_on_desktop) {
584 /* PB6 = [Bit 2 = FreeSync Active] */
585 if (vrr->state != VRR_STATE_DISABLED &&
586 vrr->state != VRR_STATE_UNSUPPORTED)
587 infopacket->sb[6] |= 0x04;
588 } else {
589 if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
590 vrr->state == VRR_STATE_ACTIVE_FIXED)
591 infopacket->sb[6] |= 0x04;
592 }
593
594 // For v1 & 2 infoframes program nominal if non-fs mode, otherwise full range
595 /* PB7 = FreeSync Minimum refresh rate (Hz) */
596 if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
597 vrr->state == VRR_STATE_ACTIVE_FIXED) {
598 infopacket->sb[7] = (unsigned char)((vrr->min_refresh_in_uhz + 500000) / 1000000);
599 } else {
600 infopacket->sb[7] = (unsigned char)((vrr->max_refresh_in_uhz + 500000) / 1000000);
601 }
602
603 /* PB8 = FreeSync Maximum refresh rate (Hz)
604 * Note: We should never go above the field rate of the mode timing set.
605 */
606 infopacket->sb[8] = (unsigned char)((vrr->max_refresh_in_uhz + 500000) / 1000000);
607 }
608
build_vrr_infopacket_data_v3(const struct mod_vrr_params * vrr,struct dc_info_packet * infopacket,bool freesync_on_desktop)609 static void build_vrr_infopacket_data_v3(const struct mod_vrr_params *vrr,
610 struct dc_info_packet *infopacket,
611 bool freesync_on_desktop)
612 {
613 unsigned int min_refresh;
614 unsigned int max_refresh;
615 unsigned int fixed_refresh;
616 unsigned int min_programmed;
617
618 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
619 infopacket->sb[1] = 0x1A;
620
621 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
622 infopacket->sb[2] = 0x00;
623
624 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
625 infopacket->sb[3] = 0x00;
626
627 /* PB4 = Reserved */
628
629 /* PB5 = Reserved */
630
631 /* PB6 = [Bits 7:3 = Reserved] */
632
633 /* PB6 = [Bit 0 = FreeSync Supported] */
634 if (vrr->state != VRR_STATE_UNSUPPORTED)
635 infopacket->sb[6] |= 0x01;
636
637 /* PB6 = [Bit 1 = FreeSync Enabled] */
638 if (vrr->state != VRR_STATE_DISABLED &&
639 vrr->state != VRR_STATE_UNSUPPORTED)
640 infopacket->sb[6] |= 0x02;
641
642 /* PB6 = [Bit 2 = FreeSync Active] */
643 if (freesync_on_desktop) {
644 if (vrr->state != VRR_STATE_DISABLED &&
645 vrr->state != VRR_STATE_UNSUPPORTED)
646 infopacket->sb[6] |= 0x04;
647 } else {
648 if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
649 vrr->state == VRR_STATE_ACTIVE_FIXED)
650 infopacket->sb[6] |= 0x04;
651 }
652
653 min_refresh = (vrr->min_refresh_in_uhz + 500000) / 1000000;
654 max_refresh = (vrr->max_refresh_in_uhz + 500000) / 1000000;
655 fixed_refresh = (vrr->fixed_refresh_in_uhz + 500000) / 1000000;
656
657 min_programmed = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? fixed_refresh :
658 (vrr->state == VRR_STATE_ACTIVE_VARIABLE) ? min_refresh :
659 (vrr->state == VRR_STATE_INACTIVE) ? min_refresh :
660 max_refresh; // Non-fs case, program nominal range
661
662 /* PB7 = FreeSync Minimum refresh rate (Hz) */
663 infopacket->sb[7] = min_programmed & 0xFF;
664
665 /* PB8 = FreeSync Maximum refresh rate (Hz) */
666 infopacket->sb[8] = max_refresh & 0xFF;
667
668 /* PB11 : MSB FreeSync Minimum refresh rate [Hz] - bits 9:8 */
669 infopacket->sb[11] = (min_programmed >> 8) & 0x03;
670
671 /* PB12 : MSB FreeSync Maximum refresh rate [Hz] - bits 9:8 */
672 infopacket->sb[12] = (max_refresh >> 8) & 0x03;
673
674 /* PB16 : Reserved bits 7:1, FixedRate bit 0 */
675 infopacket->sb[16] = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? 1 : 0;
676 }
677
build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf,struct dc_info_packet * infopacket)678 static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf,
679 struct dc_info_packet *infopacket)
680 {
681 if (app_tf != TRANSFER_FUNC_UNKNOWN) {
682 infopacket->valid = true;
683
684 if (app_tf == TRANSFER_FUNC_PQ2084)
685 infopacket->sb[9] |= 0x20; // PB9 = [Bit 5 = PQ EOTF Active]
686 else {
687 infopacket->sb[6] |= 0x08; // PB6 = [Bit 3 = Native Color Active]
688 if (app_tf == TRANSFER_FUNC_GAMMA_22)
689 infopacket->sb[9] |= 0x04; // PB9 = [Bit 2 = Gamma 2.2 EOTF Active]
690 }
691 }
692 }
693
build_vrr_infopacket_header_v1(enum signal_type signal,struct dc_info_packet * infopacket,unsigned int * payload_size)694 static void build_vrr_infopacket_header_v1(enum signal_type signal,
695 struct dc_info_packet *infopacket,
696 unsigned int *payload_size)
697 {
698 if (dc_is_hdmi_signal(signal)) {
699
700 /* HEADER */
701
702 /* HB0 = Packet Type = 0x83 (Source Product
703 * Descriptor InfoFrame)
704 */
705 infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;
706
707 /* HB1 = Version = 0x01 */
708 infopacket->hb1 = 0x01;
709
710 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
711 infopacket->hb2 = 0x08;
712
713 *payload_size = 0x08;
714
715 } else if (dc_is_dp_signal(signal)) {
716
717 /* HEADER */
718
719 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
720 * when used to associate audio related info packets
721 */
722 infopacket->hb0 = 0x00;
723
724 /* HB1 = Packet Type = 0x83 (Source Product
725 * Descriptor InfoFrame)
726 */
727 infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;
728
729 /* HB2 = [Bits 7:0 = Least significant eight bits -
730 * For INFOFRAME, the value must be 1Bh]
731 */
732 infopacket->hb2 = 0x1B;
733
734 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
735 * [Bits 1:0 = Most significant two bits = 0x00]
736 */
737 infopacket->hb3 = 0x04;
738
739 *payload_size = 0x1B;
740 }
741 }
742
build_vrr_infopacket_header_v2(enum signal_type signal,struct dc_info_packet * infopacket,unsigned int * payload_size)743 static void build_vrr_infopacket_header_v2(enum signal_type signal,
744 struct dc_info_packet *infopacket,
745 unsigned int *payload_size)
746 {
747 if (dc_is_hdmi_signal(signal)) {
748
749 /* HEADER */
750
751 /* HB0 = Packet Type = 0x83 (Source Product
752 * Descriptor InfoFrame)
753 */
754 infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;
755
756 /* HB1 = Version = 0x02 */
757 infopacket->hb1 = 0x02;
758
759 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x09] */
760 infopacket->hb2 = 0x09;
761
762 *payload_size = 0x09;
763 } else if (dc_is_dp_signal(signal)) {
764
765 /* HEADER */
766
767 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
768 * when used to associate audio related info packets
769 */
770 infopacket->hb0 = 0x00;
771
772 /* HB1 = Packet Type = 0x83 (Source Product
773 * Descriptor InfoFrame)
774 */
775 infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;
776
777 /* HB2 = [Bits 7:0 = Least significant eight bits -
778 * For INFOFRAME, the value must be 1Bh]
779 */
780 infopacket->hb2 = 0x1B;
781
782 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x2]
783 * [Bits 1:0 = Most significant two bits = 0x00]
784 */
785 infopacket->hb3 = 0x08;
786
787 *payload_size = 0x1B;
788 }
789 }
790
build_vrr_infopacket_header_v3(enum signal_type signal,struct dc_info_packet * infopacket,unsigned int * payload_size)791 static void build_vrr_infopacket_header_v3(enum signal_type signal,
792 struct dc_info_packet *infopacket,
793 unsigned int *payload_size)
794 {
795 unsigned char version;
796
797 version = 3;
798 if (dc_is_hdmi_signal(signal)) {
799
800 /* HEADER */
801
802 /* HB0 = Packet Type = 0x83 (Source Product
803 * Descriptor InfoFrame)
804 */
805 infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;
806
807 /* HB1 = Version = 0x03 */
808 infopacket->hb1 = version;
809
810 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length] */
811 infopacket->hb2 = 0x10;
812
813 *payload_size = 0x10;
814 } else if (dc_is_dp_signal(signal)) {
815
816 /* HEADER */
817
818 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
819 * when used to associate audio related info packets
820 */
821 infopacket->hb0 = 0x00;
822
823 /* HB1 = Packet Type = 0x83 (Source Product
824 * Descriptor InfoFrame)
825 */
826 infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;
827
828 /* HB2 = [Bits 7:0 = Least significant eight bits -
829 * For INFOFRAME, the value must be 1Bh]
830 */
831 infopacket->hb2 = 0x1B;
832
833 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x2]
834 * [Bits 1:0 = Most significant two bits = 0x00]
835 */
836
837 infopacket->hb3 = (version & 0x3F) << 2;
838
839 *payload_size = 0x1B;
840 }
841 }
842
build_vrr_infopacket_checksum(unsigned int * payload_size,struct dc_info_packet * infopacket)843 static void build_vrr_infopacket_checksum(unsigned int *payload_size,
844 struct dc_info_packet *infopacket)
845 {
846 /* Calculate checksum */
847 unsigned int idx = 0;
848 unsigned char checksum = 0;
849
850 checksum += infopacket->hb0;
851 checksum += infopacket->hb1;
852 checksum += infopacket->hb2;
853 checksum += infopacket->hb3;
854
855 for (idx = 1; idx <= *payload_size; idx++)
856 checksum += infopacket->sb[idx];
857
858 /* PB0 = Checksum (one byte complement) */
859 infopacket->sb[0] = (unsigned char)(0x100 - checksum);
860
861 infopacket->valid = true;
862 }
863
build_vrr_infopacket_v1(enum signal_type signal,const struct mod_vrr_params * vrr,struct dc_info_packet * infopacket,bool freesync_on_desktop)864 static void build_vrr_infopacket_v1(enum signal_type signal,
865 const struct mod_vrr_params *vrr,
866 struct dc_info_packet *infopacket,
867 bool freesync_on_desktop)
868 {
869 /* SPD info packet for FreeSync */
870 unsigned int payload_size = 0;
871
872 build_vrr_infopacket_header_v1(signal, infopacket, &payload_size);
873 build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop);
874 build_vrr_infopacket_checksum(&payload_size, infopacket);
875
876 infopacket->valid = true;
877 }
878
build_vrr_infopacket_v2(enum signal_type signal,const struct mod_vrr_params * vrr,enum color_transfer_func app_tf,struct dc_info_packet * infopacket,bool freesync_on_desktop)879 static void build_vrr_infopacket_v2(enum signal_type signal,
880 const struct mod_vrr_params *vrr,
881 enum color_transfer_func app_tf,
882 struct dc_info_packet *infopacket,
883 bool freesync_on_desktop)
884 {
885 unsigned int payload_size = 0;
886
887 build_vrr_infopacket_header_v2(signal, infopacket, &payload_size);
888 build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop);
889
890 build_vrr_infopacket_fs2_data(app_tf, infopacket);
891
892 build_vrr_infopacket_checksum(&payload_size, infopacket);
893
894 infopacket->valid = true;
895 }
896
build_vrr_infopacket_v3(enum signal_type signal,const struct mod_vrr_params * vrr,enum color_transfer_func app_tf,struct dc_info_packet * infopacket,bool freesync_on_desktop)897 static void build_vrr_infopacket_v3(enum signal_type signal,
898 const struct mod_vrr_params *vrr,
899 enum color_transfer_func app_tf,
900 struct dc_info_packet *infopacket,
901 bool freesync_on_desktop)
902 {
903 unsigned int payload_size = 0;
904
905 build_vrr_infopacket_header_v3(signal, infopacket, &payload_size);
906 build_vrr_infopacket_data_v3(vrr, infopacket, freesync_on_desktop);
907
908 build_vrr_infopacket_fs2_data(app_tf, infopacket);
909
910 build_vrr_infopacket_checksum(&payload_size, infopacket);
911
912 infopacket->valid = true;
913 }
914
build_vrr_infopacket_sdp_v1_3(enum vrr_packet_type packet_type,struct dc_info_packet * infopacket)915 static void build_vrr_infopacket_sdp_v1_3(enum vrr_packet_type packet_type,
916 struct dc_info_packet *infopacket)
917 {
918 uint8_t idx = 0, size = 0;
919
920 size = ((packet_type == PACKET_TYPE_FS_V1) ? 0x08 :
921 (packet_type == PACKET_TYPE_FS_V3) ? 0x10 :
922 0x09);
923
924 for (idx = infopacket->hb2; idx > 1; idx--) // Data Byte Count: 0x1B
925 infopacket->sb[idx] = infopacket->sb[idx-1];
926
927 infopacket->sb[1] = size; // Length
928 infopacket->sb[0] = (infopacket->hb3 >> 2) & 0x3F;//Version
929 infopacket->hb3 = (0x13 << 2); // Header,SDP 1.3
930 infopacket->hb2 = 0x1D;
931 }
932
mod_freesync_build_vrr_infopacket(struct mod_freesync * mod_freesync,const struct dc_stream_state * stream,const struct mod_vrr_params * vrr,enum vrr_packet_type packet_type,enum color_transfer_func app_tf,struct dc_info_packet * infopacket,bool pack_sdp_v1_3)933 void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
934 const struct dc_stream_state *stream,
935 const struct mod_vrr_params *vrr,
936 enum vrr_packet_type packet_type,
937 enum color_transfer_func app_tf,
938 struct dc_info_packet *infopacket,
939 bool pack_sdp_v1_3)
940 {
941 /* SPD info packet for FreeSync
942 * VTEM info packet for HdmiVRR
943 * Check if Freesync is supported. Return if false. If true,
944 * set the corresponding bit in the info packet
945 */
946 if (!vrr->send_info_frame)
947 return;
948
949 switch (packet_type) {
950 case PACKET_TYPE_FS_V3:
951 build_vrr_infopacket_v3(stream->signal, vrr, app_tf, infopacket, stream->freesync_on_desktop);
952 break;
953 case PACKET_TYPE_FS_V2:
954 build_vrr_infopacket_v2(stream->signal, vrr, app_tf, infopacket, stream->freesync_on_desktop);
955 break;
956 case PACKET_TYPE_VRR:
957 case PACKET_TYPE_FS_V1:
958 default:
959 build_vrr_infopacket_v1(stream->signal, vrr, infopacket, stream->freesync_on_desktop);
960 }
961
962 if (true == pack_sdp_v1_3 &&
963 true == dc_is_dp_signal(stream->signal) &&
964 packet_type != PACKET_TYPE_VRR &&
965 packet_type != PACKET_TYPE_VTEM)
966 build_vrr_infopacket_sdp_v1_3(packet_type, infopacket);
967 }
968
mod_freesync_build_vrr_params(struct mod_freesync * mod_freesync,const struct dc_stream_state * stream,struct mod_freesync_config * in_config,struct mod_vrr_params * in_out_vrr)969 void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
970 const struct dc_stream_state *stream,
971 struct mod_freesync_config *in_config,
972 struct mod_vrr_params *in_out_vrr)
973 {
974 struct core_freesync *core_freesync = NULL;
975 unsigned long long nominal_field_rate_in_uhz = 0;
976 unsigned long long rounded_nominal_in_uhz = 0;
977 unsigned int refresh_range = 0;
978 unsigned long long min_refresh_in_uhz = 0;
979 unsigned long long max_refresh_in_uhz = 0;
980 unsigned long long min_hardware_refresh_in_uhz = 0;
981
982 if (mod_freesync == NULL)
983 return;
984
985 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
986
987 /* Calculate nominal field rate for stream */
988 nominal_field_rate_in_uhz =
989 mod_freesync_calc_nominal_field_rate(stream);
990
991 if (stream->ctx->dc->caps.max_v_total != 0 && stream->timing.h_total != 0) {
992 min_hardware_refresh_in_uhz = div64_u64((stream->timing.pix_clk_100hz * 100000000ULL),
993 (stream->timing.h_total * (long long)calc_max_hardware_v_total(stream)));
994 }
995 /* Limit minimum refresh rate to what can be supported by hardware */
996 min_refresh_in_uhz = min_hardware_refresh_in_uhz > in_config->min_refresh_in_uhz ?
997 min_hardware_refresh_in_uhz : in_config->min_refresh_in_uhz;
998 max_refresh_in_uhz = in_config->max_refresh_in_uhz;
999
1000 /* Full range may be larger than current video timing, so cap at nominal */
1001 if (max_refresh_in_uhz > nominal_field_rate_in_uhz)
1002 max_refresh_in_uhz = nominal_field_rate_in_uhz;
1003
1004 /* Full range may be larger than current video timing, so cap at nominal */
1005 if (min_refresh_in_uhz > max_refresh_in_uhz)
1006 min_refresh_in_uhz = max_refresh_in_uhz;
1007
1008 /* If a monitor reports exactly max refresh of 2x of min, enforce it on nominal */
1009 rounded_nominal_in_uhz =
1010 div_u64(nominal_field_rate_in_uhz + 50000, 100000) * 100000;
1011 if (in_config->max_refresh_in_uhz == (2 * in_config->min_refresh_in_uhz) &&
1012 in_config->max_refresh_in_uhz == rounded_nominal_in_uhz)
1013 min_refresh_in_uhz = div_u64(nominal_field_rate_in_uhz, 2);
1014
1015 if (!vrr_settings_require_update(core_freesync,
1016 in_config, (unsigned int)min_refresh_in_uhz, (unsigned int)max_refresh_in_uhz,
1017 in_out_vrr))
1018 return;
1019
1020 in_out_vrr->state = in_config->state;
1021 in_out_vrr->send_info_frame = in_config->vsif_supported;
1022
1023 if (in_config->state == VRR_STATE_UNSUPPORTED) {
1024 in_out_vrr->state = VRR_STATE_UNSUPPORTED;
1025 in_out_vrr->supported = false;
1026 in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1027 in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1028
1029 return;
1030
1031 } else {
1032 in_out_vrr->min_refresh_in_uhz = (unsigned int)min_refresh_in_uhz;
1033 in_out_vrr->max_duration_in_us =
1034 calc_duration_in_us_from_refresh_in_uhz(
1035 (unsigned int)min_refresh_in_uhz);
1036
1037 in_out_vrr->max_refresh_in_uhz = (unsigned int)max_refresh_in_uhz;
1038 in_out_vrr->min_duration_in_us =
1039 calc_duration_in_us_from_refresh_in_uhz(
1040 (unsigned int)max_refresh_in_uhz);
1041
1042 if (in_config->state == VRR_STATE_ACTIVE_FIXED)
1043 in_out_vrr->fixed_refresh_in_uhz = in_config->fixed_refresh_in_uhz;
1044 else
1045 in_out_vrr->fixed_refresh_in_uhz = 0;
1046
1047 refresh_range = div_u64(in_out_vrr->max_refresh_in_uhz + 500000, 1000000) -
1048 div_u64(in_out_vrr->min_refresh_in_uhz + 500000, 1000000);
1049
1050 in_out_vrr->supported = true;
1051 }
1052
1053 in_out_vrr->fixed.ramping_active = in_config->ramping;
1054
1055 in_out_vrr->btr.btr_enabled = in_config->btr;
1056
1057 if (in_out_vrr->max_refresh_in_uhz < (2 * in_out_vrr->min_refresh_in_uhz))
1058 in_out_vrr->btr.btr_enabled = false;
1059 else {
1060 in_out_vrr->btr.margin_in_us = in_out_vrr->max_duration_in_us -
1061 2 * in_out_vrr->min_duration_in_us;
1062 if (in_out_vrr->btr.margin_in_us > BTR_MAX_MARGIN)
1063 in_out_vrr->btr.margin_in_us = BTR_MAX_MARGIN;
1064 }
1065
1066 in_out_vrr->btr.btr_active = false;
1067 in_out_vrr->btr.inserted_duration_in_us = 0;
1068 in_out_vrr->btr.frames_to_insert = 0;
1069 in_out_vrr->btr.frame_counter = 0;
1070 in_out_vrr->fixed.fixed_active = false;
1071 in_out_vrr->fixed.target_refresh_in_uhz = 0;
1072
1073 in_out_vrr->btr.mid_point_in_us =
1074 (in_out_vrr->min_duration_in_us +
1075 in_out_vrr->max_duration_in_us) / 2;
1076
1077 if (in_out_vrr->state == VRR_STATE_UNSUPPORTED) {
1078 in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1079 in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1080 } else if (in_out_vrr->state == VRR_STATE_DISABLED) {
1081 in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1082 in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1083 } else if (in_out_vrr->state == VRR_STATE_INACTIVE) {
1084 in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1085 in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1086 } else if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
1087 refresh_range >= MIN_REFRESH_RANGE) {
1088
1089 in_out_vrr->adjust.v_total_min =
1090 mod_freesync_calc_v_total_from_refresh(stream,
1091 in_out_vrr->max_refresh_in_uhz);
1092 in_out_vrr->adjust.v_total_max =
1093 mod_freesync_calc_v_total_from_refresh(stream,
1094 in_out_vrr->min_refresh_in_uhz);
1095 } else if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED) {
1096 in_out_vrr->fixed.target_refresh_in_uhz =
1097 in_out_vrr->fixed_refresh_in_uhz;
1098 if (in_out_vrr->fixed.ramping_active &&
1099 in_out_vrr->fixed.fixed_active) {
1100 /* Do not update vtotals if ramping is already active
1101 * in order to continue ramp from current refresh.
1102 */
1103 in_out_vrr->fixed.fixed_active = true;
1104 } else {
1105 in_out_vrr->fixed.fixed_active = true;
1106 in_out_vrr->adjust.v_total_min =
1107 mod_freesync_calc_v_total_from_refresh(stream,
1108 in_out_vrr->fixed.target_refresh_in_uhz);
1109 in_out_vrr->adjust.v_total_max =
1110 in_out_vrr->adjust.v_total_min;
1111 }
1112 } else {
1113 in_out_vrr->state = VRR_STATE_INACTIVE;
1114 in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1115 in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1116 }
1117
1118 in_out_vrr->adjust.allow_otg_v_count_halt = (in_config->state == VRR_STATE_ACTIVE_FIXED) ? true : false;
1119 }
1120
mod_freesync_handle_preflip(struct mod_freesync * mod_freesync,const struct dc_plane_state * plane,const struct dc_stream_state * stream,unsigned int curr_time_stamp_in_us,struct mod_vrr_params * in_out_vrr)1121 void mod_freesync_handle_preflip(struct mod_freesync *mod_freesync,
1122 const struct dc_plane_state *plane,
1123 const struct dc_stream_state *stream,
1124 unsigned int curr_time_stamp_in_us,
1125 struct mod_vrr_params *in_out_vrr)
1126 {
1127 struct core_freesync *core_freesync = NULL;
1128 unsigned int last_render_time_in_us = 0;
1129
1130 if (mod_freesync == NULL)
1131 return;
1132
1133 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1134
1135 if (in_out_vrr->supported &&
1136 in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE) {
1137
1138 last_render_time_in_us = curr_time_stamp_in_us -
1139 plane->time.prev_update_time_in_us;
1140
1141 if (in_out_vrr->btr.btr_enabled) {
1142 apply_below_the_range(core_freesync,
1143 stream,
1144 last_render_time_in_us,
1145 in_out_vrr);
1146 } else {
1147 apply_fixed_refresh(core_freesync,
1148 stream,
1149 last_render_time_in_us,
1150 in_out_vrr);
1151 }
1152
1153 determine_flip_interval_workaround_req(in_out_vrr,
1154 curr_time_stamp_in_us);
1155
1156 }
1157 }
1158
mod_freesync_handle_v_update(struct mod_freesync * mod_freesync,const struct dc_stream_state * stream,struct mod_vrr_params * in_out_vrr)1159 void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
1160 const struct dc_stream_state *stream,
1161 struct mod_vrr_params *in_out_vrr)
1162 {
1163 struct core_freesync *core_freesync = NULL;
1164 unsigned int cur_timestamp_in_us;
1165 unsigned long long cur_tick;
1166
1167 if ((mod_freesync == NULL) || (stream == NULL) || (in_out_vrr == NULL))
1168 return;
1169
1170 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1171
1172 if (in_out_vrr->supported == false)
1173 return;
1174
1175 cur_tick = dm_get_timestamp(core_freesync->dc->ctx);
1176 cur_timestamp_in_us = (unsigned int)
1177 div_u64(dm_get_elapse_time_in_ns(core_freesync->dc->ctx, cur_tick, 0), 1000);
1178
1179 in_out_vrr->flip_interval.vsyncs_between_flip++;
1180 in_out_vrr->flip_interval.v_update_timestamp_in_us = cur_timestamp_in_us;
1181
1182 if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
1183 (in_out_vrr->flip_interval.flip_interval_workaround_active ||
1184 (!in_out_vrr->flip_interval.flip_interval_workaround_active &&
1185 in_out_vrr->flip_interval.program_flip_interval_workaround))) {
1186 // set freesync vmin vmax to nominal for workaround
1187 in_out_vrr->adjust.v_total_min =
1188 mod_freesync_calc_v_total_from_refresh(
1189 stream, in_out_vrr->max_refresh_in_uhz);
1190 in_out_vrr->adjust.v_total_max =
1191 in_out_vrr->adjust.v_total_min;
1192 in_out_vrr->flip_interval.program_flip_interval_workaround = false;
1193 in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup = true;
1194 return;
1195 }
1196
1197 if (in_out_vrr->state != VRR_STATE_ACTIVE_VARIABLE &&
1198 in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup) {
1199 in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup = false;
1200 in_out_vrr->flip_interval.flip_interval_detect_counter = 0;
1201 in_out_vrr->flip_interval.vsyncs_between_flip = 0;
1202 in_out_vrr->flip_interval.vsync_to_flip_in_us = 0;
1203 }
1204
1205 /* Below the Range Logic */
1206
1207 /* Only execute if in fullscreen mode */
1208 if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
1209 in_out_vrr->btr.btr_active) {
1210 /* TODO: pass in flag for Pre-DCE12 ASIC
1211 * in order for frame variable duration to take affect,
1212 * it needs to be done one VSYNC early, which is at
1213 * frameCounter == 1.
1214 * For DCE12 and newer updates to V_TOTAL_MIN/MAX
1215 * will take affect on current frame
1216 */
1217 if (in_out_vrr->btr.frames_to_insert ==
1218 in_out_vrr->btr.frame_counter) {
1219 in_out_vrr->adjust.v_total_min =
1220 calc_v_total_from_duration(stream,
1221 in_out_vrr,
1222 in_out_vrr->btr.inserted_duration_in_us);
1223 in_out_vrr->adjust.v_total_max =
1224 in_out_vrr->adjust.v_total_min;
1225 }
1226
1227 if (in_out_vrr->btr.frame_counter > 0)
1228 in_out_vrr->btr.frame_counter--;
1229
1230 /* Restore FreeSync */
1231 if (in_out_vrr->btr.frame_counter == 0) {
1232 in_out_vrr->adjust.v_total_min =
1233 mod_freesync_calc_v_total_from_refresh(stream,
1234 in_out_vrr->max_refresh_in_uhz);
1235 in_out_vrr->adjust.v_total_max =
1236 mod_freesync_calc_v_total_from_refresh(stream,
1237 in_out_vrr->min_refresh_in_uhz);
1238 }
1239 }
1240
1241 /* If in fullscreen freesync mode or in video, do not program
1242 * static screen ramp values
1243 */
1244 if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE)
1245 in_out_vrr->fixed.ramping_active = false;
1246
1247 /* Gradual Static Screen Ramping Logic
1248 * Execute if ramp is active and user enabled freesync static screen
1249 */
1250 if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED &&
1251 in_out_vrr->fixed.ramping_active) {
1252 update_v_total_for_static_ramp(
1253 core_freesync, stream, in_out_vrr);
1254 }
1255 }
1256
mod_freesync_calc_nominal_field_rate(const struct dc_stream_state * stream)1257 unsigned long long mod_freesync_calc_nominal_field_rate(
1258 const struct dc_stream_state *stream)
1259 {
1260 unsigned long long nominal_field_rate_in_uhz = 0;
1261 unsigned int total = stream->timing.h_total * stream->timing.v_total;
1262
1263 /* Calculate nominal field rate for stream, rounded up to nearest integer */
1264 nominal_field_rate_in_uhz = stream->timing.pix_clk_100hz;
1265 nominal_field_rate_in_uhz *= 100000000ULL;
1266
1267 nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz, total);
1268
1269 return nominal_field_rate_in_uhz;
1270 }
1271
mod_freesync_get_freesync_enabled(struct mod_vrr_params * pVrr)1272 bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr)
1273 {
1274 return (pVrr->state != VRR_STATE_UNSUPPORTED) && (pVrr->state != VRR_STATE_DISABLED);
1275 }
1276