1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/tcp.h>
34 #include <linux/if_vlan.h>
35 #include <net/geneve.h>
36 #include <net/dsfield.h>
37 #include "en.h"
38 #include "en/txrx.h"
39 #include "ipoib/ipoib.h"
40 #include "en_accel/en_accel.h"
41 #include "en_accel/ipsec_rxtx.h"
42 #include "en_accel/macsec.h"
43 #include "en/ptp.h"
44 #include <net/ipv6.h>
45
mlx5e_dma_unmap_wqe_err(struct mlx5e_txqsq * sq,u8 num_dma)46 static void mlx5e_dma_unmap_wqe_err(struct mlx5e_txqsq *sq, u8 num_dma)
47 {
48 int i;
49
50 for (i = 0; i < num_dma; i++) {
51 struct mlx5e_sq_dma *last_pushed_dma =
52 mlx5e_dma_get(sq, --sq->dma_fifo_pc);
53
54 mlx5e_tx_dma_unmap(sq->pdev, last_pushed_dma);
55 }
56 }
57
mlx5e_skb_l2_header_offset(struct sk_buff * skb)58 static inline int mlx5e_skb_l2_header_offset(struct sk_buff *skb)
59 {
60 #define MLX5E_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
61
62 return max(skb_network_offset(skb), MLX5E_MIN_INLINE);
63 }
64
mlx5e_skb_l3_header_offset(struct sk_buff * skb)65 static inline int mlx5e_skb_l3_header_offset(struct sk_buff *skb)
66 {
67 if (skb_transport_header_was_set(skb))
68 return skb_transport_offset(skb);
69 else
70 return mlx5e_skb_l2_header_offset(skb);
71 }
72
mlx5e_calc_min_inline(enum mlx5_inline_modes mode,struct sk_buff * skb)73 static inline u16 mlx5e_calc_min_inline(enum mlx5_inline_modes mode,
74 struct sk_buff *skb)
75 {
76 u16 hlen;
77
78 switch (mode) {
79 case MLX5_INLINE_MODE_NONE:
80 return 0;
81 case MLX5_INLINE_MODE_TCP_UDP:
82 hlen = eth_get_headlen(skb->dev, skb->data, skb_headlen(skb));
83 if (hlen == ETH_HLEN && !skb_vlan_tag_present(skb))
84 hlen += VLAN_HLEN;
85 break;
86 case MLX5_INLINE_MODE_IP:
87 hlen = mlx5e_skb_l3_header_offset(skb);
88 break;
89 case MLX5_INLINE_MODE_L2:
90 default:
91 hlen = mlx5e_skb_l2_header_offset(skb);
92 }
93 return min_t(u16, hlen, skb_headlen(skb));
94 }
95
96 #define MLX5_UNSAFE_MEMCPY_DISCLAIMER \
97 "This copy has been bounds-checked earlier in " \
98 "mlx5i_sq_calc_wqe_attr() and intentionally " \
99 "crosses a flex array boundary. Since it is " \
100 "performance sensitive, splitting the copy is " \
101 "undesirable."
102
mlx5e_insert_vlan(void * start,struct sk_buff * skb,u16 ihs)103 static inline void mlx5e_insert_vlan(void *start, struct sk_buff *skb, u16 ihs)
104 {
105 struct vlan_ethhdr *vhdr = (struct vlan_ethhdr *)start;
106 int cpy1_sz = 2 * ETH_ALEN;
107 int cpy2_sz = ihs - cpy1_sz;
108
109 memcpy(&vhdr->addrs, skb->data, cpy1_sz);
110 vhdr->h_vlan_proto = skb->vlan_proto;
111 vhdr->h_vlan_TCI = cpu_to_be16(skb_vlan_tag_get(skb));
112 unsafe_memcpy(&vhdr->h_vlan_encapsulated_proto,
113 skb->data + cpy1_sz,
114 cpy2_sz,
115 MLX5_UNSAFE_MEMCPY_DISCLAIMER);
116 }
117
118 static inline void
mlx5e_txwqe_build_eseg_csum(struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5e_accel_tx_state * accel,struct mlx5_wqe_eth_seg * eseg)119 mlx5e_txwqe_build_eseg_csum(struct mlx5e_txqsq *sq, struct sk_buff *skb,
120 struct mlx5e_accel_tx_state *accel,
121 struct mlx5_wqe_eth_seg *eseg)
122 {
123 if (unlikely(mlx5e_ipsec_txwqe_build_eseg_csum(sq, skb, eseg)))
124 return;
125
126 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
127 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM;
128 if (skb->encapsulation) {
129 eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM |
130 MLX5_ETH_WQE_L4_INNER_CSUM;
131 sq->stats->csum_partial_inner++;
132 } else {
133 eseg->cs_flags |= MLX5_ETH_WQE_L4_CSUM;
134 sq->stats->csum_partial++;
135 }
136 #ifdef CONFIG_MLX5_EN_TLS
137 } else if (unlikely(accel && accel->tls.tls_tisn)) {
138 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
139 sq->stats->csum_partial++;
140 #endif
141 } else
142 sq->stats->csum_none++;
143 }
144
145 /* Returns the number of header bytes that we plan
146 * to inline later in the transmit descriptor
147 */
148 static inline u16
mlx5e_tx_get_gso_ihs(struct mlx5e_txqsq * sq,struct sk_buff * skb,int * hopbyhop)149 mlx5e_tx_get_gso_ihs(struct mlx5e_txqsq *sq, struct sk_buff *skb, int *hopbyhop)
150 {
151 struct mlx5e_sq_stats *stats = sq->stats;
152 u16 ihs;
153
154 *hopbyhop = 0;
155 if (skb->encapsulation) {
156 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4)
157 ihs = skb_inner_transport_offset(skb) +
158 sizeof(struct udphdr);
159 else
160 ihs = skb_inner_tcp_all_headers(skb);
161 stats->tso_inner_packets++;
162 stats->tso_inner_bytes += skb->len - ihs;
163 } else {
164 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
165 ihs = skb_transport_offset(skb) + sizeof(struct udphdr);
166 } else {
167 ihs = skb_tcp_all_headers(skb);
168 if (ipv6_has_hopopt_jumbo(skb)) {
169 *hopbyhop = sizeof(struct hop_jumbo_hdr);
170 ihs -= sizeof(struct hop_jumbo_hdr);
171 }
172 }
173 stats->tso_packets++;
174 stats->tso_bytes += skb->len - ihs - *hopbyhop;
175 }
176
177 return ihs;
178 }
179
180 static inline int
mlx5e_txwqe_build_dsegs(struct mlx5e_txqsq * sq,struct sk_buff * skb,unsigned char * skb_data,u16 headlen,struct mlx5_wqe_data_seg * dseg)181 mlx5e_txwqe_build_dsegs(struct mlx5e_txqsq *sq, struct sk_buff *skb,
182 unsigned char *skb_data, u16 headlen,
183 struct mlx5_wqe_data_seg *dseg)
184 {
185 dma_addr_t dma_addr = 0;
186 u8 num_dma = 0;
187 int i;
188
189 if (headlen) {
190 dma_addr = dma_map_single(sq->pdev, skb_data, headlen,
191 DMA_TO_DEVICE);
192 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
193 goto dma_unmap_wqe_err;
194
195 dseg->addr = cpu_to_be64(dma_addr);
196 dseg->lkey = sq->mkey_be;
197 dseg->byte_count = cpu_to_be32(headlen);
198
199 mlx5e_dma_push_single(sq, dma_addr, headlen);
200 num_dma++;
201 dseg++;
202 }
203
204 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
205 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
206 int fsz = skb_frag_size(frag);
207
208 dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
209 DMA_TO_DEVICE);
210 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
211 goto dma_unmap_wqe_err;
212
213 dseg->addr = cpu_to_be64(dma_addr);
214 dseg->lkey = sq->mkey_be;
215 dseg->byte_count = cpu_to_be32(fsz);
216
217 mlx5e_dma_push_netmem(sq, skb_frag_netmem(frag), dma_addr, fsz);
218 num_dma++;
219 dseg++;
220 }
221
222 return num_dma;
223
224 dma_unmap_wqe_err:
225 mlx5e_dma_unmap_wqe_err(sq, num_dma);
226 return -ENOMEM;
227 }
228
229 struct mlx5e_tx_attr {
230 u32 num_bytes;
231 u16 headlen;
232 u16 ihs;
233 __be16 mss;
234 u16 insz;
235 u8 opcode;
236 u8 hopbyhop;
237 };
238
239 struct mlx5e_tx_wqe_attr {
240 u16 ds_cnt;
241 u16 ds_cnt_inl;
242 u16 ds_cnt_ids;
243 u8 num_wqebbs;
244 };
245
246 static u8
mlx5e_tx_wqe_inline_mode(struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5e_accel_tx_state * accel)247 mlx5e_tx_wqe_inline_mode(struct mlx5e_txqsq *sq, struct sk_buff *skb,
248 struct mlx5e_accel_tx_state *accel)
249 {
250 u8 mode;
251
252 #ifdef CONFIG_MLX5_EN_TLS
253 if (accel && accel->tls.tls_tisn)
254 return MLX5_INLINE_MODE_TCP_UDP;
255 #endif
256
257 mode = sq->min_inline_mode;
258
259 if (skb_vlan_tag_present(skb))
260 mode = max_t(u8, MLX5_INLINE_MODE_L2, mode);
261
262 return mode;
263 }
264
mlx5e_sq_xmit_prepare(struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5e_accel_tx_state * accel,struct mlx5e_tx_attr * attr)265 static void mlx5e_sq_xmit_prepare(struct mlx5e_txqsq *sq, struct sk_buff *skb,
266 struct mlx5e_accel_tx_state *accel,
267 struct mlx5e_tx_attr *attr)
268 {
269 struct mlx5e_sq_stats *stats = sq->stats;
270
271 if (skb_is_gso(skb)) {
272 int hopbyhop;
273 u16 ihs = mlx5e_tx_get_gso_ihs(sq, skb, &hopbyhop);
274
275 *attr = (struct mlx5e_tx_attr) {
276 .opcode = MLX5_OPCODE_LSO,
277 .mss = cpu_to_be16(skb_shinfo(skb)->gso_size),
278 .ihs = ihs,
279 .num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs,
280 .headlen = skb_headlen(skb) - ihs - hopbyhop,
281 .hopbyhop = hopbyhop,
282 };
283
284 stats->packets += skb_shinfo(skb)->gso_segs;
285 } else {
286 u8 mode = mlx5e_tx_wqe_inline_mode(sq, skb, accel);
287 u16 ihs = mlx5e_calc_min_inline(mode, skb);
288
289 *attr = (struct mlx5e_tx_attr) {
290 .opcode = MLX5_OPCODE_SEND,
291 .mss = cpu_to_be16(0),
292 .ihs = ihs,
293 .num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN),
294 .headlen = skb_headlen(skb) - ihs,
295 };
296
297 stats->packets++;
298 }
299
300 attr->insz = mlx5e_accel_tx_ids_len(sq, accel);
301 stats->bytes += attr->num_bytes;
302 }
303
mlx5e_sq_calc_wqe_attr(struct sk_buff * skb,const struct mlx5e_tx_attr * attr,struct mlx5e_tx_wqe_attr * wqe_attr)304 static void mlx5e_sq_calc_wqe_attr(struct sk_buff *skb, const struct mlx5e_tx_attr *attr,
305 struct mlx5e_tx_wqe_attr *wqe_attr)
306 {
307 u16 ds_cnt = MLX5E_TX_WQE_EMPTY_DS_COUNT;
308 u16 ds_cnt_inl = 0;
309 u16 ds_cnt_ids = 0;
310
311 /* Sync the calculation with MLX5E_MAX_TX_WQEBBS. */
312
313 if (attr->insz)
314 ds_cnt_ids = DIV_ROUND_UP(sizeof(struct mlx5_wqe_inline_seg) + attr->insz,
315 MLX5_SEND_WQE_DS);
316
317 ds_cnt += !!attr->headlen + skb_shinfo(skb)->nr_frags + ds_cnt_ids;
318 if (attr->ihs) {
319 u16 inl = attr->ihs - INL_HDR_START_SZ;
320
321 if (skb_vlan_tag_present(skb))
322 inl += VLAN_HLEN;
323
324 ds_cnt_inl = DIV_ROUND_UP(inl, MLX5_SEND_WQE_DS);
325 if (WARN_ON_ONCE(ds_cnt_inl > MLX5E_MAX_TX_INLINE_DS))
326 netdev_warn(skb->dev, "ds_cnt_inl = %u > max %u\n", ds_cnt_inl,
327 (u16)MLX5E_MAX_TX_INLINE_DS);
328 ds_cnt += ds_cnt_inl;
329 }
330
331 *wqe_attr = (struct mlx5e_tx_wqe_attr) {
332 .ds_cnt = ds_cnt,
333 .ds_cnt_inl = ds_cnt_inl,
334 .ds_cnt_ids = ds_cnt_ids,
335 .num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS),
336 };
337 }
338
mlx5e_tx_skb_update_ts_flags(struct sk_buff * skb)339 static void mlx5e_tx_skb_update_ts_flags(struct sk_buff *skb)
340 {
341 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
342 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
343 skb_tx_timestamp(skb);
344 }
345
mlx5e_tx_check_stop(struct mlx5e_txqsq * sq)346 static void mlx5e_tx_check_stop(struct mlx5e_txqsq *sq)
347 {
348 if (unlikely(!mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, sq->stop_room))) {
349 netif_tx_stop_queue(sq->txq);
350 sq->stats->stopped++;
351 }
352 }
353
mlx5e_tx_flush(struct mlx5e_txqsq * sq)354 static void mlx5e_tx_flush(struct mlx5e_txqsq *sq)
355 {
356 struct mlx5e_tx_wqe_info *wi;
357 struct mlx5e_tx_wqe *wqe;
358 u16 pi;
359
360 /* Must not be called when a MPWQE session is active but empty. */
361 mlx5e_tx_mpwqe_ensure_complete(sq);
362
363 pi = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->pc);
364 wi = &sq->db.wqe_info[pi];
365
366 *wi = (struct mlx5e_tx_wqe_info) {
367 .num_wqebbs = 1,
368 };
369
370 wqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
371 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl);
372 }
373
374 static inline void
mlx5e_txwqe_complete(struct mlx5e_txqsq * sq,struct sk_buff * skb,const struct mlx5e_tx_attr * attr,const struct mlx5e_tx_wqe_attr * wqe_attr,u8 num_dma,struct mlx5e_tx_wqe_info * wi,struct mlx5_wqe_ctrl_seg * cseg,struct mlx5_wqe_eth_seg * eseg,bool xmit_more)375 mlx5e_txwqe_complete(struct mlx5e_txqsq *sq, struct sk_buff *skb,
376 const struct mlx5e_tx_attr *attr,
377 const struct mlx5e_tx_wqe_attr *wqe_attr, u8 num_dma,
378 struct mlx5e_tx_wqe_info *wi, struct mlx5_wqe_ctrl_seg *cseg,
379 struct mlx5_wqe_eth_seg *eseg, bool xmit_more)
380 {
381 struct mlx5_wq_cyc *wq = &sq->wq;
382 bool send_doorbell;
383
384 *wi = (struct mlx5e_tx_wqe_info) {
385 .skb = skb,
386 .num_bytes = attr->num_bytes,
387 .num_dma = num_dma,
388 .num_wqebbs = wqe_attr->num_wqebbs,
389 .num_fifo_pkts = 0,
390 };
391
392 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | attr->opcode);
393 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | wqe_attr->ds_cnt);
394
395 mlx5e_tx_skb_update_ts_flags(skb);
396
397 sq->pc += wi->num_wqebbs;
398
399 mlx5e_tx_check_stop(sq);
400
401 if (unlikely(sq->ptpsq &&
402 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) {
403 u8 metadata_index = be32_to_cpu(eseg->flow_table_metadata);
404
405 mlx5e_ptp_metadata_fifo_pop(&sq->ptpsq->metadata_freelist);
406
407 mlx5e_skb_cb_hwtstamp_init(skb);
408 mlx5e_ptp_metadata_map_put(&sq->ptpsq->metadata_map, skb,
409 metadata_index);
410 /* ensure skb is put on metadata_map before tracking the index */
411 wmb();
412 mlx5e_ptpsq_track_metadata(sq->ptpsq, metadata_index);
413 if (!netif_tx_queue_stopped(sq->txq) &&
414 mlx5e_ptpsq_metadata_freelist_empty(sq->ptpsq)) {
415 netif_tx_stop_queue(sq->txq);
416 sq->stats->stopped++;
417 }
418 skb_get(skb);
419 }
420
421 send_doorbell = __netdev_tx_sent_queue(sq->txq, attr->num_bytes, xmit_more);
422 if (send_doorbell)
423 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, cseg);
424 }
425
426 static void
mlx5e_sq_xmit_wqe(struct mlx5e_txqsq * sq,struct sk_buff * skb,const struct mlx5e_tx_attr * attr,const struct mlx5e_tx_wqe_attr * wqe_attr,struct mlx5e_tx_wqe * wqe,u16 pi,bool xmit_more)427 mlx5e_sq_xmit_wqe(struct mlx5e_txqsq *sq, struct sk_buff *skb,
428 const struct mlx5e_tx_attr *attr, const struct mlx5e_tx_wqe_attr *wqe_attr,
429 struct mlx5e_tx_wqe *wqe, u16 pi, bool xmit_more)
430 {
431 struct mlx5_wqe_ctrl_seg *cseg;
432 struct mlx5_wqe_eth_seg *eseg;
433 struct mlx5_wqe_data_seg *dseg;
434 struct mlx5e_tx_wqe_info *wi;
435 u16 ihs = attr->ihs;
436 struct ipv6hdr *h6;
437 struct mlx5e_sq_stats *stats = sq->stats;
438 int num_dma;
439
440 stats->xmit_more += xmit_more;
441
442 /* fill wqe */
443 wi = &sq->db.wqe_info[pi];
444 cseg = &wqe->ctrl;
445 eseg = &wqe->eth;
446 dseg = wqe->data;
447
448 eseg->mss = attr->mss;
449
450 if (ihs) {
451 u8 *start = eseg->inline_hdr.start;
452
453 if (unlikely(attr->hopbyhop)) {
454 /* remove the HBH header.
455 * Layout: [Ethernet header][IPv6 header][HBH][TCP header]
456 */
457 if (skb_vlan_tag_present(skb)) {
458 mlx5e_insert_vlan(start, skb, ETH_HLEN + sizeof(*h6));
459 ihs += VLAN_HLEN;
460 h6 = (struct ipv6hdr *)(start + sizeof(struct vlan_ethhdr));
461 } else {
462 unsafe_memcpy(start, skb->data,
463 ETH_HLEN + sizeof(*h6),
464 MLX5_UNSAFE_MEMCPY_DISCLAIMER);
465 h6 = (struct ipv6hdr *)(start + ETH_HLEN);
466 }
467 h6->nexthdr = IPPROTO_TCP;
468 /* Copy the TCP header after the IPv6 one */
469 memcpy(h6 + 1,
470 skb->data + ETH_HLEN + sizeof(*h6) +
471 sizeof(struct hop_jumbo_hdr),
472 tcp_hdrlen(skb));
473 /* Leave ipv6 payload_len set to 0, as LSO v2 specs request. */
474 } else if (skb_vlan_tag_present(skb)) {
475 mlx5e_insert_vlan(start, skb, ihs);
476 ihs += VLAN_HLEN;
477 stats->added_vlan_packets++;
478 } else {
479 unsafe_memcpy(eseg->inline_hdr.start, skb->data,
480 attr->ihs,
481 MLX5_UNSAFE_MEMCPY_DISCLAIMER);
482 }
483 eseg->inline_hdr.sz |= cpu_to_be16(ihs);
484 dseg += wqe_attr->ds_cnt_inl;
485 }
486
487 dseg += wqe_attr->ds_cnt_ids;
488 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb->data + attr->ihs + attr->hopbyhop,
489 attr->headlen, dseg);
490 if (unlikely(num_dma < 0))
491 goto err_drop;
492
493 mlx5e_txwqe_complete(sq, skb, attr, wqe_attr, num_dma, wi, cseg, eseg, xmit_more);
494
495 return;
496
497 err_drop:
498 stats->dropped++;
499 dev_kfree_skb_any(skb);
500 mlx5e_tx_flush(sq);
501 }
502
mlx5e_tx_skb_supports_mpwqe(struct sk_buff * skb,struct mlx5e_tx_attr * attr)503 static bool mlx5e_tx_skb_supports_mpwqe(struct sk_buff *skb, struct mlx5e_tx_attr *attr)
504 {
505 return !skb_is_nonlinear(skb) && !skb_vlan_tag_present(skb) && !attr->ihs &&
506 !attr->insz && !mlx5e_macsec_skb_is_offload(skb);
507 }
508
mlx5e_tx_mpwqe_same_eseg(struct mlx5e_txqsq * sq,struct mlx5_wqe_eth_seg * eseg)509 static bool mlx5e_tx_mpwqe_same_eseg(struct mlx5e_txqsq *sq, struct mlx5_wqe_eth_seg *eseg)
510 {
511 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
512
513 /* Assumes the session is already running and has at least one packet. */
514 return !memcmp(&session->wqe->eth, eseg, MLX5E_ACCEL_ESEG_LEN);
515 }
516
mlx5e_tx_mpwqe_session_start(struct mlx5e_txqsq * sq,struct mlx5_wqe_eth_seg * eseg)517 static void mlx5e_tx_mpwqe_session_start(struct mlx5e_txqsq *sq,
518 struct mlx5_wqe_eth_seg *eseg)
519 {
520 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
521 struct mlx5e_tx_wqe *wqe;
522 u16 pi, num_wqebbs;
523
524 pi = mlx5e_txqsq_get_next_pi_anysize(sq, &num_wqebbs);
525 wqe = MLX5E_TX_FETCH_WQE(sq, pi);
526 net_prefetchw(wqe->data);
527
528 *session = (struct mlx5e_tx_mpwqe) {
529 .wqe = wqe,
530 .bytes_count = 0,
531 .ds_count = MLX5E_TX_WQE_EMPTY_DS_COUNT,
532 .ds_count_max = num_wqebbs * MLX5_SEND_WQEBB_NUM_DS,
533 .pkt_count = 0,
534 .inline_on = 0,
535 };
536
537 memcpy(&session->wqe->eth, eseg, MLX5E_ACCEL_ESEG_LEN);
538
539 sq->stats->mpwqe_blks++;
540 }
541
mlx5e_tx_mpwqe_session_is_active(struct mlx5e_txqsq * sq)542 static bool mlx5e_tx_mpwqe_session_is_active(struct mlx5e_txqsq *sq)
543 {
544 return sq->mpwqe.wqe;
545 }
546
mlx5e_tx_mpwqe_add_dseg(struct mlx5e_txqsq * sq,struct mlx5e_xmit_data * txd)547 static void mlx5e_tx_mpwqe_add_dseg(struct mlx5e_txqsq *sq, struct mlx5e_xmit_data *txd)
548 {
549 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
550 struct mlx5_wqe_data_seg *dseg;
551
552 dseg = (struct mlx5_wqe_data_seg *)session->wqe + session->ds_count;
553
554 session->pkt_count++;
555 session->bytes_count += txd->len;
556
557 dseg->addr = cpu_to_be64(txd->dma_addr);
558 dseg->byte_count = cpu_to_be32(txd->len);
559 dseg->lkey = sq->mkey_be;
560 session->ds_count++;
561
562 sq->stats->mpwqe_pkts++;
563 }
564
mlx5e_tx_mpwqe_session_complete(struct mlx5e_txqsq * sq)565 static struct mlx5_wqe_ctrl_seg *mlx5e_tx_mpwqe_session_complete(struct mlx5e_txqsq *sq)
566 {
567 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
568 u8 ds_count = session->ds_count;
569 struct mlx5_wqe_ctrl_seg *cseg;
570 struct mlx5e_tx_wqe_info *wi;
571 u16 pi;
572
573 cseg = &session->wqe->ctrl;
574 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_ENHANCED_MPSW);
575 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_count);
576
577 pi = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->pc);
578 wi = &sq->db.wqe_info[pi];
579 *wi = (struct mlx5e_tx_wqe_info) {
580 .skb = NULL,
581 .num_bytes = session->bytes_count,
582 .num_wqebbs = DIV_ROUND_UP(ds_count, MLX5_SEND_WQEBB_NUM_DS),
583 .num_dma = session->pkt_count,
584 .num_fifo_pkts = session->pkt_count,
585 };
586
587 sq->pc += wi->num_wqebbs;
588
589 session->wqe = NULL;
590
591 mlx5e_tx_check_stop(sq);
592
593 return cseg;
594 }
595
596 static void
mlx5e_sq_xmit_mpwqe(struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5_wqe_eth_seg * eseg,bool xmit_more)597 mlx5e_sq_xmit_mpwqe(struct mlx5e_txqsq *sq, struct sk_buff *skb,
598 struct mlx5_wqe_eth_seg *eseg, bool xmit_more)
599 {
600 struct mlx5_wqe_ctrl_seg *cseg;
601 struct mlx5e_xmit_data txd;
602
603 txd.data = skb->data;
604 txd.len = skb->len;
605
606 txd.dma_addr = dma_map_single(sq->pdev, txd.data, txd.len, DMA_TO_DEVICE);
607 if (unlikely(dma_mapping_error(sq->pdev, txd.dma_addr)))
608 goto err_unmap;
609
610 if (!mlx5e_tx_mpwqe_session_is_active(sq)) {
611 mlx5e_tx_mpwqe_session_start(sq, eseg);
612 } else if (!mlx5e_tx_mpwqe_same_eseg(sq, eseg)) {
613 mlx5e_tx_mpwqe_session_complete(sq);
614 mlx5e_tx_mpwqe_session_start(sq, eseg);
615 }
616
617 sq->stats->xmit_more += xmit_more;
618
619 mlx5e_dma_push_single(sq, txd.dma_addr, txd.len);
620 mlx5e_skb_fifo_push(&sq->db.skb_fifo, skb);
621 mlx5e_tx_mpwqe_add_dseg(sq, &txd);
622 mlx5e_tx_skb_update_ts_flags(skb);
623
624 if (unlikely(mlx5e_tx_mpwqe_is_full(&sq->mpwqe))) {
625 /* Might stop the queue and affect the retval of __netdev_tx_sent_queue. */
626 cseg = mlx5e_tx_mpwqe_session_complete(sq);
627
628 if (__netdev_tx_sent_queue(sq->txq, txd.len, xmit_more))
629 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, cseg);
630 } else if (__netdev_tx_sent_queue(sq->txq, txd.len, xmit_more)) {
631 /* Might stop the queue, but we were asked to ring the doorbell anyway. */
632 cseg = mlx5e_tx_mpwqe_session_complete(sq);
633
634 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, cseg);
635 }
636
637 return;
638
639 err_unmap:
640 sq->stats->dropped++;
641 dev_kfree_skb_any(skb);
642 mlx5e_tx_flush(sq);
643 }
644
mlx5e_tx_mpwqe_ensure_complete(struct mlx5e_txqsq * sq)645 void mlx5e_tx_mpwqe_ensure_complete(struct mlx5e_txqsq *sq)
646 {
647 /* Unlikely in non-MPWQE workloads; not important in MPWQE workloads. */
648 if (unlikely(mlx5e_tx_mpwqe_session_is_active(sq)))
649 mlx5e_tx_mpwqe_session_complete(sq);
650 }
651
mlx5e_cqe_ts_id_eseg(struct mlx5e_ptpsq * ptpsq,struct sk_buff * skb,struct mlx5_wqe_eth_seg * eseg)652 static void mlx5e_cqe_ts_id_eseg(struct mlx5e_ptpsq *ptpsq, struct sk_buff *skb,
653 struct mlx5_wqe_eth_seg *eseg)
654 {
655 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
656 eseg->flow_table_metadata =
657 cpu_to_be32(mlx5e_ptp_metadata_fifo_peek(&ptpsq->metadata_freelist));
658 }
659
mlx5e_txwqe_build_eseg(struct mlx5e_priv * priv,struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5e_accel_tx_state * accel,struct mlx5_wqe_eth_seg * eseg,u16 ihs)660 static void mlx5e_txwqe_build_eseg(struct mlx5e_priv *priv, struct mlx5e_txqsq *sq,
661 struct sk_buff *skb, struct mlx5e_accel_tx_state *accel,
662 struct mlx5_wqe_eth_seg *eseg, u16 ihs)
663 {
664 mlx5e_accel_tx_eseg(priv, skb, eseg, ihs);
665 mlx5e_txwqe_build_eseg_csum(sq, skb, accel, eseg);
666 if (unlikely(sq->ptpsq))
667 mlx5e_cqe_ts_id_eseg(sq->ptpsq, skb, eseg);
668 }
669
mlx5e_xmit(struct sk_buff * skb,struct net_device * dev)670 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev)
671 {
672 struct mlx5e_priv *priv = netdev_priv(dev);
673 struct mlx5e_accel_tx_state accel = {};
674 struct mlx5e_tx_wqe_attr wqe_attr;
675 struct mlx5e_tx_attr attr;
676 struct mlx5e_tx_wqe *wqe;
677 struct mlx5e_txqsq *sq;
678 u16 pi;
679
680 /* All changes to txq2sq are performed in sync with mlx5e_xmit, when the
681 * queue being changed is disabled, and smp_wmb guarantees that the
682 * changes are visible before mlx5e_xmit tries to read from txq2sq. It
683 * guarantees that the value of txq2sq[qid] doesn't change while
684 * mlx5e_xmit is running on queue number qid. smb_wmb is paired with
685 * HARD_TX_LOCK around ndo_start_xmit, which serves as an ACQUIRE.
686 */
687 sq = priv->txq2sq[skb_get_queue_mapping(skb)];
688 if (unlikely(!sq)) {
689 /* Two cases when sq can be NULL:
690 * 1. The HTB node is registered, and mlx5e_select_queue
691 * selected its queue ID, but the SQ itself is not yet created.
692 * 2. HTB SQ creation failed. Similar to the previous case, but
693 * the SQ won't be created.
694 */
695 dev_kfree_skb_any(skb);
696 return NETDEV_TX_OK;
697 }
698
699 /* May send SKBs and WQEs. */
700 if (unlikely(!mlx5e_accel_tx_begin(dev, sq, skb, &accel)))
701 return NETDEV_TX_OK;
702
703 mlx5e_sq_xmit_prepare(sq, skb, &accel, &attr);
704
705 if (test_bit(MLX5E_SQ_STATE_MPWQE, &sq->state)) {
706 if (mlx5e_tx_skb_supports_mpwqe(skb, &attr)) {
707 struct mlx5_wqe_eth_seg eseg = {};
708
709 mlx5e_txwqe_build_eseg(priv, sq, skb, &accel, &eseg, attr.ihs);
710 mlx5e_sq_xmit_mpwqe(sq, skb, &eseg, netdev_xmit_more());
711 return NETDEV_TX_OK;
712 }
713
714 mlx5e_tx_mpwqe_ensure_complete(sq);
715 }
716
717 mlx5e_sq_calc_wqe_attr(skb, &attr, &wqe_attr);
718 pi = mlx5e_txqsq_get_next_pi(sq, wqe_attr.num_wqebbs);
719 wqe = MLX5E_TX_FETCH_WQE(sq, pi);
720
721 /* May update the WQE, but may not post other WQEs. */
722 mlx5e_accel_tx_finish(sq, wqe, &accel,
723 (struct mlx5_wqe_inline_seg *)(wqe->data + wqe_attr.ds_cnt_inl));
724 mlx5e_txwqe_build_eseg(priv, sq, skb, &accel, &wqe->eth, attr.ihs);
725 mlx5e_sq_xmit_wqe(sq, skb, &attr, &wqe_attr, wqe, pi, netdev_xmit_more());
726
727 return NETDEV_TX_OK;
728 }
729
mlx5e_tx_wi_dma_unmap(struct mlx5e_txqsq * sq,struct mlx5e_tx_wqe_info * wi,u32 * dma_fifo_cc)730 static void mlx5e_tx_wi_dma_unmap(struct mlx5e_txqsq *sq, struct mlx5e_tx_wqe_info *wi,
731 u32 *dma_fifo_cc)
732 {
733 int i;
734
735 for (i = 0; i < wi->num_dma; i++) {
736 struct mlx5e_sq_dma *dma = mlx5e_dma_get(sq, (*dma_fifo_cc)++);
737
738 mlx5e_tx_dma_unmap(sq->pdev, dma);
739 }
740 }
741
mlx5e_consume_skb(struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5_cqe64 * cqe,int napi_budget)742 static void mlx5e_consume_skb(struct mlx5e_txqsq *sq, struct sk_buff *skb,
743 struct mlx5_cqe64 *cqe, int napi_budget)
744 {
745 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
746 struct skb_shared_hwtstamps hwts = {};
747 u64 ts = get_cqe_ts(cqe);
748
749 hwts.hwtstamp = mlx5e_cqe_ts_to_ns(sq->ptp_cyc2time, sq->clock, ts);
750 if (sq->ptpsq) {
751 mlx5e_skb_cb_hwtstamp_handler(skb, MLX5E_SKB_CB_CQE_HWTSTAMP,
752 hwts.hwtstamp, sq->ptpsq->cq_stats);
753 } else {
754 skb_tstamp_tx(skb, &hwts);
755 sq->stats->timestamps++;
756 }
757 }
758
759 napi_consume_skb(skb, napi_budget);
760 }
761
mlx5e_tx_wi_consume_fifo_skbs(struct mlx5e_txqsq * sq,struct mlx5e_tx_wqe_info * wi,struct mlx5_cqe64 * cqe,int napi_budget)762 static void mlx5e_tx_wi_consume_fifo_skbs(struct mlx5e_txqsq *sq, struct mlx5e_tx_wqe_info *wi,
763 struct mlx5_cqe64 *cqe, int napi_budget)
764 {
765 int i;
766
767 for (i = 0; i < wi->num_fifo_pkts; i++) {
768 struct sk_buff *skb = mlx5e_skb_fifo_pop(&sq->db.skb_fifo);
769
770 mlx5e_consume_skb(sq, skb, cqe, napi_budget);
771 }
772 }
773
mlx5e_txqsq_wake(struct mlx5e_txqsq * sq)774 void mlx5e_txqsq_wake(struct mlx5e_txqsq *sq)
775 {
776 if (netif_tx_queue_stopped(sq->txq) &&
777 mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, sq->stop_room) &&
778 !mlx5e_ptpsq_metadata_freelist_empty(sq->ptpsq) &&
779 !test_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state)) {
780 netif_tx_wake_queue(sq->txq);
781 sq->stats->wake++;
782 }
783 }
784
mlx5e_poll_tx_cq(struct mlx5e_cq * cq,int napi_budget)785 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget)
786 {
787 struct mlx5e_sq_stats *stats;
788 struct mlx5e_txqsq *sq;
789 struct mlx5_cqe64 *cqe;
790 u32 dma_fifo_cc;
791 u32 nbytes;
792 u16 npkts;
793 u16 sqcc;
794 int i;
795
796 sq = container_of(cq, struct mlx5e_txqsq, cq);
797
798 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
799 return false;
800
801 cqe = mlx5_cqwq_get_cqe(&cq->wq);
802 if (!cqe)
803 return false;
804
805 stats = sq->stats;
806
807 npkts = 0;
808 nbytes = 0;
809
810 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
811 * otherwise a cq overrun may occur
812 */
813 sqcc = sq->cc;
814
815 /* avoid dirtying sq cache line every cqe */
816 dma_fifo_cc = sq->dma_fifo_cc;
817
818 i = 0;
819 do {
820 struct mlx5e_tx_wqe_info *wi;
821 u16 wqe_counter;
822 bool last_wqe;
823 u16 ci;
824
825 mlx5_cqwq_pop(&cq->wq);
826
827 wqe_counter = be16_to_cpu(cqe->wqe_counter);
828
829 do {
830 last_wqe = (sqcc == wqe_counter);
831
832 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
833 wi = &sq->db.wqe_info[ci];
834
835 sqcc += wi->num_wqebbs;
836
837 if (likely(wi->skb)) {
838 mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc);
839 mlx5e_consume_skb(sq, wi->skb, cqe, napi_budget);
840
841 npkts++;
842 nbytes += wi->num_bytes;
843 continue;
844 }
845
846 if (unlikely(mlx5e_ktls_tx_try_handle_resync_dump_comp(sq, wi,
847 &dma_fifo_cc)))
848 continue;
849
850 if (wi->num_fifo_pkts) {
851 mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc);
852 mlx5e_tx_wi_consume_fifo_skbs(sq, wi, cqe, napi_budget);
853
854 npkts += wi->num_fifo_pkts;
855 nbytes += wi->num_bytes;
856 }
857 } while (!last_wqe);
858
859 if (unlikely(get_cqe_opcode(cqe) == MLX5_CQE_REQ_ERR)) {
860 if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING,
861 &sq->state)) {
862 mlx5e_dump_error_cqe(&sq->cq, sq->sqn,
863 (struct mlx5_err_cqe *)cqe);
864 mlx5_wq_cyc_wqe_dump(&sq->wq, ci, wi->num_wqebbs);
865 queue_work(cq->workqueue, &sq->recover_work);
866 }
867 stats->cqe_err++;
868 }
869
870 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
871
872 stats->cqes += i;
873
874 mlx5_cqwq_update_db_record(&cq->wq);
875
876 /* ensure cq space is freed before enabling more cqes */
877 wmb();
878
879 sq->dma_fifo_cc = dma_fifo_cc;
880 sq->cc = sqcc;
881
882 netdev_tx_completed_queue(sq->txq, npkts, nbytes);
883
884 mlx5e_txqsq_wake(sq);
885
886 return (i == MLX5E_TX_CQ_POLL_BUDGET);
887 }
888
mlx5e_tx_wi_kfree_fifo_skbs(struct mlx5e_txqsq * sq,struct mlx5e_tx_wqe_info * wi)889 static void mlx5e_tx_wi_kfree_fifo_skbs(struct mlx5e_txqsq *sq, struct mlx5e_tx_wqe_info *wi)
890 {
891 int i;
892
893 for (i = 0; i < wi->num_fifo_pkts; i++)
894 dev_kfree_skb_any(mlx5e_skb_fifo_pop(&sq->db.skb_fifo));
895 }
896
mlx5e_free_txqsq_descs(struct mlx5e_txqsq * sq)897 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq)
898 {
899 struct mlx5e_tx_wqe_info *wi;
900 u32 dma_fifo_cc, nbytes = 0;
901 u16 ci, sqcc, npkts = 0;
902
903 sqcc = sq->cc;
904 dma_fifo_cc = sq->dma_fifo_cc;
905
906 while (sqcc != sq->pc) {
907 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
908 wi = &sq->db.wqe_info[ci];
909
910 sqcc += wi->num_wqebbs;
911
912 if (likely(wi->skb)) {
913 mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc);
914 dev_kfree_skb_any(wi->skb);
915
916 npkts++;
917 nbytes += wi->num_bytes;
918 continue;
919 }
920
921 if (unlikely(mlx5e_ktls_tx_try_handle_resync_dump_comp(sq, wi, &dma_fifo_cc)))
922 continue;
923
924 if (wi->num_fifo_pkts) {
925 mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc);
926 mlx5e_tx_wi_kfree_fifo_skbs(sq, wi);
927
928 npkts += wi->num_fifo_pkts;
929 nbytes += wi->num_bytes;
930 }
931 }
932
933 sq->dma_fifo_cc = dma_fifo_cc;
934 sq->cc = sqcc;
935
936 netdev_tx_completed_queue(sq->txq, npkts, nbytes);
937 }
938
939 #ifdef CONFIG_MLX5_CORE_IPOIB
940 static inline void
mlx5i_txwqe_build_datagram(struct mlx5_av * av,u32 dqpn,u32 dqkey,struct mlx5_wqe_datagram_seg * dseg)941 mlx5i_txwqe_build_datagram(struct mlx5_av *av, u32 dqpn, u32 dqkey,
942 struct mlx5_wqe_datagram_seg *dseg)
943 {
944 memcpy(&dseg->av, av, sizeof(struct mlx5_av));
945 dseg->av.dqp_dct = cpu_to_be32(dqpn | MLX5_EXTENDED_UD_AV);
946 dseg->av.key.qkey.qkey = cpu_to_be32(dqkey);
947 }
948
mlx5i_sq_calc_wqe_attr(struct sk_buff * skb,const struct mlx5e_tx_attr * attr,struct mlx5e_tx_wqe_attr * wqe_attr)949 static void mlx5i_sq_calc_wqe_attr(struct sk_buff *skb,
950 const struct mlx5e_tx_attr *attr,
951 struct mlx5e_tx_wqe_attr *wqe_attr)
952 {
953 u16 ds_cnt = sizeof(struct mlx5i_tx_wqe) / MLX5_SEND_WQE_DS;
954 u16 ds_cnt_inl = 0;
955
956 ds_cnt += !!attr->headlen + skb_shinfo(skb)->nr_frags;
957
958 if (attr->ihs) {
959 u16 inl = attr->ihs - INL_HDR_START_SZ;
960
961 ds_cnt_inl = DIV_ROUND_UP(inl, MLX5_SEND_WQE_DS);
962 ds_cnt += ds_cnt_inl;
963 }
964
965 *wqe_attr = (struct mlx5e_tx_wqe_attr) {
966 .ds_cnt = ds_cnt,
967 .ds_cnt_inl = ds_cnt_inl,
968 .num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS),
969 };
970 }
971
mlx5i_sq_xmit(struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5_av * av,u32 dqpn,u32 dqkey,bool xmit_more)972 void mlx5i_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
973 struct mlx5_av *av, u32 dqpn, u32 dqkey, bool xmit_more)
974 {
975 struct mlx5e_tx_wqe_attr wqe_attr;
976 struct mlx5e_tx_attr attr;
977 struct mlx5i_tx_wqe *wqe;
978
979 struct mlx5_wqe_datagram_seg *datagram;
980 struct mlx5_wqe_ctrl_seg *cseg;
981 struct mlx5_wqe_eth_seg *eseg;
982 struct mlx5_wqe_data_seg *dseg;
983 struct mlx5e_tx_wqe_info *wi;
984
985 struct mlx5e_sq_stats *stats = sq->stats;
986 int num_dma;
987 u16 pi;
988
989 mlx5e_sq_xmit_prepare(sq, skb, NULL, &attr);
990 mlx5i_sq_calc_wqe_attr(skb, &attr, &wqe_attr);
991
992 pi = mlx5e_txqsq_get_next_pi(sq, wqe_attr.num_wqebbs);
993 wqe = MLX5I_SQ_FETCH_WQE(sq, pi);
994
995 stats->xmit_more += xmit_more;
996
997 /* fill wqe */
998 wi = &sq->db.wqe_info[pi];
999 cseg = &wqe->ctrl;
1000 datagram = &wqe->datagram;
1001 eseg = &wqe->eth;
1002 dseg = wqe->data;
1003
1004 mlx5i_txwqe_build_datagram(av, dqpn, dqkey, datagram);
1005
1006 mlx5e_txwqe_build_eseg_csum(sq, skb, NULL, eseg);
1007
1008 eseg->mss = attr.mss;
1009
1010 if (attr.ihs) {
1011 if (unlikely(attr.hopbyhop)) {
1012 struct ipv6hdr *h6;
1013
1014 /* remove the HBH header.
1015 * Layout: [Ethernet header][IPv6 header][HBH][TCP header]
1016 */
1017 unsafe_memcpy(eseg->inline_hdr.start, skb->data,
1018 ETH_HLEN + sizeof(*h6),
1019 MLX5_UNSAFE_MEMCPY_DISCLAIMER);
1020 h6 = (struct ipv6hdr *)((char *)eseg->inline_hdr.start + ETH_HLEN);
1021 h6->nexthdr = IPPROTO_TCP;
1022 /* Copy the TCP header after the IPv6 one */
1023 unsafe_memcpy(h6 + 1,
1024 skb->data + ETH_HLEN + sizeof(*h6) +
1025 sizeof(struct hop_jumbo_hdr),
1026 tcp_hdrlen(skb),
1027 MLX5_UNSAFE_MEMCPY_DISCLAIMER);
1028 /* Leave ipv6 payload_len set to 0, as LSO v2 specs request. */
1029 } else {
1030 unsafe_memcpy(eseg->inline_hdr.start, skb->data,
1031 attr.ihs,
1032 MLX5_UNSAFE_MEMCPY_DISCLAIMER);
1033 }
1034 eseg->inline_hdr.sz = cpu_to_be16(attr.ihs);
1035 dseg += wqe_attr.ds_cnt_inl;
1036 }
1037
1038 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb->data + attr.ihs + attr.hopbyhop,
1039 attr.headlen, dseg);
1040 if (unlikely(num_dma < 0))
1041 goto err_drop;
1042
1043 mlx5e_txwqe_complete(sq, skb, &attr, &wqe_attr, num_dma, wi, cseg, eseg, xmit_more);
1044
1045 return;
1046
1047 err_drop:
1048 stats->dropped++;
1049 dev_kfree_skb_any(skb);
1050 mlx5e_tx_flush(sq);
1051 }
1052 #endif
1053