1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 // Copyright (c) 2020 Mellanox Technologies
3
4 #include "en/ptp.h"
5 #include "en/health.h"
6 #include "en/txrx.h"
7 #include "en/params.h"
8 #include "en/fs_tt_redirect.h"
9 #include <linux/list.h>
10 #include <linux/spinlock.h>
11 #include <net/netdev_lock.h>
12
13 struct mlx5e_ptp_fs {
14 struct mlx5_flow_handle *l2_rule;
15 struct mlx5_flow_handle *udp_v4_rule;
16 struct mlx5_flow_handle *udp_v6_rule;
17 bool valid;
18 };
19
20 struct mlx5e_ptp_params {
21 struct mlx5e_params params;
22 struct mlx5e_sq_param txq_sq_param;
23 struct mlx5e_rq_param rq_param;
24 };
25
26 struct mlx5e_ptp_port_ts_cqe_tracker {
27 u8 metadata_id;
28 bool inuse : 1;
29 struct list_head entry;
30 };
31
32 struct mlx5e_ptp_port_ts_cqe_list {
33 struct mlx5e_ptp_port_ts_cqe_tracker *nodes;
34 struct list_head tracker_list_head;
35 /* Sync list operations in xmit and napi_poll contexts */
36 spinlock_t tracker_list_lock;
37 };
38
39 static inline void
mlx5e_ptp_port_ts_cqe_list_add(struct mlx5e_ptp_port_ts_cqe_list * list,u8 metadata)40 mlx5e_ptp_port_ts_cqe_list_add(struct mlx5e_ptp_port_ts_cqe_list *list, u8 metadata)
41 {
42 struct mlx5e_ptp_port_ts_cqe_tracker *tracker = &list->nodes[metadata];
43
44 WARN_ON_ONCE(tracker->inuse);
45 tracker->inuse = true;
46 spin_lock_bh(&list->tracker_list_lock);
47 list_add_tail(&tracker->entry, &list->tracker_list_head);
48 spin_unlock_bh(&list->tracker_list_lock);
49 }
50
51 static void
mlx5e_ptp_port_ts_cqe_list_remove(struct mlx5e_ptp_port_ts_cqe_list * list,u8 metadata)52 mlx5e_ptp_port_ts_cqe_list_remove(struct mlx5e_ptp_port_ts_cqe_list *list, u8 metadata)
53 {
54 struct mlx5e_ptp_port_ts_cqe_tracker *tracker = &list->nodes[metadata];
55
56 WARN_ON_ONCE(!tracker->inuse);
57 tracker->inuse = false;
58 spin_lock_bh(&list->tracker_list_lock);
59 list_del(&tracker->entry);
60 spin_unlock_bh(&list->tracker_list_lock);
61 }
62
mlx5e_ptpsq_track_metadata(struct mlx5e_ptpsq * ptpsq,u8 metadata)63 void mlx5e_ptpsq_track_metadata(struct mlx5e_ptpsq *ptpsq, u8 metadata)
64 {
65 mlx5e_ptp_port_ts_cqe_list_add(ptpsq->ts_cqe_pending_list, metadata);
66 }
67
68 struct mlx5e_skb_cb_hwtstamp {
69 ktime_t cqe_hwtstamp;
70 ktime_t port_hwtstamp;
71 };
72
mlx5e_skb_cb_hwtstamp_init(struct sk_buff * skb)73 void mlx5e_skb_cb_hwtstamp_init(struct sk_buff *skb)
74 {
75 memset(skb->cb, 0, sizeof(struct mlx5e_skb_cb_hwtstamp));
76 }
77
mlx5e_skb_cb_get_hwts(struct sk_buff * skb)78 static struct mlx5e_skb_cb_hwtstamp *mlx5e_skb_cb_get_hwts(struct sk_buff *skb)
79 {
80 BUILD_BUG_ON(sizeof(struct mlx5e_skb_cb_hwtstamp) > sizeof(skb->cb));
81 return (struct mlx5e_skb_cb_hwtstamp *)skb->cb;
82 }
83
mlx5e_skb_cb_hwtstamp_tx(struct sk_buff * skb,struct mlx5e_ptp_cq_stats * cq_stats)84 static void mlx5e_skb_cb_hwtstamp_tx(struct sk_buff *skb,
85 struct mlx5e_ptp_cq_stats *cq_stats)
86 {
87 struct skb_shared_hwtstamps hwts = {};
88 ktime_t diff;
89
90 diff = abs(mlx5e_skb_cb_get_hwts(skb)->port_hwtstamp -
91 mlx5e_skb_cb_get_hwts(skb)->cqe_hwtstamp);
92
93 /* Maximal allowed diff is 1 / 128 second */
94 if (diff > (NSEC_PER_SEC >> 7)) {
95 cq_stats->abort++;
96 cq_stats->abort_abs_diff_ns += diff;
97 return;
98 }
99
100 hwts.hwtstamp = mlx5e_skb_cb_get_hwts(skb)->port_hwtstamp;
101 skb_tstamp_tx(skb, &hwts);
102 }
103
mlx5e_skb_cb_hwtstamp_handler(struct sk_buff * skb,int hwtstamp_type,ktime_t hwtstamp,struct mlx5e_ptp_cq_stats * cq_stats)104 void mlx5e_skb_cb_hwtstamp_handler(struct sk_buff *skb, int hwtstamp_type,
105 ktime_t hwtstamp,
106 struct mlx5e_ptp_cq_stats *cq_stats)
107 {
108 switch (hwtstamp_type) {
109 case (MLX5E_SKB_CB_CQE_HWTSTAMP):
110 mlx5e_skb_cb_get_hwts(skb)->cqe_hwtstamp = hwtstamp;
111 break;
112 case (MLX5E_SKB_CB_PORT_HWTSTAMP):
113 mlx5e_skb_cb_get_hwts(skb)->port_hwtstamp = hwtstamp;
114 break;
115 }
116
117 /* If both CQEs arrive, check and report the port tstamp, and clear skb cb as
118 * skb soon to be released.
119 */
120 if (!mlx5e_skb_cb_get_hwts(skb)->cqe_hwtstamp ||
121 !mlx5e_skb_cb_get_hwts(skb)->port_hwtstamp)
122 return;
123
124 mlx5e_skb_cb_hwtstamp_tx(skb, cq_stats);
125 memset(skb->cb, 0, sizeof(struct mlx5e_skb_cb_hwtstamp));
126 }
127
128 static struct sk_buff *
mlx5e_ptp_metadata_map_lookup(struct mlx5e_ptp_metadata_map * map,u16 metadata)129 mlx5e_ptp_metadata_map_lookup(struct mlx5e_ptp_metadata_map *map, u16 metadata)
130 {
131 return map->data[metadata];
132 }
133
134 static struct sk_buff *
mlx5e_ptp_metadata_map_remove(struct mlx5e_ptp_metadata_map * map,u16 metadata)135 mlx5e_ptp_metadata_map_remove(struct mlx5e_ptp_metadata_map *map, u16 metadata)
136 {
137 struct sk_buff *skb;
138
139 skb = map->data[metadata];
140 map->data[metadata] = NULL;
141
142 return skb;
143 }
144
mlx5e_ptp_metadata_map_unhealthy(struct mlx5e_ptp_metadata_map * map)145 static bool mlx5e_ptp_metadata_map_unhealthy(struct mlx5e_ptp_metadata_map *map)
146 {
147 /* Considered beginning unhealthy state if size * 15 / 2^4 cannot be reclaimed. */
148 return map->undelivered_counter > (map->capacity >> 4) * 15;
149 }
150
mlx5e_ptpsq_mark_ts_cqes_undelivered(struct mlx5e_ptpsq * ptpsq,ktime_t port_tstamp)151 static void mlx5e_ptpsq_mark_ts_cqes_undelivered(struct mlx5e_ptpsq *ptpsq,
152 ktime_t port_tstamp)
153 {
154 struct mlx5e_ptp_port_ts_cqe_list *cqe_list = ptpsq->ts_cqe_pending_list;
155 ktime_t timeout = ns_to_ktime(MLX5E_PTP_TS_CQE_UNDELIVERED_TIMEOUT);
156 struct mlx5e_ptp_metadata_map *metadata_map = &ptpsq->metadata_map;
157 struct mlx5e_ptp_port_ts_cqe_tracker *pos, *n;
158
159 spin_lock_bh(&cqe_list->tracker_list_lock);
160 list_for_each_entry_safe(pos, n, &cqe_list->tracker_list_head, entry) {
161 struct sk_buff *skb =
162 mlx5e_ptp_metadata_map_lookup(metadata_map, pos->metadata_id);
163 ktime_t dma_tstamp = mlx5e_skb_cb_get_hwts(skb)->cqe_hwtstamp;
164
165 if (!dma_tstamp ||
166 ktime_after(ktime_add(dma_tstamp, timeout), port_tstamp))
167 break;
168
169 metadata_map->undelivered_counter++;
170 WARN_ON_ONCE(!pos->inuse);
171 pos->inuse = false;
172 list_del(&pos->entry);
173 ptpsq->cq_stats->lost_cqe++;
174 }
175 spin_unlock_bh(&cqe_list->tracker_list_lock);
176 }
177
178 #define PTP_WQE_CTR2IDX(val) ((val) & ptpsq->ts_cqe_ctr_mask)
179
mlx5e_ptp_handle_ts_cqe(struct mlx5e_ptpsq * ptpsq,struct mlx5_cqe64 * cqe,u8 * md_buff,u8 * md_buff_sz,int budget)180 static void mlx5e_ptp_handle_ts_cqe(struct mlx5e_ptpsq *ptpsq,
181 struct mlx5_cqe64 *cqe,
182 u8 *md_buff,
183 u8 *md_buff_sz,
184 int budget)
185 {
186 struct mlx5e_ptp_port_ts_cqe_list *pending_cqe_list = ptpsq->ts_cqe_pending_list;
187 u8 metadata_id = PTP_WQE_CTR2IDX(be16_to_cpu(cqe->wqe_counter));
188 bool is_err_cqe = !!MLX5E_RX_ERR_CQE(cqe);
189 struct mlx5e_txqsq *sq = &ptpsq->txqsq;
190 struct sk_buff *skb;
191 ktime_t hwtstamp;
192
193 if (likely(pending_cqe_list->nodes[metadata_id].inuse)) {
194 mlx5e_ptp_port_ts_cqe_list_remove(pending_cqe_list, metadata_id);
195 } else {
196 /* Reclaim space in the unlikely event CQE was delivered after
197 * marking it late.
198 */
199 ptpsq->metadata_map.undelivered_counter--;
200 ptpsq->cq_stats->late_cqe++;
201 }
202
203 skb = mlx5e_ptp_metadata_map_remove(&ptpsq->metadata_map, metadata_id);
204
205 if (unlikely(is_err_cqe)) {
206 ptpsq->cq_stats->err_cqe++;
207 goto out;
208 }
209
210 hwtstamp = mlx5e_cqe_ts_to_ns(sq->ptp_cyc2time, sq->clock, get_cqe_ts(cqe));
211 mlx5e_skb_cb_hwtstamp_handler(skb, MLX5E_SKB_CB_PORT_HWTSTAMP,
212 hwtstamp, ptpsq->cq_stats);
213 ptpsq->cq_stats->cqe++;
214
215 mlx5e_ptpsq_mark_ts_cqes_undelivered(ptpsq, hwtstamp);
216 out:
217 napi_consume_skb(skb, budget);
218 md_buff[(*md_buff_sz)++] = metadata_id;
219 if (unlikely(mlx5e_ptp_metadata_map_unhealthy(&ptpsq->metadata_map)) &&
220 !test_and_set_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state))
221 queue_work(ptpsq->txqsq.priv->wq, &ptpsq->report_unhealthy_work);
222 }
223
mlx5e_ptp_poll_ts_cq(struct mlx5e_cq * cq,int napi_budget)224 static bool mlx5e_ptp_poll_ts_cq(struct mlx5e_cq *cq, int napi_budget)
225 {
226 struct mlx5e_ptpsq *ptpsq = container_of(cq, struct mlx5e_ptpsq, ts_cq);
227 int budget = min(napi_budget, MLX5E_TX_CQ_POLL_BUDGET);
228 u8 metadata_buff[MLX5E_TX_CQ_POLL_BUDGET];
229 u8 metadata_buff_sz = 0;
230 struct mlx5_cqwq *cqwq;
231 struct mlx5_cqe64 *cqe;
232 int work_done = 0;
233
234 cqwq = &cq->wq;
235
236 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &ptpsq->txqsq.state)))
237 return false;
238
239 cqe = mlx5_cqwq_get_cqe(cqwq);
240 if (!cqe)
241 return false;
242
243 do {
244 mlx5_cqwq_pop(cqwq);
245
246 mlx5e_ptp_handle_ts_cqe(ptpsq, cqe,
247 metadata_buff, &metadata_buff_sz, napi_budget);
248 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(cqwq)));
249
250 mlx5_cqwq_update_db_record(cqwq);
251
252 /* ensure cq space is freed before enabling more cqes */
253 wmb();
254
255 while (metadata_buff_sz > 0)
256 mlx5e_ptp_metadata_fifo_push(&ptpsq->metadata_freelist,
257 metadata_buff[--metadata_buff_sz]);
258
259 mlx5e_txqsq_wake(&ptpsq->txqsq);
260
261 return work_done == budget;
262 }
263
mlx5e_ptp_napi_poll(struct napi_struct * napi,int budget)264 static int mlx5e_ptp_napi_poll(struct napi_struct *napi, int budget)
265 {
266 struct mlx5e_ptp *c = container_of(napi, struct mlx5e_ptp, napi);
267 struct mlx5e_ch_stats *ch_stats = c->stats;
268 struct mlx5e_rq *rq = &c->rq;
269 bool busy = false;
270 int work_done = 0;
271 int i;
272
273 rcu_read_lock();
274
275 ch_stats->poll++;
276
277 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
278 for (i = 0; i < c->num_tc; i++) {
279 busy |= mlx5e_poll_tx_cq(&c->ptpsq[i].txqsq.cq, budget);
280 busy |= mlx5e_ptp_poll_ts_cq(&c->ptpsq[i].ts_cq, budget);
281 }
282 }
283 if (test_bit(MLX5E_PTP_STATE_RX, c->state) && likely(budget)) {
284 work_done = mlx5e_poll_rx_cq(&rq->cq, budget);
285 busy |= work_done == budget;
286 busy |= INDIRECT_CALL_2(rq->post_wqes,
287 mlx5e_post_rx_mpwqes,
288 mlx5e_post_rx_wqes,
289 rq);
290 }
291
292 if (busy) {
293 work_done = budget;
294 goto out;
295 }
296
297 if (unlikely(!napi_complete_done(napi, work_done)))
298 goto out;
299
300 ch_stats->arm++;
301
302 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
303 for (i = 0; i < c->num_tc; i++) {
304 mlx5e_cq_arm(&c->ptpsq[i].txqsq.cq);
305 mlx5e_cq_arm(&c->ptpsq[i].ts_cq);
306 }
307 }
308 if (test_bit(MLX5E_PTP_STATE_RX, c->state))
309 mlx5e_cq_arm(&rq->cq);
310
311 out:
312 rcu_read_unlock();
313
314 return work_done;
315 }
316
mlx5e_ptp_alloc_txqsq(struct mlx5e_ptp * c,int txq_ix,struct mlx5e_params * params,struct mlx5e_sq_param * param,struct mlx5e_txqsq * sq,int tc,struct mlx5e_ptpsq * ptpsq)317 static int mlx5e_ptp_alloc_txqsq(struct mlx5e_ptp *c, int txq_ix,
318 struct mlx5e_params *params,
319 struct mlx5e_sq_param *param,
320 struct mlx5e_txqsq *sq, int tc,
321 struct mlx5e_ptpsq *ptpsq)
322 {
323 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
324 struct mlx5_core_dev *mdev = c->mdev;
325 struct mlx5_wq_cyc *wq = &sq->wq;
326 int err;
327 int node;
328
329 sq->pdev = c->pdev;
330 sq->clock = mdev->clock;
331 sq->mkey_be = c->mkey_be;
332 sq->netdev = c->netdev;
333 sq->priv = c->priv;
334 sq->mdev = mdev;
335 sq->ch_ix = MLX5E_PTP_CHANNEL_IX;
336 sq->txq_ix = txq_ix;
337 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
338 sq->min_inline_mode = params->tx_min_inline_mode;
339 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
340 sq->stats = &c->priv->ptp_stats.sq[tc];
341 sq->ptpsq = ptpsq;
342 INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
343 sq->stop_room = param->stop_room;
344 sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
345
346 node = dev_to_node(mlx5_core_dma_dev(mdev));
347
348 param->wq.db_numa_node = node;
349 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
350 if (err)
351 return err;
352 wq->db = &wq->db[MLX5_SND_DBR];
353
354 err = mlx5e_alloc_txqsq_db(sq, node);
355 if (err)
356 goto err_sq_wq_destroy;
357
358 return 0;
359
360 err_sq_wq_destroy:
361 mlx5_wq_destroy(&sq->wq_ctrl);
362
363 return err;
364 }
365
mlx5e_ptp_destroy_sq(struct mlx5_core_dev * mdev,u32 sqn)366 static void mlx5e_ptp_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
367 {
368 mlx5_core_destroy_sq(mdev, sqn);
369 }
370
mlx5e_ptp_alloc_traffic_db(struct mlx5e_ptpsq * ptpsq,int numa)371 static int mlx5e_ptp_alloc_traffic_db(struct mlx5e_ptpsq *ptpsq, int numa)
372 {
373 struct mlx5e_ptp_metadata_fifo *metadata_freelist = &ptpsq->metadata_freelist;
374 struct mlx5e_ptp_metadata_map *metadata_map = &ptpsq->metadata_map;
375 struct mlx5e_ptp_port_ts_cqe_list *cqe_list;
376 int db_sz;
377 int md;
378
379 cqe_list = kvzalloc_node(sizeof(*ptpsq->ts_cqe_pending_list), GFP_KERNEL, numa);
380 if (!cqe_list)
381 return -ENOMEM;
382 ptpsq->ts_cqe_pending_list = cqe_list;
383
384 db_sz = min_t(u32, mlx5_wq_cyc_get_size(&ptpsq->txqsq.wq),
385 1 << MLX5_CAP_GEN_2(ptpsq->txqsq.mdev,
386 ts_cqe_metadata_size2wqe_counter));
387 ptpsq->ts_cqe_ctr_mask = db_sz - 1;
388
389 cqe_list->nodes = kvzalloc_node(array_size(db_sz, sizeof(*cqe_list->nodes)),
390 GFP_KERNEL, numa);
391 if (!cqe_list->nodes)
392 goto free_cqe_list;
393 INIT_LIST_HEAD(&cqe_list->tracker_list_head);
394 spin_lock_init(&cqe_list->tracker_list_lock);
395
396 metadata_freelist->data =
397 kvzalloc_node(array_size(db_sz, sizeof(*metadata_freelist->data)),
398 GFP_KERNEL, numa);
399 if (!metadata_freelist->data)
400 goto free_cqe_list_nodes;
401 metadata_freelist->mask = ptpsq->ts_cqe_ctr_mask;
402
403 for (md = 0; md < db_sz; ++md) {
404 cqe_list->nodes[md].metadata_id = md;
405 metadata_freelist->data[md] = md;
406 }
407 metadata_freelist->pc = db_sz;
408
409 metadata_map->data =
410 kvzalloc_node(array_size(db_sz, sizeof(*metadata_map->data)),
411 GFP_KERNEL, numa);
412 if (!metadata_map->data)
413 goto free_metadata_freelist;
414 metadata_map->capacity = db_sz;
415
416 return 0;
417
418 free_metadata_freelist:
419 kvfree(metadata_freelist->data);
420 free_cqe_list_nodes:
421 kvfree(cqe_list->nodes);
422 free_cqe_list:
423 kvfree(cqe_list);
424 return -ENOMEM;
425 }
426
mlx5e_ptp_drain_metadata_map(struct mlx5e_ptp_metadata_map * map)427 static void mlx5e_ptp_drain_metadata_map(struct mlx5e_ptp_metadata_map *map)
428 {
429 int idx;
430
431 for (idx = 0; idx < map->capacity; ++idx) {
432 struct sk_buff *skb = map->data[idx];
433
434 dev_kfree_skb_any(skb);
435 }
436 }
437
mlx5e_ptp_free_traffic_db(struct mlx5e_ptpsq * ptpsq)438 static void mlx5e_ptp_free_traffic_db(struct mlx5e_ptpsq *ptpsq)
439 {
440 mlx5e_ptp_drain_metadata_map(&ptpsq->metadata_map);
441 kvfree(ptpsq->metadata_map.data);
442 kvfree(ptpsq->metadata_freelist.data);
443 kvfree(ptpsq->ts_cqe_pending_list->nodes);
444 kvfree(ptpsq->ts_cqe_pending_list);
445 }
446
mlx5e_ptpsq_unhealthy_work(struct work_struct * work)447 static void mlx5e_ptpsq_unhealthy_work(struct work_struct *work)
448 {
449 struct mlx5e_ptpsq *ptpsq =
450 container_of(work, struct mlx5e_ptpsq, report_unhealthy_work);
451 struct mlx5e_txqsq *sq = &ptpsq->txqsq;
452
453 /* Recovering the PTP SQ means re-enabling NAPI, which requires the
454 * netdev instance lock. However, SQ closing has to wait for this work
455 * task to finish while also holding the same lock. So either get the
456 * lock or find that the SQ is no longer enabled and thus this work is
457 * not relevant anymore.
458 */
459 while (!netdev_trylock(sq->netdev)) {
460 if (!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state))
461 return;
462 msleep(20);
463 }
464
465 mlx5e_reporter_tx_ptpsq_unhealthy(ptpsq);
466 netdev_unlock(sq->netdev);
467 }
468
mlx5e_ptp_open_txqsq(struct mlx5e_ptp * c,u32 tisn,int txq_ix,struct mlx5e_ptp_params * cparams,int tc,struct mlx5e_ptpsq * ptpsq)469 static int mlx5e_ptp_open_txqsq(struct mlx5e_ptp *c, u32 tisn,
470 int txq_ix, struct mlx5e_ptp_params *cparams,
471 int tc, struct mlx5e_ptpsq *ptpsq)
472 {
473 struct mlx5e_sq_param *sqp = &cparams->txq_sq_param;
474 struct mlx5e_txqsq *txqsq = &ptpsq->txqsq;
475 struct mlx5e_create_sq_param csp = {};
476 int err;
477
478 err = mlx5e_ptp_alloc_txqsq(c, txq_ix, &cparams->params, sqp,
479 txqsq, tc, ptpsq);
480 if (err)
481 return err;
482
483 csp.tisn = tisn;
484 csp.tis_lst_sz = 1;
485 csp.cqn = txqsq->cq.mcq.cqn;
486 csp.wq_ctrl = &txqsq->wq_ctrl;
487 csp.min_inline_mode = txqsq->min_inline_mode;
488 csp.ts_cqe_to_dest_cqn = ptpsq->ts_cq.mcq.cqn;
489
490 err = mlx5e_create_sq_rdy(c->mdev, sqp, &csp, 0, &txqsq->sqn);
491 if (err)
492 goto err_free_txqsq;
493
494 err = mlx5e_ptp_alloc_traffic_db(ptpsq, dev_to_node(mlx5_core_dma_dev(c->mdev)));
495 if (err)
496 goto err_free_txqsq;
497
498 INIT_WORK(&ptpsq->report_unhealthy_work, mlx5e_ptpsq_unhealthy_work);
499
500 return 0;
501
502 err_free_txqsq:
503 mlx5e_free_txqsq(txqsq);
504
505 return err;
506 }
507
mlx5e_ptp_close_txqsq(struct mlx5e_ptpsq * ptpsq)508 static void mlx5e_ptp_close_txqsq(struct mlx5e_ptpsq *ptpsq)
509 {
510 struct mlx5e_txqsq *sq = &ptpsq->txqsq;
511 struct mlx5_core_dev *mdev = sq->mdev;
512
513 if (current_work() != &ptpsq->report_unhealthy_work)
514 cancel_work_sync(&ptpsq->report_unhealthy_work);
515 mlx5e_ptp_free_traffic_db(ptpsq);
516 cancel_work_sync(&sq->recover_work);
517 mlx5e_ptp_destroy_sq(mdev, sq->sqn);
518 mlx5e_free_txqsq_descs(sq);
519 mlx5e_free_txqsq(sq);
520 }
521
mlx5e_ptp_open_txqsqs(struct mlx5e_ptp * c,struct mlx5e_ptp_params * cparams)522 static int mlx5e_ptp_open_txqsqs(struct mlx5e_ptp *c,
523 struct mlx5e_ptp_params *cparams)
524 {
525 struct mlx5e_params *params = &cparams->params;
526 u8 num_tc = mlx5e_get_dcb_num_tc(params);
527 int ix_base;
528 int err;
529 int tc;
530
531 ix_base = num_tc * params->num_channels;
532
533 for (tc = 0; tc < num_tc; tc++) {
534 int txq_ix = ix_base + tc;
535 u32 tisn;
536
537 tisn = mlx5e_profile_get_tisn(c->mdev, c->priv, c->priv->profile,
538 c->lag_port, tc);
539 err = mlx5e_ptp_open_txqsq(c, tisn, txq_ix, cparams, tc, &c->ptpsq[tc]);
540 if (err)
541 goto close_txqsq;
542 }
543
544 return 0;
545
546 close_txqsq:
547 for (--tc; tc >= 0; tc--)
548 mlx5e_ptp_close_txqsq(&c->ptpsq[tc]);
549
550 return err;
551 }
552
mlx5e_ptp_close_txqsqs(struct mlx5e_ptp * c)553 static void mlx5e_ptp_close_txqsqs(struct mlx5e_ptp *c)
554 {
555 int tc;
556
557 for (tc = 0; tc < c->num_tc; tc++)
558 mlx5e_ptp_close_txqsq(&c->ptpsq[tc]);
559 }
560
mlx5e_ptp_open_tx_cqs(struct mlx5e_ptp * c,struct mlx5e_ptp_params * cparams)561 static int mlx5e_ptp_open_tx_cqs(struct mlx5e_ptp *c,
562 struct mlx5e_ptp_params *cparams)
563 {
564 struct mlx5e_params *params = &cparams->params;
565 struct mlx5e_create_cq_param ccp = {};
566 struct dim_cq_moder ptp_moder = {};
567 struct mlx5e_cq_param *cq_param;
568 u8 num_tc;
569 int err;
570 int tc;
571
572 num_tc = mlx5e_get_dcb_num_tc(params);
573
574 ccp.netdev = c->netdev;
575 ccp.wq = c->priv->wq;
576 ccp.node = dev_to_node(mlx5_core_dma_dev(c->mdev));
577 ccp.ch_stats = c->stats;
578 ccp.napi = &c->napi;
579 ccp.ix = MLX5E_PTP_CHANNEL_IX;
580
581 cq_param = &cparams->txq_sq_param.cqp;
582
583 for (tc = 0; tc < num_tc; tc++) {
584 struct mlx5e_cq *cq = &c->ptpsq[tc].txqsq.cq;
585
586 err = mlx5e_open_cq(c->mdev, ptp_moder, cq_param, &ccp, cq);
587 if (err)
588 goto out_err_txqsq_cq;
589 }
590
591 for (tc = 0; tc < num_tc; tc++) {
592 struct mlx5e_cq *cq = &c->ptpsq[tc].ts_cq;
593 struct mlx5e_ptpsq *ptpsq = &c->ptpsq[tc];
594
595 err = mlx5e_open_cq(c->mdev, ptp_moder, cq_param, &ccp, cq);
596 if (err)
597 goto out_err_ts_cq;
598
599 ptpsq->cq_stats = &c->priv->ptp_stats.cq[tc];
600 }
601
602 return 0;
603
604 out_err_ts_cq:
605 for (--tc; tc >= 0; tc--)
606 mlx5e_close_cq(&c->ptpsq[tc].ts_cq);
607 tc = num_tc;
608 out_err_txqsq_cq:
609 for (--tc; tc >= 0; tc--)
610 mlx5e_close_cq(&c->ptpsq[tc].txqsq.cq);
611
612 return err;
613 }
614
mlx5e_ptp_open_rx_cq(struct mlx5e_ptp * c,struct mlx5e_ptp_params * cparams)615 static int mlx5e_ptp_open_rx_cq(struct mlx5e_ptp *c,
616 struct mlx5e_ptp_params *cparams)
617 {
618 struct mlx5e_create_cq_param ccp = {};
619 struct dim_cq_moder ptp_moder = {};
620 struct mlx5e_cq_param *cq_param;
621 struct mlx5e_cq *cq = &c->rq.cq;
622
623 ccp.netdev = c->netdev;
624 ccp.wq = c->priv->wq;
625 ccp.node = dev_to_node(mlx5_core_dma_dev(c->mdev));
626 ccp.ch_stats = c->stats;
627 ccp.napi = &c->napi;
628 ccp.ix = MLX5E_PTP_CHANNEL_IX;
629
630 cq_param = &cparams->rq_param.cqp;
631
632 return mlx5e_open_cq(c->mdev, ptp_moder, cq_param, &ccp, cq);
633 }
634
mlx5e_ptp_close_tx_cqs(struct mlx5e_ptp * c)635 static void mlx5e_ptp_close_tx_cqs(struct mlx5e_ptp *c)
636 {
637 int tc;
638
639 for (tc = 0; tc < c->num_tc; tc++)
640 mlx5e_close_cq(&c->ptpsq[tc].ts_cq);
641
642 for (tc = 0; tc < c->num_tc; tc++)
643 mlx5e_close_cq(&c->ptpsq[tc].txqsq.cq);
644 }
645
mlx5e_ptp_build_sq_param(struct mlx5_core_dev * mdev,struct mlx5e_params * params,struct mlx5e_sq_param * param)646 static void mlx5e_ptp_build_sq_param(struct mlx5_core_dev *mdev,
647 struct mlx5e_params *params,
648 struct mlx5e_sq_param *param)
649 {
650 void *sqc = param->sqc;
651 void *wq;
652
653 mlx5e_build_sq_param_common(mdev, param);
654
655 wq = MLX5_ADDR_OF(sqc, sqc, wq);
656 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
657 param->stop_room = mlx5e_stop_room_for_max_wqe(mdev);
658 mlx5e_build_tx_cq_param(mdev, params, ¶m->cqp);
659 }
660
mlx5e_ptp_build_rq_param(struct mlx5_core_dev * mdev,struct net_device * netdev,struct mlx5e_ptp_params * ptp_params)661 static void mlx5e_ptp_build_rq_param(struct mlx5_core_dev *mdev,
662 struct net_device *netdev,
663 struct mlx5e_ptp_params *ptp_params)
664 {
665 struct mlx5e_rq_param *rq_params = &ptp_params->rq_param;
666 struct mlx5e_params *params = &ptp_params->params;
667
668 params->rq_wq_type = MLX5_WQ_TYPE_CYCLIC;
669 mlx5e_init_rq_type_params(mdev, params);
670 params->sw_mtu = netdev->max_mtu;
671 mlx5e_build_rq_param(mdev, params, NULL, rq_params);
672 }
673
mlx5e_ptp_build_params(struct mlx5e_ptp * c,struct mlx5e_ptp_params * cparams,struct mlx5e_params * orig)674 static void mlx5e_ptp_build_params(struct mlx5e_ptp *c,
675 struct mlx5e_ptp_params *cparams,
676 struct mlx5e_params *orig)
677 {
678 struct mlx5e_params *params = &cparams->params;
679
680 params->tx_min_inline_mode = orig->tx_min_inline_mode;
681 params->num_channels = orig->num_channels;
682 params->hard_mtu = orig->hard_mtu;
683 params->sw_mtu = orig->sw_mtu;
684 params->mqprio = orig->mqprio;
685
686 /* SQ */
687 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
688 params->log_sq_size =
689 min(MLX5_CAP_GEN_2(c->mdev, ts_cqe_metadata_size2wqe_counter),
690 MLX5E_PTP_MAX_LOG_SQ_SIZE);
691 params->log_sq_size = min(params->log_sq_size, orig->log_sq_size);
692 mlx5e_ptp_build_sq_param(c->mdev, params, &cparams->txq_sq_param);
693 }
694 /* RQ */
695 if (test_bit(MLX5E_PTP_STATE_RX, c->state)) {
696 params->vlan_strip_disable = orig->vlan_strip_disable;
697 mlx5e_ptp_build_rq_param(c->mdev, c->netdev, cparams);
698 }
699 }
700
mlx5e_init_ptp_rq(struct mlx5e_ptp * c,struct mlx5e_params * params,struct mlx5e_rq * rq)701 static int mlx5e_init_ptp_rq(struct mlx5e_ptp *c, struct mlx5e_params *params,
702 struct mlx5e_rq *rq)
703 {
704 struct mlx5_core_dev *mdev = c->mdev;
705 struct mlx5e_priv *priv = c->priv;
706 int err;
707
708 rq->wq_type = params->rq_wq_type;
709 rq->pdev = c->pdev;
710 rq->netdev = priv->netdev;
711 rq->priv = priv;
712 rq->clock = mdev->clock;
713 rq->tstamp = &priv->tstamp;
714 rq->mdev = mdev;
715 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
716 rq->stats = &c->priv->ptp_stats.rq;
717 rq->ix = MLX5E_PTP_CHANNEL_IX;
718 rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
719 err = mlx5e_rq_set_handlers(rq, params, false);
720 if (err)
721 return err;
722
723 return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, 0);
724 }
725
mlx5e_ptp_open_rq(struct mlx5e_ptp * c,struct mlx5e_params * params,struct mlx5e_rq_param * rq_param)726 static int mlx5e_ptp_open_rq(struct mlx5e_ptp *c, struct mlx5e_params *params,
727 struct mlx5e_rq_param *rq_param)
728 {
729 int node = dev_to_node(c->mdev->device);
730 int err, sd_ix;
731 u16 q_counter;
732
733 err = mlx5e_init_ptp_rq(c, params, &c->rq);
734 if (err)
735 return err;
736
737 sd_ix = mlx5_sd_ch_ix_get_dev_ix(c->mdev, MLX5E_PTP_CHANNEL_IX);
738 q_counter = c->priv->q_counter[sd_ix];
739 return mlx5e_open_rq(params, rq_param, NULL, node, q_counter, &c->rq);
740 }
741
mlx5e_ptp_open_queues(struct mlx5e_ptp * c,struct mlx5e_ptp_params * cparams)742 static int mlx5e_ptp_open_queues(struct mlx5e_ptp *c,
743 struct mlx5e_ptp_params *cparams)
744 {
745 int err;
746
747 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
748 err = mlx5e_ptp_open_tx_cqs(c, cparams);
749 if (err)
750 return err;
751
752 err = mlx5e_ptp_open_txqsqs(c, cparams);
753 if (err)
754 goto close_tx_cqs;
755 }
756 if (test_bit(MLX5E_PTP_STATE_RX, c->state)) {
757 err = mlx5e_ptp_open_rx_cq(c, cparams);
758 if (err)
759 goto close_txqsq;
760
761 err = mlx5e_ptp_open_rq(c, &cparams->params, &cparams->rq_param);
762 if (err)
763 goto close_rx_cq;
764 }
765 return 0;
766
767 close_rx_cq:
768 if (test_bit(MLX5E_PTP_STATE_RX, c->state))
769 mlx5e_close_cq(&c->rq.cq);
770 close_txqsq:
771 if (test_bit(MLX5E_PTP_STATE_TX, c->state))
772 mlx5e_ptp_close_txqsqs(c);
773 close_tx_cqs:
774 if (test_bit(MLX5E_PTP_STATE_TX, c->state))
775 mlx5e_ptp_close_tx_cqs(c);
776
777 return err;
778 }
779
mlx5e_ptp_close_queues(struct mlx5e_ptp * c)780 static void mlx5e_ptp_close_queues(struct mlx5e_ptp *c)
781 {
782 if (test_bit(MLX5E_PTP_STATE_RX, c->state)) {
783 mlx5e_close_rq(&c->rq);
784 mlx5e_close_cq(&c->rq.cq);
785 }
786 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
787 mlx5e_ptp_close_txqsqs(c);
788 mlx5e_ptp_close_tx_cqs(c);
789 }
790 }
791
mlx5e_ptp_set_state(struct mlx5e_ptp * c,struct mlx5e_params * params)792 static int mlx5e_ptp_set_state(struct mlx5e_ptp *c, struct mlx5e_params *params)
793 {
794 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_TX_PORT_TS))
795 __set_bit(MLX5E_PTP_STATE_TX, c->state);
796
797 if (params->ptp_rx)
798 __set_bit(MLX5E_PTP_STATE_RX, c->state);
799
800 return bitmap_empty(c->state, MLX5E_PTP_STATE_NUM_STATES) ? -EINVAL : 0;
801 }
802
mlx5e_ptp_rx_unset_fs(struct mlx5e_flow_steering * fs)803 static void mlx5e_ptp_rx_unset_fs(struct mlx5e_flow_steering *fs)
804 {
805 struct mlx5e_ptp_fs *ptp_fs = mlx5e_fs_get_ptp(fs);
806
807 if (!ptp_fs->valid)
808 return;
809
810 mlx5e_fs_tt_redirect_del_rule(ptp_fs->l2_rule);
811 mlx5e_fs_tt_redirect_any_destroy(fs);
812
813 mlx5e_fs_tt_redirect_del_rule(ptp_fs->udp_v6_rule);
814 mlx5e_fs_tt_redirect_del_rule(ptp_fs->udp_v4_rule);
815 mlx5e_fs_tt_redirect_udp_destroy(fs);
816 ptp_fs->valid = false;
817 }
818
mlx5e_ptp_rx_set_fs(struct mlx5e_priv * priv)819 static int mlx5e_ptp_rx_set_fs(struct mlx5e_priv *priv)
820 {
821 u32 tirn = mlx5e_rx_res_get_tirn_ptp(priv->rx_res);
822 struct mlx5e_flow_steering *fs = priv->fs;
823 struct mlx5_flow_handle *rule;
824 struct mlx5e_ptp_fs *ptp_fs;
825 int err;
826
827 ptp_fs = mlx5e_fs_get_ptp(fs);
828 if (ptp_fs->valid)
829 return 0;
830
831 err = mlx5e_fs_tt_redirect_udp_create(fs);
832 if (err)
833 goto out_free;
834
835 rule = mlx5e_fs_tt_redirect_udp_add_rule(fs, MLX5_TT_IPV4_UDP,
836 tirn, PTP_EV_PORT);
837 if (IS_ERR(rule)) {
838 err = PTR_ERR(rule);
839 goto out_destroy_fs_udp;
840 }
841 ptp_fs->udp_v4_rule = rule;
842
843 rule = mlx5e_fs_tt_redirect_udp_add_rule(fs, MLX5_TT_IPV6_UDP,
844 tirn, PTP_EV_PORT);
845 if (IS_ERR(rule)) {
846 err = PTR_ERR(rule);
847 goto out_destroy_udp_v4_rule;
848 }
849 ptp_fs->udp_v6_rule = rule;
850
851 err = mlx5e_fs_tt_redirect_any_create(fs);
852 if (err)
853 goto out_destroy_udp_v6_rule;
854
855 rule = mlx5e_fs_tt_redirect_any_add_rule(fs, tirn, ETH_P_1588);
856 if (IS_ERR(rule)) {
857 err = PTR_ERR(rule);
858 goto out_destroy_fs_any;
859 }
860 ptp_fs->l2_rule = rule;
861 ptp_fs->valid = true;
862
863 return 0;
864
865 out_destroy_fs_any:
866 mlx5e_fs_tt_redirect_any_destroy(fs);
867 out_destroy_udp_v6_rule:
868 mlx5e_fs_tt_redirect_del_rule(ptp_fs->udp_v6_rule);
869 out_destroy_udp_v4_rule:
870 mlx5e_fs_tt_redirect_del_rule(ptp_fs->udp_v4_rule);
871 out_destroy_fs_udp:
872 mlx5e_fs_tt_redirect_udp_destroy(fs);
873 out_free:
874 return err;
875 }
876
mlx5e_ptp_open(struct mlx5e_priv * priv,struct mlx5e_params * params,u8 lag_port,struct mlx5e_ptp ** cp)877 int mlx5e_ptp_open(struct mlx5e_priv *priv, struct mlx5e_params *params,
878 u8 lag_port, struct mlx5e_ptp **cp)
879 {
880 struct net_device *netdev = priv->netdev;
881 struct mlx5_core_dev *mdev = priv->mdev;
882 struct mlx5e_ptp_params *cparams;
883 struct mlx5e_ptp *c;
884 int err;
885
886
887 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, dev_to_node(mlx5_core_dma_dev(mdev)));
888 cparams = kvzalloc(sizeof(*cparams), GFP_KERNEL);
889 if (!c || !cparams) {
890 err = -ENOMEM;
891 goto err_free;
892 }
893
894 c->priv = priv;
895 c->mdev = priv->mdev;
896 c->tstamp = &priv->tstamp;
897 c->pdev = mlx5_core_dma_dev(priv->mdev);
898 c->netdev = priv->netdev;
899 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey);
900 c->num_tc = mlx5e_get_dcb_num_tc(params);
901 c->stats = &priv->ptp_stats.ch;
902 c->lag_port = lag_port;
903
904 err = mlx5e_ptp_set_state(c, params);
905 if (err)
906 goto err_free;
907
908 netif_napi_add_locked(netdev, &c->napi, mlx5e_ptp_napi_poll);
909
910 mlx5e_ptp_build_params(c, cparams, params);
911
912 err = mlx5e_ptp_open_queues(c, cparams);
913 if (unlikely(err))
914 goto err_napi_del;
915
916 if (test_bit(MLX5E_PTP_STATE_RX, c->state))
917 priv->rx_ptp_opened = true;
918
919 *cp = c;
920
921 kvfree(cparams);
922
923 return 0;
924
925 err_napi_del:
926 netif_napi_del_locked(&c->napi);
927 err_free:
928 kvfree(cparams);
929 kvfree(c);
930 return err;
931 }
932
mlx5e_ptp_close(struct mlx5e_ptp * c)933 void mlx5e_ptp_close(struct mlx5e_ptp *c)
934 {
935 mlx5e_ptp_close_queues(c);
936 netif_napi_del_locked(&c->napi);
937
938 kvfree(c);
939 }
940
mlx5e_ptp_activate_channel(struct mlx5e_ptp * c)941 void mlx5e_ptp_activate_channel(struct mlx5e_ptp *c)
942 {
943 int tc;
944
945 napi_enable_locked(&c->napi);
946
947 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
948 for (tc = 0; tc < c->num_tc; tc++)
949 mlx5e_activate_txqsq(&c->ptpsq[tc].txqsq);
950 }
951 if (test_bit(MLX5E_PTP_STATE_RX, c->state)) {
952 mlx5e_ptp_rx_set_fs(c->priv);
953 mlx5e_activate_rq(&c->rq);
954 netif_queue_set_napi(c->netdev, c->rq.ix, NETDEV_QUEUE_TYPE_RX, &c->napi);
955 }
956 mlx5e_trigger_napi_sched(&c->napi);
957 }
958
mlx5e_ptp_deactivate_channel(struct mlx5e_ptp * c)959 void mlx5e_ptp_deactivate_channel(struct mlx5e_ptp *c)
960 {
961 int tc;
962
963 if (test_bit(MLX5E_PTP_STATE_RX, c->state)) {
964 netif_queue_set_napi(c->netdev, c->rq.ix, NETDEV_QUEUE_TYPE_RX, NULL);
965 mlx5e_deactivate_rq(&c->rq);
966 }
967
968 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
969 for (tc = 0; tc < c->num_tc; tc++)
970 mlx5e_deactivate_txqsq(&c->ptpsq[tc].txqsq);
971 }
972
973 napi_disable_locked(&c->napi);
974 }
975
mlx5e_ptp_get_rqn(struct mlx5e_ptp * c,u32 * rqn)976 int mlx5e_ptp_get_rqn(struct mlx5e_ptp *c, u32 *rqn)
977 {
978 if (!c || !test_bit(MLX5E_PTP_STATE_RX, c->state))
979 return -EINVAL;
980
981 *rqn = c->rq.rqn;
982 return 0;
983 }
984
mlx5e_ptp_alloc_rx_fs(struct mlx5e_flow_steering * fs,const struct mlx5e_profile * profile)985 int mlx5e_ptp_alloc_rx_fs(struct mlx5e_flow_steering *fs,
986 const struct mlx5e_profile *profile)
987 {
988 struct mlx5e_ptp_fs *ptp_fs;
989
990 if (!mlx5e_profile_feature_cap(profile, PTP_RX))
991 return 0;
992
993 ptp_fs = kzalloc(sizeof(*ptp_fs), GFP_KERNEL);
994 if (!ptp_fs)
995 return -ENOMEM;
996 mlx5e_fs_set_ptp(fs, ptp_fs);
997
998 return 0;
999 }
1000
mlx5e_ptp_free_rx_fs(struct mlx5e_flow_steering * fs,const struct mlx5e_profile * profile)1001 void mlx5e_ptp_free_rx_fs(struct mlx5e_flow_steering *fs,
1002 const struct mlx5e_profile *profile)
1003 {
1004 struct mlx5e_ptp_fs *ptp_fs = mlx5e_fs_get_ptp(fs);
1005
1006 if (!mlx5e_profile_feature_cap(profile, PTP_RX))
1007 return;
1008
1009 mlx5e_ptp_rx_unset_fs(fs);
1010 kfree(ptp_fs);
1011 }
1012
mlx5e_ptp_rx_manage_fs(struct mlx5e_priv * priv,bool set)1013 int mlx5e_ptp_rx_manage_fs(struct mlx5e_priv *priv, bool set)
1014 {
1015 struct mlx5e_ptp *c = priv->channels.ptp;
1016
1017 if (!mlx5e_profile_feature_cap(priv->profile, PTP_RX))
1018 return 0;
1019
1020 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1021 return 0;
1022
1023 if (set) {
1024 if (!c || !test_bit(MLX5E_PTP_STATE_RX, c->state)) {
1025 netdev_WARN_ONCE(priv->netdev, "Don't try to add PTP RX-FS rules");
1026 return -EINVAL;
1027 }
1028 return mlx5e_ptp_rx_set_fs(priv);
1029 }
1030 /* set == false */
1031 if (c && test_bit(MLX5E_PTP_STATE_RX, c->state)) {
1032 netdev_WARN_ONCE(priv->netdev, "Don't try to remove PTP RX-FS rules");
1033 return -EINVAL;
1034 }
1035 mlx5e_ptp_rx_unset_fs(priv->fs);
1036 return 0;
1037 }
1038