1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2019 Mellanox Technologies. */
3
4 #include "dr_types.h"
5
6 enum dr_action_domain {
7 DR_ACTION_DOMAIN_NIC_INGRESS,
8 DR_ACTION_DOMAIN_NIC_EGRESS,
9 DR_ACTION_DOMAIN_FDB_INGRESS,
10 DR_ACTION_DOMAIN_FDB_EGRESS,
11 DR_ACTION_DOMAIN_MAX,
12 };
13
14 enum dr_action_valid_state {
15 DR_ACTION_STATE_ERR,
16 DR_ACTION_STATE_NO_ACTION,
17 DR_ACTION_STATE_REFORMAT,
18 DR_ACTION_STATE_MODIFY_HDR,
19 DR_ACTION_STATE_MODIFY_VLAN,
20 DR_ACTION_STATE_NON_TERM,
21 DR_ACTION_STATE_TERM,
22 DR_ACTION_STATE_MAX,
23 };
24
25 static const enum dr_action_valid_state
26 next_action_state[DR_ACTION_DOMAIN_MAX][DR_ACTION_STATE_MAX][DR_ACTION_TYP_MAX] = {
27 [DR_ACTION_DOMAIN_NIC_INGRESS] = {
28 [DR_ACTION_STATE_NO_ACTION] = {
29 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
30 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
31 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
32 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_NON_TERM,
33 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
34 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_REFORMAT,
35 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_REFORMAT,
36 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
37 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
38 },
39 [DR_ACTION_STATE_REFORMAT] = {
40 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
41 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
42 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
43 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_REFORMAT,
44 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_REFORMAT,
45 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
46 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
47 },
48 [DR_ACTION_STATE_MODIFY_HDR] = {
49 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
50 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
51 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
52 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_MODIFY_HDR,
53 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR,
54 },
55 [DR_ACTION_STATE_MODIFY_VLAN] = {
56 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
57 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
58 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
59 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_MODIFY_VLAN,
60 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_VLAN,
61 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
62 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
63 },
64 [DR_ACTION_STATE_NON_TERM] = {
65 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
66 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
67 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
68 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_NON_TERM,
69 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
70 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_REFORMAT,
71 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_REFORMAT,
72 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
73 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
74 },
75 [DR_ACTION_STATE_TERM] = {
76 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM,
77 },
78 },
79 [DR_ACTION_DOMAIN_NIC_EGRESS] = {
80 [DR_ACTION_STATE_NO_ACTION] = {
81 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
82 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
83 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
84 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT,
85 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT,
86 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
87 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
88 },
89 [DR_ACTION_STATE_REFORMAT] = {
90 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
91 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
92 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_REFORMAT,
93 },
94 [DR_ACTION_STATE_MODIFY_HDR] = {
95 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
96 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
97 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR,
98 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT,
99 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT,
100 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
101 },
102 [DR_ACTION_STATE_MODIFY_VLAN] = {
103 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
104 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
105 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_VLAN,
106 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
107 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT,
108 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT,
109 },
110 [DR_ACTION_STATE_NON_TERM] = {
111 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
112 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
113 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
114 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT,
115 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT,
116 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
117 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
118 },
119 [DR_ACTION_STATE_TERM] = {
120 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM,
121 },
122 },
123 [DR_ACTION_DOMAIN_FDB_INGRESS] = {
124 [DR_ACTION_STATE_NO_ACTION] = {
125 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
126 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
127 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
128 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_REFORMAT,
129 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_REFORMAT,
130 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
131 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
132 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
133 },
134 [DR_ACTION_STATE_REFORMAT] = {
135 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
136 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
137 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_REFORMAT,
138 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
139 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
140 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
141 },
142 [DR_ACTION_STATE_MODIFY_HDR] = {
143 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
144 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
145 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR,
146 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
147 },
148 [DR_ACTION_STATE_MODIFY_VLAN] = {
149 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
150 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
151 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
152 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_VLAN,
153 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
154 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
155 },
156 [DR_ACTION_STATE_NON_TERM] = {
157 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
158 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
159 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
160 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_REFORMAT,
161 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_REFORMAT,
162 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
163 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
164 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
165 },
166 [DR_ACTION_STATE_TERM] = {
167 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM,
168 },
169 },
170 [DR_ACTION_DOMAIN_FDB_EGRESS] = {
171 [DR_ACTION_STATE_NO_ACTION] = {
172 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
173 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
174 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
175 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
176 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT,
177 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT,
178 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
179 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
180 },
181 [DR_ACTION_STATE_REFORMAT] = {
182 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
183 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
184 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_REFORMAT,
185 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
186 },
187 [DR_ACTION_STATE_MODIFY_HDR] = {
188 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
189 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
190 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR,
191 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT,
192 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT,
193 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
194 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
195 },
196 [DR_ACTION_STATE_MODIFY_VLAN] = {
197 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
198 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
199 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
200 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_VLAN,
201 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT,
202 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT,
203 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
204 },
205 [DR_ACTION_STATE_NON_TERM] = {
206 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
207 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
208 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
209 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
210 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT,
211 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT,
212 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
213 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
214 },
215 [DR_ACTION_STATE_TERM] = {
216 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM,
217 },
218 },
219 };
220
221 struct dr_action_modify_field_conv {
222 u16 hw_field;
223 u8 start;
224 u8 end;
225 u8 l3_type;
226 u8 l4_type;
227 };
228
229 static const struct dr_action_modify_field_conv dr_action_conv_arr[] = {
230 [MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16] = {
231 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_1, .start = 16, .end = 47,
232 },
233 [MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0] = {
234 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_1, .start = 0, .end = 15,
235 },
236 [MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE] = {
237 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_2, .start = 32, .end = 47,
238 },
239 [MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16] = {
240 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_0, .start = 16, .end = 47,
241 },
242 [MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0] = {
243 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_0, .start = 0, .end = 15,
244 },
245 [MLX5_ACTION_IN_FIELD_OUT_IP_DSCP] = {
246 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_1, .start = 0, .end = 5,
247 },
248 [MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS] = {
249 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_0, .start = 48, .end = 56,
250 .l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_TCP,
251 },
252 [MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT] = {
253 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_0, .start = 0, .end = 15,
254 .l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_TCP,
255 },
256 [MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT] = {
257 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_0, .start = 16, .end = 31,
258 .l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_TCP,
259 },
260 [MLX5_ACTION_IN_FIELD_OUT_IP_TTL] = {
261 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_1, .start = 8, .end = 15,
262 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV4,
263 },
264 [MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT] = {
265 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_1, .start = 8, .end = 15,
266 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
267 },
268 [MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT] = {
269 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_0, .start = 0, .end = 15,
270 .l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_UDP,
271 },
272 [MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT] = {
273 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_0, .start = 16, .end = 31,
274 .l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_UDP,
275 },
276 [MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96] = {
277 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_3, .start = 32, .end = 63,
278 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
279 },
280 [MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64] = {
281 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_3, .start = 0, .end = 31,
282 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
283 },
284 [MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32] = {
285 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_4, .start = 32, .end = 63,
286 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
287 },
288 [MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0] = {
289 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_4, .start = 0, .end = 31,
290 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
291 },
292 [MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96] = {
293 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_0, .start = 32, .end = 63,
294 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
295 },
296 [MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64] = {
297 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_0, .start = 0, .end = 31,
298 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
299 },
300 [MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32] = {
301 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_2, .start = 32, .end = 63,
302 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
303 },
304 [MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0] = {
305 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_2, .start = 0, .end = 31,
306 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
307 },
308 [MLX5_ACTION_IN_FIELD_OUT_SIPV4] = {
309 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_0, .start = 0, .end = 31,
310 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV4,
311 },
312 [MLX5_ACTION_IN_FIELD_OUT_DIPV4] = {
313 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_0, .start = 32, .end = 63,
314 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV4,
315 },
316 [MLX5_ACTION_IN_FIELD_METADATA_REG_A] = {
317 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_METADATA, .start = 0, .end = 31,
318 },
319 [MLX5_ACTION_IN_FIELD_METADATA_REG_B] = {
320 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_METADATA, .start = 32, .end = 63,
321 },
322 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_0] = {
323 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_0, .start = 32, .end = 63,
324 },
325 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_1] = {
326 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_0, .start = 0, .end = 31,
327 },
328 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_2] = {
329 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_1, .start = 32, .end = 63,
330 },
331 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_3] = {
332 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_1, .start = 0, .end = 31,
333 },
334 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_4] = {
335 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_2, .start = 32, .end = 63,
336 },
337 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_5] = {
338 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_2, .start = 0, .end = 31,
339 },
340 [MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM] = {
341 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_1, .start = 32, .end = 63,
342 },
343 [MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM] = {
344 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_1, .start = 0, .end = 31,
345 },
346 [MLX5_ACTION_IN_FIELD_OUT_FIRST_VID] = {
347 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_2, .start = 0, .end = 15,
348 },
349 };
350
351 #define MAX_VLANS 2
352 struct dr_action_vlan_info {
353 int count;
354 u32 headers[MAX_VLANS];
355 };
356
357 struct dr_action_apply_attr {
358 u32 modify_index;
359 u16 modify_actions;
360 u32 decap_index;
361 u16 decap_actions;
362 u8 decap_with_vlan:1;
363 u64 final_icm_addr;
364 u32 flow_tag;
365 u32 ctr_id;
366 u16 gvmi;
367 u16 hit_gvmi;
368 u32 reformat_id;
369 u32 reformat_size;
370 struct dr_action_vlan_info vlans;
371 };
372
373 static int
dr_action_reformat_to_action_type(enum mlx5dr_action_reformat_type reformat_type,enum mlx5dr_action_type * action_type)374 dr_action_reformat_to_action_type(enum mlx5dr_action_reformat_type reformat_type,
375 enum mlx5dr_action_type *action_type)
376 {
377 switch (reformat_type) {
378 case DR_ACTION_REFORMAT_TYP_TNL_L2_TO_L2:
379 *action_type = DR_ACTION_TYP_TNL_L2_TO_L2;
380 break;
381 case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L2:
382 *action_type = DR_ACTION_TYP_L2_TO_TNL_L2;
383 break;
384 case DR_ACTION_REFORMAT_TYP_TNL_L3_TO_L2:
385 *action_type = DR_ACTION_TYP_TNL_L3_TO_L2;
386 break;
387 case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L3:
388 *action_type = DR_ACTION_TYP_L2_TO_TNL_L3;
389 break;
390 default:
391 return -EINVAL;
392 }
393
394 return 0;
395 }
396
dr_actions_init_next_ste(u8 ** last_ste,u32 * added_stes,enum mlx5dr_ste_entry_type entry_type,u16 gvmi)397 static void dr_actions_init_next_ste(u8 **last_ste,
398 u32 *added_stes,
399 enum mlx5dr_ste_entry_type entry_type,
400 u16 gvmi)
401 {
402 (*added_stes)++;
403 *last_ste += DR_STE_SIZE;
404 mlx5dr_ste_init(*last_ste, MLX5DR_STE_LU_TYPE_DONT_CARE, entry_type, gvmi);
405 }
406
dr_actions_apply_tx(struct mlx5dr_domain * dmn,u8 * action_type_set,u8 * last_ste,struct dr_action_apply_attr * attr,u32 * added_stes)407 static void dr_actions_apply_tx(struct mlx5dr_domain *dmn,
408 u8 *action_type_set,
409 u8 *last_ste,
410 struct dr_action_apply_attr *attr,
411 u32 *added_stes)
412 {
413 bool encap = action_type_set[DR_ACTION_TYP_L2_TO_TNL_L2] ||
414 action_type_set[DR_ACTION_TYP_L2_TO_TNL_L3];
415
416 /* We want to make sure the modify header comes before L2
417 * encapsulation. The reason for that is that we support
418 * modify headers for outer headers only
419 */
420 if (action_type_set[DR_ACTION_TYP_MODIFY_HDR]) {
421 mlx5dr_ste_set_entry_type(last_ste, MLX5DR_STE_TYPE_MODIFY_PKT);
422 mlx5dr_ste_set_rewrite_actions(last_ste,
423 attr->modify_actions,
424 attr->modify_index);
425 }
426
427 if (action_type_set[DR_ACTION_TYP_PUSH_VLAN]) {
428 int i;
429
430 for (i = 0; i < attr->vlans.count; i++) {
431 if (i || action_type_set[DR_ACTION_TYP_MODIFY_HDR])
432 dr_actions_init_next_ste(&last_ste,
433 added_stes,
434 MLX5DR_STE_TYPE_TX,
435 attr->gvmi);
436
437 mlx5dr_ste_set_tx_push_vlan(last_ste,
438 attr->vlans.headers[i],
439 encap);
440 }
441 }
442
443 if (encap) {
444 /* Modify header and encapsulation require a different STEs.
445 * Since modify header STE format doesn't support encapsulation
446 * tunneling_action.
447 */
448 if (action_type_set[DR_ACTION_TYP_MODIFY_HDR] ||
449 action_type_set[DR_ACTION_TYP_PUSH_VLAN])
450 dr_actions_init_next_ste(&last_ste,
451 added_stes,
452 MLX5DR_STE_TYPE_TX,
453 attr->gvmi);
454
455 mlx5dr_ste_set_tx_encap(last_ste,
456 attr->reformat_id,
457 attr->reformat_size,
458 action_type_set[DR_ACTION_TYP_L2_TO_TNL_L3]);
459 /* Whenever prio_tag_required enabled, we can be sure that the
460 * previous table (ACL) already push vlan to our packet,
461 * And due to HW limitation we need to set this bit, otherwise
462 * push vlan + reformat will not work.
463 */
464 if (MLX5_CAP_GEN(dmn->mdev, prio_tag_required))
465 mlx5dr_ste_set_go_back_bit(last_ste);
466 }
467
468 if (action_type_set[DR_ACTION_TYP_CTR])
469 mlx5dr_ste_set_counter_id(last_ste, attr->ctr_id);
470 }
471
dr_actions_apply_rx(u8 * action_type_set,u8 * last_ste,struct dr_action_apply_attr * attr,u32 * added_stes)472 static void dr_actions_apply_rx(u8 *action_type_set,
473 u8 *last_ste,
474 struct dr_action_apply_attr *attr,
475 u32 *added_stes)
476 {
477 if (action_type_set[DR_ACTION_TYP_CTR])
478 mlx5dr_ste_set_counter_id(last_ste, attr->ctr_id);
479
480 if (action_type_set[DR_ACTION_TYP_TNL_L3_TO_L2]) {
481 mlx5dr_ste_set_entry_type(last_ste, MLX5DR_STE_TYPE_MODIFY_PKT);
482 mlx5dr_ste_set_rx_decap_l3(last_ste, attr->decap_with_vlan);
483 mlx5dr_ste_set_rewrite_actions(last_ste,
484 attr->decap_actions,
485 attr->decap_index);
486 }
487
488 if (action_type_set[DR_ACTION_TYP_TNL_L2_TO_L2])
489 mlx5dr_ste_set_rx_decap(last_ste);
490
491 if (action_type_set[DR_ACTION_TYP_POP_VLAN]) {
492 int i;
493
494 for (i = 0; i < attr->vlans.count; i++) {
495 if (i ||
496 action_type_set[DR_ACTION_TYP_TNL_L2_TO_L2] ||
497 action_type_set[DR_ACTION_TYP_TNL_L3_TO_L2])
498 dr_actions_init_next_ste(&last_ste,
499 added_stes,
500 MLX5DR_STE_TYPE_RX,
501 attr->gvmi);
502
503 mlx5dr_ste_set_rx_pop_vlan(last_ste);
504 }
505 }
506
507 if (action_type_set[DR_ACTION_TYP_MODIFY_HDR]) {
508 if (mlx5dr_ste_get_entry_type(last_ste) == MLX5DR_STE_TYPE_MODIFY_PKT)
509 dr_actions_init_next_ste(&last_ste,
510 added_stes,
511 MLX5DR_STE_TYPE_MODIFY_PKT,
512 attr->gvmi);
513 else
514 mlx5dr_ste_set_entry_type(last_ste, MLX5DR_STE_TYPE_MODIFY_PKT);
515
516 mlx5dr_ste_set_rewrite_actions(last_ste,
517 attr->modify_actions,
518 attr->modify_index);
519 }
520
521 if (action_type_set[DR_ACTION_TYP_TAG]) {
522 if (mlx5dr_ste_get_entry_type(last_ste) == MLX5DR_STE_TYPE_MODIFY_PKT)
523 dr_actions_init_next_ste(&last_ste,
524 added_stes,
525 MLX5DR_STE_TYPE_RX,
526 attr->gvmi);
527
528 mlx5dr_ste_rx_set_flow_tag(last_ste, attr->flow_tag);
529 }
530 }
531
532 /* Apply the actions on the rule STE array starting from the last_ste.
533 * Actions might require more than one STE, new_num_stes will return
534 * the new size of the STEs array, rule with actions.
535 */
dr_actions_apply(struct mlx5dr_domain * dmn,enum mlx5dr_ste_entry_type ste_type,u8 * action_type_set,u8 * last_ste,struct dr_action_apply_attr * attr,u32 * new_num_stes)536 static void dr_actions_apply(struct mlx5dr_domain *dmn,
537 enum mlx5dr_ste_entry_type ste_type,
538 u8 *action_type_set,
539 u8 *last_ste,
540 struct dr_action_apply_attr *attr,
541 u32 *new_num_stes)
542 {
543 u32 added_stes = 0;
544
545 if (ste_type == MLX5DR_STE_TYPE_RX)
546 dr_actions_apply_rx(action_type_set, last_ste, attr, &added_stes);
547 else
548 dr_actions_apply_tx(dmn, action_type_set, last_ste, attr, &added_stes);
549
550 last_ste += added_stes * DR_STE_SIZE;
551 *new_num_stes += added_stes;
552
553 mlx5dr_ste_set_hit_gvmi(last_ste, attr->hit_gvmi);
554 mlx5dr_ste_set_hit_addr(last_ste, attr->final_icm_addr, 1);
555 }
556
557 static enum dr_action_domain
dr_action_get_action_domain(enum mlx5dr_domain_type domain,enum mlx5dr_ste_entry_type ste_type)558 dr_action_get_action_domain(enum mlx5dr_domain_type domain,
559 enum mlx5dr_ste_entry_type ste_type)
560 {
561 switch (domain) {
562 case MLX5DR_DOMAIN_TYPE_NIC_RX:
563 return DR_ACTION_DOMAIN_NIC_INGRESS;
564 case MLX5DR_DOMAIN_TYPE_NIC_TX:
565 return DR_ACTION_DOMAIN_NIC_EGRESS;
566 case MLX5DR_DOMAIN_TYPE_FDB:
567 if (ste_type == MLX5DR_STE_TYPE_RX)
568 return DR_ACTION_DOMAIN_FDB_INGRESS;
569 return DR_ACTION_DOMAIN_FDB_EGRESS;
570 default:
571 WARN_ON(true);
572 return DR_ACTION_DOMAIN_MAX;
573 }
574 }
575
576 static
dr_action_validate_and_get_next_state(enum dr_action_domain action_domain,u32 action_type,u32 * state)577 int dr_action_validate_and_get_next_state(enum dr_action_domain action_domain,
578 u32 action_type,
579 u32 *state)
580 {
581 u32 cur_state = *state;
582
583 /* Check action state machine is valid */
584 *state = next_action_state[action_domain][cur_state][action_type];
585
586 if (*state == DR_ACTION_STATE_ERR)
587 return -EOPNOTSUPP;
588
589 return 0;
590 }
591
dr_action_handle_cs_recalc(struct mlx5dr_domain * dmn,struct mlx5dr_action * dest_action,u64 * final_icm_addr)592 static int dr_action_handle_cs_recalc(struct mlx5dr_domain *dmn,
593 struct mlx5dr_action *dest_action,
594 u64 *final_icm_addr)
595 {
596 int ret;
597
598 switch (dest_action->action_type) {
599 case DR_ACTION_TYP_FT:
600 /* Allow destination flow table only if table is a terminating
601 * table, since there is an *assumption* that in such case FW
602 * will recalculate the CS.
603 */
604 if (dest_action->dest_tbl.is_fw_tbl) {
605 *final_icm_addr = dest_action->dest_tbl.fw_tbl.rx_icm_addr;
606 } else {
607 mlx5dr_dbg(dmn,
608 "Destination FT should be terminating when modify TTL is used\n");
609 return -EINVAL;
610 }
611 break;
612
613 case DR_ACTION_TYP_VPORT:
614 /* If destination is vport we will get the FW flow table
615 * that recalculates the CS and forwards to the vport.
616 */
617 ret = mlx5dr_domain_cache_get_recalc_cs_ft_addr(dest_action->vport.dmn,
618 dest_action->vport.caps->num,
619 final_icm_addr);
620 if (ret) {
621 mlx5dr_err(dmn, "Failed to get FW cs recalc flow table\n");
622 return ret;
623 }
624 break;
625
626 default:
627 break;
628 }
629
630 return 0;
631 }
632
633 #define WITH_VLAN_NUM_HW_ACTIONS 6
634
mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher * matcher,struct mlx5dr_matcher_rx_tx * nic_matcher,struct mlx5dr_action * actions[],u32 num_actions,u8 * ste_arr,u32 * new_hw_ste_arr_sz)635 int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher,
636 struct mlx5dr_matcher_rx_tx *nic_matcher,
637 struct mlx5dr_action *actions[],
638 u32 num_actions,
639 u8 *ste_arr,
640 u32 *new_hw_ste_arr_sz)
641 {
642 struct mlx5dr_domain_rx_tx *nic_dmn = nic_matcher->nic_tbl->nic_dmn;
643 bool rx_rule = nic_dmn->ste_type == MLX5DR_STE_TYPE_RX;
644 struct mlx5dr_domain *dmn = matcher->tbl->dmn;
645 u8 action_type_set[DR_ACTION_TYP_MAX] = {};
646 struct mlx5dr_action *dest_action = NULL;
647 u32 state = DR_ACTION_STATE_NO_ACTION;
648 struct dr_action_apply_attr attr = {};
649 enum dr_action_domain action_domain;
650 bool recalc_cs_required = false;
651 u8 *last_ste;
652 int i, ret;
653
654 attr.gvmi = dmn->info.caps.gvmi;
655 attr.hit_gvmi = dmn->info.caps.gvmi;
656 attr.final_icm_addr = nic_dmn->default_icm_addr;
657 action_domain = dr_action_get_action_domain(dmn->type, nic_dmn->ste_type);
658
659 for (i = 0; i < num_actions; i++) {
660 struct mlx5dr_action *action;
661 int max_actions_type = 1;
662 u32 action_type;
663
664 action = actions[i];
665 action_type = action->action_type;
666
667 switch (action_type) {
668 case DR_ACTION_TYP_DROP:
669 attr.final_icm_addr = nic_dmn->drop_icm_addr;
670 break;
671 case DR_ACTION_TYP_FT:
672 dest_action = action;
673 if (!action->dest_tbl.is_fw_tbl) {
674 if (action->dest_tbl.tbl->dmn != dmn) {
675 mlx5dr_err(dmn,
676 "Destination table belongs to a different domain\n");
677 goto out_invalid_arg;
678 }
679 if (action->dest_tbl.tbl->level <= matcher->tbl->level) {
680 mlx5_core_warn_once(dmn->mdev,
681 "Connecting table to a lower/same level destination table\n");
682 mlx5dr_dbg(dmn,
683 "Connecting table at level %d to a destination table at level %d\n",
684 matcher->tbl->level,
685 action->dest_tbl.tbl->level);
686 }
687 attr.final_icm_addr = rx_rule ?
688 action->dest_tbl.tbl->rx.s_anchor->chunk->icm_addr :
689 action->dest_tbl.tbl->tx.s_anchor->chunk->icm_addr;
690 } else {
691 struct mlx5dr_cmd_query_flow_table_details output;
692 int ret;
693
694 /* get the relevant addresses */
695 if (!action->dest_tbl.fw_tbl.rx_icm_addr) {
696 ret = mlx5dr_cmd_query_flow_table(dmn->mdev,
697 action->dest_tbl.fw_tbl.type,
698 action->dest_tbl.fw_tbl.id,
699 &output);
700 if (!ret) {
701 action->dest_tbl.fw_tbl.tx_icm_addr =
702 output.sw_owner_icm_root_1;
703 action->dest_tbl.fw_tbl.rx_icm_addr =
704 output.sw_owner_icm_root_0;
705 } else {
706 mlx5dr_err(dmn,
707 "Failed mlx5_cmd_query_flow_table ret: %d\n",
708 ret);
709 return ret;
710 }
711 }
712 attr.final_icm_addr = rx_rule ?
713 action->dest_tbl.fw_tbl.rx_icm_addr :
714 action->dest_tbl.fw_tbl.tx_icm_addr;
715 }
716 break;
717 case DR_ACTION_TYP_QP:
718 mlx5dr_info(dmn, "Domain doesn't support QP\n");
719 goto out_invalid_arg;
720 case DR_ACTION_TYP_CTR:
721 attr.ctr_id = action->ctr.ctr_id +
722 action->ctr.offeset;
723 break;
724 case DR_ACTION_TYP_TAG:
725 attr.flow_tag = action->flow_tag;
726 break;
727 case DR_ACTION_TYP_TNL_L2_TO_L2:
728 break;
729 case DR_ACTION_TYP_TNL_L3_TO_L2:
730 attr.decap_index = action->rewrite.index;
731 attr.decap_actions = action->rewrite.num_of_actions;
732 attr.decap_with_vlan =
733 attr.decap_actions == WITH_VLAN_NUM_HW_ACTIONS;
734 break;
735 case DR_ACTION_TYP_MODIFY_HDR:
736 attr.modify_index = action->rewrite.index;
737 attr.modify_actions = action->rewrite.num_of_actions;
738 recalc_cs_required = action->rewrite.modify_ttl;
739 break;
740 case DR_ACTION_TYP_L2_TO_TNL_L2:
741 case DR_ACTION_TYP_L2_TO_TNL_L3:
742 attr.reformat_size = action->reformat.reformat_size;
743 attr.reformat_id = action->reformat.reformat_id;
744 break;
745 case DR_ACTION_TYP_VPORT:
746 attr.hit_gvmi = action->vport.caps->vhca_gvmi;
747 dest_action = action;
748 if (rx_rule) {
749 /* Loopback on WIRE vport is not supported */
750 if (action->vport.caps->num == WIRE_PORT)
751 goto out_invalid_arg;
752
753 attr.final_icm_addr = action->vport.caps->icm_address_rx;
754 } else {
755 attr.final_icm_addr = action->vport.caps->icm_address_tx;
756 }
757 break;
758 case DR_ACTION_TYP_POP_VLAN:
759 max_actions_type = MAX_VLANS;
760 attr.vlans.count++;
761 break;
762 case DR_ACTION_TYP_PUSH_VLAN:
763 max_actions_type = MAX_VLANS;
764 if (attr.vlans.count == MAX_VLANS)
765 return -EINVAL;
766
767 attr.vlans.headers[attr.vlans.count++] = action->push_vlan.vlan_hdr;
768 break;
769 default:
770 goto out_invalid_arg;
771 }
772
773 /* Check action duplication */
774 if (++action_type_set[action_type] > max_actions_type) {
775 mlx5dr_err(dmn, "Action type %d supports only max %d time(s)\n",
776 action_type, max_actions_type);
777 goto out_invalid_arg;
778 }
779
780 /* Check action state machine is valid */
781 if (dr_action_validate_and_get_next_state(action_domain,
782 action_type,
783 &state)) {
784 mlx5dr_err(dmn, "Invalid action sequence provided\n");
785 return -EOPNOTSUPP;
786 }
787 }
788
789 *new_hw_ste_arr_sz = nic_matcher->num_of_builders;
790 last_ste = ste_arr + DR_STE_SIZE * (nic_matcher->num_of_builders - 1);
791
792 /* Due to a HW bug, modifying TTL on RX flows will cause an incorrect
793 * checksum calculation. In this case we will use a FW table to
794 * recalculate.
795 */
796 if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB &&
797 rx_rule && recalc_cs_required && dest_action) {
798 ret = dr_action_handle_cs_recalc(dmn, dest_action, &attr.final_icm_addr);
799 if (ret) {
800 mlx5dr_err(dmn,
801 "Failed to handle checksum recalculation err %d\n",
802 ret);
803 return ret;
804 }
805 }
806
807 dr_actions_apply(dmn,
808 nic_dmn->ste_type,
809 action_type_set,
810 last_ste,
811 &attr,
812 new_hw_ste_arr_sz);
813
814 return 0;
815
816 out_invalid_arg:
817 return -EINVAL;
818 }
819
820 #define CVLAN_ETHERTYPE 0x8100
821 #define SVLAN_ETHERTYPE 0x88a8
822 #define HDR_LEN_L2_ONLY 14
823 #define HDR_LEN_L2_VLAN 18
824 #define REWRITE_HW_ACTION_NUM 6
825
dr_actions_l2_rewrite(struct mlx5dr_domain * dmn,struct mlx5dr_action * action,void * data,size_t data_sz)826 static int dr_actions_l2_rewrite(struct mlx5dr_domain *dmn,
827 struct mlx5dr_action *action,
828 void *data, size_t data_sz)
829 {
830 struct mlx5_ifc_l2_hdr_bits *l2_hdr = data;
831 u64 ops[REWRITE_HW_ACTION_NUM] = {};
832 u32 hdr_fld_4b;
833 u16 hdr_fld_2b;
834 u16 vlan_type;
835 bool vlan;
836 int i = 0;
837 int ret;
838
839 vlan = (data_sz != HDR_LEN_L2_ONLY);
840
841 /* dmac_47_16 */
842 MLX5_SET(dr_action_hw_set, ops + i,
843 opcode, MLX5DR_ACTION_MDFY_HW_OP_SET);
844 MLX5_SET(dr_action_hw_set, ops + i,
845 destination_length, 0);
846 MLX5_SET(dr_action_hw_set, ops + i,
847 destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_0);
848 MLX5_SET(dr_action_hw_set, ops + i,
849 destination_left_shifter, 16);
850 hdr_fld_4b = MLX5_GET(l2_hdr, l2_hdr, dmac_47_16);
851 MLX5_SET(dr_action_hw_set, ops + i,
852 inline_data, hdr_fld_4b);
853 i++;
854
855 /* smac_47_16 */
856 MLX5_SET(dr_action_hw_set, ops + i,
857 opcode, MLX5DR_ACTION_MDFY_HW_OP_SET);
858 MLX5_SET(dr_action_hw_set, ops + i,
859 destination_length, 0);
860 MLX5_SET(dr_action_hw_set, ops + i,
861 destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_1);
862 MLX5_SET(dr_action_hw_set, ops + i,
863 destination_left_shifter, 16);
864 hdr_fld_4b = (MLX5_GET(l2_hdr, l2_hdr, smac_31_0) >> 16 |
865 MLX5_GET(l2_hdr, l2_hdr, smac_47_32) << 16);
866 MLX5_SET(dr_action_hw_set, ops + i,
867 inline_data, hdr_fld_4b);
868 i++;
869
870 /* dmac_15_0 */
871 MLX5_SET(dr_action_hw_set, ops + i,
872 opcode, MLX5DR_ACTION_MDFY_HW_OP_SET);
873 MLX5_SET(dr_action_hw_set, ops + i,
874 destination_length, 16);
875 MLX5_SET(dr_action_hw_set, ops + i,
876 destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_0);
877 MLX5_SET(dr_action_hw_set, ops + i,
878 destination_left_shifter, 0);
879 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, dmac_15_0);
880 MLX5_SET(dr_action_hw_set, ops + i,
881 inline_data, hdr_fld_2b);
882 i++;
883
884 /* ethertype + (optional) vlan */
885 MLX5_SET(dr_action_hw_set, ops + i,
886 opcode, MLX5DR_ACTION_MDFY_HW_OP_SET);
887 MLX5_SET(dr_action_hw_set, ops + i,
888 destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_2);
889 MLX5_SET(dr_action_hw_set, ops + i,
890 destination_left_shifter, 32);
891 if (!vlan) {
892 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, ethertype);
893 MLX5_SET(dr_action_hw_set, ops + i, inline_data, hdr_fld_2b);
894 MLX5_SET(dr_action_hw_set, ops + i, destination_length, 16);
895 } else {
896 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, ethertype);
897 vlan_type = hdr_fld_2b == SVLAN_ETHERTYPE ? DR_STE_SVLAN : DR_STE_CVLAN;
898 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, vlan);
899 hdr_fld_4b = (vlan_type << 16) | hdr_fld_2b;
900 MLX5_SET(dr_action_hw_set, ops + i, inline_data, hdr_fld_4b);
901 MLX5_SET(dr_action_hw_set, ops + i, destination_length, 18);
902 }
903 i++;
904
905 /* smac_15_0 */
906 MLX5_SET(dr_action_hw_set, ops + i,
907 opcode, MLX5DR_ACTION_MDFY_HW_OP_SET);
908 MLX5_SET(dr_action_hw_set, ops + i,
909 destination_length, 16);
910 MLX5_SET(dr_action_hw_set, ops + i,
911 destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_1);
912 MLX5_SET(dr_action_hw_set, ops + i,
913 destination_left_shifter, 0);
914 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, smac_31_0);
915 MLX5_SET(dr_action_hw_set, ops + i,
916 inline_data, hdr_fld_2b);
917 i++;
918
919 if (vlan) {
920 MLX5_SET(dr_action_hw_set, ops + i,
921 opcode, MLX5DR_ACTION_MDFY_HW_OP_SET);
922 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, vlan_type);
923 MLX5_SET(dr_action_hw_set, ops + i,
924 inline_data, hdr_fld_2b);
925 MLX5_SET(dr_action_hw_set, ops + i,
926 destination_length, 16);
927 MLX5_SET(dr_action_hw_set, ops + i,
928 destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_2);
929 MLX5_SET(dr_action_hw_set, ops + i,
930 destination_left_shifter, 0);
931 i++;
932 }
933
934 action->rewrite.data = (void *)ops;
935 action->rewrite.num_of_actions = i;
936
937 ret = mlx5dr_send_postsend_action(dmn, action);
938 if (ret) {
939 mlx5dr_dbg(dmn, "Writing encapsulation action to ICM failed\n");
940 return ret;
941 }
942
943 return 0;
944 }
945
946 static struct mlx5dr_action *
dr_action_create_generic(enum mlx5dr_action_type action_type)947 dr_action_create_generic(enum mlx5dr_action_type action_type)
948 {
949 struct mlx5dr_action *action;
950
951 action = kzalloc(sizeof(*action), GFP_KERNEL);
952 if (!action)
953 return NULL;
954
955 action->action_type = action_type;
956 refcount_set(&action->refcount, 1);
957
958 return action;
959 }
960
mlx5dr_action_create_drop(void)961 struct mlx5dr_action *mlx5dr_action_create_drop(void)
962 {
963 return dr_action_create_generic(DR_ACTION_TYP_DROP);
964 }
965
966 struct mlx5dr_action *
mlx5dr_action_create_dest_table_num(struct mlx5dr_domain * dmn,u32 table_num)967 mlx5dr_action_create_dest_table_num(struct mlx5dr_domain *dmn, u32 table_num)
968 {
969 struct mlx5dr_action *action;
970
971 action = dr_action_create_generic(DR_ACTION_TYP_FT);
972 if (!action)
973 return NULL;
974
975 action->dest_tbl.is_fw_tbl = true;
976 action->dest_tbl.fw_tbl.dmn = dmn;
977 action->dest_tbl.fw_tbl.id = table_num;
978 action->dest_tbl.fw_tbl.type = FS_FT_FDB;
979 refcount_inc(&dmn->refcount);
980
981 return action;
982 }
983
984 struct mlx5dr_action *
mlx5dr_action_create_dest_table(struct mlx5dr_table * tbl)985 mlx5dr_action_create_dest_table(struct mlx5dr_table *tbl)
986 {
987 struct mlx5dr_action *action;
988
989 refcount_inc(&tbl->refcount);
990
991 action = dr_action_create_generic(DR_ACTION_TYP_FT);
992 if (!action)
993 goto dec_ref;
994
995 action->dest_tbl.tbl = tbl;
996
997 return action;
998
999 dec_ref:
1000 refcount_dec(&tbl->refcount);
1001 return NULL;
1002 }
1003
1004 struct mlx5dr_action *
mlx5dr_action_create_mult_dest_tbl(struct mlx5dr_domain * dmn,struct mlx5dr_action_dest * dests,u32 num_of_dests)1005 mlx5dr_action_create_mult_dest_tbl(struct mlx5dr_domain *dmn,
1006 struct mlx5dr_action_dest *dests,
1007 u32 num_of_dests)
1008 {
1009 struct mlx5dr_cmd_flow_destination_hw_info *hw_dests;
1010 struct mlx5dr_action **ref_actions;
1011 struct mlx5dr_action *action;
1012 bool reformat_req = false;
1013 u32 num_of_ref = 0;
1014 int ret;
1015 int i;
1016
1017 if (dmn->type != MLX5DR_DOMAIN_TYPE_FDB) {
1018 mlx5dr_err(dmn, "Multiple destination support is for FDB only\n");
1019 return NULL;
1020 }
1021
1022 hw_dests = kzalloc(sizeof(*hw_dests) * num_of_dests, GFP_KERNEL);
1023 if (!hw_dests)
1024 return NULL;
1025
1026 ref_actions = kzalloc(sizeof(*ref_actions) * num_of_dests * 2, GFP_KERNEL);
1027 if (!ref_actions)
1028 goto free_hw_dests;
1029
1030 for (i = 0; i < num_of_dests; i++) {
1031 struct mlx5dr_action *reformat_action = dests[i].reformat;
1032 struct mlx5dr_action *dest_action = dests[i].dest;
1033
1034 ref_actions[num_of_ref++] = dest_action;
1035
1036 switch (dest_action->action_type) {
1037 case DR_ACTION_TYP_VPORT:
1038 hw_dests[i].vport.flags = MLX5_FLOW_DEST_VPORT_VHCA_ID;
1039 hw_dests[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1040 hw_dests[i].vport.num = dest_action->vport.caps->num;
1041 hw_dests[i].vport.vhca_id = dest_action->vport.caps->vhca_gvmi;
1042 if (reformat_action) {
1043 reformat_req = true;
1044 hw_dests[i].vport.reformat_id =
1045 reformat_action->reformat.reformat_id;
1046 ref_actions[num_of_ref++] = reformat_action;
1047 hw_dests[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
1048 }
1049 break;
1050
1051 case DR_ACTION_TYP_FT:
1052 hw_dests[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1053 if (dest_action->dest_tbl.is_fw_tbl)
1054 hw_dests[i].ft_id = dest_action->dest_tbl.fw_tbl.id;
1055 else
1056 hw_dests[i].ft_id = dest_action->dest_tbl.tbl->table_id;
1057 break;
1058
1059 default:
1060 mlx5dr_dbg(dmn, "Invalid multiple destinations action\n");
1061 goto free_ref_actions;
1062 }
1063 }
1064
1065 action = dr_action_create_generic(DR_ACTION_TYP_FT);
1066 if (!action)
1067 goto free_ref_actions;
1068
1069 ret = mlx5dr_fw_create_md_tbl(dmn,
1070 hw_dests,
1071 num_of_dests,
1072 reformat_req,
1073 &action->dest_tbl.fw_tbl.id,
1074 &action->dest_tbl.fw_tbl.group_id);
1075 if (ret)
1076 goto free_action;
1077
1078 refcount_inc(&dmn->refcount);
1079
1080 for (i = 0; i < num_of_ref; i++)
1081 refcount_inc(&ref_actions[i]->refcount);
1082
1083 action->dest_tbl.is_fw_tbl = true;
1084 action->dest_tbl.fw_tbl.dmn = dmn;
1085 action->dest_tbl.fw_tbl.type = FS_FT_FDB;
1086 action->dest_tbl.fw_tbl.ref_actions = ref_actions;
1087 action->dest_tbl.fw_tbl.num_of_ref_actions = num_of_ref;
1088
1089 kfree(hw_dests);
1090
1091 return action;
1092
1093 free_action:
1094 kfree(action);
1095 free_ref_actions:
1096 kfree(ref_actions);
1097 free_hw_dests:
1098 kfree(hw_dests);
1099 return NULL;
1100 }
1101
1102 struct mlx5dr_action *
mlx5dr_action_create_dest_flow_fw_table(struct mlx5dr_domain * dmn,struct mlx5_flow_table * ft)1103 mlx5dr_action_create_dest_flow_fw_table(struct mlx5dr_domain *dmn,
1104 struct mlx5_flow_table *ft)
1105 {
1106 struct mlx5dr_action *action;
1107
1108 action = dr_action_create_generic(DR_ACTION_TYP_FT);
1109 if (!action)
1110 return NULL;
1111
1112 action->dest_tbl.is_fw_tbl = 1;
1113 action->dest_tbl.fw_tbl.type = ft->type;
1114 action->dest_tbl.fw_tbl.id = ft->id;
1115 action->dest_tbl.fw_tbl.dmn = dmn;
1116
1117 refcount_inc(&dmn->refcount);
1118
1119 return action;
1120 }
1121
1122 struct mlx5dr_action *
mlx5dr_action_create_flow_counter(u32 counter_id)1123 mlx5dr_action_create_flow_counter(u32 counter_id)
1124 {
1125 struct mlx5dr_action *action;
1126
1127 action = dr_action_create_generic(DR_ACTION_TYP_CTR);
1128 if (!action)
1129 return NULL;
1130
1131 action->ctr.ctr_id = counter_id;
1132
1133 return action;
1134 }
1135
mlx5dr_action_create_tag(u32 tag_value)1136 struct mlx5dr_action *mlx5dr_action_create_tag(u32 tag_value)
1137 {
1138 struct mlx5dr_action *action;
1139
1140 action = dr_action_create_generic(DR_ACTION_TYP_TAG);
1141 if (!action)
1142 return NULL;
1143
1144 action->flow_tag = tag_value & 0xffffff;
1145
1146 return action;
1147 }
1148
1149 static int
dr_action_verify_reformat_params(enum mlx5dr_action_type reformat_type,struct mlx5dr_domain * dmn,size_t data_sz,void * data)1150 dr_action_verify_reformat_params(enum mlx5dr_action_type reformat_type,
1151 struct mlx5dr_domain *dmn,
1152 size_t data_sz,
1153 void *data)
1154 {
1155 if ((!data && data_sz) || (data && !data_sz) || reformat_type >
1156 DR_ACTION_TYP_L2_TO_TNL_L3) {
1157 mlx5dr_dbg(dmn, "Invalid reformat parameter!\n");
1158 goto out_err;
1159 }
1160
1161 if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB)
1162 return 0;
1163
1164 if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_RX) {
1165 if (reformat_type != DR_ACTION_TYP_TNL_L2_TO_L2 &&
1166 reformat_type != DR_ACTION_TYP_TNL_L3_TO_L2) {
1167 mlx5dr_dbg(dmn, "Action reformat type not support on RX domain\n");
1168 goto out_err;
1169 }
1170 } else if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_TX) {
1171 if (reformat_type != DR_ACTION_TYP_L2_TO_TNL_L2 &&
1172 reformat_type != DR_ACTION_TYP_L2_TO_TNL_L3) {
1173 mlx5dr_dbg(dmn, "Action reformat type not support on TX domain\n");
1174 goto out_err;
1175 }
1176 }
1177
1178 return 0;
1179
1180 out_err:
1181 return -EINVAL;
1182 }
1183
1184 #define ACTION_CACHE_LINE_SIZE 64
1185
1186 static int
dr_action_create_reformat_action(struct mlx5dr_domain * dmn,size_t data_sz,void * data,struct mlx5dr_action * action)1187 dr_action_create_reformat_action(struct mlx5dr_domain *dmn,
1188 size_t data_sz, void *data,
1189 struct mlx5dr_action *action)
1190 {
1191 u32 reformat_id;
1192 int ret;
1193
1194 switch (action->action_type) {
1195 case DR_ACTION_TYP_L2_TO_TNL_L2:
1196 case DR_ACTION_TYP_L2_TO_TNL_L3:
1197 {
1198 enum mlx5_reformat_ctx_type rt;
1199
1200 if (action->action_type == DR_ACTION_TYP_L2_TO_TNL_L2)
1201 rt = MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL;
1202 else
1203 rt = MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
1204
1205 ret = mlx5dr_cmd_create_reformat_ctx(dmn->mdev, rt, data_sz, data,
1206 &reformat_id);
1207 if (ret)
1208 return ret;
1209
1210 action->reformat.reformat_id = reformat_id;
1211 action->reformat.reformat_size = data_sz;
1212 return 0;
1213 }
1214 case DR_ACTION_TYP_TNL_L2_TO_L2:
1215 {
1216 return 0;
1217 }
1218 case DR_ACTION_TYP_TNL_L3_TO_L2:
1219 {
1220 /* Only Ethernet frame is supported, with VLAN (18) or without (14) */
1221 if (data_sz != HDR_LEN_L2_ONLY && data_sz != HDR_LEN_L2_VLAN)
1222 return -EINVAL;
1223
1224 action->rewrite.chunk = mlx5dr_icm_alloc_chunk(dmn->action_icm_pool,
1225 DR_CHUNK_SIZE_8);
1226 if (!action->rewrite.chunk)
1227 return -ENOMEM;
1228
1229 action->rewrite.index = (action->rewrite.chunk->icm_addr -
1230 dmn->info.caps.hdr_modify_icm_addr) /
1231 ACTION_CACHE_LINE_SIZE;
1232
1233 ret = dr_actions_l2_rewrite(dmn, action, data, data_sz);
1234 if (ret) {
1235 mlx5dr_icm_free_chunk(action->rewrite.chunk);
1236 return ret;
1237 }
1238 return 0;
1239 }
1240 default:
1241 mlx5dr_info(dmn, "Reformat type is not supported %d\n", action->action_type);
1242 return -EINVAL;
1243 }
1244 }
1245
mlx5dr_action_create_pop_vlan(void)1246 struct mlx5dr_action *mlx5dr_action_create_pop_vlan(void)
1247 {
1248 return dr_action_create_generic(DR_ACTION_TYP_POP_VLAN);
1249 }
1250
mlx5dr_action_create_push_vlan(struct mlx5dr_domain * dmn,__be32 vlan_hdr)1251 struct mlx5dr_action *mlx5dr_action_create_push_vlan(struct mlx5dr_domain *dmn,
1252 __be32 vlan_hdr)
1253 {
1254 u32 vlan_hdr_h = ntohl(vlan_hdr);
1255 u16 ethertype = vlan_hdr_h >> 16;
1256 struct mlx5dr_action *action;
1257
1258 if (ethertype != SVLAN_ETHERTYPE && ethertype != CVLAN_ETHERTYPE) {
1259 mlx5dr_dbg(dmn, "Invalid vlan ethertype\n");
1260 return NULL;
1261 }
1262
1263 action = dr_action_create_generic(DR_ACTION_TYP_PUSH_VLAN);
1264 if (!action)
1265 return NULL;
1266
1267 action->push_vlan.vlan_hdr = vlan_hdr_h;
1268 return action;
1269 }
1270
1271 struct mlx5dr_action *
mlx5dr_action_create_packet_reformat(struct mlx5dr_domain * dmn,enum mlx5dr_action_reformat_type reformat_type,size_t data_sz,void * data)1272 mlx5dr_action_create_packet_reformat(struct mlx5dr_domain *dmn,
1273 enum mlx5dr_action_reformat_type reformat_type,
1274 size_t data_sz,
1275 void *data)
1276 {
1277 enum mlx5dr_action_type action_type;
1278 struct mlx5dr_action *action;
1279 int ret;
1280
1281 refcount_inc(&dmn->refcount);
1282
1283 /* General checks */
1284 ret = dr_action_reformat_to_action_type(reformat_type, &action_type);
1285 if (ret) {
1286 mlx5dr_dbg(dmn, "Invalid reformat_type provided\n");
1287 goto dec_ref;
1288 }
1289
1290 ret = dr_action_verify_reformat_params(action_type, dmn, data_sz, data);
1291 if (ret)
1292 goto dec_ref;
1293
1294 action = dr_action_create_generic(action_type);
1295 if (!action)
1296 goto dec_ref;
1297
1298 action->reformat.dmn = dmn;
1299
1300 ret = dr_action_create_reformat_action(dmn,
1301 data_sz,
1302 data,
1303 action);
1304 if (ret) {
1305 mlx5dr_dbg(dmn, "Failed creating reformat action %d\n", ret);
1306 goto free_action;
1307 }
1308
1309 return action;
1310
1311 free_action:
1312 kfree(action);
1313 dec_ref:
1314 refcount_dec(&dmn->refcount);
1315 return NULL;
1316 }
1317
1318 static const struct dr_action_modify_field_conv *
dr_action_modify_get_hw_info(u16 sw_field)1319 dr_action_modify_get_hw_info(u16 sw_field)
1320 {
1321 const struct dr_action_modify_field_conv *hw_action_info;
1322
1323 if (sw_field >= ARRAY_SIZE(dr_action_conv_arr))
1324 goto not_found;
1325
1326 hw_action_info = &dr_action_conv_arr[sw_field];
1327 if (!hw_action_info->end && !hw_action_info->start)
1328 goto not_found;
1329
1330 return hw_action_info;
1331
1332 not_found:
1333 return NULL;
1334 }
1335
1336 static int
dr_action_modify_sw_to_hw_add(struct mlx5dr_domain * dmn,__be64 * sw_action,__be64 * hw_action,const struct dr_action_modify_field_conv ** ret_hw_info)1337 dr_action_modify_sw_to_hw_add(struct mlx5dr_domain *dmn,
1338 __be64 *sw_action,
1339 __be64 *hw_action,
1340 const struct dr_action_modify_field_conv **ret_hw_info)
1341 {
1342 const struct dr_action_modify_field_conv *hw_action_info;
1343 u8 max_length;
1344 u16 sw_field;
1345 u32 data;
1346
1347 /* Get SW modify action data */
1348 sw_field = MLX5_GET(set_action_in, sw_action, field);
1349 data = MLX5_GET(set_action_in, sw_action, data);
1350
1351 /* Convert SW data to HW modify action format */
1352 hw_action_info = dr_action_modify_get_hw_info(sw_field);
1353 if (!hw_action_info) {
1354 mlx5dr_dbg(dmn, "Modify add action invalid field given\n");
1355 return -EINVAL;
1356 }
1357
1358 max_length = hw_action_info->end - hw_action_info->start + 1;
1359
1360 MLX5_SET(dr_action_hw_set, hw_action,
1361 opcode, MLX5DR_ACTION_MDFY_HW_OP_ADD);
1362
1363 MLX5_SET(dr_action_hw_set, hw_action, destination_field_code,
1364 hw_action_info->hw_field);
1365
1366 MLX5_SET(dr_action_hw_set, hw_action, destination_left_shifter,
1367 hw_action_info->start);
1368
1369 /* PRM defines that length zero specific length of 32bits */
1370 MLX5_SET(dr_action_hw_set, hw_action, destination_length,
1371 max_length == 32 ? 0 : max_length);
1372
1373 MLX5_SET(dr_action_hw_set, hw_action, inline_data, data);
1374
1375 *ret_hw_info = hw_action_info;
1376
1377 return 0;
1378 }
1379
1380 static int
dr_action_modify_sw_to_hw_set(struct mlx5dr_domain * dmn,__be64 * sw_action,__be64 * hw_action,const struct dr_action_modify_field_conv ** ret_hw_info)1381 dr_action_modify_sw_to_hw_set(struct mlx5dr_domain *dmn,
1382 __be64 *sw_action,
1383 __be64 *hw_action,
1384 const struct dr_action_modify_field_conv **ret_hw_info)
1385 {
1386 const struct dr_action_modify_field_conv *hw_action_info;
1387 u8 offset, length, max_length;
1388 u16 sw_field;
1389 u32 data;
1390
1391 /* Get SW modify action data */
1392 length = MLX5_GET(set_action_in, sw_action, length);
1393 offset = MLX5_GET(set_action_in, sw_action, offset);
1394 sw_field = MLX5_GET(set_action_in, sw_action, field);
1395 data = MLX5_GET(set_action_in, sw_action, data);
1396
1397 /* Convert SW data to HW modify action format */
1398 hw_action_info = dr_action_modify_get_hw_info(sw_field);
1399 if (!hw_action_info) {
1400 mlx5dr_dbg(dmn, "Modify set action invalid field given\n");
1401 return -EINVAL;
1402 }
1403
1404 /* PRM defines that length zero specific length of 32bits */
1405 length = length ? length : 32;
1406
1407 max_length = hw_action_info->end - hw_action_info->start + 1;
1408
1409 if (length + offset > max_length) {
1410 mlx5dr_dbg(dmn, "Modify action length + offset exceeds limit\n");
1411 return -EINVAL;
1412 }
1413
1414 MLX5_SET(dr_action_hw_set, hw_action,
1415 opcode, MLX5DR_ACTION_MDFY_HW_OP_SET);
1416
1417 MLX5_SET(dr_action_hw_set, hw_action, destination_field_code,
1418 hw_action_info->hw_field);
1419
1420 MLX5_SET(dr_action_hw_set, hw_action, destination_left_shifter,
1421 hw_action_info->start + offset);
1422
1423 MLX5_SET(dr_action_hw_set, hw_action, destination_length,
1424 length == 32 ? 0 : length);
1425
1426 MLX5_SET(dr_action_hw_set, hw_action, inline_data, data);
1427
1428 *ret_hw_info = hw_action_info;
1429
1430 return 0;
1431 }
1432
1433 static int
dr_action_modify_sw_to_hw_copy(struct mlx5dr_domain * dmn,__be64 * sw_action,__be64 * hw_action,const struct dr_action_modify_field_conv ** ret_dst_hw_info,const struct dr_action_modify_field_conv ** ret_src_hw_info)1434 dr_action_modify_sw_to_hw_copy(struct mlx5dr_domain *dmn,
1435 __be64 *sw_action,
1436 __be64 *hw_action,
1437 const struct dr_action_modify_field_conv **ret_dst_hw_info,
1438 const struct dr_action_modify_field_conv **ret_src_hw_info)
1439 {
1440 u8 src_offset, dst_offset, src_max_length, dst_max_length, length;
1441 const struct dr_action_modify_field_conv *hw_dst_action_info;
1442 const struct dr_action_modify_field_conv *hw_src_action_info;
1443 u16 src_field, dst_field;
1444
1445 /* Get SW modify action data */
1446 src_field = MLX5_GET(copy_action_in, sw_action, src_field);
1447 dst_field = MLX5_GET(copy_action_in, sw_action, dst_field);
1448 src_offset = MLX5_GET(copy_action_in, sw_action, src_offset);
1449 dst_offset = MLX5_GET(copy_action_in, sw_action, dst_offset);
1450 length = MLX5_GET(copy_action_in, sw_action, length);
1451
1452 /* Convert SW data to HW modify action format */
1453 hw_src_action_info = dr_action_modify_get_hw_info(src_field);
1454 hw_dst_action_info = dr_action_modify_get_hw_info(dst_field);
1455 if (!hw_src_action_info || !hw_dst_action_info) {
1456 mlx5dr_dbg(dmn, "Modify copy action invalid field given\n");
1457 return -EINVAL;
1458 }
1459
1460 /* PRM defines that length zero specific length of 32bits */
1461 length = length ? length : 32;
1462
1463 src_max_length = hw_src_action_info->end -
1464 hw_src_action_info->start + 1;
1465 dst_max_length = hw_dst_action_info->end -
1466 hw_dst_action_info->start + 1;
1467
1468 if (length + src_offset > src_max_length ||
1469 length + dst_offset > dst_max_length) {
1470 mlx5dr_dbg(dmn, "Modify action length + offset exceeds limit\n");
1471 return -EINVAL;
1472 }
1473
1474 MLX5_SET(dr_action_hw_copy, hw_action,
1475 opcode, MLX5DR_ACTION_MDFY_HW_OP_COPY);
1476
1477 MLX5_SET(dr_action_hw_copy, hw_action, destination_field_code,
1478 hw_dst_action_info->hw_field);
1479
1480 MLX5_SET(dr_action_hw_copy, hw_action, destination_left_shifter,
1481 hw_dst_action_info->start + dst_offset);
1482
1483 MLX5_SET(dr_action_hw_copy, hw_action, destination_length,
1484 length == 32 ? 0 : length);
1485
1486 MLX5_SET(dr_action_hw_copy, hw_action, source_field_code,
1487 hw_src_action_info->hw_field);
1488
1489 MLX5_SET(dr_action_hw_copy, hw_action, source_left_shifter,
1490 hw_src_action_info->start + dst_offset);
1491
1492 *ret_dst_hw_info = hw_dst_action_info;
1493 *ret_src_hw_info = hw_src_action_info;
1494
1495 return 0;
1496 }
1497
1498 static int
dr_action_modify_sw_to_hw(struct mlx5dr_domain * dmn,__be64 * sw_action,__be64 * hw_action,const struct dr_action_modify_field_conv ** ret_dst_hw_info,const struct dr_action_modify_field_conv ** ret_src_hw_info)1499 dr_action_modify_sw_to_hw(struct mlx5dr_domain *dmn,
1500 __be64 *sw_action,
1501 __be64 *hw_action,
1502 const struct dr_action_modify_field_conv **ret_dst_hw_info,
1503 const struct dr_action_modify_field_conv **ret_src_hw_info)
1504 {
1505 u8 action;
1506 int ret;
1507
1508 *hw_action = 0;
1509 *ret_src_hw_info = NULL;
1510
1511 /* Get SW modify action type */
1512 action = MLX5_GET(set_action_in, sw_action, action_type);
1513
1514 switch (action) {
1515 case MLX5_ACTION_TYPE_SET:
1516 ret = dr_action_modify_sw_to_hw_set(dmn, sw_action,
1517 hw_action,
1518 ret_dst_hw_info);
1519 break;
1520
1521 case MLX5_ACTION_TYPE_ADD:
1522 ret = dr_action_modify_sw_to_hw_add(dmn, sw_action,
1523 hw_action,
1524 ret_dst_hw_info);
1525 break;
1526
1527 case MLX5_ACTION_TYPE_COPY:
1528 ret = dr_action_modify_sw_to_hw_copy(dmn, sw_action,
1529 hw_action,
1530 ret_dst_hw_info,
1531 ret_src_hw_info);
1532 break;
1533
1534 default:
1535 mlx5dr_info(dmn, "Unsupported action_type for modify action\n");
1536 ret = -EOPNOTSUPP;
1537 }
1538
1539 return ret;
1540 }
1541
1542 static int
dr_action_modify_check_set_field_limitation(struct mlx5dr_action * action,const __be64 * sw_action)1543 dr_action_modify_check_set_field_limitation(struct mlx5dr_action *action,
1544 const __be64 *sw_action)
1545 {
1546 u16 sw_field = MLX5_GET(set_action_in, sw_action, field);
1547 struct mlx5dr_domain *dmn = action->rewrite.dmn;
1548
1549 if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_A) {
1550 action->rewrite.allow_rx = 0;
1551 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_TX) {
1552 mlx5dr_dbg(dmn, "Unsupported field %d for RX/FDB set action\n",
1553 sw_field);
1554 return -EINVAL;
1555 }
1556 } else if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_B) {
1557 action->rewrite.allow_tx = 0;
1558 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_RX) {
1559 mlx5dr_dbg(dmn, "Unsupported field %d for TX/FDB set action\n",
1560 sw_field);
1561 return -EINVAL;
1562 }
1563 }
1564
1565 if (!action->rewrite.allow_rx && !action->rewrite.allow_tx) {
1566 mlx5dr_dbg(dmn, "Modify SET actions not supported on both RX and TX\n");
1567 return -EINVAL;
1568 }
1569
1570 return 0;
1571 }
1572
1573 static int
dr_action_modify_check_add_field_limitation(struct mlx5dr_action * action,const __be64 * sw_action)1574 dr_action_modify_check_add_field_limitation(struct mlx5dr_action *action,
1575 const __be64 *sw_action)
1576 {
1577 u16 sw_field = MLX5_GET(set_action_in, sw_action, field);
1578 struct mlx5dr_domain *dmn = action->rewrite.dmn;
1579
1580 if (sw_field != MLX5_ACTION_IN_FIELD_OUT_IP_TTL &&
1581 sw_field != MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT &&
1582 sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM &&
1583 sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM) {
1584 mlx5dr_dbg(dmn, "Unsupported field %d for add action\n",
1585 sw_field);
1586 return -EINVAL;
1587 }
1588
1589 return 0;
1590 }
1591
1592 static int
dr_action_modify_check_copy_field_limitation(struct mlx5dr_action * action,const __be64 * sw_action)1593 dr_action_modify_check_copy_field_limitation(struct mlx5dr_action *action,
1594 const __be64 *sw_action)
1595 {
1596 struct mlx5dr_domain *dmn = action->rewrite.dmn;
1597 u16 sw_fields[2];
1598 int i;
1599
1600 sw_fields[0] = MLX5_GET(copy_action_in, sw_action, src_field);
1601 sw_fields[1] = MLX5_GET(copy_action_in, sw_action, dst_field);
1602
1603 for (i = 0; i < 2; i++) {
1604 if (sw_fields[i] == MLX5_ACTION_IN_FIELD_METADATA_REG_A) {
1605 action->rewrite.allow_rx = 0;
1606 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_TX) {
1607 mlx5dr_dbg(dmn, "Unsupported field %d for RX/FDB set action\n",
1608 sw_fields[i]);
1609 return -EINVAL;
1610 }
1611 } else if (sw_fields[i] == MLX5_ACTION_IN_FIELD_METADATA_REG_B) {
1612 action->rewrite.allow_tx = 0;
1613 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_RX) {
1614 mlx5dr_dbg(dmn, "Unsupported field %d for TX/FDB set action\n",
1615 sw_fields[i]);
1616 return -EINVAL;
1617 }
1618 }
1619 }
1620
1621 if (!action->rewrite.allow_rx && !action->rewrite.allow_tx) {
1622 mlx5dr_dbg(dmn, "Modify copy actions not supported on both RX and TX\n");
1623 return -EINVAL;
1624 }
1625
1626 return 0;
1627 }
1628
1629 static int
dr_action_modify_check_field_limitation(struct mlx5dr_action * action,const __be64 * sw_action)1630 dr_action_modify_check_field_limitation(struct mlx5dr_action *action,
1631 const __be64 *sw_action)
1632 {
1633 struct mlx5dr_domain *dmn = action->rewrite.dmn;
1634 u8 action_type;
1635 int ret;
1636
1637 action_type = MLX5_GET(set_action_in, sw_action, action_type);
1638
1639 switch (action_type) {
1640 case MLX5_ACTION_TYPE_SET:
1641 ret = dr_action_modify_check_set_field_limitation(action,
1642 sw_action);
1643 break;
1644
1645 case MLX5_ACTION_TYPE_ADD:
1646 ret = dr_action_modify_check_add_field_limitation(action,
1647 sw_action);
1648 break;
1649
1650 case MLX5_ACTION_TYPE_COPY:
1651 ret = dr_action_modify_check_copy_field_limitation(action,
1652 sw_action);
1653 break;
1654
1655 default:
1656 mlx5dr_info(dmn, "Unsupported action %d modify action\n",
1657 action_type);
1658 ret = -EOPNOTSUPP;
1659 }
1660
1661 return ret;
1662 }
1663
1664 static bool
dr_action_modify_check_is_ttl_modify(const void * sw_action)1665 dr_action_modify_check_is_ttl_modify(const void *sw_action)
1666 {
1667 u16 sw_field = MLX5_GET(set_action_in, sw_action, field);
1668
1669 return sw_field == MLX5_ACTION_IN_FIELD_OUT_IP_TTL;
1670 }
1671
dr_actions_convert_modify_header(struct mlx5dr_action * action,u32 max_hw_actions,u32 num_sw_actions,__be64 sw_actions[],__be64 hw_actions[],u32 * num_hw_actions,bool * modify_ttl)1672 static int dr_actions_convert_modify_header(struct mlx5dr_action *action,
1673 u32 max_hw_actions,
1674 u32 num_sw_actions,
1675 __be64 sw_actions[],
1676 __be64 hw_actions[],
1677 u32 *num_hw_actions,
1678 bool *modify_ttl)
1679 {
1680 const struct dr_action_modify_field_conv *hw_dst_action_info;
1681 const struct dr_action_modify_field_conv *hw_src_action_info;
1682 u16 hw_field = MLX5DR_ACTION_MDFY_HW_FLD_RESERVED;
1683 u32 l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_NONE;
1684 u32 l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_NONE;
1685 struct mlx5dr_domain *dmn = action->rewrite.dmn;
1686 int ret, i, hw_idx = 0;
1687 __be64 *sw_action;
1688 __be64 hw_action;
1689
1690 *modify_ttl = false;
1691
1692 action->rewrite.allow_rx = 1;
1693 action->rewrite.allow_tx = 1;
1694
1695 for (i = 0; i < num_sw_actions; i++) {
1696 sw_action = &sw_actions[i];
1697
1698 ret = dr_action_modify_check_field_limitation(action,
1699 sw_action);
1700 if (ret)
1701 return ret;
1702
1703 if (!(*modify_ttl))
1704 *modify_ttl = dr_action_modify_check_is_ttl_modify(sw_action);
1705
1706 /* Convert SW action to HW action */
1707 ret = dr_action_modify_sw_to_hw(dmn,
1708 sw_action,
1709 &hw_action,
1710 &hw_dst_action_info,
1711 &hw_src_action_info);
1712 if (ret)
1713 return ret;
1714
1715 /* Due to a HW limitation we cannot modify 2 different L3 types */
1716 if (l3_type && hw_dst_action_info->l3_type &&
1717 hw_dst_action_info->l3_type != l3_type) {
1718 mlx5dr_dbg(dmn, "Action list can't support two different L3 types\n");
1719 return -EINVAL;
1720 }
1721 if (hw_dst_action_info->l3_type)
1722 l3_type = hw_dst_action_info->l3_type;
1723
1724 /* Due to a HW limitation we cannot modify two different L4 types */
1725 if (l4_type && hw_dst_action_info->l4_type &&
1726 hw_dst_action_info->l4_type != l4_type) {
1727 mlx5dr_dbg(dmn, "Action list can't support two different L4 types\n");
1728 return -EINVAL;
1729 }
1730 if (hw_dst_action_info->l4_type)
1731 l4_type = hw_dst_action_info->l4_type;
1732
1733 /* HW reads and executes two actions at once this means we
1734 * need to create a gap if two actions access the same field
1735 */
1736 if ((hw_idx % 2) && (hw_field == hw_dst_action_info->hw_field ||
1737 (hw_src_action_info &&
1738 hw_field == hw_src_action_info->hw_field))) {
1739 /* Check if after gap insertion the total number of HW
1740 * modify actions doesn't exceeds the limit
1741 */
1742 hw_idx++;
1743 if ((num_sw_actions + hw_idx - i) >= max_hw_actions) {
1744 mlx5dr_dbg(dmn, "Modify header action number exceeds HW limit\n");
1745 return -EINVAL;
1746 }
1747 }
1748 hw_field = hw_dst_action_info->hw_field;
1749
1750 hw_actions[hw_idx] = hw_action;
1751 hw_idx++;
1752 }
1753
1754 *num_hw_actions = hw_idx;
1755
1756 return 0;
1757 }
1758
dr_action_create_modify_action(struct mlx5dr_domain * dmn,size_t actions_sz,__be64 actions[],struct mlx5dr_action * action)1759 static int dr_action_create_modify_action(struct mlx5dr_domain *dmn,
1760 size_t actions_sz,
1761 __be64 actions[],
1762 struct mlx5dr_action *action)
1763 {
1764 struct mlx5dr_icm_chunk *chunk;
1765 u32 max_hw_actions;
1766 u32 num_hw_actions;
1767 u32 num_sw_actions;
1768 __be64 *hw_actions;
1769 bool modify_ttl;
1770 int ret;
1771
1772 num_sw_actions = actions_sz / DR_MODIFY_ACTION_SIZE;
1773 max_hw_actions = mlx5dr_icm_pool_chunk_size_to_entries(DR_CHUNK_SIZE_16);
1774
1775 if (num_sw_actions > max_hw_actions) {
1776 mlx5dr_dbg(dmn, "Max number of actions %d exceeds limit %d\n",
1777 num_sw_actions, max_hw_actions);
1778 return -EINVAL;
1779 }
1780
1781 chunk = mlx5dr_icm_alloc_chunk(dmn->action_icm_pool, DR_CHUNK_SIZE_16);
1782 if (!chunk)
1783 return -ENOMEM;
1784
1785 hw_actions = kcalloc(1, max_hw_actions * DR_MODIFY_ACTION_SIZE, GFP_KERNEL);
1786 if (!hw_actions) {
1787 ret = -ENOMEM;
1788 goto free_chunk;
1789 }
1790
1791 ret = dr_actions_convert_modify_header(action,
1792 max_hw_actions,
1793 num_sw_actions,
1794 actions,
1795 hw_actions,
1796 &num_hw_actions,
1797 &modify_ttl);
1798 if (ret)
1799 goto free_hw_actions;
1800
1801 action->rewrite.chunk = chunk;
1802 action->rewrite.modify_ttl = modify_ttl;
1803 action->rewrite.data = (u8 *)hw_actions;
1804 action->rewrite.num_of_actions = num_hw_actions;
1805 action->rewrite.index = (chunk->icm_addr -
1806 dmn->info.caps.hdr_modify_icm_addr) /
1807 ACTION_CACHE_LINE_SIZE;
1808
1809 ret = mlx5dr_send_postsend_action(dmn, action);
1810 if (ret)
1811 goto free_hw_actions;
1812
1813 return 0;
1814
1815 free_hw_actions:
1816 kfree(hw_actions);
1817 free_chunk:
1818 mlx5dr_icm_free_chunk(chunk);
1819 return ret;
1820 }
1821
1822 struct mlx5dr_action *
mlx5dr_action_create_modify_header(struct mlx5dr_domain * dmn,u32 flags,size_t actions_sz,__be64 actions[])1823 mlx5dr_action_create_modify_header(struct mlx5dr_domain *dmn,
1824 u32 flags,
1825 size_t actions_sz,
1826 __be64 actions[])
1827 {
1828 struct mlx5dr_action *action;
1829 int ret = 0;
1830
1831 refcount_inc(&dmn->refcount);
1832
1833 if (actions_sz % DR_MODIFY_ACTION_SIZE) {
1834 mlx5dr_dbg(dmn, "Invalid modify actions size provided\n");
1835 goto dec_ref;
1836 }
1837
1838 action = dr_action_create_generic(DR_ACTION_TYP_MODIFY_HDR);
1839 if (!action)
1840 goto dec_ref;
1841
1842 action->rewrite.dmn = dmn;
1843
1844 ret = dr_action_create_modify_action(dmn,
1845 actions_sz,
1846 actions,
1847 action);
1848 if (ret) {
1849 mlx5dr_dbg(dmn, "Failed creating modify header action %d\n", ret);
1850 goto free_action;
1851 }
1852
1853 return action;
1854
1855 free_action:
1856 kfree(action);
1857 dec_ref:
1858 refcount_dec(&dmn->refcount);
1859 return NULL;
1860 }
1861
1862 struct mlx5dr_action *
mlx5dr_action_create_dest_vport(struct mlx5dr_domain * dmn,u32 vport,u8 vhca_id_valid,u16 vhca_id)1863 mlx5dr_action_create_dest_vport(struct mlx5dr_domain *dmn,
1864 u32 vport, u8 vhca_id_valid,
1865 u16 vhca_id)
1866 {
1867 struct mlx5dr_cmd_vport_cap *vport_cap;
1868 struct mlx5dr_domain *vport_dmn;
1869 struct mlx5dr_action *action;
1870 u8 peer_vport;
1871
1872 peer_vport = vhca_id_valid && (vhca_id != dmn->info.caps.gvmi);
1873 vport_dmn = peer_vport ? dmn->peer_dmn : dmn;
1874 if (!vport_dmn) {
1875 mlx5dr_dbg(dmn, "No peer vport domain for given vhca_id\n");
1876 return NULL;
1877 }
1878
1879 if (vport_dmn->type != MLX5DR_DOMAIN_TYPE_FDB) {
1880 mlx5dr_dbg(dmn, "Domain doesn't support vport actions\n");
1881 return NULL;
1882 }
1883
1884 vport_cap = mlx5dr_get_vport_cap(&vport_dmn->info.caps, vport);
1885 if (!vport_cap) {
1886 mlx5dr_dbg(dmn, "Failed to get vport %d caps\n", vport);
1887 return NULL;
1888 }
1889
1890 action = dr_action_create_generic(DR_ACTION_TYP_VPORT);
1891 if (!action)
1892 return NULL;
1893
1894 action->vport.dmn = vport_dmn;
1895 action->vport.caps = vport_cap;
1896
1897 return action;
1898 }
1899
mlx5dr_action_destroy(struct mlx5dr_action * action)1900 int mlx5dr_action_destroy(struct mlx5dr_action *action)
1901 {
1902 if (refcount_read(&action->refcount) > 1)
1903 return -EBUSY;
1904
1905 switch (action->action_type) {
1906 case DR_ACTION_TYP_FT:
1907 if (action->dest_tbl.is_fw_tbl)
1908 refcount_dec(&action->dest_tbl.fw_tbl.dmn->refcount);
1909 else
1910 refcount_dec(&action->dest_tbl.tbl->refcount);
1911
1912 if (action->dest_tbl.is_fw_tbl &&
1913 action->dest_tbl.fw_tbl.num_of_ref_actions) {
1914 struct mlx5dr_action **ref_actions;
1915 int i;
1916
1917 ref_actions = action->dest_tbl.fw_tbl.ref_actions;
1918 for (i = 0; i < action->dest_tbl.fw_tbl.num_of_ref_actions; i++)
1919 refcount_dec(&ref_actions[i]->refcount);
1920
1921 kfree(ref_actions);
1922
1923 mlx5dr_fw_destroy_md_tbl(action->dest_tbl.fw_tbl.dmn,
1924 action->dest_tbl.fw_tbl.id,
1925 action->dest_tbl.fw_tbl.group_id);
1926 }
1927 break;
1928 case DR_ACTION_TYP_TNL_L2_TO_L2:
1929 refcount_dec(&action->reformat.dmn->refcount);
1930 break;
1931 case DR_ACTION_TYP_TNL_L3_TO_L2:
1932 mlx5dr_icm_free_chunk(action->rewrite.chunk);
1933 refcount_dec(&action->reformat.dmn->refcount);
1934 break;
1935 case DR_ACTION_TYP_L2_TO_TNL_L2:
1936 case DR_ACTION_TYP_L2_TO_TNL_L3:
1937 mlx5dr_cmd_destroy_reformat_ctx((action->reformat.dmn)->mdev,
1938 action->reformat.reformat_id);
1939 refcount_dec(&action->reformat.dmn->refcount);
1940 break;
1941 case DR_ACTION_TYP_MODIFY_HDR:
1942 mlx5dr_icm_free_chunk(action->rewrite.chunk);
1943 kfree(action->rewrite.data);
1944 refcount_dec(&action->rewrite.dmn->refcount);
1945 break;
1946 default:
1947 break;
1948 }
1949
1950 kfree(action);
1951 return 0;
1952 }
1953