1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2019, Mellanox Technologies */
3
4 #ifndef __MLX5_DEVLINK_H__
5 #define __MLX5_DEVLINK_H__
6
7 #include <net/devlink.h>
8
9 enum mlx5_devlink_resource_id {
10 MLX5_DL_RES_MAX_LOCAL_SFS = 1,
11 MLX5_DL_RES_MAX_EXTERNAL_SFS,
12
13 __MLX5_ID_RES_MAX,
14 MLX5_ID_RES_MAX = __MLX5_ID_RES_MAX - 1,
15 };
16
17 enum mlx5_devlink_param_id {
18 MLX5_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
19 MLX5_DEVLINK_PARAM_ID_FLOW_STEERING_MODE,
20 MLX5_DEVLINK_PARAM_ID_ESW_LARGE_GROUP_NUM,
21 MLX5_DEVLINK_PARAM_ID_ESW_PORT_METADATA,
22 MLX5_DEVLINK_PARAM_ID_ESW_MULTIPORT,
23 MLX5_DEVLINK_PARAM_ID_HAIRPIN_NUM_QUEUES,
24 MLX5_DEVLINK_PARAM_ID_HAIRPIN_QUEUE_SIZE,
25 MLX5_DEVLINK_PARAM_ID_PCIE_CONG_IN_LOW,
26 MLX5_DEVLINK_PARAM_ID_PCIE_CONG_IN_HIGH,
27 MLX5_DEVLINK_PARAM_ID_PCIE_CONG_OUT_LOW,
28 MLX5_DEVLINK_PARAM_ID_PCIE_CONG_OUT_HIGH,
29 MLX5_DEVLINK_PARAM_ID_CQE_COMPRESSION_TYPE,
30 MLX5_DEVLINK_PARAM_ID_SWP_L4_CSUM_MODE,
31 };
32
33 struct mlx5_trap_ctx {
34 int id;
35 int action;
36 };
37
38 struct mlx5_devlink_trap {
39 struct mlx5_trap_ctx trap;
40 void *item;
41 struct list_head list;
42 };
43
44 struct mlx5_devlink_trap_event_ctx {
45 struct mlx5_trap_ctx *trap;
46 int err;
47 };
48
49 struct mlx5_core_dev;
50 void mlx5_devlink_trap_report(struct mlx5_core_dev *dev, int trap_id, struct sk_buff *skb,
51 struct devlink_port *dl_port);
52 int mlx5_devlink_trap_get_num_active(struct mlx5_core_dev *dev);
53 int mlx5_devlink_traps_get_action(struct mlx5_core_dev *dev, int trap_id,
54 enum devlink_trap_action *action);
55 int mlx5_devlink_traps_register(struct devlink *devlink);
56 void mlx5_devlink_traps_unregister(struct devlink *devlink);
57
58 struct devlink *mlx5_devlink_alloc(struct device *dev);
59 void mlx5_devlink_free(struct devlink *devlink);
60 int mlx5_devlink_params_register(struct devlink *devlink);
61 void mlx5_devlink_params_unregister(struct devlink *devlink);
62
mlx5_core_is_eth_enabled(struct mlx5_core_dev * dev)63 static inline bool mlx5_core_is_eth_enabled(struct mlx5_core_dev *dev)
64 {
65 union devlink_param_value val;
66 int err;
67
68 err = devl_param_driverinit_value_get(priv_to_devlink(dev),
69 DEVLINK_PARAM_GENERIC_ID_ENABLE_ETH,
70 &val);
71 return err ? false : val.vbool;
72 }
73
74 #endif /* __MLX5_DEVLINK_H__ */
75