1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include <linux/mlx5/vport.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
52 #endif
53 #include <net/devlink.h>
54 #include "mlx5_core.h"
55 #include "lib/eq.h"
56 #include "fs_core.h"
57 #include "lib/mpfs.h"
58 #include "eswitch.h"
59 #include "devlink.h"
60 #include "fw_reset.h"
61 #include "lib/mlx5.h"
62 #include "fpga/core.h"
63 #include "fpga/ipsec.h"
64 #include "accel/ipsec.h"
65 #include "accel/tls.h"
66 #include "lib/clock.h"
67 #include "lib/vxlan.h"
68 #include "lib/geneve.h"
69 #include "lib/devcom.h"
70 #include "lib/pci_vsc.h"
71 #include "diag/fw_tracer.h"
72 #include "ecpf.h"
73 #include "lib/hv_vhca.h"
74 #include "diag/rsc_dump.h"
75
76 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
77 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
78 MODULE_LICENSE("Dual BSD/GPL");
79 MODULE_VERSION(DRIVER_VERSION);
80
81 unsigned int mlx5_core_debug_mask;
82 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
83 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
84
85 #define MLX5_DEFAULT_PROF 2
86 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
87 module_param_named(prof_sel, prof_sel, uint, 0444);
88 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
89
90 static u32 sw_owner_id[4];
91
92 enum {
93 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
94 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
95 };
96
97 static struct mlx5_profile profile[] = {
98 [0] = {
99 .mask = 0,
100 },
101 [1] = {
102 .mask = MLX5_PROF_MASK_QP_SIZE,
103 .log_max_qp = 12,
104 },
105 [2] = {
106 .mask = MLX5_PROF_MASK_QP_SIZE |
107 MLX5_PROF_MASK_MR_CACHE,
108 .log_max_qp = 18,
109 .mr_cache[0] = {
110 .size = 500,
111 .limit = 250
112 },
113 .mr_cache[1] = {
114 .size = 500,
115 .limit = 250
116 },
117 .mr_cache[2] = {
118 .size = 500,
119 .limit = 250
120 },
121 .mr_cache[3] = {
122 .size = 500,
123 .limit = 250
124 },
125 .mr_cache[4] = {
126 .size = 500,
127 .limit = 250
128 },
129 .mr_cache[5] = {
130 .size = 500,
131 .limit = 250
132 },
133 .mr_cache[6] = {
134 .size = 500,
135 .limit = 250
136 },
137 .mr_cache[7] = {
138 .size = 500,
139 .limit = 250
140 },
141 .mr_cache[8] = {
142 .size = 500,
143 .limit = 250
144 },
145 .mr_cache[9] = {
146 .size = 500,
147 .limit = 250
148 },
149 .mr_cache[10] = {
150 .size = 500,
151 .limit = 250
152 },
153 .mr_cache[11] = {
154 .size = 500,
155 .limit = 250
156 },
157 .mr_cache[12] = {
158 .size = 64,
159 .limit = 32
160 },
161 .mr_cache[13] = {
162 .size = 32,
163 .limit = 16
164 },
165 .mr_cache[14] = {
166 .size = 16,
167 .limit = 8
168 },
169 .mr_cache[15] = {
170 .size = 8,
171 .limit = 4
172 },
173 },
174 };
175
176 #define FW_INIT_TIMEOUT_MILI 2000
177 #define FW_INIT_WAIT_MS 2
178 #define FW_PRE_INIT_TIMEOUT_MILI 120000
179 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000
180
fw_initializing(struct mlx5_core_dev * dev)181 static int fw_initializing(struct mlx5_core_dev *dev)
182 {
183 return ioread32be(&dev->iseg->initializing) >> 31;
184 }
185
wait_fw_init(struct mlx5_core_dev * dev,u32 max_wait_mili,u32 warn_time_mili)186 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
187 u32 warn_time_mili)
188 {
189 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
190 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
191 int err = 0;
192
193 BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL);
194
195 while (fw_initializing(dev)) {
196 if (time_after(jiffies, end)) {
197 err = -EBUSY;
198 break;
199 }
200 if (warn_time_mili && time_after(jiffies, warn)) {
201 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n",
202 jiffies_to_msecs(end - warn) / 1000);
203 warn = jiffies + msecs_to_jiffies(warn_time_mili);
204 }
205 msleep(FW_INIT_WAIT_MS);
206 }
207
208 return err;
209 }
210
mlx5_set_driver_version(struct mlx5_core_dev * dev)211 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
212 {
213 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
214 driver_version);
215 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
216 int remaining_size = driver_ver_sz;
217 char *string;
218
219 if (!MLX5_CAP_GEN(dev, driver_version))
220 return;
221
222 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
223
224 strncpy(string, "Linux", remaining_size);
225
226 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
227 strncat(string, ",", remaining_size);
228
229 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
230 strncat(string, DRIVER_NAME, remaining_size);
231
232 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
233 strncat(string, ",", remaining_size);
234
235 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
236 strncat(string, DRIVER_VERSION, remaining_size);
237
238 /*Send the command*/
239 MLX5_SET(set_driver_version_in, in, opcode,
240 MLX5_CMD_OP_SET_DRIVER_VERSION);
241
242 mlx5_cmd_exec_in(dev, set_driver_version, in);
243 }
244
set_dma_caps(struct pci_dev * pdev)245 static int set_dma_caps(struct pci_dev *pdev)
246 {
247 int err;
248
249 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
250 if (err) {
251 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
252 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
253 if (err) {
254 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
255 return err;
256 }
257 }
258
259 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
260 if (err) {
261 dev_warn(&pdev->dev,
262 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
263 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
264 if (err) {
265 dev_err(&pdev->dev,
266 "Can't set consistent PCI DMA mask, aborting\n");
267 return err;
268 }
269 }
270
271 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
272 return err;
273 }
274
mlx5_pci_enable_device(struct mlx5_core_dev * dev)275 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
276 {
277 struct pci_dev *pdev = dev->pdev;
278 int err = 0;
279
280 mutex_lock(&dev->pci_status_mutex);
281 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
282 err = pci_enable_device(pdev);
283 if (!err)
284 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
285 }
286 mutex_unlock(&dev->pci_status_mutex);
287
288 return err;
289 }
290
mlx5_pci_disable_device(struct mlx5_core_dev * dev)291 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
292 {
293 struct pci_dev *pdev = dev->pdev;
294
295 mutex_lock(&dev->pci_status_mutex);
296 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
297 pci_disable_device(pdev);
298 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
299 }
300 mutex_unlock(&dev->pci_status_mutex);
301 }
302
request_bar(struct pci_dev * pdev)303 static int request_bar(struct pci_dev *pdev)
304 {
305 int err = 0;
306
307 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
308 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
309 return -ENODEV;
310 }
311
312 err = pci_request_regions(pdev, DRIVER_NAME);
313 if (err)
314 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
315
316 return err;
317 }
318
release_bar(struct pci_dev * pdev)319 static void release_bar(struct pci_dev *pdev)
320 {
321 pci_release_regions(pdev);
322 }
323
324 struct mlx5_reg_host_endianness {
325 u8 he;
326 u8 rsvd[15];
327 };
328
329 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
330
331 enum {
332 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
333 MLX5_DEV_CAP_FLAG_DCT,
334 };
335
to_fw_pkey_sz(struct mlx5_core_dev * dev,u32 size)336 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
337 {
338 switch (size) {
339 case 128:
340 return 0;
341 case 256:
342 return 1;
343 case 512:
344 return 2;
345 case 1024:
346 return 3;
347 case 2048:
348 return 4;
349 case 4096:
350 return 5;
351 default:
352 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
353 return 0;
354 }
355 }
356
mlx5_core_get_caps_mode(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type,enum mlx5_cap_mode cap_mode)357 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
358 enum mlx5_cap_type cap_type,
359 enum mlx5_cap_mode cap_mode)
360 {
361 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
362 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
363 void *out, *hca_caps;
364 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
365 int err;
366
367 memset(in, 0, sizeof(in));
368 out = kzalloc(out_sz, GFP_KERNEL);
369 if (!out)
370 return -ENOMEM;
371
372 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
373 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
374 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
375 if (err) {
376 mlx5_core_warn(dev,
377 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
378 cap_type, cap_mode, err);
379 goto query_ex;
380 }
381
382 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
383
384 switch (cap_mode) {
385 case HCA_CAP_OPMOD_GET_MAX:
386 memcpy(dev->caps.hca_max[cap_type], hca_caps,
387 MLX5_UN_SZ_BYTES(hca_cap_union));
388 break;
389 case HCA_CAP_OPMOD_GET_CUR:
390 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
391 MLX5_UN_SZ_BYTES(hca_cap_union));
392 break;
393 default:
394 mlx5_core_warn(dev,
395 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
396 cap_type, cap_mode);
397 err = -EINVAL;
398 break;
399 }
400 query_ex:
401 kfree(out);
402 return err;
403 }
404
mlx5_core_get_caps(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type)405 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
406 {
407 int ret;
408
409 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
410 if (ret)
411 return ret;
412 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
413 }
414
set_caps(struct mlx5_core_dev * dev,void * in,int opmod)415 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
416 {
417 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
418 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
419 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
420 }
421
handle_hca_cap_atomic(struct mlx5_core_dev * dev,void * set_ctx)422 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
423 {
424 void *set_hca_cap;
425 int req_endianness;
426 int err;
427
428 if (!MLX5_CAP_GEN(dev, atomic))
429 return 0;
430
431 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
432 if (err)
433 return err;
434
435 req_endianness =
436 MLX5_CAP_ATOMIC(dev,
437 supported_atomic_req_8B_endianness_mode_1);
438
439 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
440 return 0;
441
442 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
443
444 /* Set requestor to host endianness */
445 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
446 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
447
448 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
449 }
450
handle_hca_cap_odp(struct mlx5_core_dev * dev,void * set_ctx)451 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
452 {
453 void *set_hca_cap;
454 bool do_set = false;
455 int err;
456
457 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
458 !MLX5_CAP_GEN(dev, pg))
459 return 0;
460
461 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
462 if (err)
463 return err;
464
465 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
466 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP],
467 MLX5_ST_SZ_BYTES(odp_cap));
468
469 #define ODP_CAP_SET_MAX(dev, field) \
470 do { \
471 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
472 if (_res) { \
473 do_set = true; \
474 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
475 } \
476 } while (0)
477
478 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
479 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
480 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
481 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
482 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
483 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
484 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
485 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
486 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
487 ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
488 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
489 ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
490 ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
491 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
492
493 if (!do_set)
494 return 0;
495
496 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
497 }
498
handle_hca_cap(struct mlx5_core_dev * dev,void * set_ctx)499 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
500 {
501 struct mlx5_profile *prof = dev->profile;
502 void *set_hca_cap;
503 int err;
504
505 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
506 if (err)
507 return err;
508
509 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
510 capability);
511 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
512 MLX5_ST_SZ_BYTES(cmd_hca_cap));
513
514 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
515 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
516 128);
517 /* we limit the size of the pkey table to 128 entries for now */
518 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
519 to_fw_pkey_sz(dev, 128));
520
521 /* Check log_max_qp from HCA caps to set in current profile */
522 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
523 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
524 profile[prof_sel].log_max_qp,
525 MLX5_CAP_GEN_MAX(dev, log_max_qp));
526 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
527 }
528 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
529 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
530 prof->log_max_qp);
531
532 /* disable cmdif checksum */
533 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
534
535 /* Enable 4K UAR only when HCA supports it and page size is bigger
536 * than 4K.
537 */
538 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
539 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
540
541 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
542
543 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
544 MLX5_SET(cmd_hca_cap,
545 set_hca_cap,
546 cache_line_128byte,
547 cache_line_size() >= 128 ? 1 : 0);
548
549 if (MLX5_CAP_GEN_MAX(dev, dct))
550 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
551
552 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
553 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
554
555 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
556 MLX5_SET(cmd_hca_cap,
557 set_hca_cap,
558 num_vhca_ports,
559 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
560
561 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
562 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
563
564 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
565 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
566
567 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
568 }
569
handle_hca_cap_roce(struct mlx5_core_dev * dev,void * set_ctx)570 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
571 {
572 void *set_hca_cap;
573 int err;
574
575 if (!MLX5_CAP_GEN(dev, roce))
576 return 0;
577
578 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
579 if (err)
580 return err;
581
582 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
583 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
584 return 0;
585
586 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
587 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ROCE],
588 MLX5_ST_SZ_BYTES(roce_cap));
589 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
590
591 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
592 return err;
593 }
594
set_hca_cap(struct mlx5_core_dev * dev)595 static int set_hca_cap(struct mlx5_core_dev *dev)
596 {
597 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
598 void *set_ctx;
599 int err;
600
601 set_ctx = kzalloc(set_sz, GFP_KERNEL);
602 if (!set_ctx)
603 return -ENOMEM;
604
605 err = handle_hca_cap(dev, set_ctx);
606 if (err) {
607 mlx5_core_err(dev, "handle_hca_cap failed\n");
608 goto out;
609 }
610
611 memset(set_ctx, 0, set_sz);
612 err = handle_hca_cap_atomic(dev, set_ctx);
613 if (err) {
614 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
615 goto out;
616 }
617
618 memset(set_ctx, 0, set_sz);
619 err = handle_hca_cap_odp(dev, set_ctx);
620 if (err) {
621 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
622 goto out;
623 }
624
625 memset(set_ctx, 0, set_sz);
626 err = handle_hca_cap_roce(dev, set_ctx);
627 if (err) {
628 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
629 goto out;
630 }
631
632 out:
633 kfree(set_ctx);
634 return err;
635 }
636
set_hca_ctrl(struct mlx5_core_dev * dev)637 static int set_hca_ctrl(struct mlx5_core_dev *dev)
638 {
639 struct mlx5_reg_host_endianness he_in;
640 struct mlx5_reg_host_endianness he_out;
641 int err;
642
643 if (!mlx5_core_is_pf(dev))
644 return 0;
645
646 memset(&he_in, 0, sizeof(he_in));
647 he_in.he = MLX5_SET_HOST_ENDIANNESS;
648 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
649 &he_out, sizeof(he_out),
650 MLX5_REG_HOST_ENDIANNESS, 0, 1);
651 return err;
652 }
653
mlx5_core_set_hca_defaults(struct mlx5_core_dev * dev)654 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
655 {
656 int ret = 0;
657
658 /* Disable local_lb by default */
659 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
660 ret = mlx5_nic_vport_update_local_lb(dev, false);
661
662 return ret;
663 }
664
mlx5_core_enable_hca(struct mlx5_core_dev * dev,u16 func_id)665 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
666 {
667 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
668
669 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
670 MLX5_SET(enable_hca_in, in, function_id, func_id);
671 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
672 dev->caps.embedded_cpu);
673 return mlx5_cmd_exec_in(dev, enable_hca, in);
674 }
675
mlx5_core_disable_hca(struct mlx5_core_dev * dev,u16 func_id)676 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
677 {
678 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
679
680 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
681 MLX5_SET(disable_hca_in, in, function_id, func_id);
682 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
683 dev->caps.embedded_cpu);
684 return mlx5_cmd_exec_in(dev, disable_hca, in);
685 }
686
mlx5_core_set_issi(struct mlx5_core_dev * dev)687 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
688 {
689 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
690 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
691 u32 sup_issi;
692 int err;
693
694 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
695 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
696 if (err) {
697 u32 syndrome;
698 u8 status;
699
700 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
701 if (!status || syndrome == MLX5_DRIVER_SYND) {
702 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
703 err, status, syndrome);
704 return err;
705 }
706
707 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
708 dev->issi = 0;
709 return 0;
710 }
711
712 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
713
714 if (sup_issi & (1 << 1)) {
715 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
716
717 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
718 MLX5_SET(set_issi_in, set_in, current_issi, 1);
719 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
720 if (err) {
721 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
722 err);
723 return err;
724 }
725
726 dev->issi = 1;
727
728 return 0;
729 } else if (sup_issi & (1 << 0) || !sup_issi) {
730 return 0;
731 }
732
733 return -EOPNOTSUPP;
734 }
735
mlx5_pci_init(struct mlx5_core_dev * dev,struct pci_dev * pdev,const struct pci_device_id * id)736 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
737 const struct pci_device_id *id)
738 {
739 struct mlx5_priv *priv = &dev->priv;
740 int err = 0;
741
742 mutex_init(&dev->pci_status_mutex);
743 pci_set_drvdata(dev->pdev, dev);
744
745 dev->bar_addr = pci_resource_start(pdev, 0);
746 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
747
748 err = mlx5_pci_enable_device(dev);
749 if (err) {
750 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
751 return err;
752 }
753
754 err = request_bar(pdev);
755 if (err) {
756 mlx5_core_err(dev, "error requesting BARs, aborting\n");
757 goto err_disable;
758 }
759
760 pci_set_master(pdev);
761
762 err = set_dma_caps(pdev);
763 if (err) {
764 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
765 goto err_clr_master;
766 }
767
768 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
769 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
770 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
771 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
772
773 dev->iseg_base = dev->bar_addr;
774 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
775 if (!dev->iseg) {
776 err = -ENOMEM;
777 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
778 goto err_clr_master;
779 }
780
781 mlx5_pci_vsc_init(dev);
782 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
783 return 0;
784
785 err_clr_master:
786 pci_clear_master(dev->pdev);
787 release_bar(dev->pdev);
788 err_disable:
789 mlx5_pci_disable_device(dev);
790 return err;
791 }
792
mlx5_pci_close(struct mlx5_core_dev * dev)793 static void mlx5_pci_close(struct mlx5_core_dev *dev)
794 {
795 /* health work might still be active, and it needs pci bar in
796 * order to know the NIC state. Therefore, drain the health WQ
797 * before removing the pci bars
798 */
799 mlx5_drain_health_wq(dev);
800 iounmap(dev->iseg);
801 pci_clear_master(dev->pdev);
802 release_bar(dev->pdev);
803 mlx5_pci_disable_device(dev);
804 }
805
mlx5_init_once(struct mlx5_core_dev * dev)806 static int mlx5_init_once(struct mlx5_core_dev *dev)
807 {
808 int err;
809
810 dev->priv.devcom = mlx5_devcom_register_device(dev);
811 if (IS_ERR(dev->priv.devcom))
812 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
813 dev->priv.devcom);
814
815 err = mlx5_query_board_id(dev);
816 if (err) {
817 mlx5_core_err(dev, "query board id failed\n");
818 goto err_devcom;
819 }
820
821 err = mlx5_irq_table_init(dev);
822 if (err) {
823 mlx5_core_err(dev, "failed to initialize irq table\n");
824 goto err_devcom;
825 }
826
827 err = mlx5_eq_table_init(dev);
828 if (err) {
829 mlx5_core_err(dev, "failed to initialize eq\n");
830 goto err_irq_cleanup;
831 }
832
833 err = mlx5_events_init(dev);
834 if (err) {
835 mlx5_core_err(dev, "failed to initialize events\n");
836 goto err_eq_cleanup;
837 }
838
839 err = mlx5_fw_reset_init(dev);
840 if (err) {
841 mlx5_core_err(dev, "failed to initialize fw reset events\n");
842 goto err_events_cleanup;
843 }
844
845 mlx5_cq_debugfs_init(dev);
846
847 mlx5_init_reserved_gids(dev);
848
849 mlx5_init_clock(dev);
850
851 dev->vxlan = mlx5_vxlan_create(dev);
852 dev->geneve = mlx5_geneve_create(dev);
853
854 err = mlx5_init_rl_table(dev);
855 if (err) {
856 mlx5_core_err(dev, "Failed to init rate limiting\n");
857 goto err_tables_cleanup;
858 }
859
860 err = mlx5_mpfs_init(dev);
861 if (err) {
862 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
863 goto err_rl_cleanup;
864 }
865
866 err = mlx5_sriov_init(dev);
867 if (err) {
868 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
869 goto err_mpfs_cleanup;
870 }
871
872 err = mlx5_eswitch_init(dev);
873 if (err) {
874 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
875 goto err_sriov_cleanup;
876 }
877
878 err = mlx5_fpga_init(dev);
879 if (err) {
880 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
881 goto err_eswitch_cleanup;
882 }
883
884 dev->dm = mlx5_dm_create(dev);
885 if (IS_ERR(dev->dm))
886 mlx5_core_warn(dev, "Failed to init device memory%d\n", err);
887
888 dev->tracer = mlx5_fw_tracer_create(dev);
889 dev->hv_vhca = mlx5_hv_vhca_create(dev);
890 dev->rsc_dump = mlx5_rsc_dump_create(dev);
891
892 return 0;
893
894 err_eswitch_cleanup:
895 mlx5_eswitch_cleanup(dev->priv.eswitch);
896 err_sriov_cleanup:
897 mlx5_sriov_cleanup(dev);
898 err_mpfs_cleanup:
899 mlx5_mpfs_cleanup(dev);
900 err_rl_cleanup:
901 mlx5_cleanup_rl_table(dev);
902 err_tables_cleanup:
903 mlx5_geneve_destroy(dev->geneve);
904 mlx5_vxlan_destroy(dev->vxlan);
905 mlx5_cq_debugfs_cleanup(dev);
906 mlx5_fw_reset_cleanup(dev);
907 err_events_cleanup:
908 mlx5_events_cleanup(dev);
909 err_eq_cleanup:
910 mlx5_eq_table_cleanup(dev);
911 err_irq_cleanup:
912 mlx5_irq_table_cleanup(dev);
913 err_devcom:
914 mlx5_devcom_unregister_device(dev->priv.devcom);
915
916 return err;
917 }
918
mlx5_cleanup_once(struct mlx5_core_dev * dev)919 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
920 {
921 mlx5_rsc_dump_destroy(dev);
922 mlx5_hv_vhca_destroy(dev->hv_vhca);
923 mlx5_fw_tracer_destroy(dev->tracer);
924 mlx5_dm_cleanup(dev);
925 mlx5_fpga_cleanup(dev);
926 mlx5_eswitch_cleanup(dev->priv.eswitch);
927 mlx5_sriov_cleanup(dev);
928 mlx5_mpfs_cleanup(dev);
929 mlx5_cleanup_rl_table(dev);
930 mlx5_geneve_destroy(dev->geneve);
931 mlx5_vxlan_destroy(dev->vxlan);
932 mlx5_cleanup_clock(dev);
933 mlx5_cleanup_reserved_gids(dev);
934 mlx5_cq_debugfs_cleanup(dev);
935 mlx5_fw_reset_cleanup(dev);
936 mlx5_events_cleanup(dev);
937 mlx5_eq_table_cleanup(dev);
938 mlx5_irq_table_cleanup(dev);
939 mlx5_devcom_unregister_device(dev->priv.devcom);
940 }
941
mlx5_function_setup(struct mlx5_core_dev * dev,bool boot)942 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot)
943 {
944 int err;
945
946 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
947 fw_rev_min(dev), fw_rev_sub(dev));
948
949 /* Only PFs hold the relevant PCIe information for this query */
950 if (mlx5_core_is_pf(dev))
951 pcie_print_link_status(dev->pdev);
952
953 /* wait for firmware to accept initialization segments configurations
954 */
955 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL);
956 if (err) {
957 mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n",
958 FW_PRE_INIT_TIMEOUT_MILI);
959 return err;
960 }
961
962 err = mlx5_cmd_init(dev);
963 if (err) {
964 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
965 return err;
966 }
967
968 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0);
969 if (err) {
970 mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n",
971 FW_INIT_TIMEOUT_MILI);
972 goto err_cmd_cleanup;
973 }
974
975 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
976
977 err = mlx5_core_enable_hca(dev, 0);
978 if (err) {
979 mlx5_core_err(dev, "enable hca failed\n");
980 goto err_cmd_cleanup;
981 }
982
983 err = mlx5_core_set_issi(dev);
984 if (err) {
985 mlx5_core_err(dev, "failed to set issi\n");
986 goto err_disable_hca;
987 }
988
989 err = mlx5_satisfy_startup_pages(dev, 1);
990 if (err) {
991 mlx5_core_err(dev, "failed to allocate boot pages\n");
992 goto err_disable_hca;
993 }
994
995 err = set_hca_ctrl(dev);
996 if (err) {
997 mlx5_core_err(dev, "set_hca_ctrl failed\n");
998 goto reclaim_boot_pages;
999 }
1000
1001 err = set_hca_cap(dev);
1002 if (err) {
1003 mlx5_core_err(dev, "set_hca_cap failed\n");
1004 goto reclaim_boot_pages;
1005 }
1006
1007 err = mlx5_satisfy_startup_pages(dev, 0);
1008 if (err) {
1009 mlx5_core_err(dev, "failed to allocate init pages\n");
1010 goto reclaim_boot_pages;
1011 }
1012
1013 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1014 if (err) {
1015 mlx5_core_err(dev, "init hca failed\n");
1016 goto reclaim_boot_pages;
1017 }
1018
1019 mlx5_set_driver_version(dev);
1020
1021 mlx5_start_health_poll(dev);
1022
1023 err = mlx5_query_hca_caps(dev);
1024 if (err) {
1025 mlx5_core_err(dev, "query hca failed\n");
1026 goto stop_health;
1027 }
1028
1029 return 0;
1030
1031 stop_health:
1032 mlx5_stop_health_poll(dev, boot);
1033 reclaim_boot_pages:
1034 mlx5_reclaim_startup_pages(dev);
1035 err_disable_hca:
1036 mlx5_core_disable_hca(dev, 0);
1037 err_cmd_cleanup:
1038 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1039 mlx5_cmd_cleanup(dev);
1040
1041 return err;
1042 }
1043
mlx5_function_teardown(struct mlx5_core_dev * dev,bool boot)1044 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1045 {
1046 int err;
1047
1048 mlx5_stop_health_poll(dev, boot);
1049 err = mlx5_cmd_teardown_hca(dev);
1050 if (err) {
1051 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1052 return err;
1053 }
1054 mlx5_reclaim_startup_pages(dev);
1055 mlx5_core_disable_hca(dev, 0);
1056 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1057 mlx5_cmd_cleanup(dev);
1058
1059 return 0;
1060 }
1061
mlx5_load(struct mlx5_core_dev * dev)1062 static int mlx5_load(struct mlx5_core_dev *dev)
1063 {
1064 int err;
1065
1066 dev->priv.uar = mlx5_get_uars_page(dev);
1067 if (IS_ERR(dev->priv.uar)) {
1068 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1069 err = PTR_ERR(dev->priv.uar);
1070 return err;
1071 }
1072
1073 mlx5_events_start(dev);
1074 mlx5_pagealloc_start(dev);
1075
1076 err = mlx5_irq_table_create(dev);
1077 if (err) {
1078 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1079 goto err_irq_table;
1080 }
1081
1082 err = mlx5_eq_table_create(dev);
1083 if (err) {
1084 mlx5_core_err(dev, "Failed to create EQs\n");
1085 goto err_eq_table;
1086 }
1087
1088 err = mlx5_fw_tracer_init(dev->tracer);
1089 if (err) {
1090 mlx5_core_err(dev, "Failed to init FW tracer\n");
1091 goto err_fw_tracer;
1092 }
1093
1094 mlx5_fw_reset_events_start(dev);
1095 mlx5_hv_vhca_init(dev->hv_vhca);
1096
1097 err = mlx5_rsc_dump_init(dev);
1098 if (err) {
1099 mlx5_core_err(dev, "Failed to init Resource dump\n");
1100 goto err_rsc_dump;
1101 }
1102
1103 err = mlx5_fpga_device_start(dev);
1104 if (err) {
1105 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1106 goto err_fpga_start;
1107 }
1108
1109 mlx5_accel_ipsec_init(dev);
1110
1111 err = mlx5_accel_tls_init(dev);
1112 if (err) {
1113 mlx5_core_err(dev, "TLS device start failed %d\n", err);
1114 goto err_tls_start;
1115 }
1116
1117 err = mlx5_init_fs(dev);
1118 if (err) {
1119 mlx5_core_err(dev, "Failed to init flow steering\n");
1120 goto err_fs;
1121 }
1122
1123 err = mlx5_core_set_hca_defaults(dev);
1124 if (err) {
1125 mlx5_core_err(dev, "Failed to set hca defaults\n");
1126 goto err_sriov;
1127 }
1128
1129 err = mlx5_sriov_attach(dev);
1130 if (err) {
1131 mlx5_core_err(dev, "sriov init failed %d\n", err);
1132 goto err_sriov;
1133 }
1134
1135 err = mlx5_ec_init(dev);
1136 if (err) {
1137 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1138 goto err_ec;
1139 }
1140
1141 return 0;
1142
1143 err_ec:
1144 mlx5_sriov_detach(dev);
1145 err_sriov:
1146 mlx5_cleanup_fs(dev);
1147 err_fs:
1148 mlx5_accel_tls_cleanup(dev);
1149 err_tls_start:
1150 mlx5_accel_ipsec_cleanup(dev);
1151 mlx5_fpga_device_stop(dev);
1152 err_fpga_start:
1153 mlx5_rsc_dump_cleanup(dev);
1154 err_rsc_dump:
1155 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1156 mlx5_fw_reset_events_stop(dev);
1157 mlx5_fw_tracer_cleanup(dev->tracer);
1158 err_fw_tracer:
1159 mlx5_eq_table_destroy(dev);
1160 err_eq_table:
1161 mlx5_irq_table_destroy(dev);
1162 err_irq_table:
1163 mlx5_pagealloc_stop(dev);
1164 mlx5_events_stop(dev);
1165 mlx5_put_uars_page(dev, dev->priv.uar);
1166 return err;
1167 }
1168
mlx5_unload(struct mlx5_core_dev * dev)1169 static void mlx5_unload(struct mlx5_core_dev *dev)
1170 {
1171 mlx5_ec_cleanup(dev);
1172 mlx5_sriov_detach(dev);
1173 mlx5_cleanup_fs(dev);
1174 mlx5_accel_ipsec_cleanup(dev);
1175 mlx5_accel_tls_cleanup(dev);
1176 mlx5_fpga_device_stop(dev);
1177 mlx5_rsc_dump_cleanup(dev);
1178 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1179 mlx5_fw_reset_events_stop(dev);
1180 mlx5_fw_tracer_cleanup(dev->tracer);
1181 mlx5_eq_table_destroy(dev);
1182 mlx5_irq_table_destroy(dev);
1183 mlx5_pagealloc_stop(dev);
1184 mlx5_events_stop(dev);
1185 mlx5_put_uars_page(dev, dev->priv.uar);
1186 }
1187
mlx5_load_one(struct mlx5_core_dev * dev,bool boot)1188 int mlx5_load_one(struct mlx5_core_dev *dev, bool boot)
1189 {
1190 int err = 0;
1191
1192 mutex_lock(&dev->intf_state_mutex);
1193 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1194 mlx5_core_warn(dev, "interface is up, NOP\n");
1195 goto out;
1196 }
1197 /* remove any previous indication of internal error */
1198 dev->state = MLX5_DEVICE_STATE_UP;
1199
1200 err = mlx5_function_setup(dev, boot);
1201 if (err)
1202 goto err_function;
1203
1204 if (boot) {
1205 err = mlx5_init_once(dev);
1206 if (err) {
1207 mlx5_core_err(dev, "sw objs init failed\n");
1208 goto function_teardown;
1209 }
1210 }
1211
1212 err = mlx5_load(dev);
1213 if (err)
1214 goto err_load;
1215
1216 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1217
1218 if (boot) {
1219 err = mlx5_devlink_register(priv_to_devlink(dev), dev->device);
1220 if (err)
1221 goto err_devlink_reg;
1222 mlx5_register_device(dev);
1223 } else {
1224 mlx5_attach_device(dev);
1225 }
1226
1227 mutex_unlock(&dev->intf_state_mutex);
1228 return 0;
1229
1230 err_devlink_reg:
1231 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1232 mlx5_unload(dev);
1233 err_load:
1234 if (boot)
1235 mlx5_cleanup_once(dev);
1236 function_teardown:
1237 mlx5_function_teardown(dev, boot);
1238 err_function:
1239 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1240 out:
1241 mutex_unlock(&dev->intf_state_mutex);
1242 return err;
1243 }
1244
mlx5_unload_one(struct mlx5_core_dev * dev,bool cleanup)1245 void mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup)
1246 {
1247 mutex_lock(&dev->intf_state_mutex);
1248
1249 if (cleanup) {
1250 mlx5_unregister_device(dev);
1251 mlx5_devlink_unregister(priv_to_devlink(dev));
1252 } else {
1253 mlx5_detach_device(dev);
1254 }
1255
1256 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1257 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1258 __func__);
1259 if (cleanup)
1260 mlx5_cleanup_once(dev);
1261 goto out;
1262 }
1263
1264 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1265
1266 mlx5_unload(dev);
1267
1268 if (cleanup)
1269 mlx5_cleanup_once(dev);
1270
1271 mlx5_function_teardown(dev, cleanup);
1272 out:
1273 mutex_unlock(&dev->intf_state_mutex);
1274 }
1275
mlx5_mdev_init(struct mlx5_core_dev * dev,int profile_idx)1276 static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1277 {
1278 struct mlx5_priv *priv = &dev->priv;
1279 int err;
1280
1281 dev->profile = &profile[profile_idx];
1282
1283 INIT_LIST_HEAD(&priv->ctx_list);
1284 spin_lock_init(&priv->ctx_lock);
1285 mutex_init(&dev->intf_state_mutex);
1286
1287 mutex_init(&priv->bfregs.reg_head.lock);
1288 mutex_init(&priv->bfregs.wc_head.lock);
1289 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1290 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1291
1292 mutex_init(&priv->alloc_mutex);
1293 mutex_init(&priv->pgdir_mutex);
1294 INIT_LIST_HEAD(&priv->pgdir_list);
1295
1296 priv->dbg_root = debugfs_create_dir(dev_name(dev->device),
1297 mlx5_debugfs_root);
1298 err = mlx5_health_init(dev);
1299 if (err)
1300 goto err_health_init;
1301
1302 err = mlx5_pagealloc_init(dev);
1303 if (err)
1304 goto err_pagealloc_init;
1305
1306 return 0;
1307
1308 err_pagealloc_init:
1309 mlx5_health_cleanup(dev);
1310 err_health_init:
1311 debugfs_remove(dev->priv.dbg_root);
1312 mutex_destroy(&priv->pgdir_mutex);
1313 mutex_destroy(&priv->alloc_mutex);
1314 mutex_destroy(&priv->bfregs.wc_head.lock);
1315 mutex_destroy(&priv->bfregs.reg_head.lock);
1316 mutex_destroy(&dev->intf_state_mutex);
1317 return err;
1318 }
1319
mlx5_mdev_uninit(struct mlx5_core_dev * dev)1320 static void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1321 {
1322 struct mlx5_priv *priv = &dev->priv;
1323
1324 mlx5_pagealloc_cleanup(dev);
1325 mlx5_health_cleanup(dev);
1326 debugfs_remove_recursive(dev->priv.dbg_root);
1327 mutex_destroy(&priv->pgdir_mutex);
1328 mutex_destroy(&priv->alloc_mutex);
1329 mutex_destroy(&priv->bfregs.wc_head.lock);
1330 mutex_destroy(&priv->bfregs.reg_head.lock);
1331 mutex_destroy(&dev->intf_state_mutex);
1332 }
1333
1334 #define MLX5_IB_MOD "mlx5_ib"
init_one(struct pci_dev * pdev,const struct pci_device_id * id)1335 static int init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1336 {
1337 struct mlx5_core_dev *dev;
1338 struct devlink *devlink;
1339 int err;
1340
1341 devlink = mlx5_devlink_alloc();
1342 if (!devlink) {
1343 dev_err(&pdev->dev, "devlink alloc failed\n");
1344 return -ENOMEM;
1345 }
1346
1347 dev = devlink_priv(devlink);
1348 dev->device = &pdev->dev;
1349 dev->pdev = pdev;
1350
1351 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1352 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1353
1354 err = mlx5_mdev_init(dev, prof_sel);
1355 if (err)
1356 goto mdev_init_err;
1357
1358 err = mlx5_pci_init(dev, pdev, id);
1359 if (err) {
1360 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1361 err);
1362 goto pci_init_err;
1363 }
1364
1365 err = mlx5_load_one(dev, true);
1366 if (err) {
1367 mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n",
1368 err);
1369 goto err_load_one;
1370 }
1371
1372 request_module_nowait(MLX5_IB_MOD);
1373
1374 err = mlx5_crdump_enable(dev);
1375 if (err)
1376 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err);
1377
1378 pci_save_state(pdev);
1379 devlink_reload_enable(devlink);
1380 return 0;
1381
1382 err_load_one:
1383 mlx5_pci_close(dev);
1384 pci_init_err:
1385 mlx5_mdev_uninit(dev);
1386 mdev_init_err:
1387 mlx5_devlink_free(devlink);
1388
1389 return err;
1390 }
1391
remove_one(struct pci_dev * pdev)1392 static void remove_one(struct pci_dev *pdev)
1393 {
1394 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1395 struct devlink *devlink = priv_to_devlink(dev);
1396
1397 devlink_reload_disable(devlink);
1398 mlx5_crdump_disable(dev);
1399 mlx5_drain_health_wq(dev);
1400 mlx5_unload_one(dev, true);
1401 mlx5_pci_close(dev);
1402 mlx5_mdev_uninit(dev);
1403 mlx5_devlink_free(devlink);
1404 }
1405
mlx5_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)1406 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1407 pci_channel_state_t state)
1408 {
1409 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1410
1411 mlx5_core_info(dev, "%s was called\n", __func__);
1412
1413 mlx5_enter_error_state(dev, false);
1414 mlx5_error_sw_reset(dev);
1415 mlx5_unload_one(dev, false);
1416 mlx5_drain_health_wq(dev);
1417 mlx5_pci_disable_device(dev);
1418
1419 return state == pci_channel_io_perm_failure ?
1420 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1421 }
1422
1423 /* wait for the device to show vital signs by waiting
1424 * for the health counter to start counting.
1425 */
wait_vital(struct pci_dev * pdev)1426 static int wait_vital(struct pci_dev *pdev)
1427 {
1428 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1429 struct mlx5_core_health *health = &dev->priv.health;
1430 const int niter = 100;
1431 u32 last_count = 0;
1432 u32 count;
1433 int i;
1434
1435 for (i = 0; i < niter; i++) {
1436 count = ioread32be(health->health_counter);
1437 if (count && count != 0xffffffff) {
1438 if (last_count && last_count != count) {
1439 mlx5_core_info(dev,
1440 "wait vital counter value 0x%x after %d iterations\n",
1441 count, i);
1442 return 0;
1443 }
1444 last_count = count;
1445 }
1446 msleep(50);
1447 }
1448
1449 return -ETIMEDOUT;
1450 }
1451
mlx5_pci_slot_reset(struct pci_dev * pdev)1452 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1453 {
1454 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1455 int err;
1456
1457 mlx5_core_info(dev, "%s was called\n", __func__);
1458
1459 err = mlx5_pci_enable_device(dev);
1460 if (err) {
1461 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1462 __func__, err);
1463 return PCI_ERS_RESULT_DISCONNECT;
1464 }
1465
1466 pci_set_master(pdev);
1467 pci_restore_state(pdev);
1468 pci_save_state(pdev);
1469
1470 if (wait_vital(pdev)) {
1471 mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__);
1472 return PCI_ERS_RESULT_DISCONNECT;
1473 }
1474
1475 return PCI_ERS_RESULT_RECOVERED;
1476 }
1477
mlx5_pci_resume(struct pci_dev * pdev)1478 static void mlx5_pci_resume(struct pci_dev *pdev)
1479 {
1480 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1481 int err;
1482
1483 mlx5_core_info(dev, "%s was called\n", __func__);
1484
1485 err = mlx5_load_one(dev, false);
1486 if (err)
1487 mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n",
1488 __func__, err);
1489 else
1490 mlx5_core_info(dev, "%s: device recovered\n", __func__);
1491 }
1492
1493 static const struct pci_error_handlers mlx5_err_handler = {
1494 .error_detected = mlx5_pci_err_detected,
1495 .slot_reset = mlx5_pci_slot_reset,
1496 .resume = mlx5_pci_resume
1497 };
1498
mlx5_try_fast_unload(struct mlx5_core_dev * dev)1499 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1500 {
1501 bool fast_teardown = false, force_teardown = false;
1502 int ret = 1;
1503
1504 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1505 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1506
1507 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1508 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1509
1510 if (!fast_teardown && !force_teardown)
1511 return -EOPNOTSUPP;
1512
1513 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1514 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1515 return -EAGAIN;
1516 }
1517
1518 /* Panic tear down fw command will stop the PCI bus communication
1519 * with the HCA, so the health polll is no longer needed.
1520 */
1521 mlx5_drain_health_wq(dev);
1522 mlx5_stop_health_poll(dev, false);
1523
1524 ret = mlx5_cmd_fast_teardown_hca(dev);
1525 if (!ret)
1526 goto succeed;
1527
1528 ret = mlx5_cmd_force_teardown_hca(dev);
1529 if (!ret)
1530 goto succeed;
1531
1532 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1533 mlx5_start_health_poll(dev);
1534 return ret;
1535
1536 succeed:
1537 mlx5_enter_error_state(dev, true);
1538
1539 /* Some platforms requiring freeing the IRQ's in the shutdown
1540 * flow. If they aren't freed they can't be allocated after
1541 * kexec. There is no need to cleanup the mlx5_core software
1542 * contexts.
1543 */
1544 mlx5_core_eq_free_irqs(dev);
1545
1546 return 0;
1547 }
1548
shutdown(struct pci_dev * pdev)1549 static void shutdown(struct pci_dev *pdev)
1550 {
1551 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1552 int err;
1553
1554 mlx5_core_info(dev, "Shutdown was called\n");
1555 err = mlx5_try_fast_unload(dev);
1556 if (err)
1557 mlx5_unload_one(dev, false);
1558 mlx5_pci_disable_device(dev);
1559 }
1560
mlx5_suspend(struct pci_dev * pdev,pm_message_t state)1561 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
1562 {
1563 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1564
1565 mlx5_unload_one(dev, false);
1566
1567 return 0;
1568 }
1569
mlx5_resume(struct pci_dev * pdev)1570 static int mlx5_resume(struct pci_dev *pdev)
1571 {
1572 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1573
1574 return mlx5_load_one(dev, false);
1575 }
1576
1577 static const struct pci_device_id mlx5_core_pci_table[] = {
1578 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1579 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1580 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1581 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1582 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1583 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1584 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1585 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1586 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1587 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1588 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1589 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1590 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
1591 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
1592 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
1593 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
1594 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1595 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1596 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
1597 { 0, }
1598 };
1599
1600 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1601
mlx5_disable_device(struct mlx5_core_dev * dev)1602 void mlx5_disable_device(struct mlx5_core_dev *dev)
1603 {
1604 mlx5_error_sw_reset(dev);
1605 mlx5_unload_one(dev, false);
1606 }
1607
mlx5_recover_device(struct mlx5_core_dev * dev)1608 void mlx5_recover_device(struct mlx5_core_dev *dev)
1609 {
1610 mlx5_pci_disable_device(dev);
1611 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1612 mlx5_pci_resume(dev->pdev);
1613 }
1614
1615 static struct pci_driver mlx5_core_driver = {
1616 .name = DRIVER_NAME,
1617 .id_table = mlx5_core_pci_table,
1618 .probe = init_one,
1619 .remove = remove_one,
1620 .suspend = mlx5_suspend,
1621 .resume = mlx5_resume,
1622 .shutdown = shutdown,
1623 .err_handler = &mlx5_err_handler,
1624 .sriov_configure = mlx5_core_sriov_configure,
1625 };
1626
mlx5_core_verify_params(void)1627 static void mlx5_core_verify_params(void)
1628 {
1629 if (prof_sel >= ARRAY_SIZE(profile)) {
1630 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1631 prof_sel,
1632 ARRAY_SIZE(profile) - 1,
1633 MLX5_DEFAULT_PROF);
1634 prof_sel = MLX5_DEFAULT_PROF;
1635 }
1636 }
1637
init(void)1638 static int __init init(void)
1639 {
1640 int err;
1641
1642 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1643
1644 mlx5_core_verify_params();
1645 mlx5_fpga_ipsec_build_fs_cmds();
1646 mlx5_register_debugfs();
1647
1648 err = pci_register_driver(&mlx5_core_driver);
1649 if (err)
1650 goto err_debug;
1651
1652 #ifdef CONFIG_MLX5_CORE_EN
1653 mlx5e_init();
1654 #endif
1655
1656 return 0;
1657
1658 err_debug:
1659 mlx5_unregister_debugfs();
1660 return err;
1661 }
1662
cleanup(void)1663 static void __exit cleanup(void)
1664 {
1665 #ifdef CONFIG_MLX5_CORE_EN
1666 mlx5e_cleanup();
1667 #endif
1668 pci_unregister_driver(&mlx5_core_driver);
1669 mlx5_unregister_debugfs();
1670 }
1671
1672 module_init(init);
1673 module_exit(cleanup);
1674