1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
5 */
6
7 #include <drm/drm_managed.h>
8
9 #include "dpu_kms.h"
10 #include "dpu_hw_catalog.h"
11 #include "dpu_hwio.h"
12 #include "dpu_hw_lm.h"
13 #include "dpu_hw_mdss.h"
14
15 #define LM_OP_MODE 0x00
16 #define LM_OUT_SIZE 0x04
17 #define LM_BORDER_COLOR_0 0x08
18 #define LM_BORDER_COLOR_1 0x010
19
20 /* These register are offset to mixer base + stage base */
21 #define LM_BLEND0_OP 0x00
22
23 /* <v12 DPU with offset to mixer base + stage base */
24 #define LM_BLEND0_CONST_ALPHA 0x04
25 #define LM_FG_COLOR_FILL_COLOR_0 0x08
26 #define LM_FG_COLOR_FILL_COLOR_1 0x0C
27 #define LM_FG_COLOR_FILL_SIZE 0x10
28 #define LM_FG_COLOR_FILL_XY 0x14
29
30 /* >= v12 DPU */
31 #define LM_BG_SRC_SEL_V12 0x14
32 #define LM_BG_SRC_SEL_V12_RESET_VALUE 0x0000c0c0
33 #define LM_BORDER_COLOR_0_V12 0x1c
34 #define LM_BORDER_COLOR_1_V12 0x20
35
36 /* >= v12 DPU with offset to mixer base + stage base */
37 #define LM_BLEND0_FG_SRC_SEL_V12 0x04
38 #define LM_BLEND0_CONST_ALPHA_V12 0x08
39 #define LM_FG_COLOR_FILL_COLOR_0_V12 0x0c
40 #define LM_FG_COLOR_FILL_COLOR_1_V12 0x10
41 #define LM_FG_COLOR_FILL_SIZE_V12 0x14
42 #define LM_FG_COLOR_FILL_XY_V12 0x18
43
44 #define LM_BLEND0_FG_ALPHA 0x04
45 #define LM_BLEND0_BG_ALPHA 0x08
46
47 #define LM_MISR_CTRL 0x310
48 #define LM_MISR_SIGNATURE 0x314
49
50
51 /**
52 * _stage_offset(): returns the relative offset of the blend registers
53 * for the stage to be setup
54 * @ctx: mixer ctx contains the mixer to be programmed
55 * @stage: stage index to setup
56 */
_stage_offset(struct dpu_hw_mixer * ctx,enum dpu_stage stage)57 static inline int _stage_offset(struct dpu_hw_mixer *ctx, enum dpu_stage stage)
58 {
59 const struct dpu_lm_sub_blks *sblk = ctx->cap->sblk;
60 if (stage != DPU_STAGE_BASE && stage <= sblk->maxblendstages)
61 return sblk->blendstage_base[stage - DPU_STAGE_0];
62
63 return -EINVAL;
64 }
65
dpu_hw_lm_setup_out(struct dpu_hw_mixer * ctx,struct dpu_hw_mixer_cfg * mixer)66 static void dpu_hw_lm_setup_out(struct dpu_hw_mixer *ctx,
67 struct dpu_hw_mixer_cfg *mixer)
68 {
69 struct dpu_hw_blk_reg_map *c = &ctx->hw;
70 u32 outsize;
71 u32 op_mode;
72
73 op_mode = DPU_REG_READ(c, LM_OP_MODE);
74
75 outsize = mixer->out_height << 16 | mixer->out_width;
76 DPU_REG_WRITE(c, LM_OUT_SIZE, outsize);
77
78 /* SPLIT_LEFT_RIGHT */
79 if (mixer->right_mixer)
80 op_mode |= BIT(31);
81 else
82 op_mode &= ~BIT(31);
83 DPU_REG_WRITE(c, LM_OP_MODE, op_mode);
84 }
85
dpu_hw_lm_setup_border_color(struct dpu_hw_mixer * ctx,struct dpu_mdss_color * color,u8 border_en)86 static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx,
87 struct dpu_mdss_color *color,
88 u8 border_en)
89 {
90 struct dpu_hw_blk_reg_map *c = &ctx->hw;
91
92 if (border_en) {
93 DPU_REG_WRITE(c, LM_BORDER_COLOR_0,
94 (color->color_0 & 0xFFF) |
95 ((color->color_1 & 0xFFF) << 0x10));
96 DPU_REG_WRITE(c, LM_BORDER_COLOR_1,
97 (color->color_2 & 0xFFF) |
98 ((color->color_3 & 0xFFF) << 0x10));
99 }
100 }
101
dpu_hw_lm_setup_border_color_v12(struct dpu_hw_mixer * ctx,struct dpu_mdss_color * color,u8 border_en)102 static void dpu_hw_lm_setup_border_color_v12(struct dpu_hw_mixer *ctx,
103 struct dpu_mdss_color *color,
104 u8 border_en)
105 {
106 struct dpu_hw_blk_reg_map *c = &ctx->hw;
107
108 if (border_en) {
109 DPU_REG_WRITE(c, LM_BORDER_COLOR_0_V12,
110 (color->color_0 & 0x3ff) |
111 ((color->color_1 & 0x3ff) << 16));
112 DPU_REG_WRITE(c, LM_BORDER_COLOR_1_V12,
113 (color->color_2 & 0x3ff) |
114 ((color->color_3 & 0x3ff) << 16));
115 }
116 }
117
dpu_hw_lm_setup_misr(struct dpu_hw_mixer * ctx)118 static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx)
119 {
120 dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, 0x0);
121 }
122
dpu_hw_lm_collect_misr(struct dpu_hw_mixer * ctx,u32 * misr_value)123 static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value)
124 {
125 return dpu_hw_collect_misr(&ctx->hw, LM_MISR_CTRL, LM_MISR_SIGNATURE, misr_value);
126 }
127
dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer * ctx,u32 stage,u32 fg_alpha,u32 bg_alpha,u32 blend_op)128 static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer *ctx,
129 u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)
130 {
131 struct dpu_hw_blk_reg_map *c = &ctx->hw;
132 int stage_off;
133 u32 const_alpha;
134
135 if (stage == DPU_STAGE_BASE)
136 return;
137
138 stage_off = _stage_offset(ctx, stage);
139 if (WARN_ON(stage_off < 0))
140 return;
141
142 const_alpha = (bg_alpha & 0xFF) | ((fg_alpha & 0xFF) << 16);
143 DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha);
144 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
145 }
146
147 static void
dpu_hw_lm_setup_blend_config_combined_alpha_v12(struct dpu_hw_mixer * ctx,u32 stage,u32 fg_alpha,u32 bg_alpha,u32 blend_op)148 dpu_hw_lm_setup_blend_config_combined_alpha_v12(struct dpu_hw_mixer *ctx,
149 u32 stage, u32 fg_alpha,
150 u32 bg_alpha, u32 blend_op)
151 {
152 struct dpu_hw_blk_reg_map *c = &ctx->hw;
153 int stage_off;
154 u32 const_alpha;
155
156 if (stage == DPU_STAGE_BASE)
157 return;
158
159 stage_off = _stage_offset(ctx, stage);
160 if (WARN_ON(stage_off < 0))
161 return;
162
163 const_alpha = (bg_alpha & 0x3ff) | ((fg_alpha & 0x3ff) << 16);
164 DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA_V12 + stage_off, const_alpha);
165 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
166 }
167
dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer * ctx,u32 stage,u32 fg_alpha,u32 bg_alpha,u32 blend_op)168 static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx,
169 u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)
170 {
171 struct dpu_hw_blk_reg_map *c = &ctx->hw;
172 int stage_off;
173
174 if (stage == DPU_STAGE_BASE)
175 return;
176
177 stage_off = _stage_offset(ctx, stage);
178 if (WARN_ON(stage_off < 0))
179 return;
180
181 DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha);
182 DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha);
183 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
184 }
185
dpu_hw_lm_setup_color3(struct dpu_hw_mixer * ctx,uint32_t mixer_op_mode)186 static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx,
187 uint32_t mixer_op_mode)
188 {
189 struct dpu_hw_blk_reg_map *c = &ctx->hw;
190 int op_mode;
191
192 /* read the existing op_mode configuration */
193 op_mode = DPU_REG_READ(c, LM_OP_MODE);
194
195 op_mode = (op_mode & (BIT(31) | BIT(30))) | mixer_op_mode;
196
197 DPU_REG_WRITE(c, LM_OP_MODE, op_mode);
198 }
199
dpu_hw_lm_setup_color3_v12(struct dpu_hw_mixer * ctx,uint32_t mixer_op_mode)200 static void dpu_hw_lm_setup_color3_v12(struct dpu_hw_mixer *ctx,
201 uint32_t mixer_op_mode)
202 {
203 struct dpu_hw_blk_reg_map *c = &ctx->hw;
204 int op_mode, stages, stage_off, i;
205
206 stages = ctx->cap->sblk->maxblendstages;
207 if (stages <= 0)
208 return;
209
210 for (i = DPU_STAGE_0; i <= stages; i++) {
211 stage_off = _stage_offset(ctx, i);
212 if (WARN_ON(stage_off < 0))
213 return;
214
215 /* set color_out3 bit in blend0_op when enabled in mixer_op_mode */
216 op_mode = DPU_REG_READ(c, LM_BLEND0_OP + stage_off);
217 if (mixer_op_mode & BIT(i))
218 op_mode |= BIT(30);
219 else
220 op_mode &= ~BIT(30);
221
222 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, op_mode);
223 }
224 }
225
_set_staged_sspp(u32 stage,struct dpu_hw_stage_cfg * stage_cfg,int pipes_per_stage,u32 * value)226 static int _set_staged_sspp(u32 stage, struct dpu_hw_stage_cfg *stage_cfg,
227 int pipes_per_stage, u32 *value)
228 {
229 int i;
230 u32 pipe_type = 0, pipe_id = 0, rec_id = 0;
231 u32 src_sel[PIPES_PER_STAGE];
232
233 *value = LM_BG_SRC_SEL_V12_RESET_VALUE;
234 if (!stage_cfg || !pipes_per_stage)
235 return 0;
236
237 for (i = 0; i < pipes_per_stage; i++) {
238 enum dpu_sspp pipe = stage_cfg->stage[stage][i];
239 enum dpu_sspp_multirect_index rect_index = stage_cfg->multirect_index[stage][i];
240
241 src_sel[i] = LM_BG_SRC_SEL_V12_RESET_VALUE;
242
243 if (!pipe)
244 continue;
245
246 /* translate pipe data to SWI pipe_type, pipe_id */
247 if (pipe >= SSPP_DMA0 && pipe <= SSPP_DMA5) {
248 pipe_type = 0;
249 pipe_id = pipe - SSPP_DMA0;
250 } else if (pipe >= SSPP_VIG0 && pipe <= SSPP_VIG3) {
251 pipe_type = 1;
252 pipe_id = pipe - SSPP_VIG0;
253 } else {
254 DPU_ERROR("invalid rec-%d pipe:%d\n", i, pipe);
255 return -EINVAL;
256 }
257
258 /* translate rec data to SWI rec_id */
259 if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) {
260 rec_id = 0;
261 } else if (rect_index == DPU_SSPP_RECT_1) {
262 rec_id = 1;
263 } else {
264 DPU_ERROR("invalid rec-%d rect_index:%d\n", i, rect_index);
265 rec_id = 0;
266 }
267
268 /* calculate SWI value for rec-0 and rec-1 and store it temporary buffer */
269 src_sel[i] = (((pipe_type & 0x3) << 6) | ((rec_id & 0x3) << 4) | (pipe_id & 0xf));
270 }
271
272 /* calculate final SWI register value for rec-0 and rec-1 */
273 *value = 0;
274 for (i = 0; i < pipes_per_stage; i++)
275 *value |= src_sel[i] << (i * 8);
276
277 return 0;
278 }
279
dpu_hw_lm_setup_blendstage(struct dpu_hw_mixer * ctx,enum dpu_lm lm,struct dpu_hw_stage_cfg * stage_cfg)280 static int dpu_hw_lm_setup_blendstage(struct dpu_hw_mixer *ctx, enum dpu_lm lm,
281 struct dpu_hw_stage_cfg *stage_cfg)
282 {
283 struct dpu_hw_blk_reg_map *c = &ctx->hw;
284 int i, ret, stages, stage_off, pipes_per_stage;
285 u32 value;
286
287 stages = ctx->cap->sblk->maxblendstages;
288 if (stages <= 0)
289 return -EINVAL;
290
291 if (test_bit(DPU_MIXER_SOURCESPLIT, &ctx->cap->features))
292 pipes_per_stage = PIPES_PER_STAGE;
293 else
294 pipes_per_stage = 1;
295
296 /*
297 * When stage configuration is empty, we can enable the
298 * border color by setting the corresponding LAYER_ACTIVE bit
299 * and un-staging all the pipes from the layer mixer.
300 */
301 if (!stage_cfg)
302 DPU_REG_WRITE(c, LM_BG_SRC_SEL_V12, LM_BG_SRC_SEL_V12_RESET_VALUE);
303
304 for (i = DPU_STAGE_0; i <= stages; i++) {
305 stage_off = _stage_offset(ctx, i);
306 if (stage_off < 0)
307 return stage_off;
308
309 ret = _set_staged_sspp(i, stage_cfg, pipes_per_stage, &value);
310 if (ret)
311 return ret;
312
313 DPU_REG_WRITE(c, LM_BLEND0_FG_SRC_SEL_V12 + stage_off, value);
314 }
315
316 return 0;
317 }
318
dpu_hw_lm_clear_all_blendstages(struct dpu_hw_mixer * ctx)319 static int dpu_hw_lm_clear_all_blendstages(struct dpu_hw_mixer *ctx)
320 {
321 struct dpu_hw_blk_reg_map *c = &ctx->hw;
322 int i, stages, stage_off;
323
324 stages = ctx->cap->sblk->maxblendstages;
325 if (stages <= 0)
326 return -EINVAL;
327
328 DPU_REG_WRITE(c, LM_BG_SRC_SEL_V12, LM_BG_SRC_SEL_V12_RESET_VALUE);
329
330 for (i = DPU_STAGE_0; i <= stages; i++) {
331 stage_off = _stage_offset(ctx, i);
332 if (stage_off < 0)
333 return stage_off;
334
335 DPU_REG_WRITE(c, LM_BLEND0_FG_SRC_SEL_V12 + stage_off,
336 LM_BG_SRC_SEL_V12_RESET_VALUE);
337 }
338
339 return 0;
340 }
341
342 /**
343 * dpu_hw_lm_init() - Initializes the mixer hw driver object.
344 * should be called once before accessing every mixer.
345 * @dev: Corresponding device for devres management
346 * @cfg: mixer catalog entry for which driver object is required
347 * @addr: mapped register io address of MDP
348 * @mdss_ver: DPU core's major and minor versions
349 */
dpu_hw_lm_init(struct drm_device * dev,const struct dpu_lm_cfg * cfg,void __iomem * addr,const struct dpu_mdss_version * mdss_ver)350 struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev,
351 const struct dpu_lm_cfg *cfg,
352 void __iomem *addr,
353 const struct dpu_mdss_version *mdss_ver)
354 {
355 struct dpu_hw_mixer *c;
356
357 if (cfg->pingpong == PINGPONG_NONE) {
358 DPU_DEBUG("skip mixer %d without pingpong\n", cfg->id);
359 return NULL;
360 }
361
362 c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL);
363 if (!c)
364 return ERR_PTR(-ENOMEM);
365
366 c->hw.blk_addr = addr + cfg->base;
367 c->hw.log_mask = DPU_DBG_MASK_LM;
368
369 /* Assign ops */
370 c->idx = cfg->id;
371 c->cap = cfg;
372 c->ops.setup_mixer_out = dpu_hw_lm_setup_out;
373 if (mdss_ver->core_major_ver >= 12)
374 c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha_v12;
375 else if (mdss_ver->core_major_ver >= 4)
376 c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha;
377 else
378 c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config;
379 if (mdss_ver->core_major_ver < 12) {
380 c->ops.setup_alpha_out = dpu_hw_lm_setup_color3;
381 c->ops.setup_border_color = dpu_hw_lm_setup_border_color;
382 } else {
383 c->ops.setup_alpha_out = dpu_hw_lm_setup_color3_v12;
384 c->ops.setup_blendstage = dpu_hw_lm_setup_blendstage;
385 c->ops.clear_all_blendstages = dpu_hw_lm_clear_all_blendstages;
386 c->ops.setup_border_color = dpu_hw_lm_setup_border_color_v12;
387 }
388 c->ops.setup_misr = dpu_hw_lm_setup_misr;
389 c->ops.collect_misr = dpu_hw_lm_collect_misr;
390
391 return c;
392 }
393