1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DML2_INTERNAL_SHARED_TYPES_H__ 6 #define __DML2_INTERNAL_SHARED_TYPES_H__ 7 8 #include "dml2_external_lib_deps.h" 9 #include "dml_top_types.h" 10 #include "dml2_core_shared_types.h" 11 /* 12 * DML2 MCG Types and Interfaces 13 */ 14 15 #define DML_MCG_MAX_CLK_TABLE_SIZE 20 16 17 struct dram_bw_to_min_clk_table_entry { 18 unsigned long long pre_derate_dram_bw_kbps; 19 unsigned long min_fclk_khz; 20 unsigned long min_dcfclk_khz; 21 }; 22 23 struct dml2_mcg_dram_bw_to_min_clk_table { 24 struct dram_bw_to_min_clk_table_entry entries[DML_MCG_MAX_CLK_TABLE_SIZE]; 25 26 unsigned int num_entries; 27 }; 28 29 struct dml2_mcg_min_clock_table { 30 struct { 31 unsigned int dispclk; 32 unsigned int dppclk; 33 unsigned int dscclk; 34 unsigned int dtbclk; 35 unsigned int phyclk; 36 unsigned int fclk; 37 unsigned int dcfclk; 38 } max_clocks_khz; 39 40 struct { 41 unsigned int dispclk; 42 unsigned int dppclk; 43 unsigned int dtbclk; 44 } max_ss_clocks_khz; 45 46 struct { 47 unsigned int dprefclk; 48 unsigned int xtalclk; 49 unsigned int pcierefclk; 50 unsigned int dchubrefclk; 51 unsigned int amclk; 52 } fixed_clocks_khz; 53 54 struct dml2_mcg_dram_bw_to_min_clk_table dram_bw_table; 55 }; 56 57 struct dml2_mcg_build_min_clock_table_params_in_out { 58 /* 59 * Input 60 */ 61 struct dml2_soc_bb *soc_bb; 62 struct { 63 bool perform_pseudo_build; 64 } clean_me_up; 65 66 /* 67 * Output 68 */ 69 struct dml2_mcg_min_clock_table *min_clk_table; 70 }; 71 struct dml2_mcg_instance { 72 bool (*build_min_clock_table)(struct dml2_mcg_build_min_clock_table_params_in_out *in_out); 73 }; 74 75 /* 76 * DML2 DPMM Types and Interfaces 77 */ 78 79 struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out { 80 /* 81 * Input 82 */ 83 struct dml2_core_ip_params *ip; 84 struct dml2_soc_bb *soc_bb; 85 struct dml2_mcg_min_clock_table *min_clk_table; 86 const struct display_configuation_with_meta *display_cfg; 87 struct { 88 bool perform_pseudo_map; 89 struct dml2_core_internal_soc_bb *soc_bb; 90 } clean_me_up; 91 92 /* 93 * Output 94 */ 95 struct dml2_display_cfg_programming *programming; 96 }; 97 98 struct dml2_dpmm_map_watermarks_params_in_out { 99 /* 100 * Input 101 */ 102 const struct display_configuation_with_meta *display_cfg; 103 const struct dml2_core_instance *core; 104 105 /* 106 * Output 107 */ 108 struct dml2_display_cfg_programming *programming; 109 }; 110 111 struct dml2_dpmm_scratch { 112 struct dml2_display_cfg_programming programming; 113 }; 114 115 struct dml2_dpmm_instance { 116 bool (*map_mode_to_soc_dpm)(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out); 117 bool (*map_watermarks)(struct dml2_dpmm_map_watermarks_params_in_out *in_out); 118 119 struct dml2_dpmm_scratch dpmm_scratch; 120 }; 121 122 /* 123 * DML2 Core Types and Interfaces 124 */ 125 126 struct dml2_core_initialize_in_out { 127 enum dml2_project_id project_id; 128 struct dml2_core_instance *instance; 129 struct dml2_soc_bb *soc_bb; 130 struct dml2_ip_capabilities *ip_caps; 131 132 struct dml2_mcg_min_clock_table *minimum_clock_table; 133 134 void *explicit_ip_bb; 135 unsigned int explicit_ip_bb_size; 136 137 // FIXME_STAGE2 can remove but dcn3 version still need this 138 struct { 139 struct soc_bounding_box_st *soc_bb; 140 struct soc_states_st *soc_states; 141 } legacy; 142 }; 143 144 struct core_bandwidth_requirements { 145 int urgent_bandwidth_kbytes_per_sec; 146 int average_bandwidth_kbytes_per_sec; 147 }; 148 149 struct core_plane_support_info { 150 int dpps_used; 151 int dram_change_latency_hiding_margin_in_active; 152 int active_latency_hiding_us; 153 int mall_svp_size_requirement_ways; 154 int nominal_vblank_pstate_latency_hiding_us; 155 unsigned int dram_change_vactive_det_fill_delay_us; 156 }; 157 158 struct core_stream_support_info { 159 unsigned int odms_used; 160 unsigned int num_odm_output_segments; // for odm split mode (e.g. a value of 2 for odm_mode_mso_1to2) 161 162 /* FAMS2 SubVP support info */ 163 unsigned int phantom_min_v_active; 164 unsigned int phantom_v_startup; 165 166 unsigned int phantom_v_active; 167 unsigned int phantom_v_total; 168 int vblank_reserved_time_us; 169 int num_dsc_slices; 170 bool dsc_enable; 171 }; 172 173 struct core_display_cfg_support_info { 174 bool is_supported; 175 176 struct core_stream_support_info stream_support_info[DML2_MAX_PLANES]; 177 struct core_plane_support_info plane_support_info[DML2_MAX_PLANES]; 178 179 struct { 180 struct dml2_core_internal_mode_support_info support_info; 181 } clean_me_up; 182 }; 183 184 struct dml2_core_mode_support_result { 185 struct { 186 struct { 187 unsigned long urgent_bw_sdp_kbps; 188 unsigned long average_bw_sdp_kbps; 189 unsigned long urgent_bw_dram_kbps; 190 unsigned long average_bw_dram_kbps; 191 unsigned long dcfclk_khz; 192 unsigned long fclk_khz; 193 } svp_prefetch; 194 195 struct { 196 unsigned long urgent_bw_sdp_kbps; 197 unsigned long average_bw_sdp_kbps; 198 unsigned long urgent_bw_dram_kbps; 199 unsigned long average_bw_dram_kbps; 200 unsigned long dcfclk_khz; 201 unsigned long fclk_khz; 202 } active; 203 204 unsigned int dispclk_khz; 205 unsigned int dpprefclk_khz; 206 unsigned int dtbrefclk_khz; 207 unsigned int dcfclk_deepsleep_khz; 208 unsigned int socclk_khz; 209 210 unsigned int uclk_pstate_supported; 211 unsigned int fclk_pstate_supported; 212 } global; 213 214 struct { 215 unsigned int dscclk_khz; 216 unsigned int dtbclk_khz; 217 unsigned int phyclk_khz; 218 } per_stream[DML2_MAX_PLANES]; 219 220 struct { 221 unsigned int dppclk_khz; 222 unsigned int mall_svp_allocation_mblks; 223 unsigned int mall_full_frame_allocation_mblks; 224 } per_plane[DML2_MAX_PLANES]; 225 226 struct core_display_cfg_support_info cfg_support_info; 227 }; 228 229 struct dml2_optimization_stage1_state { 230 bool performed; 231 bool success; 232 233 int min_clk_index_for_latency; 234 }; 235 236 struct dml2_optimization_stage2_state { 237 bool performed; 238 bool success; 239 240 // Whether or not each plane supports mcache 241 // The number of valid elements == display_cfg.num_planes 242 // The indexing of pstate_switch_modes matches plane_descriptors[] 243 bool per_plane_mcache_support[DML2_MAX_PLANES]; 244 struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES]; 245 }; 246 247 #define DML2_PMO_LEGACY_PREFETCH_MAX_TWAIT_OPTIONS 8 248 #define DML2_PMO_PSTATE_CANDIDATE_LIST_SIZE 10 249 #define DML2_PMO_STUTTER_CANDIDATE_LIST_SIZE 3 250 251 struct dml2_implicit_svp_meta { 252 bool valid; 253 unsigned long v_active; 254 unsigned long v_total; 255 unsigned long v_front_porch; 256 }; 257 258 struct dml2_fams2_per_method_common_meta { 259 /* generic params */ 260 unsigned int allow_start_otg_vline; 261 unsigned int allow_end_otg_vline; 262 /* scheduling params */ 263 double allow_time_us; 264 double disallow_time_us; 265 double period_us; 266 }; 267 268 struct dml2_fams2_meta { 269 bool valid; 270 double otg_vline_time_us; 271 unsigned int scheduling_delay_otg_vlines; 272 unsigned int vertical_interrupt_ack_delay_otg_vlines; 273 unsigned int allow_to_target_delay_otg_vlines; 274 unsigned int contention_delay_otg_vlines; 275 unsigned int min_allow_width_otg_vlines; 276 unsigned int nom_vtotal; 277 unsigned int vblank_start; 278 double nom_refresh_rate_hz; 279 double nom_frame_time_us; 280 unsigned int max_vtotal; 281 double min_refresh_rate_hz; 282 double max_frame_time_us; 283 unsigned int dram_clk_change_blackout_otg_vlines; 284 struct { 285 double max_vactive_det_fill_delay_us; 286 unsigned int max_vactive_det_fill_delay_otg_vlines; 287 struct dml2_fams2_per_method_common_meta common; 288 } method_vactive; 289 struct { 290 struct dml2_fams2_per_method_common_meta common; 291 } method_vblank; 292 struct { 293 unsigned int programming_delay_otg_vlines; 294 unsigned int df_throttle_delay_otg_vlines; 295 unsigned int prefetch_to_mall_delay_otg_vlines; 296 unsigned long phantom_vactive; 297 unsigned long phantom_vfp; 298 unsigned long phantom_vtotal; 299 struct dml2_fams2_per_method_common_meta common; 300 } method_subvp; 301 struct { 302 unsigned int programming_delay_otg_vlines; 303 unsigned int stretched_vtotal; 304 struct dml2_fams2_per_method_common_meta common; 305 } method_drr; 306 }; 307 308 struct dml2_optimization_stage3_state { 309 bool performed; 310 bool success; 311 312 // The pstate support mode for each plane 313 // The number of valid elements == display_cfg.num_planes 314 // The indexing of pstate_switch_modes matches plane_descriptors[] 315 enum dml2_pstate_method pstate_switch_modes[DML2_MAX_PLANES]; 316 317 // Meta-data for implicit SVP generation, indexed by stream index 318 struct dml2_implicit_svp_meta stream_svp_meta[DML2_MAX_PLANES]; 319 320 // Meta-data for FAMS2 321 bool fams2_required; 322 struct dml2_fams2_meta stream_fams2_meta[DML2_MAX_PLANES]; 323 324 int min_clk_index_for_latency; 325 }; 326 327 struct dml2_optimization_stage4_state { 328 bool performed; 329 bool success; 330 bool unoptimizable_streams[DML2_MAX_DCN_PIPES]; 331 }; 332 333 struct dml2_optimization_stage5_state { 334 bool performed; 335 bool success; 336 337 bool optimal_reserved_time_in_vblank_us; 338 bool vblank_includes_z8_optimization; 339 }; 340 341 struct display_configuation_with_meta { 342 struct dml2_display_cfg display_config; 343 344 struct dml2_core_mode_support_result mode_support_result; 345 346 // Stage 1 = Min Clocks for Latency 347 struct dml2_optimization_stage1_state stage1; 348 349 // Stage 2 = MCache 350 struct dml2_optimization_stage2_state stage2; 351 352 // Stage 3 = UCLK PState 353 struct dml2_optimization_stage3_state stage3; 354 355 // Stage 4 = Vmin 356 struct dml2_optimization_stage4_state stage4; 357 358 // Stage 5 = Stutter 359 struct dml2_optimization_stage5_state stage5; 360 }; 361 362 struct dml2_pmo_pstate_strategy { 363 enum dml2_pstate_method per_stream_pstate_method[DML2_MAX_PLANES]; 364 bool allow_state_increase; 365 }; 366 struct dml2_core_mode_support_in_out { 367 /* 368 * Inputs 369 */ 370 struct dml2_core_instance *instance; 371 const struct display_configuation_with_meta *display_cfg; 372 373 struct dml2_mcg_min_clock_table *min_clk_table; 374 int min_clk_index; 375 /* 376 * Outputs 377 */ 378 struct dml2_core_mode_support_result mode_support_result; 379 380 struct { 381 // Inputs 382 struct dml_display_cfg_st *display_cfg; 383 384 // Outputs 385 struct dml_mode_support_info_st *support_info; 386 unsigned int out_lowest_state_idx; 387 unsigned int min_fclk_khz; 388 unsigned int min_dcfclk_khz; 389 unsigned int min_dram_speed_mts; 390 unsigned int min_socclk_khz; 391 unsigned int min_dscclk_khz; 392 unsigned int min_dtbclk_khz; 393 unsigned int min_phyclk_khz; 394 } legacy; 395 }; 396 397 struct dml2_core_mode_programming_in_out { 398 /* 399 * Inputs 400 */ 401 struct dml2_core_instance *instance; 402 const struct display_configuation_with_meta *display_cfg; 403 const struct core_display_cfg_support_info *cfg_support_info; 404 /* 405 * Outputs (also Input the clk freq are also from programming struct) 406 */ 407 struct dml2_display_cfg_programming *programming; 408 409 }; 410 411 struct dml2_core_populate_informative_in_out { 412 /* 413 * Inputs 414 */ 415 struct dml2_core_instance *instance; 416 417 // If this is set, then the mode was supported, and mode programming 418 // was successfully run. 419 // Otherwise, mode programming was not run, because mode support failed. 420 bool mode_is_supported; 421 422 /* 423 * Outputs 424 */ 425 struct dml2_display_cfg_programming *programming; 426 }; 427 428 struct dml2_calculate_mcache_allocation_in_out { 429 /* 430 * Inputs 431 */ 432 struct dml2_core_instance *instance; 433 const struct dml2_plane_parameters *plane_descriptor; 434 unsigned int plane_index; 435 436 /* 437 * Outputs 438 */ 439 struct dml2_mcache_surface_allocation *mcache_allocation; 440 }; 441 442 struct dml2_core_internal_state_inputs { 443 unsigned int dummy; 444 }; 445 446 struct dml2_core_internal_state_intermediates { 447 unsigned int dummy; 448 }; 449 450 struct dml2_core_mode_support_locals { 451 union { 452 struct dml2_core_calcs_mode_support_ex mode_support_ex_params; 453 }; 454 struct dml2_display_cfg svp_expanded_display_cfg; 455 struct dml2_calculate_mcache_allocation_in_out calc_mcache_allocation_params; 456 }; 457 458 struct dml2_core_mode_programming_locals { 459 union { 460 struct dml2_core_calcs_mode_programming_ex mode_programming_ex_params; 461 }; 462 struct dml2_display_cfg svp_expanded_display_cfg; 463 }; 464 465 struct dml2_core_scratch { 466 struct dml2_core_mode_support_locals mode_support_locals; 467 struct dml2_core_mode_programming_locals mode_programming_locals; 468 int main_stream_index_from_svp_stream_index[DML2_MAX_PLANES]; 469 int svp_stream_index_from_main_stream_index[DML2_MAX_PLANES]; 470 int main_plane_index_to_phantom_plane_index[DML2_MAX_PLANES]; 471 int phantom_plane_index_to_main_plane_index[DML2_MAX_PLANES]; 472 }; 473 474 struct dml2_core_instance { 475 struct dml2_mcg_min_clock_table *minimum_clock_table; 476 struct dml2_core_internal_state_inputs inputs; 477 struct dml2_core_internal_state_intermediates intermediates; 478 479 struct dml2_core_scratch scratch; 480 481 bool (*initialize)(struct dml2_core_initialize_in_out *in_out); 482 bool (*mode_support)(struct dml2_core_mode_support_in_out *in_out); 483 bool (*mode_programming)(struct dml2_core_mode_programming_in_out *in_out); 484 bool (*populate_informative)(struct dml2_core_populate_informative_in_out *in_out); 485 bool (*calculate_mcache_allocation)(struct dml2_calculate_mcache_allocation_in_out *in_out); 486 487 struct { 488 struct dml2_core_internal_display_mode_lib mode_lib; 489 } clean_me_up; 490 }; 491 492 /* 493 * DML2 PMO Types and Interfaces 494 */ 495 496 struct dml2_pmo_initialize_in_out { 497 /* 498 * Input 499 */ 500 struct dml2_pmo_instance *instance; 501 struct dml2_soc_bb *soc_bb; 502 struct dml2_ip_capabilities *ip_caps; 503 struct dml2_pmo_options *options; 504 int mcg_clock_table_size; 505 }; 506 507 struct dml2_pmo_optimize_dcc_mcache_in_out { 508 /* 509 * Input 510 */ 511 struct dml2_pmo_instance *instance; 512 const struct dml2_display_cfg *display_config; 513 bool *dcc_mcache_supported; 514 struct core_display_cfg_support_info *cfg_support_info; 515 516 /* 517 * Output 518 */ 519 struct dml2_display_cfg *optimized_display_cfg; 520 }; 521 522 struct dml2_pmo_init_for_vmin_in_out { 523 /* 524 * Input 525 */ 526 struct dml2_pmo_instance *instance; 527 struct display_configuation_with_meta *base_display_config; 528 }; 529 530 struct dml2_pmo_test_for_vmin_in_out { 531 /* 532 * Input 533 */ 534 struct dml2_pmo_instance *instance; 535 const struct display_configuation_with_meta *display_config; 536 const struct dml2_soc_vmin_clock_limits *vmin_limits; 537 }; 538 539 struct dml2_pmo_optimize_for_vmin_in_out { 540 /* 541 * Input 542 */ 543 struct dml2_pmo_instance *instance; 544 struct display_configuation_with_meta *base_display_config; 545 546 /* 547 * Output 548 */ 549 struct display_configuation_with_meta *optimized_display_config; 550 }; 551 552 struct dml2_pmo_init_for_pstate_support_in_out { 553 /* 554 * Input 555 */ 556 struct dml2_pmo_instance *instance; 557 struct display_configuation_with_meta *base_display_config; 558 }; 559 560 struct dml2_pmo_test_for_pstate_support_in_out { 561 /* 562 * Input 563 */ 564 struct dml2_pmo_instance *instance; 565 struct display_configuation_with_meta *base_display_config; 566 }; 567 568 struct dml2_pmo_optimize_for_pstate_support_in_out { 569 /* 570 * Input 571 */ 572 struct dml2_pmo_instance *instance; 573 struct display_configuation_with_meta *base_display_config; 574 bool last_candidate_failed; 575 576 /* 577 * Output 578 */ 579 struct display_configuation_with_meta *optimized_display_config; 580 }; 581 582 struct dml2_pmo_init_for_stutter_in_out { 583 /* 584 * Input 585 */ 586 struct dml2_pmo_instance *instance; 587 struct display_configuation_with_meta *base_display_config; 588 }; 589 590 struct dml2_pmo_test_for_stutter_in_out { 591 /* 592 * Input 593 */ 594 struct dml2_pmo_instance *instance; 595 struct display_configuation_with_meta *base_display_config; 596 }; 597 598 struct dml2_pmo_optimize_for_stutter_in_out { 599 /* 600 * Input 601 */ 602 struct dml2_pmo_instance *instance; 603 struct display_configuation_with_meta *base_display_config; 604 bool last_candidate_failed; 605 606 /* 607 * Output 608 */ 609 struct display_configuation_with_meta *optimized_display_config; 610 }; 611 612 #define PMO_NO_DRR_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw - dml2_pstate_method_na + 1)) - 1) << dml2_pstate_method_na) 613 #define PMO_DRR_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_var - dml2_pstate_method_fw_vactive_drr + 1)) - 1) << dml2_pstate_method_fw_vactive_drr) 614 #define PMO_DRR_CLAMPED_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_clamped - dml2_pstate_method_fw_vactive_drr + 1)) - 1) << dml2_pstate_method_fw_vactive_drr) 615 #define PMO_DRR_VAR_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_var - dml2_pstate_method_fw_drr + 1)) - 1) << dml2_pstate_method_fw_drr) 616 #define PMO_FW_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_var - dml2_pstate_method_fw_svp + 1)) - 1) << dml2_pstate_method_fw_svp) 617 618 #define PMO_DCN4_MAX_DISPLAYS 4 619 #define PMO_DCN4_MAX_NUM_VARIANTS 2 620 #define PMO_DCN4_MAX_BASE_STRATEGIES 10 621 622 struct dml2_pmo_scratch { 623 union { 624 struct { 625 double reserved_time_candidates[DML2_MAX_PLANES][DML2_PMO_LEGACY_PREFETCH_MAX_TWAIT_OPTIONS]; 626 int reserved_time_candidates_count[DML2_MAX_PLANES]; 627 int current_candidate[DML2_MAX_PLANES]; 628 int min_latency_index; 629 int max_latency_index; 630 int cur_latency_index; 631 int stream_mask; 632 } pmo_dcn3; 633 struct { 634 struct dml2_pmo_pstate_strategy expanded_override_strategy_list[2 * 2 * 2 * 2]; 635 unsigned int num_expanded_override_strategies; 636 struct dml2_pmo_pstate_strategy pstate_strategy_candidates[DML2_PMO_PSTATE_CANDIDATE_LIST_SIZE]; 637 int num_pstate_candidates; 638 int cur_pstate_candidate; 639 640 unsigned int stream_plane_mask[DML2_MAX_PLANES]; 641 642 unsigned int stream_vactive_capability_mask; 643 644 int min_latency_index; 645 int max_latency_index; 646 int cur_latency_index; 647 648 // Stores all the implicit SVP meta information indexed by stream index of the display 649 // configuration under inspection, built at optimization stage init 650 struct dml2_implicit_svp_meta stream_svp_meta[DML2_MAX_PLANES]; 651 struct dml2_fams2_meta stream_fams2_meta[DML2_MAX_PLANES]; 652 653 unsigned int optimal_vblank_reserved_time_for_stutter_us[DML2_PMO_STUTTER_CANDIDATE_LIST_SIZE]; 654 unsigned int num_stutter_candidates; 655 unsigned int cur_stutter_candidate; 656 bool z8_vblank_optimizable; 657 658 /* mask of synchronized timings by stream index */ 659 unsigned int num_timing_groups; 660 unsigned int synchronized_timing_group_masks[DML2_MAX_PLANES]; 661 bool group_is_drr_enabled[DML2_MAX_PLANES]; 662 bool group_is_drr_active[DML2_MAX_PLANES]; 663 double group_line_time_us[DML2_MAX_PLANES]; 664 665 /* scheduling check locals */ 666 struct dml2_fams2_per_method_common_meta group_common_fams2_meta[DML2_MAX_PLANES]; 667 unsigned int sorted_group_gtl_disallow_index[DML2_MAX_PLANES]; 668 unsigned int sorted_group_gtl_period_index[DML2_MAX_PLANES]; 669 double group_phase_offset[DML2_MAX_PLANES]; 670 } pmo_dcn4; 671 }; 672 }; 673 674 struct dml2_pmo_init_data { 675 union { 676 struct { 677 /* populated once during initialization */ 678 struct dml2_pmo_pstate_strategy expanded_strategy_list_1_display[PMO_DCN4_MAX_BASE_STRATEGIES * 2]; 679 struct dml2_pmo_pstate_strategy expanded_strategy_list_2_display[PMO_DCN4_MAX_BASE_STRATEGIES * 4 * 4]; 680 struct dml2_pmo_pstate_strategy expanded_strategy_list_3_display[PMO_DCN4_MAX_BASE_STRATEGIES * 6 * 6 * 6]; 681 struct dml2_pmo_pstate_strategy expanded_strategy_list_4_display[PMO_DCN4_MAX_BASE_STRATEGIES * 8 * 8 * 8 * 8]; 682 unsigned int num_expanded_strategies_per_list[PMO_DCN4_MAX_DISPLAYS]; 683 } pmo_dcn4; 684 }; 685 }; 686 687 struct dml2_pmo_instance { 688 struct dml2_soc_bb *soc_bb; 689 struct dml2_ip_capabilities *ip_caps; 690 691 struct dml2_pmo_options *options; 692 693 int disp_clk_vmin_threshold; 694 int mpc_combine_limit; 695 int odm_combine_limit; 696 int mcg_clock_table_size; 697 union { 698 struct { 699 struct { 700 int prefetch_end_to_mall_start_us; 701 int fw_processing_delay_us; 702 int refresh_rate_limit_min; 703 int refresh_rate_limit_max; 704 } subvp; 705 } v1; 706 struct { 707 struct { 708 int refresh_rate_limit_min; 709 int refresh_rate_limit_max; 710 } subvp; 711 struct { 712 int refresh_rate_limit_min; 713 int refresh_rate_limit_max; 714 } drr; 715 } v2; 716 } fams_params; 717 718 bool (*initialize)(struct dml2_pmo_initialize_in_out *in_out); 719 bool (*optimize_dcc_mcache)(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out); 720 721 bool (*init_for_vmin)(struct dml2_pmo_init_for_vmin_in_out *in_out); 722 bool (*test_for_vmin)(struct dml2_pmo_test_for_vmin_in_out *in_out); 723 bool (*optimize_for_vmin)(struct dml2_pmo_optimize_for_vmin_in_out *in_out); 724 725 bool (*init_for_uclk_pstate)(struct dml2_pmo_init_for_pstate_support_in_out *in_out); 726 bool (*test_for_uclk_pstate)(struct dml2_pmo_test_for_pstate_support_in_out *in_out); 727 bool (*optimize_for_uclk_pstate)(struct dml2_pmo_optimize_for_pstate_support_in_out *in_out); 728 729 bool (*init_for_stutter)(struct dml2_pmo_init_for_stutter_in_out *in_out); 730 bool (*test_for_stutter)(struct dml2_pmo_test_for_stutter_in_out *in_out); 731 bool (*optimize_for_stutter)(struct dml2_pmo_optimize_for_stutter_in_out *in_out); 732 733 struct dml2_pmo_init_data init_data; 734 struct dml2_pmo_scratch scratch; 735 }; 736 737 /* 738 * DML2 MCache Types 739 */ 740 741 struct top_mcache_validate_admissability_in_out { 742 struct dml2_instance *dml2_instance; 743 744 const struct dml2_display_cfg *display_cfg; 745 const struct core_display_cfg_support_info *cfg_support_info; 746 struct dml2_mcache_surface_allocation *mcache_allocations; 747 748 bool per_plane_status[DML2_MAX_PLANES]; 749 750 struct { 751 const struct dml_mode_support_info_st *mode_support_info; 752 } legacy; 753 }; 754 755 struct top_mcache_assign_ids_in_out { 756 /* 757 * Input 758 */ 759 const struct dml2_mcache_surface_allocation *mcache_allocations; 760 int plane_count; 761 762 int per_pipe_viewport_x_start[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; 763 int per_pipe_viewport_x_end[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; 764 int pipe_count_per_plane[DML2_MAX_PLANES]; 765 766 struct dml2_display_mcache_regs *current_mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; //One set per pipe/hubp 767 768 /* 769 * Output 770 */ 771 struct dml2_display_mcache_regs mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; //One set per pipe/hubp 772 struct dml2_build_mcache_programming_in_out *mcache_programming; 773 }; 774 775 struct top_mcache_calc_mcache_count_and_offsets_in_out { 776 /* 777 * Inputs 778 */ 779 struct dml2_instance *dml2_instance; 780 const struct dml2_display_cfg *display_config; 781 782 /* 783 * Outputs 784 */ 785 struct dml2_mcache_surface_allocation *mcache_allocations; 786 }; 787 788 struct top_mcache_assign_global_mcache_ids_in_out { 789 /* 790 * Inputs/Outputs 791 */ 792 struct dml2_mcache_surface_allocation *allocations; 793 int num_allocations; 794 }; 795 796 /* 797 * DML2 Top Types 798 */ 799 800 struct dml2_initialize_instance_locals { 801 int dummy; 802 }; 803 804 struct dml2_optimization_init_function_locals { 805 union { 806 struct { 807 struct dml2_pmo_init_for_pstate_support_in_out init_params; 808 } uclk_pstate; 809 struct { 810 struct dml2_pmo_init_for_stutter_in_out stutter_params; 811 } stutter; 812 struct { 813 struct dml2_pmo_init_for_vmin_in_out init_params; 814 } vmin; 815 }; 816 }; 817 818 struct dml2_optimization_test_function_locals { 819 union { 820 struct { 821 struct top_mcache_calc_mcache_count_and_offsets_in_out calc_mcache_count_params; 822 struct top_mcache_assign_global_mcache_ids_in_out assign_global_mcache_ids_params; 823 struct top_mcache_validate_admissability_in_out validate_admissibility_params; 824 } test_mcache; 825 struct { 826 struct dml2_pmo_test_for_vmin_in_out pmo_test_vmin_params; 827 } test_vmin; 828 struct { 829 struct dml2_pmo_test_for_pstate_support_in_out test_params; 830 } uclk_pstate; 831 struct { 832 struct dml2_pmo_test_for_stutter_in_out stutter_params; 833 } stutter; 834 }; 835 }; 836 837 struct dml2_optimization_optimize_function_locals { 838 union { 839 struct { 840 struct dml2_pmo_optimize_dcc_mcache_in_out optimize_mcache_params; 841 } optimize_mcache; 842 struct { 843 struct dml2_pmo_optimize_for_vmin_in_out pmo_optimize_vmin_params; 844 } optimize_vmin; 845 struct { 846 struct dml2_pmo_optimize_for_pstate_support_in_out optimize_params; 847 } uclk_pstate; 848 struct { 849 struct dml2_pmo_optimize_for_stutter_in_out stutter_params; 850 } stutter; 851 }; 852 }; 853 854 struct dml2_optimization_phase_locals { 855 struct display_configuation_with_meta cur_candidate_display_cfg; 856 struct display_configuation_with_meta next_candidate_display_cfg; 857 struct dml2_core_mode_support_in_out mode_support_params; 858 struct dml2_optimization_init_function_locals init_function_locals; 859 struct dml2_optimization_test_function_locals test_function_locals; 860 struct dml2_optimization_optimize_function_locals optimize_function_locals; 861 }; 862 863 struct dml2_check_mode_supported_locals { 864 struct dml2_display_cfg display_cfg_working_copy; 865 struct dml2_core_mode_support_in_out mode_support_params; 866 struct dml2_optimization_phase_locals optimization_phase_locals; 867 struct display_configuation_with_meta base_display_config_with_meta; 868 struct display_configuation_with_meta optimized_display_config_with_meta; 869 struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out dppm_map_mode_params; 870 }; 871 872 struct optimization_init_function_params { 873 struct dml2_optimization_init_function_locals *locals; 874 struct dml2_instance *dml; 875 struct display_configuation_with_meta *display_config; 876 }; 877 878 struct optimization_test_function_params { 879 struct dml2_optimization_test_function_locals *locals; 880 struct dml2_instance *dml; 881 struct display_configuation_with_meta *display_config; 882 }; 883 884 struct optimization_optimize_function_params { 885 bool last_candidate_supported; 886 struct dml2_optimization_optimize_function_locals *locals; 887 struct dml2_instance *dml; 888 struct display_configuation_with_meta *display_config; 889 struct display_configuation_with_meta *optimized_display_config; 890 }; 891 892 struct optimization_phase_params { 893 struct dml2_instance *dml; 894 const struct display_configuation_with_meta *display_config; // Initial Display Configuration 895 bool (*init_function)(const struct optimization_init_function_params *params); // Test function to determine optimization is complete 896 bool (*test_function)(const struct optimization_test_function_params *params); // Test function to determine optimization is complete 897 bool (*optimize_function)(const struct optimization_optimize_function_params *params); // Function which produces a more optimized display configuration 898 struct display_configuation_with_meta *optimized_display_config; // The optimized display configuration 899 900 bool all_or_nothing; 901 }; 902 903 struct dml2_build_mode_programming_locals { 904 struct dml2_core_mode_support_in_out mode_support_params; 905 struct dml2_core_mode_programming_in_out mode_programming_params; 906 struct dml2_core_populate_informative_in_out informative_params; 907 struct dml2_pmo_optimize_dcc_mcache_in_out optimize_mcache_params; 908 struct display_configuation_with_meta base_display_config_with_meta; 909 struct display_configuation_with_meta optimized_display_config_with_meta; 910 struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out dppm_map_mode_params; 911 struct dml2_dpmm_map_watermarks_params_in_out dppm_map_watermarks_params; 912 struct dml2_optimization_phase_locals optimization_phase_locals; 913 struct optimization_phase_params min_clock_for_latency_phase; 914 struct optimization_phase_params mcache_phase; 915 struct optimization_phase_params uclk_pstate_phase; 916 struct optimization_phase_params vmin_phase; 917 struct optimization_phase_params stutter_phase; 918 }; 919 920 struct dml2_legacy_core_build_mode_programming_wrapper_locals { 921 struct dml2_core_mode_support_in_out mode_support_params; 922 struct dml2_core_mode_programming_in_out mode_programming_params; 923 struct dml2_core_populate_informative_in_out informative_params; 924 struct top_mcache_calc_mcache_count_and_offsets_in_out calc_mcache_count_params; 925 struct top_mcache_validate_admissability_in_out validate_admissibility_params; 926 struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES]; 927 struct top_mcache_assign_global_mcache_ids_in_out assign_global_mcache_ids_params; 928 struct dml2_pmo_optimize_dcc_mcache_in_out optimize_mcache_params; 929 struct dml2_display_cfg optimized_display_cfg; 930 struct core_display_cfg_support_info core_support_info; 931 }; 932 933 struct dml2_top_mcache_verify_mcache_size_locals { 934 struct dml2_calculate_mcache_allocation_in_out calc_mcache_params; 935 }; 936 937 struct dml2_top_mcache_validate_admissability_locals { 938 struct { 939 int pipe_vp_startx[DML2_MAX_DCN_PIPES]; 940 int pipe_vp_endx[DML2_MAX_DCN_PIPES]; 941 } plane0; 942 struct { 943 int pipe_vp_startx[DML2_MAX_DCN_PIPES]; 944 int pipe_vp_endx[DML2_MAX_DCN_PIPES]; 945 } plane1; 946 }; 947 948 struct dml2_top_display_cfg_support_info { 949 const struct dml2_display_cfg *display_config; 950 struct core_display_cfg_support_info core_info; 951 }; 952 953 struct dml2_top_funcs { 954 bool (*check_mode_supported)(struct dml2_check_mode_supported_in_out *in_out); 955 bool (*build_mode_programming)(struct dml2_build_mode_programming_in_out *in_out); 956 bool (*build_mcache_programming)(struct dml2_build_mcache_programming_in_out *in_out); 957 }; 958 959 struct dml2_instance { 960 enum dml2_project_id project_id; 961 962 struct dml2_core_instance core_instance; 963 struct dml2_mcg_instance mcg_instance; 964 struct dml2_dpmm_instance dpmm_instance; 965 struct dml2_pmo_instance pmo_instance; 966 967 struct dml2_soc_bb soc_bbox; 968 struct dml2_ip_capabilities ip_caps; 969 970 struct dml2_mcg_min_clock_table min_clk_table; 971 struct dml2_pmo_options pmo_options; 972 struct dml2_top_funcs funcs; 973 974 struct { 975 struct dml2_initialize_instance_locals initialize_instance_locals; 976 struct dml2_top_mcache_verify_mcache_size_locals mcache_verify_mcache_size_locals; 977 struct dml2_top_mcache_validate_admissability_locals mcache_validate_admissability_locals; 978 struct dml2_check_mode_supported_locals check_mode_supported_locals; 979 struct dml2_build_mode_programming_locals build_mode_programming_locals; 980 } scratch; 981 982 struct { 983 struct { 984 struct dml2_legacy_core_build_mode_programming_wrapper_locals legacy_core_build_mode_programming_wrapper_locals; 985 } scratch; 986 } legacy; 987 }; 988 #endif 989